JP2014120987A - A/d conversion circuit and solid-state imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an A/D conversion circuit which achieves higher precise AD conversion and to provide a solid-state imaging device.SOLUTION: A low-order latch circuit 81 latches pulse signals outputted from a plurality of delay units that are connected in a ring shape. A mismatch correction circuit 84 compares four pulse signals which are outputted from four delay units among the plurality of delay units and latched by the low-order latch circuit 81, and outputs a clock for counting to a high-order counter circuit 82 when the four pulse signals are in a prescribed state. The four delay units outputting the pulse signals inputted to the mismatch correction section 84 includes one delay unit for outputting the clock that the high-order counter circuit 82 counts and one delay unit adjacent to the delay unit, and the four delay units continue on a route where the pulse signals are transmitted.

Description

  The present invention relates to an A / D conversion circuit and a solid-state imaging device having the A / D conversion circuit.

  A TDC (Time to Digital Converter) type A / D conversion circuit is known as an A / D conversion circuit for measuring time (pulse width). FIG. 20 shows the configuration of the TDC type A / D conversion circuit, and FIG. 21 shows the operation of the TDC type A / D conversion circuit. As shown in FIG. 20, the TDC type A / D conversion circuit includes a delay circuit 102, an upper counter circuit 103, a lower latch circuit 104, and an encoder circuit 105.

  The delay circuit 102 has a configuration in which a plurality of delay units DU [1] to DU [8] are connected in a ring shape. Each delay unit has a pulse input terminal to which a pulse signal is input and a pulse output terminal that outputs the pulse signal. The pulse input terminal is connected to the pulse output terminal of the preceding delay unit, and the pulse output terminal is connected to the pulse input terminal of the subsequent delay unit. The pulse output terminal of the eighth stage delay unit DU [8] is connected to the pulse input terminal of the first stage delay unit, and the eight delay units are connected in a ring shape. These delay units delay the pulse signals input to the pulse input terminals and output them from the respective pulse output terminals. The first-stage delay unit DU [1] has a second pulse input terminal to which the start pulse φStartP is input.

  The start pulse φStartP input to the first delay unit DU [1] is sequentially transmitted to the subsequent delay unit, so that the pulse signal circulates in the delay circuit 102. Delay units DU [1] to DU [8] in delay circuit 102 output output signals φCK1 to φCK8. The output signals φCK1 to φCK8 are clock signals having different phases. Hereinafter, the output signal of the delay unit DU [n] at the n-th stage is described as φCKn.

  The higher-order counter circuit 103 performs counting (counting) using the pulse signal output from one delay unit (the eighth delay unit DU [8] in FIG. 20) constituting the delay circuit 102 as a count clock. The lower latch circuit 104 holds (latches) the output signal of each delay unit in accordance with the sampling pulse φSH. The encoder circuit 105 binarizes the value (phase data) held in the lower latch circuit 104.

  Next, the operation of the TDC type A / D conversion circuit will be described with reference to FIG. Hereinafter, for example, a case where the pulse width of the sampling pulse φSH is measured will be described. FIG. 21 shows waveforms of the sampling pulse φSH and the start pulse φStartP, the waveforms of the output signals φCK1 to φCK8 of the delay units DU [1] to DU [8] constituting the delay circuit 102, and the upper counter circuit 103. The value of the signal φOCNT indicating the counted value is shown.

  First, at the same time as the sampling pulse φSH changes from low to high, the start pulse φStartP changes from low to high (timing T101). As a result, the pulse signal circulates in the delay circuit 102 as indicated by the output signals φCK1 to φCK8 in FIG. After the elapse of a predetermined period from timing T101, at the timing when the sampling pulse φSH changes from high to low (timing T102), the lower counter circuit 104 outputs the output signal of the delay circuit 102 at the same time as the counting operation of the upper counter circuit 103 ends. Holds (latch) φCK1 to φCK8.

  At this time, the value (phase data) held by the lower latch circuit 104 corresponds to one of eight states (states 1 to 8), as shown in FIGS. FIG. 22 shows the states of the output signals φCK1 to φCK8 of the delay circuit 102 in the states 1 to 8. In each of the states 1 to 8, the combinations of the high (H) and low (L) states of the output signals φCK1 to φCK8 of the delay circuit 102 are different.

  The output signal of the lower latch circuit 104 is binarized by the encoder circuit 105. The output signal of the encoder circuit 105 is output to the subsequent circuit together with the output signal φOCNT of the higher-order counter circuit 103. The output signal φOCNT of the upper counter circuit 103 has a value corresponding to the number of times the start pulse φStartP has circulated in the delay circuit 102, and constitutes upper data of digital data. The output signal of the encoder circuit 105 has a value corresponding to the travel position of the start pulse φStartP in the delay circuit 102, and constitutes lower data of the digital data.

  In this way, digital data corresponding to the pulse width of the sampling pulse φSH can be obtained. At this time, since the value (8-bit data signal) held by the lower latch circuit 104 corresponds to any of the eight states, a 3-bit data signal is generated by binarizing this value.

  As an application destination of such a TDC type A / D conversion circuit, there is a solid-state imaging device (image sensor) used for a digital camera, a digital video camera, an endoscope, or the like. Patent Document 1 describes an example in which a TDC type A / D conversion circuit is arranged for each pixel column and the output from the pixel is A / D converted. The solid-state imaging device described in Patent Document 1 converts a pixel signal level (voltage information) into a pulse width (time information), and performs analog / digital conversion on the pulse width using a TDC A / D converter circuit. This is an image sensor of a type (so-called single slope type) that acquires digital data according to the signal level of a pixel.

  Further, the solid-state imaging device described in Patent Document 1 incorporates an encoder circuit 105 for binarizing data in a column circuit provided corresponding to each pixel column. The encoder circuit 105 determines whether the value held by the lower latch circuit 104 corresponds to any one of the states 1 to 8 shown in FIG. 22, and the delay units DU [1] to DU [8] Output signal of two consecutive delay units are sequentially compared, and the state change between the output signals of the two delay units (the output signal φCKn of the delay unit DU [n] is High and the delay unit DU [n + 1] output signal φCK (n + 1) is low). For example, if there is a state change between the output signal φCK1 of the delay unit DU [1] and the output signal φCK2 of the delay unit DU [2], the encoder circuit 105 has the value held by the lower latch circuit 104, It is determined that the value corresponds to state 2.

JP 2012-204842

  Incidentally, the output signals φCK1 to φCK8 of the delay circuit 102 are asynchronously transmitted in parallel. Therefore, when the lower latch circuit 104 holds the multiphase clock composed of the output signals φCK1 to φCK8, the value held by the lower latch circuit 104 due to the jitter of the output signals φCK1 to φCK8 of the delay circuit 102, etc. May vary as shown in FIG. At this time, in the method of sequentially comparing the output signals of the two delay units, there is a state change between the output signal φCK2 and the output signal φCK1 (state 2), or between the output signal φCK7 and the output signal φCK6. Cannot determine whether there is a state change (state 7).

  To solve the above problem, Patent Document 1 proposes a method of using output signals of three consecutive delay units in order to detect a state change between the output signals of two consecutive delay units. That is, whether or not there is a state change between the output signal φCKn of the delay unit DU [n] and the output signal φCK (n + 1) of the delay unit DU [n + 1] is determined by whether the output signal φCKn of the delay unit DU [n] Depending on whether the output signal φCK (n + 1) of the delay unit DU [n + 1] is Low and the output signal φCK (n + 2) of the delay unit DU [n + 2] is Low Determined. With this method, it is possible to detect a change in state between the output signal φCK2 and the output signal φCK1 even when the signal held by the lower latch circuit 104 varies as shown in FIG.

  Here, consider the case where the signals held by the lower latch circuit 104 vary as shown in FIG. The output signals φCK1 to φCK8 of the delay circuit 102 at this time are signals held in the lower latch circuit 104 at the timing (holding timing) of the falling position of the sampling pulse φSH, as shown in FIG. As shown in FIG. 25, at the holding timing of the lower latch circuit 104, the phases of the output signal φCK1 and the output signal φCK8 are reversed.

  According to the prior art, since the output signal φCK1 is high, the output signal φCK2 is low, and the output signal φCK3 is low, the encoder circuit 105 detects a state change between the output signal φCK1 and the output signal φCK2. Therefore, the encoder circuit 105 determines that the state is 2.

  Incidentally, the upper counter circuit 103 counts rising edges of the output signal φCK8 of the delay unit DU [8]. Therefore, at the holding timing of the lower latch circuit 104, the upper counter circuit 103 has not yet counted up.

  When there is no variation in the signal held by the lower latch circuit 104, the upper counter circuit 103 counts up at the timing when the state of the output signals φCK1 to φCK8 of the delay circuit 102 transitions from the state 8 to the state 1. Therefore, when the state of the output signals φCK1 to φCK8 of the delay circuit 102 is the state 2, the upper counter circuit 103 is set at the timing immediately before the state of the output signals φCK1 to φCK8 of the delay circuit 102 transitions from the state 8 to the state 1. It needs to be counted up. However, when the signal held by the lower latch circuit 104 varies as shown in FIG. 24, the upper counter circuit 103 is not counted up in the prior art. Therefore, a mismatch occurs between the upper bits based on the value counted by the upper counter circuit 103 and the lower bits based on the state of the signal held by the lower latch circuit 104.

  Thus, the conventional technique has a problem that when the variation in the signal held by the lower latch circuit 104 is a specific pattern, a mismatch between the upper bits and the lower bits occurs.

  The present invention has been made in view of the above-described problems, and an object thereof is to provide an A / D conversion circuit and a solid-state imaging device capable of performing A / D conversion with higher accuracy.

  The present invention has been made to solve the above-described problems, and has four or more delay units each having a pulse input terminal and a pulse output terminal, and each pulse input terminal of the plurality of delay units. Is connected to one corresponding pulse output terminal of the plurality of delay units, and any one of the plurality of delay units includes a delay circuit having a second pulse input terminal to which a pulse signal is input from the outside. A low-order latch circuit that latches pulse signals output from the plurality of delay units; a high-order counter circuit that counts a clock based on a pulse signal output from one delay unit among the plurality of delay units; Among the delay units, the three delay units that are consecutive on the path through which the pulse signal is transmitted are output by the lower latch circuit. The three pulse signals are compared, and when the state of the three pulse signals is a predetermined first state, the state change detection circuit outputs a state change detection signal, and is input to the state change detection circuit. An encode signal having a state corresponding to the delay unit that outputs the pulse signal to be output, and an encode signal latch circuit that latches the encode signal when the state change detection signal is input; and among the plurality of delay units Compares four pulse signals output from four delay units and latched by the lower latch circuit, and counts the higher counter circuit when the state of the four pulse signals is a predetermined second state. A mismatch detection circuit that outputs a clock for the delay circuit, wherein the delay circuit receives a pulse signal at a first timing, and The latch circuit latches the pulse signals output from the plurality of delay units at a second timing, the upper counter circuit starts counting at the first timing, and the upper counter circuit Counting ends at the second timing, and the four delay units are one delay unit that outputs a clock counted by the upper counter circuit, and one delay unit adjacent to the delay unit on the path And an A / D conversion circuit comprising four delay units that are continuous on the path.

  In the A / D conversion circuit of the present invention, the state change detection circuit outputs a signal indicating a result of comparing the three pulse signals while changing the combination of the three pulse signals, and the mismatch detection The circuit is a signal output from the state change detection circuit when a pulse signal output from three delay units of the four delay units and latched by the lower latch circuit is input to the state change detection circuit. And a binary comparison circuit that compares the pulse signal output from the remaining one of the four delay units and latched by the lower latch circuit.

  The present invention also relates to a pixel portion in which a plurality of pixels having photoelectric conversion elements are arranged in a matrix, a reference signal generation portion that generates a reference signal that increases or decreases over time, and an output of the pixel signal A comparison unit that starts comparison processing between the pixel signal and the reference signal at a timing, and ends the comparison processing at a timing when the reference signal satisfies a predetermined condition with respect to the pixel signal; and the A / D described above A conversion circuit, and the comparison unit, the lower latch circuit, the upper counter circuit, the state change detection circuit, the encode signal latch circuit, and the mismatch detection circuit are arranged in one column or a plurality of the pixel units. Arranged for each column, the first timing is a timing related to the start of the comparison process, and the second timing is a timing related to the end of the comparison process. A solid-state imaging device according to claim.

  According to the present invention, by providing the mismatch detection circuit, the mismatch between the upper bit based on the value counted by the upper counter circuit and the lower bit based on the state of the pulse signal latched by the lower latch circuit is corrected. Therefore, A / D conversion with higher accuracy can be performed.

1 is a block diagram showing a configuration of a solid-state imaging device according to a first embodiment of the present invention. 1 is a block diagram showing a configuration of an A / D conversion circuit according to a first embodiment of the present invention. FIG. 3 is a block diagram showing a configuration of a phase data encoding unit according to the first embodiment of the present invention. FIG. 3 is a block diagram showing a configuration of a mismatch correction unit according to the first embodiment of the present invention. FIG. 3 is a reference diagram showing a truth table defining the operation of the state change detection circuit according to the first embodiment of the present invention. FIG. 5 is a reference diagram showing a table describing the relationship between the number of delay units that output a signal to the state change detection circuit according to the first embodiment of the present invention and the encode signal. FIG. 3 is a reference diagram showing a truth table defining the operation of the mismatch detection circuit according to the first embodiment of the present invention. 3 is a timing chart showing an operation of the solid-state imaging device according to the first embodiment of the present invention. 3 is a timing chart showing an operation of the solid-state imaging device according to the first embodiment of the present invention. 3 is a timing chart showing an operation of the solid-state imaging device according to the first embodiment of the present invention. FIG. 5 is a block diagram showing a configuration of an A / D conversion circuit according to a second embodiment of the present invention. FIG. 10 is a reference diagram showing a truth table defining the operation of the mismatch detection circuit according to the second embodiment of the present invention. 6 is a timing chart showing an operation of the solid-state imaging device according to the second embodiment of the present invention. FIG. 10 is a reference diagram showing a truth table defining the operation of the state change detection circuit according to the third embodiment of the present invention. FIG. 10 is a reference diagram showing a truth table defining the operation of the mismatch detection circuit according to the third embodiment of the present invention. 6 is a timing chart showing an output signal of a delay circuit according to a third embodiment of the present invention. FIG. 10 is a reference diagram illustrating a state of an output signal of a delay circuit according to a third embodiment of the present invention. 10 is a timing chart showing the operation of the solid-state imaging device according to the third embodiment of the present invention. 10 is a timing chart showing the operation of the solid-state imaging device according to the third embodiment of the present invention. It is a block diagram which shows the structure of a TDC type A / D conversion circuit. 3 is a timing chart showing the operation of a TDC type A / D conversion circuit. FIG. 6 is a reference diagram illustrating a state of an output signal of a delay circuit included in a TDC type A / D conversion circuit. FIG. 6 is a reference diagram illustrating a state of an output signal of a delay circuit included in a TDC type A / D conversion circuit. FIG. 6 is a reference diagram illustrating a state of an output signal of a delay circuit included in a TDC type A / D conversion circuit. 6 is a timing chart showing an output signal of a delay circuit included in a TDC type A / D conversion circuit.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
First, a first embodiment of the present invention will be described. FIG. 1 shows a configuration of a solid-state imaging device according to the present embodiment. 1 includes a pixel array 2 (pixel unit) in which pixels 1 (P11 to P16, P21 to P26, P31 to P36, and P41 to P46) are two-dimensionally arranged, a vertical scanning circuit 3, Column circuit 4, ramp wave generation circuit 5 (reference signal generation unit), comparison circuit 6 (comparison unit), clock generation circuit 7, A / D conversion circuit 8, horizontal scanning circuit 9, and control circuit 10 It consists of and.

  The pixel 1 has at least a photoelectric conversion element, and generates and outputs a pixel signal corresponding to the amount of incident light. The pixel array 2 has a plurality of pixels 1 arranged in a two-dimensional matrix. In the example shown in FIG. 1, pixels 1 in 4 rows and 6 columns are arranged. The vertical scanning circuit 3 includes a shift register or a decoder, and performs row selection of the pixel array 2. The column circuit 4 is configured by a so-called CDS circuit or the like, and processes and outputs a pixel signal read from the pixel array 2.

  The ramp wave generation circuit 5 generates a reference signal (ramp wave) that increases or decreases over time. The comparison circuit 6 responds to the magnitude of the signal level of the pixel signal φPIX according to the result of comparing the signal level of the pixel signal φPIX output from the column circuit 4 and the reference signal φREF output from the ramp wave generation circuit 5 A pulse signal (output signal φCOMP) having a magnitude (pulse width) in the time axis direction is generated. The clock generation circuit 7 includes a delay circuit 71 in which a plurality of delay units are arranged in a ring shape. The number of delay units constituting the delay circuit 71 of the present embodiment may be four or more.

  The A / D conversion circuit 8 performs analog / digital conversion on the pulse width of the output signal φCOMP of the comparison circuit 6. The horizontal scanning circuit 9 is configured by a shift register, a decoder, or the like, controls the A / D conversion circuit 8, and outputs a value held by the A / D conversion circuit 8 for each column. The control circuit 10 outputs various control signals to each circuit constituting the solid-state imaging device.

  The ramp wave generation circuit 5 is configured by, for example, an integration circuit, generates a so-called ramp wave whose level changes in an inclined manner as time passes, and supplies the so-called ramp wave to one of the input terminals of the comparison circuit 6. The ramp wave generation circuit 5 is not limited to the one using an integration circuit, and a DAC circuit may be used. However, in the case of adopting a configuration in which a ramp wave is generated digitally using a DAC circuit, it is necessary to make the step of the ramp wave fine or a configuration equivalent thereto.

  In the present embodiment, six sets of the column circuit 4, the comparison circuit 6, and the A / D conversion circuit 8 are prepared and arranged for each pixel column. In this embodiment, a set of these circuits is arranged for each pixel column. However, a set of these circuits may be shared among a plurality of pixel columns.

  In the present embodiment, for example, the delay circuit 71 configuring the clock generation circuit 7 is configured by eight stages of delay units DU [1] to DU [8], similar to the delay circuit 102 illustrated in FIG. The case will be described. The clock generation circuit 7 outputs the output signal φCK8 of the delay unit DU [8] at the eighth stage as the count clock of the upper counter circuit 82.

  FIG. 2 shows a configuration of the A / D conversion circuit 8 according to the present embodiment. The A / D conversion circuit 8 includes a lower latch circuit 81, an upper counter circuit 82, a phase data encoding unit 83, a mismatch correction unit 84, and a multiplexer MUX.

  The lower latch circuit 81 receives the output signal φCOMP of the comparison circuit 6 and outputs the output signals φCK1 to φCK8 of the delay units DU [1] to DU [8] of the delay circuit 71 at the timing of the falling position of the output signal φCOMP. Is comprised of eight latch circuits L1 to L8. Each of these eight latch circuits L1 to L8 holds a 1-bit signal. Each of the latch circuits L1 to L8 outputs the output signals DU [1] to DU [8] of each delay unit to the signal transmission line 85 at a timing based on the output control signals φSW1 to φSW8.

  The upper counter circuit 82 counts (counts) the rising edge of the output signal φCK8 of the delay circuit 71 input through the latch circuit L8. The phase data encoding unit 83 binarizes the output signals DU [1] to DU [8] (phase data) of the delay circuit 71 held by the lower latch circuit 81. The mismatch correction unit 84 refers to the value held by the lower latch circuit 81 to detect a mismatch between the upper bit and the lower bit, and outputs a correction signal (count pulse) to the upper counter circuit 82 when there is a mismatch. To do. The multiplexer MUX selects either the output signal φCK8 ′ of the latch circuit L8 of the lower latch circuit 81 or the output signal φCOR of the mismatch correction unit 84 and outputs the selected signal to the upper counter circuit 82. Note that the multiplexer MUX uses the selection signal φSEL to output the output signal φCK8 ′ of the latch circuit L8 of the lower latch circuit 81 to the upper counter circuit 82 except during the mismatch correction period for correcting the mismatch between the upper bit and the lower bit. Be controlled.

  FIG. 3 shows a configuration of the phase data encoding unit 83 according to the present embodiment. The phase data encoding unit 83 includes a pulse signal latch circuit 831, a state change detection circuit 832, and an encode signal latch circuit 833.

  The pulse signal latch circuit 831 includes two latch circuits TL8311 and TL8312 that hold the signal read from the lower latch circuit 81 to the signal transmission line 85. The latch circuits TL8311 and TL8312 take in signals from the signal transmission line 85 in accordance with the latch signals φTEMPLAT8311 and φTEMPLAT8312.

  The state change detection circuit 832 has terminals A, B, C, and O. Terminal A is connected to signal transmission line 85, terminal B is connected to output terminal Q of latch circuit TL8312 of pulse signal latch circuit 831 and terminal C is connected to output terminal Q of latch circuit TL8311 of pulse signal latch circuit 831. The terminal O is connected to the encode signal latch circuit 833. When the output signal of the nth delay unit (hereinafter referred to as DU [n]) is output from the latch circuit TL8311, the (n + 1) th delay unit DU [n + 1] from the latch circuit TL8312 The output signal of the (n + 2) -th delay unit DU [n + 2] is output to the signal transmission line 85. Therefore, among the delay units DU [1] to DU [8] connected in a ring shape in the delay circuit 71, three delay units DU [n] to DU [n + 2 consecutive on the transmission path through which the pulse signal is transmitted. ] Is input to the state change detection circuit 832. The state change detection circuit 832 compares these output signals to output the output signal of the nth delay unit DU [n] and the output of the (n + 1) th delay unit DU [n + 1]. Detect state changes with the signal.

  Note that the state change detection circuit 832 detects a state change based on the truth table shown in FIG. FIG. 5 shows the state of the signal input to terminals A, B, and C of state change detection circuit 832 and the state of the signal (output signal φDET) output from terminal O of state change detection circuit 832. . When the enable signal φENCEN input to the state change detection circuit 832 is High, the output signal φDET of the state change detection circuit 832 becomes High or Low depending on the state of the signal input to the terminals A, B, and C. . When the signals input to the terminals A, B, and C are Low, Low, and High, respectively, the output signal φDET of the state change detection circuit 832 becomes High, and the state change is detected. When the enable signal φENCEN input to the state change detection circuit 832 is Low, the output signal φDET of the state change detection circuit 832 is Low regardless of the state of the signals input to the terminals A, B, and C. FIG. 6 shows a table describing the relationship between the delay unit that outputs a signal to the state change detection circuit 832 and the encode signal φBC [3: 1].

  The encode signal latch circuit 833 includes three latch circuits BCL8331, BCL8332, and BCL8333 that hold the encode signal φBC (= Binary Code) [3: 1] in accordance with the output signal φDET of the state change detection circuit 832. Each of the latch circuits BCL8331, BCL8332, and BCL8333 receives the output signal φDET of the state change detection circuit 832 as a control signal and the delay circuit 71 of the delay unit that outputs the signal output to the state change detection circuit 832. The encode signal φBC [3: 1] corresponding to the position (number of stages) in the is input.

  FIG. 4 shows a configuration of the mismatch correction unit 84 according to the present embodiment. The mismatch correction unit 84 includes a pulse signal latch circuit 841 and a mismatch detection circuit 842.

  The pulse signal latch circuit 841 includes three latch circuits TL8411, TL8412, and TL8413 that hold the signal read out to the signal transmission line 85. The latch circuits TL8411, TL8412, and TL8413 capture signals from the signal transmission line 85 in accordance with the latch signals φTEMPLAT8411, φTEMPLAT8412, and φTEMPLAT8413.

  The mismatch detection circuit 842 has terminals A, B, C, D, and O. Terminal A is connected to signal transmission line 85, terminal B is connected to output terminal Q of latch circuit TL8413 of pulse signal latch circuit 841, and terminal C is connected to output terminal Q of latch circuit TL8412 of pulse signal latch circuit 841. The terminal D is connected to the output terminal Q of the latch circuit TL8411 of the pulse signal latch circuit 841, and the terminal O is connected to the multiplexer MUX. When the output signal of the nth delay unit DU [n] is output from the latch circuit TL8411, the output signal of the (n + 1) th delay unit DU [n + 1] is output from the latch circuit TL8412. The output signal of the (n + 2) stage delay unit DU [n + 2] is output from the latch circuit TL8413, and the (n + 3) stage delay unit DU [n + 3] is output to the signal transmission line 85. An output signal is being output. Therefore, among the delay units DU [1] to DU [8] connected in a ring shape in the delay circuit 71, four delay units DU [n] to DU [n + 3 consecutive on the transmission path through which the pulse signal is transmitted. ] Is input to the mismatch detection circuit 842. The mismatch detection circuit 842 detects a mismatch between the upper bit and the lower bit by comparing these output signals.

  Mismatch detection circuit 842 detects a mismatch based on the truth table shown in FIG. FIG. 7 shows the state of signals input to terminals A, B, C, and D of mismatch detection circuit 842 and the state of a signal (output signal φCOR) output from terminal O of mismatch detection circuit 842. . When the enable signal φCOREN input to the mismatch detection circuit 842 is High, the output signal φCOR of the mismatch detection circuit 842 becomes High or Low depending on the state of the signal input to the terminals A, B, C, and D. . When the signals input to the terminals A, B, C, and D are Low, Low, High, and Low, respectively, the output signal φCOR of the mismatch detection circuit 842 becomes High, and a mismatch between the upper bit and the lower bit is detected. When the enable signal φCOREN input to the mismatch detection circuit 842 is low, the output signal φCOR of the mismatch detection circuit 842 is low regardless of the state of the signal input to the terminals A, B, C, and D.

  Next, the operation of the solid-state imaging device according to the present embodiment will be described with reference to FIG. First, at timing T1, the pixel selection signal φSL1 changes from low to high. As a result, the pixel 1 (P11, P12, P13, P14, P15, P16) in the first row is selected, and the pixel signal of the pixel 1 (P11, P12, P13, P14, P15, P16) is input to the column circuit 4 Is done. The column circuit 4 outputs a pixel signal φPIX obtained by processing the input pixel signal. Hereinafter, the pixel signal of the pixel Pnm (n = row number, m = column number) is described as φPIX (Pnm). In FIG. 8, only the pixel signal processing in the first column is described. In parallel with the processing of the pixel signals in the first column, the processing of the pixel signals in the second to sixth columns is performed by a circuit corresponding to each column.

  At timing T1 (first timing), when the start pulse φStartP changes from low to high, the clock generation circuit 7 starts outputting the clock signals (φCK1 to φCK8), and the ramp wave generation circuit 5 The reference signal φREF, which increases as time elapses, starts to be output, the output signal φCOMP of the comparison circuit 6 changes from Low to High, and the comparison circuit 6 starts the comparison process of the reference signal φREF and the pixel signal φPIX. At this timing T1, the upper counter circuit 82 starts counting the output signal φCK8 ′ of the latch circuit L8 of the lower latch circuit 81.

  Subsequently, when the magnitude relationship between the signal levels of the reference signal φREF and the pixel signal φPIX is reversed at timing T2 (second timing), the output signal φCOMP of the comparison circuit 6 changes from High to Low. At this timing T2, the lower latch circuit 81 holds the output signal (phase data) of the delay circuit 71. Thereby, the upper counter circuit 82 ends the counting operation of the output signal φCK8 ′ of the latch circuit L8 of the lower latch circuit 81.

  Subsequently, at timing T3, the pixel selection signal φSL1 changes from High to Low, and the output of the pixel signal in the first row is completed. Subsequently, the value held by the lower latch circuit 81 during the encoding period (between timings T3 and T4) is binarized by the phase data encoding unit 83. Details of the binarization by the phase data encoding unit 83 will be described later.

  Subsequently, during the mismatch correction period (between timings T4 and T5), the mismatch correction unit 84 detects a mismatch between the upper bit and the lower bit, and if there is a mismatch, the value counted by the upper counter circuit 82 is corrected. Details of mismatch detection by the mismatch correction unit 84 will be described later.

  Subsequently, when the column selection signal φH1 changes from low to high at timing T5, the A / D conversion result of the pixel signal φPIX (P11) held by the A / D conversion circuit 8 in the first column is output. Thereafter, similarly, the column selection signals φH2 to φH6 are sequentially changed from low to high, whereby the read operation of the first row is completed.

  Thereafter, the pixel signals in the second to sixth rows can be read in the same manner as in the first row, whereby digital data of all the pixel signals generated in the pixel array 2 can be obtained.

  Next, an operation related to the encoding period (between T3 and T4) will be described with reference to FIG. Hereinafter, a case where the output signals φCK1 to φCK8 of the delay circuit 71 vary as shown in FIG. 24 due to jitter at the holding timing of the lower latch circuit 81 will be described.

  First, at timing T31, the output control signal φSW8 and the latch signal φTEMPLAT8311 become High. As a result, the output signal φCK8 of the eighth stage delay unit DU [8] held by the lower latch circuit 81 is output to the signal transmission line 85, and the latch circuit TL8311 of the pulse signal latch circuit 831 is signal transmission line. The output signal φCK8 of the delay unit DU [8] from the 85th stage to the eighth stage is captured. Thereafter, when the latch signal φTEMPLAT8311 becomes Low, the latch circuit TL8311 holds the output signal φCK8 of the delay unit DU [8] at the eighth stage.

Subsequently, the output control signal φSW1 and the latch signal φTEMPLAT8312 become High at the same time as the output control signal φSW8 becomes Low at timing T32. At timing T32, the encode signal φBC [3: 1] becomes 0 ₍₁₀₎ . Note that (10) means a decimal number. As a result, the output signal φCK1 of the first delay unit DU [1] held by the lower latch circuit 81 is output to the signal transmission line 85, and the latch circuit TL8312 of the pulse signal latch circuit 831 is also connected to the signal transmission line. From 85, the output signal φCK1 of the delay unit DU [1] in the first stage is fetched. Thereafter, the latch signal φTEMPLAT8312 becomes Low, so that the latch circuit TL8312 holds the output signal φCK1 of the first delay unit DU [1].

  Subsequently, at the timing T33, the output control signal φSW2 becomes High at the same time as the output control signal φSW1 becomes Low. As a result, the output signal φCK2 of the second-stage delay unit DU [2] held by the lower latch circuit 81 is output to the signal transmission line 85. At this time, the output signals φCK2 of the second-stage delay unit DU [2] and the output signals φCK1, 8 of the first-stage delay unit DU [1] are connected to the terminals A, B, and C of the state change detection circuit 832 respectively. The output signal φCK8 of the delay unit DU [8] at the stage is input. As shown in FIG. 24, the output signal φCK2 of the second delay unit DU [2], the output signal φCK1 of the first delay unit DU [1], and the output signal of the eighth delay unit DU [8] Since φCK8 is Low, High, and Low, respectively, the output signal φDET of the state change detection circuit 832 is Low according to the truth table shown in FIG.

  Subsequently, at time T34, the output control signal φSW1 and the latch signal φTEMPLAT8311 become High at the same time as the output control signal φSW2 becomes Low. As a result, the output signal φCK1 of the first delay unit DU [1] held by the lower latch circuit 81 is output to the signal transmission line 85, and the latch circuit TL8311 of the pulse signal latch circuit 831 is From 85, the output signal φCK1 of the delay unit DU [1] in the first stage is fetched. Thereafter, when the latch signal φTEMPLAT8311 becomes Low, the latch circuit TL8311 holds the output signal φCK1 of the delay unit DU [1] at the first stage.

Subsequently, at the timing T35, the output control signal φSW2 and the latch signal φTEMPLAT8312 become High at the same time as the output control signal φSW1 becomes Low. At timing T35, the encode signal φBC [3: 1] becomes 1 ₍₁₀₎ . As a result, the output signal φCK2 of the second-stage delay unit DU [2] held by the lower latch circuit 81 is output to the signal transmission line 85, and the latch circuit TL8312 of the pulse signal latch circuit 831 is also connected to the signal transmission line. The output signal φCK2 of the delay unit DU [2] in the second stage from 85 is captured. Thereafter, when the latch signal φTEMPLAT8312 becomes Low, the latch circuit TL8312 holds the output signal φCK2 of the second-stage delay unit DU [2].

Subsequently, at the timing T36, the output control signal φSW3 becomes High at the same time as the output control signal φSW2 becomes Low. As a result, the output signal φCK3 of the third-stage delay unit DU [3] held by the lower latch circuit 81 is output to the signal transmission line 85. At this time, the output signal φCK3 of the third-stage delay unit DU [3] and the output signal φCK2, 1 of the second-stage delay unit DU [2] are respectively connected to the terminals A, B, and C of the state change detection circuit 832. The output signal φCK1 of the stage delay unit DU [1] is input. As shown in FIG. 24, the output signal φCK3 of the third delay unit DU [3], the output signal φCK2 of the second delay unit DU [2], and the output signal of the first delay unit DU [1] Since φCK1 is Low, Low, and High, respectively, the output signal φDET of the state change detection circuit 832 becomes High according to the truth table shown in FIG. Since the output signal φDET of the state change detection circuit 832 is High, the encode signal latch circuit 833 takes in the encode signal φBC [3: 1] = 1 ₍₁₀₎ .

Subsequently, at the timing T37, the output control signal φSW2 and the latch signal φTEMPLAT8311 become High at the same time as the output control signal φSW3 becomes Low. As a result, the output signal φCK2 of the second-stage delay unit DU [2] held by the lower latch circuit 81 is output to the signal transmission line 85, and the latch circuit TL8311 of the pulse signal latch circuit 831 is also connected to the signal transmission line. The output signal φCK2 of the delay unit DU [2] in the second stage from 85 is captured. Further, since the enable signal φENCEN becomes Low at timing T37, the output signal φDET of the state change detection circuit 832 becomes Low. At this time, the encode signal latch circuit 833 holds the encode signal φBC [3: 1] = 1 ₍₁₀₎ . Thereafter, when the latch signal φTEMPLAT8311 becomes Low, the latch circuit TL8311 holds the output signal φCK2 of the second-stage delay unit DU [2].

Thereafter, similarly, until the timing T39 via the timing T38, the state change detection circuit 832 outputs the output signal of the nth delay unit DU [n] and the (n + 1) th delay unit DU [n + 1]. ] And the output signal of the (n + 2) stage delay unit DU [n + 2] are sequentially compared. During this time, since the state change detection circuit 832 does not detect the state change, the encode signal latch circuit 833 keeps the encode signal φBC [3: 1] = 1 ₍₁₀₎ .

  Since the lower latch circuit 81 holds the value shown in FIG. 24, a mismatch between the upper bits and the lower bits (the upper counter circuit 82 is not counting up) occurs in the encoding period.

  Next, the operation in the mismatch correction period (T4 to T5) will be described with reference to FIG. During the mismatch correction period, the selection signal φSEL is High, and the output signal φCOR of the mismatch detection circuit 842 is input to the upper counter circuit 82. Since it is known that a mismatch occurs when the state of the signal held by the lower latch circuit 81 is the state shown in FIG. 24, the mismatch detection circuit 842 includes the delay unit DU [3] in the third stage. Output signal φCK3, output signal φCK2 of second delay unit DU [2], output signal φCK1 of first delay unit DU [1], output signal φCK8 of eighth delay unit DU [8] Is detected in a predetermined state (Low, Low, High, Low).

  First, at timing T41, the output control signal φSW8 and the latch signal φTEMPLAT8411 become High. As a result, the output signal φCK8 of the delay unit DU [8] in the eighth stage held by the lower latch circuit 81 is output to the signal transmission line 85, and the latch circuit TL8411 of the pulse signal latch circuit 841 is The output signal φCK8 of the delay unit DU [8] from the 85th stage to the eighth stage is captured. Thereafter, when the latch signal φTEMPLAT8311 becomes Low, the latch circuit TL8311 holds the output signal φCK8 of the delay unit DU [8] at the eighth stage.

  At timings T42 to T43, the output signal φCK1 of the first delay unit DU [1] and the output signal φCK2 of the second delay unit DU [2] are pulse signal latched in the same procedure as the timings T41 to T42. It is held in the latch circuits TL8412 and TL8413 of the circuit 841.

  Subsequently, the output control signal φSW3 becomes High at timing T43. As a result, the output signal φCK3 of the delay unit DU [3] at the third stage is output to the signal transmission line 85. At this time, the terminals A, B, C, and D of the mismatch detection circuit 842 are respectively connected to the output signal φCK3 of the third delay unit DU [3], the output signal φCK2 of the second delay unit DU [2], The output signal φCK1 of the first delay unit DU [1] and the output signal φCK8 of the eighth delay unit DU [8] are input. As shown in FIG. 24, the output signal φCK3 of the third delay unit DU [3], the output signal φCK2 of the second delay unit DU [2], and the output signal of the first delay unit DU [1] Since the output signal φCK8 of the delay unit DU [8] at φCK1 and the eighth stage is Low, Low, High, and Low, respectively, the output signal φCOR of the mismatch detection circuit 842 becomes High according to the truth table shown in FIG. Since the output signal φCOR of the mismatch detection circuit 842 becomes High, the upper counter circuit 82 counts up at timing T43. Thereby, the mismatch between the upper bits and the lower bits is corrected.

  Note that when the state of the signal held by the lower latch circuit 81 is other than the state shown in FIG. 24, a mismatch does not occur, and the mismatch detection circuit 842 does not detect the mismatch. Therefore, in this case, encoding is performed in the same manner as in the prior art.

  In the above operation, the mismatch between the upper bits and the lower bits can be corrected. Therefore, according to the present embodiment, it is possible to perform A / D conversion with higher accuracy. In addition, a high-precision solid-state imaging device can be provided by arranging a high-precision A / D conversion circuit for each column.

  Note that a delay unit that outputs a signal input to the mismatch detection circuit 842 when the mismatch detection circuit 842 detects a mismatch is a delay unit that outputs a signal that is a count clock of the higher-order counter circuit 82 (in the above example, 8). If there are four consecutive delay units including at least a delay unit DU [8] in the stage and a delay unit adjacent to the delay unit (in the above example, the delay unit DU [1] in the first stage) Good.

  In connection with the operation of detecting the state change, by providing three signal transmission lines connected to the state change detection circuit 832, the output signal of the delay unit DU [n] and the delay unit DU [n + 1] The phase data encoding unit 83 may be configured to input the output signal and the output signal of the delay unit DU [n + 2] to the state change detection circuit 832 without going through the pulse signal latch circuit 831.

  In connection with the operation of detecting the mismatch, by providing four signal transmission lines connected to the mismatch detection circuit 842, the output signal φCK8 of the delay unit DU [8] and the output signal φCK1 of the delay unit DU [1] And the mismatch correction unit 84 so that the output signal φCK2 of the delay unit DU [2] and the output signal φCK3 of the delay unit DU [3] are input to the mismatch detection circuit 842 without going through the pulse signal latch circuit 841. It may be configured.

(Second embodiment)
Next, a second embodiment of the present invention will be described. FIG. 11 shows a configuration of the A / D conversion circuit 8a according to the present embodiment. Since the configuration other than the mismatch correction unit 84a is the same as that of the first embodiment, the description thereof is omitted.

  The mismatch correction unit 84a includes a pulse signal latch circuit 84a1 and a mismatch detection circuit 84a2. The pulse signal latch circuit 84a1 holds the signal read to the signal transmission line 85. The mismatch detection circuit 84a2 has terminals A and B. The terminal A is connected to the pulse signal latch circuit 84a1, and the terminal B is connected to the phase data encoding unit 83. The mismatch detection circuit 84a2 compares the signal obtained by inverting the output signal of the pulse signal latch circuit 84a1 with the output signal φDET of the state change detection circuit 832 constituting the phase data encoding unit 83, so that the upper bit and the lower bit This is a binary comparison circuit for detecting a mismatch.

  The mismatch detection circuit 84a2 detects a mismatch based on the truth table shown in FIG. FIG. 12 shows the state of the signal input to the terminals A and B of the mismatch detection circuit 84a2 and the state of the signal (output signal φCOR) output from the terminal O of the mismatch detection circuit 84a2. The output signal φCOR of the mismatch detection circuit 84a2 becomes High or Low depending on the state of the signal input to the terminals A and B. When the signals input to the terminals A and B are Low and High, respectively, the output signal φCOR of the mismatch detection circuit 84a2 becomes High, and a mismatch between the upper bit and the lower bit is detected.

  Next, the operation of the mismatch correction unit 84a according to the present embodiment will be described with reference to FIG. Note that the operation other than the mismatch correction period is the same as the operation described in the first embodiment, and thus the description thereof is omitted. Further, the lower latch circuit 81 holds the signal shown in FIG. 24, as in the first embodiment. Hereinafter, a case where a mismatch between the upper bits and the lower bits occurs in the encoding period will be described. In the mismatch correction period, the encode signal latch circuit 833 is controlled so as to continue to hold the encode signal held in the encode period regardless of the output of the state change detection circuit 832.

  First, at timing T4a1, the output control signal φSW8 and the latch signal φTEMPLAT84a1 become high. As a result, the output signal φCK8 of the eighth-stage delay unit DU [8] held by the lower latch circuit 81 is output to the signal transmission line 85, and the pulse signal latch circuit 84a1 is used for the eighth-stage delay unit DU. Take the output signal φCK8 of [8].

  Subsequently, at timings T4a2 to T4a3, the output signal φCK1 of the first delay unit DU [1] and the output signal φCK2 of the second delay unit DU [2] are generated in the same procedure as the timings T4a1 to T4a2. It is held in the latch circuits TL8311 and TL8312 of the pulse signal latch circuit 831 of the phase data encoding unit 83.

  Subsequently, the output control signal φSW3 becomes High at timing T4a3. As a result, the output signal φCK3 of the delay unit DU [3] at the third stage is output to the signal transmission line 85. Further, the enable signal φENCEN becomes High at timing T4a3. At this time, the output signal φCK3 of the third-stage delay unit DU [3] and the output signal φCK2, 1 of the second-stage delay unit DU [2] are respectively connected to the terminals A, B, and C of the state change detection circuit 832. The output signal φCK1 of the stage delay unit DU [1] is input. As shown in FIG. 24, the output signal φCK3 of the third delay unit DU [3], the output signal φCK2 of the second delay unit DU [2], and the output signal of the first delay unit DU [1] Since φCK1 is Low, Low, and High, respectively, the output signal φDET of the state change detection circuit 832 is High according to the truth table shown in FIG.

  At this time, the output signal of the pulse signal latch circuit 84a1 and the output signal φDET of the state change detection circuit 832 are input to the terminals A and B of the mismatch detection circuit 84a2, respectively. The pulse signal latch circuit 84a1 holds the output signal φCK8 of the eighth-stage delay unit DU [8]. As shown in FIG. 24, the output signal φCK8 of the eighth-stage delay unit DU [8] is Low. is there. Further, as described above, the output signal φDET of the state change detection circuit 832 is High. The mismatch detection circuit 84a2 compares the signal obtained by inverting the output signal of the pulse signal latch circuit 84a1 with the output signal φDET of the state change detection circuit 832. Therefore, the output signal of the mismatch detection circuit 84a2 according to the truth table shown in FIG. φCOR becomes High. Since the output signal φCOR of the mismatch detection circuit 842 becomes High, the upper counter circuit 82 counts up at timing T4a3. Thereby, the mismatch between the upper bits and the lower bits is corrected.

  In the above operation, the mismatch detection circuit 84a2 uses the output signal of the state change detection circuit 832 to output the output signal φCK3 of the third-stage delay unit DU [3] and the second-stage delay unit DU [2]. A process equivalent to the process of comparing the output signal φCK2, the output signal φCK1 of the first-stage delay unit DU [1], and the output signal φCK8 of the eighth-stage delay unit DU [8] can be performed. For this reason, according to this embodiment, in addition to obtaining the same effect as that of the first embodiment, the mismatch detection circuit can be downsized. Therefore, according to the present embodiment, it is possible to provide a solid-state imaging device that is highly accurate and suppresses an increase in circuit scale.

(Third embodiment)
Next, a third embodiment of the present invention will be described. The state change detection circuit 832 according to the first embodiment includes an output signal of the delay unit DU [n], an output signal of the delay unit DU [n + 1], and an output signal of the delay unit DU [n + 2]. Although the state change between the output signal of the delay unit DU [n] and the output signal of the delay unit DU [n + 1] is detected, the state change detection circuit 832 according to the third embodiment includes the delay unit DU [ n-1] output signal, delay unit DU [n] output signal, delay unit DU [n + 1] output signal, delay unit DU [n] output signal and delay unit DU [n + 1] Detects a change in state with the output signal.

  The state change detection circuit 832 according to the third embodiment detects a state change based on the truth table shown in FIG. FIG. 14 shows the state of the signal input to terminals A, B, and C of state change detection circuit 832 and the state of the signal (output signal φDET) output from terminal O of state change detection circuit 832. . When the enable signal φENCEN input to the state change detection circuit 832 is High, the output signal φDET of the state change detection circuit 832 becomes High or Low depending on the state of the signal input to the terminals A, B, and C. . When the signals input to the terminals A, B, and C are Low, High, and High, respectively, the output signal φDET of the state change detection circuit 832 becomes High, and the state change is detected. When the enable signal φENCEN input to the state change detection circuit 832 is Low, the output signal φDET of the state change detection circuit 832 is Low regardless of the state of the signals input to the terminals A, B, and C.

  Further, the mismatch detection circuit 842 according to the third embodiment detects a mismatch based on the truth table shown in FIG. FIG. 15 shows the state of signals input to terminals A, B, C, and D of mismatch detection circuit 842 and the state of a signal (output signal φCOR) output from terminal O of mismatch detection circuit 842. . When the enable signal φCOREN input to the mismatch detection circuit 842 is High, the output signal φCOR of the mismatch detection circuit 842 becomes High or Low depending on the state of the signal input to the terminals A, B, C, and D. . When the signals input to the terminals A, B, C, and D are High, Low, High, and High, respectively, the output signal φCOR of the mismatch detection circuit 842 becomes High, and a mismatch between the upper bit and the lower bit is detected. When the enable signal φCOREN input to the mismatch detection circuit 842 is low, the output signal φCOR of the mismatch detection circuit 842 is low regardless of the state of the signal input to the terminals A, B, C, and D.

  Further, the upper counter circuit 82 according to the third embodiment receives the output signal φCOR of the mismatch detection circuit 842 and subtracts one count. Since the configuration other than the above is the same as that of the first embodiment, the description thereof is omitted.

  Next, the operation of the solid-state imaging device according to this embodiment will be described. The operations other than the encoding period and the mismatch correction period are the same as those described in the first embodiment, and thus description thereof is omitted. Hereinafter, for example, as shown in FIG. 16, a case where the phases of the output signal φCK7 and the output signal φCK8 are reversed due to the jitter of the output signals φCK1 to φCK8 of the delay circuit 71 at the holding timing of the lower latch circuit 81 will be described. . At this time, the lower latch circuit 81 holds the signal in the state shown in FIG.

  Hereinafter, the operation during the encoding period (corresponding to the timings T3 to T4 in FIG. 8) will be described with reference to FIG. First, at timing T3b1, the output control signal φSW7 and the latch signal φTEMPLAT8311 become High. As a result, the output signal φCK7 of the seventh-stage delay unit DU [7] held by the lower latch circuit 81 is output to the signal transmission line 85, and the latch circuit TL8311 of the pulse signal latch circuit 831 is also connected to the signal transmission line. The output signal φCK7 of the delay unit DU [7] from the 85th stage to the seventh stage is captured. Thereafter, the latch signal φTEMPLAT8311 becomes Low, so that the latch circuit TL8311 holds the output signal φCK7 of the seventh-stage delay unit DU [7].

Subsequently, the output control signal φSW8 and the latch signal φTEMPLAT8312 become High at the same time as the output control signal φSW7 becomes Low at the timing T3b2. At timing T3b2, the encode signal φBC [3: 1] becomes 0 ₍₁₀₎ . As a result, the output signal φCK8 of the eighth-stage delay unit DU [8] held by the lower latch circuit 81 is output to the signal transmission line 85, and the latch circuit TL8312 of the pulse signal latch circuit 831 is also connected to the signal transmission line. The output signal φCK8 of the delay unit DU [8] from the 85th stage to the eighth stage is captured. Thereafter, the latch signal φTEMPLAT8312 becomes Low, so that the latch circuit TL8312 holds the output signal φCK8 of the eighth delay unit DU [8].

  Subsequently, at the timing T3b3, the output control signal φSW1 becomes High at the same time as the output control signal φSW8 becomes Low. As a result, the output signal φCK1 of the first-stage delay unit DU [1] held by the lower latch circuit 81 is output to the signal transmission line 85. At this time, the output signals φCK1 of the first-stage delay unit DU [1] and the output signals φCK8, 7 of the eighth-stage delay unit DU [8] are respectively connected to the terminals A, B, and C of the state change detection circuit 832. The output signal φCK7 of the delay unit DU [7] at the stage is input. As shown in FIG. 17, the output signal φCK1 of the first delay unit DU [1], the output signal φCK8 of the eighth delay unit DU [8], and the output signal of the seventh delay unit DU [7] Since φCK7 is Low, High, and Low, respectively, the output signal φDET of the state change detection circuit 832 is Low according to the truth table shown in FIG.

  Thereafter, similarly, until timing T3b4, the state change detection circuit 832 outputs the output signal of the n−1th delay unit DU [n−1] and the output signal of the nth delay unit DU [n] (n + 1) The comparison processing with the output signal of the delay unit DU [n + 1] at the stage is sequentially performed. During this time, the state change detection circuit 832 does not detect a state change.

  Subsequently, at timing T3b4, the output control signal φSW5 and the latch signal φTEMPLAT8311 become High. As a result, the output signal φCK5 of the fifth-stage delay unit DU [5] held by the lower latch circuit 81 is output to the signal transmission line 85, and the latch circuit TL8311 of the pulse signal latch circuit 831 is also connected to the signal transmission line. The output signal φCK5 of the delay unit DU [5] at the fifth stage from 85 is taken in. Thereafter, when the latch signal φTEMPLAT8311 becomes Low, the latch circuit TL8311 holds the output signal φCK5 of the delay unit DU [5] at the fifth stage.

Subsequently, the output control signal φSW6 and the latch signal φTEMPLAT8312 become High at the same time as the output control signal φSW5 becomes Low at the timing T3b5. At timing T3b5, the encode signal φBC [3: 1] becomes 6 ₍₁₀₎ . As a result, the output signal φCK6 of the sixth-stage delay unit DU [6] held by the lower latch circuit 81 is output to the signal transmission line 85, and the latch circuit TL8312 of the pulse signal latch circuit 831 is output to the signal transmission line. The output signal φCK6 of the delay unit DU [6] from the 85th stage to the sixth stage is captured. Thereafter, when the latch signal φTEMPLAT8312 becomes Low, the latch circuit TL8312 holds the output signal φCK6 of the sixth-stage delay unit DU [6].

Subsequently, at the timing T3b6, the output control signal φSW7 becomes High at the same time as the output control signal φSW6 becomes Low. As a result, the output signal φCK7 of the seventh-stage delay unit DU [7] held by the lower latch circuit 81 is output to the signal transmission line 85. At this time, the output signal φCK7 of the seventh-stage delay unit DU [7] and the output signal φCK6, 5 of the sixth-stage delay unit DU [6] are respectively connected to the terminals A, B, and C of the state change detection circuit 832. The output signal φCK5 of the delay unit DU [5] at the stage is input. As shown in FIG. 17, the output signal φCK7 of the seventh delay unit DU [7], the output signal φCK6 of the sixth delay unit DU [6], and the output signal of the fifth delay unit DU [5] Since φCK5 is Low, High, and High, respectively, the output signal φDET of the state change detection circuit 832 becomes High according to the truth table shown in FIG. Since the output signal φDET of the state change detection circuit 832 is High, the encode signal latch circuit 833 takes in the encode signal φBC [3: 1] = 6 ₍₁₀₎ .

Subsequently, the output control signal φSW6 and the latch signal φTEMPLAT8311 become High at the same time as the output control signal φSW7 becomes Low at the timing T3b7. As a result, the output signal φCK6 of the sixth-stage delay unit DU [6] held by the lower latch circuit 81 is output to the signal transmission line 85, and the latch circuit TL8311 of the pulse signal latch circuit 831 is also connected to the signal transmission line. The output signal φCK6 of the delay unit DU [6] from the 85th stage to the sixth stage is captured. Further, since the enable signal φENCEN becomes Low at timing T3b7, the output signal φDET of the state change detection circuit 832 becomes Low. At this time, the encode signal latch circuit 833 holds the encode signal φBC [3: 1] = 6 ₍₁₀₎ . Thereafter, the latch signal φTEMPLAT8311 becomes Low, so that the latch circuit TL8311 holds the output signal φCK6 of the sixth-stage delay unit DU [6].

Thereafter, the same operation is performed, and during timing T3b7 to T3b8, the state change detection circuit 832 outputs the output signal φCK6 of the sixth-stage delay unit DU [6] and the output of the seventh-stage delay unit DU [7]. Comparison processing of the signal φCK7 and the output signal φCK8 of the delay unit DU [8] at the eighth stage is sequentially performed. During this time, since the state change detection circuit 832 does not detect the state change, the encode signal latch circuit 833 keeps the encode signal φBC [3: 1] = 6 ₍₁₀₎ .

  As shown in FIG. 16, the output signal φCK8 of the delay unit DU [8] transitions from Low to High at the timing immediately before the output signal φCOMP of the comparison circuit 6 is inverted (the same timing as the holding timing). ing. Therefore, the upper counter circuit 82 counts up at the timing when the output signal φCOMP of the comparison circuit 6 is inverted.

  On the other hand, by the above operation, the state change detection circuit 832 detects a state change between the output signal φCK6 of the delay unit DU [6] and the output signal φCK7 of the delay unit DU [7] in the encoding period. If the phases of the output signal φCK7 and the output signal φCK8 are not reversed at the timing when the output signal φCOMP of the comparison circuit 6 is inverted, the upper counter circuit 82 should not have counted up. For this reason, in this embodiment, a mismatch between the upper bits and the lower bits (the upper counter circuit 82 counts up by one count) occurs.

  Next, the operation in the mismatch correction period (corresponding to timings T4 to T5 in FIG. 8) will be described with reference to FIG. During the mismatch correction period, the selection signal φSEL is High, and the output signal φCOR of the mismatch detection circuit 842 is input to the upper counter circuit 82. Since it is known that a mismatch occurs when the state of the signal held by the lower latch circuit 81 is the state shown in FIG. 17, the mismatch detection circuit 842 includes the delay unit DU [8] in the eighth stage. State of output signal φCK8, output signal φCK7 of 7th delay unit DU [7], output signal φCK6 of 6th delay unit DU [6], output signal φCK5 of 5th delay unit DU [5] Is detected in a predetermined state (High, Low, High, High).

  First, at timing T4b1, the output control signal φSW5 and the latch signal φTEMPLAT8411 become High. As a result, the output signal φCK5 of the fifth-stage delay unit DU [5] held by the lower latch circuit 81 is output to the signal transmission line 85, and the latch circuit TL8411 of the pulse signal latch circuit 841 is The output signal φCK5 of the delay unit DU [5] at the fifth stage from 85 is taken in. Thereafter, when the latch signal φTEMPLAT8411 becomes Low, the latch circuit TL8411 holds the output signal φCK5 of the delay unit DU [5] at the fifth stage.

  At timings T4b2 to T4b3, the output signal φCK6 of the sixth-stage delay unit DU [6] and the output signal φCK7 of the seventh-stage delay unit DU [7] are pulse signal latched in the same procedure as the timing T4b1 to T4b2 It is held in the latch circuits TL8412 and TL8413 of the circuit 841.

  Subsequently, the output control signal φSW8 becomes High at timing T4b3. As a result, the output signal φCK8 of the eighth-stage delay unit DU [8] is output to the signal transmission line 85. At this time, the terminals A, B, C, and D of the mismatch detection circuit 842 have an output signal φCK8 of the eighth-stage delay unit DU [8], an output signal φCK7 of the seventh-stage delay unit DU [7], respectively. The output signal φCK6 of the sixth-stage delay unit DU [6] and the output signal φCK5 of the fifth-stage delay unit DU [5] are input. As shown in FIG. 17, the output signal φCK8 of the eighth delay unit DU [8], the output signal φCK7 of the seventh delay unit DU [7], and the output signal of the sixth delay unit DU [6] Since the output signal φCK5 of the delay unit DU [5] at φCK6 and the fifth stage is High, Low, High, and High, respectively, the output signal φCOR of the mismatch detection circuit 842 becomes High according to the truth table shown in FIG. Since the output signal φCOR of the mismatch detection circuit 842 becomes High, the upper counter circuit 82 counts down at timing T43. Thereby, the mismatch between the upper bits and the lower bits is corrected.

  Note that when the state of the signal held by the lower latch circuit 81 is other than the state shown in FIG. 17, no mismatch occurs, and the mismatch detection circuit 842 does not detect the mismatch. Therefore, in this case, encoding is performed in the same manner as in the prior art.

  In the above operation, the mismatch between the upper bits and the lower bits can be corrected. Therefore, according to the present embodiment, it is possible to perform A / D conversion with higher accuracy. In addition, a high-precision solid-state imaging device can be provided by arranging a high-precision A / D conversion circuit for each column.

  Note that a delay unit that outputs a signal input to the mismatch detection circuit 842 when the mismatch detection circuit 842 detects a mismatch is a delay unit that outputs a signal that is a count clock of the higher-order counter circuit 82 (in the above example, 8). If there are four consecutive delay units including at least a delay unit DU [8] in the stage and a delay unit adjacent to the delay unit (in the above example, the delay unit DU [7] in the seventh stage) Good.

  In connection with the operation of detecting the state change, by providing three signal transmission lines connected to the state change detection circuit 832, the output signal of the delay unit DU [n-1] and the delay unit DU [n] The phase data encoding unit 83 may be configured to input the output signal and the output signal of the delay unit DU [n + 1] to the state change detection circuit 832 without passing through the pulse signal latch circuit 831.

  In connection with the operation of detecting the mismatch, by providing four signal transmission lines connected to the mismatch detection circuit 842, the output signal φCK8 of the delay unit DU [8] and the output signal φCK7 of the delay unit DU [7] And the mismatch correction unit 84 so that the output signal φCK6 of the delay unit DU [6] and the output signal φCK5 of the delay unit DU [5] are input to the mismatch detection circuit 842 without going through the pulse signal latch circuit 841. It may be configured.

  As described above, the embodiments of the present invention have been described in detail with reference to the drawings. However, the specific configuration is not limited to the above-described embodiments, and includes design changes and the like without departing from the gist of the present invention. .

  1 pixel, 2 pixel array, 3 vertical scanning circuit, 4 columns circuit, 5 ramp wave generation circuit, 6 comparison circuit, 7 clock generation circuit, 8, 8a A / D conversion circuit, 9 horizontal scanning circuit, 10 control circuit, 71 , 102 Delay circuit, 81, 104 Lower latch circuit, 82, 103 Upper counter circuit, 83 Phase data encoding unit, 84, 84a Mismatch correction unit, 105 Encoder circuit, 831, 841, 84a1 Pulse signal latch circuit, 832 State change Detection circuit, 833 encode signal latch circuit, 842, 84a2 mismatch detection circuit, MUX multiplexer

Claims (3)

4 or more delay units each having a pulse input terminal and a pulse output terminal, and each pulse input terminal of the plurality of delay units is connected to one corresponding pulse output terminal of the plurality of delay units. Any one of the plurality of delay units includes a delay circuit having a second pulse input terminal to which a pulse signal is input from the outside;
A lower latch circuit for latching pulse signals output from the plurality of delay units;
An upper counter circuit that counts a clock based on a pulse signal output from one delay unit among the plurality of delay units;
Among the plurality of delay units, the three pulse signals output from three delay units that are consecutive on the path through which the pulse signal is transmitted and latched by the lower latch circuit are compared, and the state of the three pulse signals is A state change detection circuit that outputs a state change detection signal when in a predetermined first state;
An encode signal latch circuit that latches the encode signal when an encode signal having a state corresponding to a delay unit that outputs a pulse signal input to the state change detection circuit is input and the state change detection signal is input; ,
Comparing four pulse signals output from four delay units of the plurality of delay units and latched by the lower latch circuit, and when the state of the four pulse signals is a predetermined second state A mismatch detection circuit that outputs a clock for counting to the upper counter circuit, and
The delay circuit receives a pulse signal at a first timing,
The lower latch circuit latches a pulse signal output from the plurality of delay units at a second timing,
The upper counter circuit starts counting at the first timing,
The upper counter circuit ends counting at the second timing,
The four delay units include one delay unit that outputs a clock counted by the upper counter circuit, and one delay unit adjacent to the delay unit on the path, and is continuous on the path 4 Is one delay unit,
A / D conversion circuit characterized by that. The state change detection circuit outputs a signal indicating a result of comparing the three pulse signals while changing the combination of the three pulse signals.
The mismatch detection circuit is output from the state change detection circuit when a pulse signal output from three delay units of the four delay units and latched by the lower latch circuit is input to the state change detection circuit. A binary comparison circuit that compares the received signal and the pulse signal output from the remaining one of the four delay units and latched by the lower latch circuit,
An A / D conversion circuit according to claim 1. A pixel portion in which a plurality of pixels having photoelectric conversion elements are arranged in a matrix;
A reference signal generator that generates a reference signal that increases or decreases over time;
A comparison unit that starts comparison processing between the pixel signal and the reference signal at a timing related to the output of the pixel signal, and ends the comparison processing at a timing when the reference signal satisfies a predetermined condition with respect to the pixel signal; ,
An A / D conversion circuit according to claim 1,
The comparison unit, the lower latch circuit, the upper counter circuit, the state change detection circuit, the encode signal latch circuit, and the mismatch detection circuit are arranged for one column or a plurality of columns of the pixel unit,
The first timing is a timing related to the start of the comparison process,
The second timing is a timing related to the end of the comparison process.
A solid-state imaging device.

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