JP2020027935A - Semiconductor device, semiconductor substrate, and method of manufacturing semiconductor device - Google Patents

Abstract

To achieve both the voltage characteristics and the mechanical strength of a diode element.SOLUTION: A semiconductor device includes a substrate 1 having a first surface and a second surface, a concave portion 10 formed on the first surface, and a first doped region 13 formed in the substrate by performing a thermal diffusion process on the first surface having the concave portion. The shortest distance between a portion corresponding to the concave portion of the first doped region and the second surface is smaller than the shortest distance between a portion other than the concave portion of the first surface of the first doped region and the second surface.SELECTED DRAWING: Figure 2(b)

Description

The present invention relates to a semiconductor device, a substrate for manufacturing the semiconductor device, and a method for manufacturing the semiconductor device, and more particularly, to a semiconductor device having a recess, a substrate for manufacturing a semiconductor device having the recess, and the recess. The present invention relates to a method for manufacturing a semiconductor device having

One well-known technique is to drive P-doped (eg, boron and other IIIA elements) and N-doped (eg, phosphorus and other IVA elements) into the substrate by thermal diffusion treatment on both sides of the substrate, respectively. (Drive-in). Since the processing process requires a long time and a high temperature, the consumed energy is high, and this is the stage where the energy is most consumed in the whole manufacturing process of the diode element. In general, in the thermal diffusion process for driving in the dope, the temperature is usually higher than 1100 ° C. and the time is always more than 150 hours, but the drive-in depth of the P-doped or N-doped is about 150 It only reaches ~ 180 microns (μm).

In order to keep the wafer at a constant mechanical strength and avoid rupture or fracturing in the manufacturing process of the device, in the actual process of the industry, in order to avoid fracturing in the process and reducing the yield, usually 4 Inch wafers require a thickness of at least 350-400 microns.

In general, the maximum depth due to the thermal diffusion of phosphorus-doped and boron-doped is about 150 microns, and when the thickness of the wafer is greater than 300 microns, both sides of the wafer were subjected to thermal diffusion of phosphorus-doped and boron-doped, respectively. Later, the region where the dope is not driven in at the high temperature twice remains. Subtracting the diffusion depth of phosphorus and boron from the thickness of the wafer, respectively, results in the thickness or width of the twice undoped region, which is referred to as the base width.

According to the Poisson's equation, the charge concentration and the base width of the PN junction affect the voltage characteristics of the diode element. On the other hand, the region where undoping is not performed twice is the region where the resistance is the highest in the diode element, and not only maintains the voltage but also causes resistance during current conduction. In other words, the larger the base width, the higher the conduction energy loss during operation of the diode element. Therefore, when designing the device structure, it is necessary to strictly control the base width in order to control the characteristics of the forward voltage (VF) and the reverse voltage (VR) of the diode device. The well-known art generally uses epi-wafers to provide sufficient substrate thickness (mechanical strength) to provide a highly doped and lightly doped epi-semiconductor layer (epi) on a thick substrate. layer) and the base width (the thickness of the epi semiconductor layer is the sum of the doping depth and the base width that maintains the set reverse bias to maintain the voltage characteristics and the minimum resistance of the device. Is set).

One well-known method for designing a diode element having a fast recovery characteristic is to dope a carrier lifetime killer into the element and distribute it in a region near the PN junction. . When the diode device is switched from the forward bias mode to the reverse bias mode, the carrier lifetime killer doped into the device accelerates the recombination of the remaining charges (ie, electrons and holes) near the PN junction, and the current Can be shortened, that is, the reverse recovery time.

In general, the carrier lifetime killer is doped with platinum (Pt) or gold (Au) by thermal diffusion from the surface of the wafer (P-doped or N-doped surface). Since the remaining charge is mainly near the PN junction, platinum or gold doping also needs to be distributed near the PN junction to effectively accelerate the recombination of the remaining charge in the diode. Therefore, a diode element with a deeper PN junction would drive a higher-concentration carrier lifetime killer closer to the deeper PN junction to accelerate the recombination of electrons and holes without a higher temperature thermal diffusion treatment. It's not enough to make it. On the other hand, if a sufficient carrier lifetime killer cannot be driven by a sufficient depth, the reverse recovery time of the diode element cannot be effectively reduced.

In summary, in the manufacture of diode elements, the wafer substrate needs to have a certain thickness in order to maintain the mechanical strength and the yield of the process. In order to reduce the resistance of the doping, it is necessary to increase the temperature and / or time of the thermal diffusion process so that the dope is driven in to a sufficient depth, which not only consumes considerable energy in the process but also increases carrier life. Doping a time killer is also disadvantageous for shortening the reverse recovery time of the diode element. Therefore, conventionally, when designing a diode element, the above-described limitations cannot be overcome, and only a compromise can be made depending on the situation, and the flexibility of controlling the parameters of the element is poor.

In order to solve the problems in the prior art, the present invention proposes a diode element having a concave structure, and a method for manufacturing the diode element performs a thermal diffusion process after forming a concave on a wafer substrate. Therefore, in the region corresponding to the concave portion, the distance between the P-doped region and the N-doped region is reduced, and the base width of the entire device is equivalently reduced. In other words, it is possible to obtain a voltage / current characteristic equivalent to a well-known diode element having no concave portion by only the shallow P and N-doped regions, and to significantly reduce energy consumed during the thermal diffusion process. be able to.

As one embodiment of the present invention, there is provided a semiconductor device including a substrate having a first surface and a second surface and having a recess on the first surface. The semiconductor element further includes a first doped region formed in the substrate by performing a thermal diffusion process on the first surface having the concave portion, and a portion of the first doped region corresponding to the concave portion and the first doped region. The shortest distance to the second surface is made smaller than the shortest distance between a portion of the first doped region other than the concave portion of the first surface and the second surface. The semiconductor device may further include a second doped region formed in the substrate by performing a thermal diffusion process on the second surface. The recess may be, for example, a cylindrical space.

As another aspect of the present invention, a plurality of recesses including a wafer having a first surface and a second surface formed on the first surface by an etching process, and the positions of these recesses are to be manufactured. Provided is a semiconductor substrate for manufacturing a plurality of semiconductor elements further including a plurality of recesses corresponding to the positions (or specific corresponding positions) of these diode elements. In the semiconductor substrate, these concave portions may be, for example, cylindrical spaces.

Using the semiconductor substrate as described above, as another aspect of the present invention, a method for manufacturing a semiconductor element is provided, in which a first surface of the semiconductor substrate is subjected to a thermal diffusion process to form a semiconductor device. Forming the first doped region, the shortest distance between the portion corresponding to the concave portion of the first doped region and the second surface is other than the concave portion of the first surface of the first doped region. It is smaller than the shortest distance between the corresponding part and the second surface. In the method of manufacturing a semiconductor device described here, before or after forming the first doped region, a second doped region is formed in the semiconductor substrate by performing a thermal diffusion process on the second surface of the semiconductor substrate. May be. Further, after the formation of the first doped region and the second doped region, the carrier lifetime killer is driven into the semiconductor substrate by performing a thermal diffusion process on the first or second surface of the semiconductor substrate. You may make it.

Therefore, according to the present invention, at least the following unexpected effects can be achieved.
(1) The voltage / current characteristics of the diode element can be controlled more effectively and flexibly by appropriately designing the geometric structure of the recess, such as the shape, depth, width, etc. Can be adjusted more flexibly.
(2) If a concave structure is added to the conventional diode element, the forward voltage VF of the diode element can be reduced, that is, the loss of energy transport of the element can be reduced.
(3) Since the diode element having the concave structure can achieve the voltage / current characteristics equivalent to those of the diode element having no concave structure when the depths of the P and N dopings are relatively shallow, The energy consumption of the equipment during the heat diffusion process can be reduced, the time required for the heat diffusion process can be reduced, and the production efficiency can be improved.
(4) If the concave structure is applied to the high-speed recovery of a diode, the PN junction depth is relatively shallow, and the drive-in depth required for the carrier lifetime killer is also reduced. The time can be reduced, the temperature can be reduced, and the reverse recovery time of the diode element can be reduced.
(5) Even if the concave structure is added, sufficient mechanical strength of the wafer is maintained, and a situation in which the wafer is broken in the process is avoided. In other words, it is not necessary to sacrifice the mechanical strength and the process yield while realizing the above-mentioned effect. When a PN diode element having a concave structure performs a glass passivation process (GPP), since the depth of a groove to be formed is relatively shallow, the mechanical strength of the wafer and the process yield are relatively reduced. It can also be improved.

Schematic diagram of a partial structure of a known diode element Schematic diagram of a semiconductor substrate having a concave portion according to the present invention. Schematic diagram of a partial structure of a diode element having a concave portion according to the present invention. Schematic view of a partial structure of a diode element having two concave portions according to the present invention. Schematic view of a wafer having a plurality of concave portions according to the present invention. Schematic diagram of a prior art diode element structure used to perform computer simulation Schematic diagram of the diode element structure of the present invention used for performing computer simulation Schematic diagram of another prior art diode element structure used to perform computer simulation Computer simulation results of forward voltage by the structure shown in Fig. 4 (a), Fig. 4 (b) and Fig. 4 (c) Computer simulation results of reverse voltage by the structure shown in Fig. 4 (a), Fig. 4 (b) and Fig. 4 (c) Schematic diagram in which drive-in of a carrier lifetime killer is performed by the diode structure of the present invention Schematic diagram in which glass passivation processing is performed by the diode structure of the present invention

Specific embodiments

With reference to the drawings, a specific embodiment of the present invention will be described as follows. The structures and geometric relationships shown in the drawings are for illustrative purposes only, and do not represent the actual structure or geometry of the device or element, and are also not intended to limit all configurations of the device or element. Absent. For example, P and N doped regions formed in a semiconductor substrate by a thermal diffusion process do not have a uniform distribution of doping concentration and, in fact, have no clear boundaries with undoped regions in the substrate. However, by setting the critical value of the doping concentration, the boundary of the doped region can be limited. Similarly, since the geometry or structure of the doped region is difficult to describe in text, it is more appropriate to limit the manufacturing method (eg, thermal diffusion treatment) when describing the doped region (eg, in the claims). Because the distribution of the dope depends on conditions such as the properties of the dope and the substrate material, the diffusion temperature and the time, which is well known and common knowledge. Those having ordinary knowledge in the art to which the present invention pertains can easily infer, from materials and process conditions, the element structure or geometry to be formed accordingly.

FIG. 1 is a partial schematic view of a conventional diode element. The semiconductor substrate 1 may be, for example, a silicon (Si) wafer, and a doped or undoped silicon wafer may be used. . One of the conventional methods for manufacturing a diode element is to perform P and N doping on two surfaces of the semiconductor substrate 1 by thermal diffusion processing, respectively, to perform the first doped region 11 and the second doped region 12 shown in FIG. Is formed. As described above, in order to maintain the yield and make the distance (base width) between the P and N doped regions sufficiently small, it is necessary to drive the P and N doped regions to a sufficient depth. That is, a large diffusion depth is required to form a diode element having a deep junction. On the other hand, FIG. 2 is a schematic view of the diode element proposed in the present invention and a method of manufacturing the same. Unlike the conventional diode structure of FIG. 1, the present invention forms a recess 10 on a semiconductor substrate 1 as shown in FIG. Next, as shown in FIG. 2B, P and N-doped thermal diffusion processes are performed on the two surfaces of the semiconductor substrate 1 to form a first doped region 13 and a second doped region 14.

As shown in FIG. 3, in the actual process, the substrate having the concave portions 10 is formed by etching the wafer 2 to form a plurality of concave portions 20 and then performing another subsequent process. Thus, these recesses 20 can correspond to each position of the die.

As can be seen from FIG. 2B, the structural feature of the diode of the present invention mainly lies in the distribution of the first doped region 13. Since the thermal diffusion process is performed after forming the concave portion 10, the first doped region 13 and the second doped region 14 have a close distance D2 at a portion corresponding to the concave portion, and D2 is It is smaller than the distance D1 in a portion corresponding to the portion other than the concave portion of the 2-doped region 14. In other words, a part of the distance between the first doped region 13 and the second doped region 14 can be controlled by the geometric structure of the concave portion 10. It should be noted that the cross section of the recess 10 shown in FIG. 2 is rectangular, and the corresponding three-dimensional structure may be a cylindrical space or a rectangular parallelepiped space. Further, the rectangular cross section is merely one embodiment of the concave portion 10 of the present invention, and the cross sectional shape is not limited to a rectangle, and may be, for example, an inverted triangle or an inverted semicircle. In addition to the shape, its geometric dimensions (eg, depth, width) can be appropriately selected according to needs, and those having ordinary knowledge in the art to which the present invention pertains can design properly themselves. it can. Although FIG. 2 only discloses one in which one recess 10 is formed on one surface of the semiconductor substrate 1, two or more recesses are formed on one surface of one diode element (die). Alternatively, the thermal diffusion treatment of the dope may be performed after forming the concave portions on both surfaces. For example, when the lateral dimension (horizontal direction in FIG. 2 (b)) of the diode element is large, if a single concave portion cannot be formed to satisfy the desired voltage characteristics and mechanical strength simultaneously, More than one recess can be formed on a single die, and each recess can have the same or different geometry. This increases design flexibility and provides voltage characteristics and mechanical strength that are usually incompatible with a single recess. FIG. 2 (c) shows a schematic diagram of a structure having two recesses in a single diode element, where the two recesses may be spatially symmetric or asymmetric depending on the needs of carrier conduction or recombination. The two concave portions may have the same or different shapes and geometric structures (the first concave portion 101 and the second concave portion, like the cross section shown in FIG. 2C). The cross section of the concave portion 102 is rectangular, but may have different widths, and the two concave portions may be provided asymmetrically with respect to the horizontal center point in FIG. Looking down from above, the first concave portion 101 and the second concave portion 102 may have specific distributions having different sizes.)

In the embodiment of the present invention, the formation of the concave portion and the thermal diffusion treatment of the dope are both well-known semiconductor manufacturing technologies, and the technology to which the present invention belongs without detailed description of the process and parameters in this specification. The person having ordinary knowledge in the field of the above should be able to realize based on well-known technology. For example, for a PN diode, the recess can be selectively formed on a P-doped surface or an N-doped surface depending on device and process characteristics.

The diode element having the concave portion proposed in the present invention can change the distribution of at least one doped region by forming the concave portion on the substrate and change the characteristics of the diode element. Hereinafter, the effect of improving the characteristics of the diode element of the present invention will be described by a computer simulation method, taking the voltage / current characteristics as an example. FIGS. 4A to 4C show element structures used for performing a computer simulation. FIG. 4A shows a known diode element structure. FIG. 4B shows a diode element structure having a concave portion according to the present invention, and the temperature and time of the thermal diffusion treatment of the dope are the same as those in FIG. 4A. FIG. 4 (c) also shows a diode element structure of a well-known technology, but uses a higher temperature and longer time thermal diffusion process of doping than in FIG. 4 (a), so that FIG. The diffusion depth of the dope increases, and the base width decreases. 4A to 4C, the units on the horizontal axis and the vertical axis are all microns, and the doping polarity of each element is as shown in the drawings. FIG. 5 shows forward bias characteristics by computer simulation based on the three structures shown in FIGS. 4 (a) to 4 (c). As can be seen from FIG. 5, the device structure of the present invention (FIG. 4 (b)) has a lower forward voltage VF (at forward bias) than the known diode device (FIG. 4 (a)) using the same doped diffusion conditions. ), Can be greatly reduced. Even if the diffusion depth of the dope (FIG. 4 (c)) in the known diode element is greatly increased, its VF is still higher than that of the present invention. In other words, the diode element having the concave portion of the present invention can obtain a lower VF under the same doping diffusion condition (corresponding to the same energy consumption). Further, according to the known technology, even if the diffusion depth of the dope becomes deeper (corresponding to more energy consumption), the effect of reducing the VF still does not reach the present invention. On the other hand, FIG. 6 shows that the voltage / current characteristics of the device structure of the present invention appearing at the time of reverse bias are not clearly different from those of the known art. Based on the same principle, a diode element including two or more recesses (for example, the one shown in FIG. 2 (c)) has similar voltage / current characteristics to those of ordinary skill in the art to which the present invention pertains. And it can be expected that the plurality of recesses can further increase design flexibility, for example, control of forward current density (current density is closely related to conduction resistance), or The mechanical strength of a specific portion of the die is improved by designing a small concave portion (or having no concave portion partially), but not limited to this.

As can be seen from the description in the preceding paragraph, the diode device having the concave portion of the present invention can certainly improve (or at least change) the characteristics of the device. Therefore, in the actual device design process, using computer simulation technology, the concave structure of the present invention can be changed in consideration of the application field, expected device characteristics, process capability, cost, etc., and the purpose can be effectively improved. The parameters of the device structure to be achieved and the process conditions can be obtained. In other words, those having ordinary skill in the art to which the present invention pertains can determine the best or optimal device structure and process condition parameters by simple attempts. In the actual process, technologies such as etching, thermal diffusion processing, measurement of device structure and characteristics are all sufficiently mature, so that those having ordinary knowledge in the art to which the present invention pertains should be able to make simple attempts. Alone can realize the structure of the present invention and verify its effects.

In addition to the voltage / current characteristics, other effects of the diode element having a concave portion according to the present invention will be further described below.

In order to provide diode devices with fast recovery characteristics, one well known procedure is to dope a carrier lifetime killer (eg, gold or platinum) near the PN junction of the device. When doping of the carrier lifetime killer is performed by a thermal diffusion process on the diode element structure having the concave portion illustrated in FIG. 2B, the structure illustrated in FIG. 7 can be formed. The upper and lower figures respectively show the drive-in depth 15 diffused from two surfaces. The beneficial effect of the diode element of the present invention on doping of the carrier lifetime killer has at least two aspects. First, the concave structure on the surface allows the carrier lifetime killer to be driven more easily to the ideal depth. Next, a diode element having a concave structure can employ a shallow PN-doped region, and accordingly, the carrier lifetime killer may be driven to a relatively shallow depth. The fact that the concave structure can be formed at a specific region and a specific depth in the die range also contributes to doping the carrier lifetime killer at a specific position to generate a desired specific die reverse recovery time and waveform. Therefore, referring to the above description, according to the present invention, by forming the recess on the diode element, the conditions for forming the recess according to needs (for example, forming on the surface of P or N dope, In addition to the quantity, the geometrical structure of each concave portion, etc., it is possible to control the doping conditions of the carrier lifetime killer (for example, from the surface having the concave portion or not having the concave portion). Diffusion, diffusion from a P or N-doped surface, diffusion temperature and time, etc., are not limited thereto, and desired device characteristics can be realized.

In the well-known diode manufacturing process, the glass passivation process (GPP) mainly including forming grooves and burying glass to form an element structure as shown in FIG. Good. The depth of the groove 16 for embedding glass is affected by the depth of the second doped region 14. As described above, in the diode element having a concave portion proposed in the present invention, the depth of the second doped region 14 can be reduced to reduce the depth required for the groove 16. In the process of glass passivation, if a shallow groove is formed, the yield of the process can be relatively improved.In addition, when a groove is formed by wet etching, a deep groove can easily form a beak on the top of the groove. Therefore, the glass adhesion or coating effect is likely to be poor. Shallow grooves can avoid these problems.

The foregoing is merely illustrative of the embodiments and advantages of the present invention, and is not an exhaustive list of all possible variations. According to the concept of the present invention, a person having ordinary knowledge in the technical field to which the present invention pertains can make various modifications included in the concept of the present invention by modifying the content based on the contents disclosed in the present specification. Specific changes can be realized. The scope of the rights asserted by the applicant is as set forth in the claims, and the meaning and equivalent scope of the language of each claim are included in the scope of the patent.

1: Semiconductor substrate
2: Wafer
10: recess
11: First doped region
12: Second doped region
13: 1st doped region
14: Second doped region
15: Carrier lifetime killer drive-in depth
16: groove
20: recess
101: 1st recess
102: 2nd recess
D1: Distance
D2: Distance

Claims (10)

A substrate having a first surface and a second surface,
A first recess formed on the first surface,
A first doped region formed in the substrate by performing a thermal diffusion process on the first surface having the first concave portion,
Including
The shortest distance between the portion corresponding to the first concave portion of the first doped region and the second surface is a portion corresponding to a portion other than the first concave portion of the first surface of the first doped region and the second surface. Semiconductor element smaller than the shortest distance between 2. The semiconductor device according to claim 1, further comprising a second doped region formed in the substrate by performing a thermal diffusion process on the second surface. 2. The semiconductor device according to claim 1, wherein the first doped region is a P-doped region or an N-doped region. 2. The semiconductor device according to claim 1, further comprising a second concave portion having the same or different geometric structure as the first concave portion and formed on the first surface symmetrically or asymmetrically with the first concave portion. A wafer having a first surface and a second surface,
A plurality of first recesses formed on the first surface by the etching process, the positions of these plurality of first recesses are a plurality of first recesses corresponding to the positions of these diode elements to be manufactured. And a semiconductor substrate for manufacturing a plurality of semiconductor elements. A plurality of second recesses formed on the first surface simultaneously with the first recesses by the etching process, and the positions of the plurality of second recesses correspond to the positions of these diode elements to be manufactured. 6. The semiconductor substrate for manufacturing a plurality of semiconductor elements according to claim 5, further comprising a plurality of second recesses. 6. The semiconductor substrate for manufacturing a plurality of semiconductor elements according to claim 5, wherein the first concave portions are cylindrical or rectangular parallelepiped spaces. A method for manufacturing a semiconductor device using the semiconductor substrate according to claim 5,
Including performing a thermal diffusion process on the first surface of the semiconductor substrate to form a first doped region in the semiconductor substrate,
The shortest distance between the portion corresponding to these first recesses of the first doped region and the second surface is the same as the portion of the first surface of the first doped region corresponding to other than these first recesses and the second surface. (2) A method for manufacturing a semiconductor element smaller than the shortest distance from the surface. Before or after forming the first doped region, further comprising forming a second doped region in the semiconductor substrate by performing a thermal diffusion process on the second surface of the semiconductor substrate. A method for manufacturing a semiconductor device. After forming the first doped region and the second doped region, a carrier lifetime killer is driven into the semiconductor substrate by performing a thermal diffusion process on the first or second surface of the semiconductor substrate. 10. The method for manufacturing a semiconductor device according to claim 8, further comprising the step of:

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