JP2018198505A - Gate driving device - Google Patents

Abstract

To provide a gate drive device capable of turning off a semiconductor device without destruction and with reduced loss in control of an off operation. An IGBT is connected in parallel, and a gate voltage is supplied from a gate driving device. The gate drive device 3 includes gate cutoff circuits 4, 5, gate-off circuits 6, 7, a normal gate-off circuit 8, a drive control unit 9, and a detection circuit 10. The gate-off circuits 6 and 7 form a high-speed gate-off path and a gate-off fixed path for turning off the IGBTs 1 and 2, respectively. When turning off the IGBT 2 with both the IGBTs 1 and 2 turned on, the gate cutoff circuit 5 is turned off, and then the gate off circuit 7 is operated. After the IGBT 2 is turned off in the high-speed gate-off path, it is kept off in the gate-off fixed path. When the IGBTs 1 and 2 are turned off at the same time, the gates are normally turned off slowly by the gate-off circuit 8. [Selection diagram] Fig. 1

Description

  The present invention relates to a gate driving device for controlling off of a gate control type semiconductor element.

  As a gate drive type semiconductor element, for example, in a gate drive device for driving a gate such as an IGBT (Insulated Gate Bipolar Transistor), a structure in which a plurality of semiconductor power elements are connected in parallel is used to supply power to a load. is there. This is because the on-resistance loss can be reduced by lowering the on-resistance of the semiconductor power device by connecting in parallel when a large current flows.

  However, when a plurality of semiconductor power devices are connected in parallel and driven, the switching loss increases in proportion to the number of the semiconductor power devices, and particularly when switching is performed with a high collector voltage. For this reason, there is a problem that increasing the number of semiconductor power elements connected in parallel to cause a large current to flow increases the loss.

JP 2014-230307 A

  The present invention has been made in consideration of the above-described circumstances, and the object of the present invention is to prevent loss of the semiconductor device without destroying the semiconductor device in the control of the off operation in a configuration in which a plurality of gate-driven semiconductor devices are used in parallel. Another object of the present invention is to provide a gate drive device that can be turned off in a reduced state.

  The gate driving device according to claim 1 controls on / off driving of a plurality of gate-driven semiconductor elements connected in parallel, and is switched according to an on-operation based on currents flowing through the plurality of semiconductor elements. In a gate driving device for setting one that maintains an ON state among the plurality of semiconductor elements under a condition that loss and ON loss are reduced, a normal gate-off circuit that turns off all of the plurality of semiconductor elements, and the plurality of semiconductor elements A high-speed gate-off circuit that turns off some of the semiconductor devices in an on-state, and the normal gate-off circuit is configured so that a surge current generated when the plurality of semiconductor elements are turned off is less than a breakdown tolerance. The high-speed gate-off circuit is configured to be turned off by changing the gate voltage at a low speed. Those portions of the device, is configured to turn off by changing the gate voltage at a speed higher than the normal gate-off circuit.

  By adopting the above configuration, in the on operation, the on state of the plurality of semiconductor elements is maintained on the condition that the switching loss and the on loss due to the on operation are reduced based on the current flowing through the plurality of semiconductor elements. Set things and turn off others. In the off operation, when a plurality of semiconductor elements are simultaneously turned off, a normal gate off circuit is formed by a normal gate off circuit to turn off the semiconductor elements. In addition, when turning off some of the plurality of semiconductor elements in a state where an on-state exists, a high-speed gate-off circuit is formed by a high-speed gate-off circuit to turn off the target one.

  As a result, when all of the semiconductor elements are turned off, when the off operation is normally performed using the gate-off circuit, the gate voltage is changed at a low speed so that the surge current generated at the time of turning off is equal to or lower than the breakdown tolerance. Can do. Also, when turning off some of the plurality of semiconductor elements using a high-speed gate-off circuit when some of them are turned on, there is an on-state. Since the generated surge current is small, it can be turned off at high speed.

Electrical configuration diagram showing one embodiment Diagram showing the flow of on-time processing Diagram showing the flow of processing when off Time chart showing changes in signal, current and voltage of each part (Part 1) Time chart showing changes in signal, current and voltage of each part (Part 2)

Hereinafter, an embodiment of the present invention will be described with reference to FIGS.
In this embodiment, as shown in FIG. 1, two IGBTs (Insulated Gate Bipolar Transistors) 1 and IGBTs 2 are used as a plurality of gate-controlled semiconductor elements. The IGBT 1 has a sense emitter SE1 for monitoring current in addition to the collector C1, the emitter E1, and the gate G1. Similarly, the IGBT 2 has a sense emitter SE2 for monitoring the device current in addition to the collector C2, the emitter E2, and the gate G2. IGBT1 and IGBT2 are provided in a power supply path to a load (not shown), and have a parallel drive system configuration in which the collectors C1 and C2 are connected in common and the emitters E1 and E2 are connected in common.

  The two IGBTs 1 and 2 are controlled to be turned on and off by the gate driving device 3 based on a gate switching signal SG given from the outside. The gate driving device 3 includes a first gate cutoff circuit 4, a second gate cutoff circuit 5, a first gate off circuit 6, a second gate off circuit 7, a normal gate off circuit 8, a drive control unit 9, and a detection circuit 10.

  The first gate cutoff circuit 4 includes a P-channel type MOSFET 4a, the source of the MOSFET 4a is connected to the DC power supply VD, and the drain is connected to the terminal A through the resistor 4b. The gate of the MOSFET 4a is supplied with a drive signal from the drive control unit 9 via the driver 4c. The terminal A is connected to the gate of the IGBT 1 and outputs a gate drive voltage VG1.

  The second gate cutoff circuit 5 includes a P-channel type MOSFET 5a, the source of the MOSFET 5a is connected to the DC power supply VD, and the drain is connected to the terminal B via the resistor 5b. The gate of the MOSFET 5a is supplied with a drive signal from the drive control unit 9 via the driver 5c. The terminal B is connected to the gate of the IGBT 2 and outputs a gate drive voltage VG2.

  The first gate-off circuit 6 includes an N-channel MOSFET 6a as an off MOSFET, the drain of the MOSFET 6a is connected to the terminal A, and the source is connected to the ground. A drive signal is given to the gate of the MOSFET 6a from the drive control unit 9 via the driver 6b. The first gate-off circuit 6 is configured to have a gate-off fixing circuit and a high-speed gate-off circuit for the IGBT 1, and the MOSFET 6 a is shared.

  A first gate-off fixed path is formed by the MOSFET 6a and the driver 6b. The gate of the MOSFET 6a is supplied with a drive signal from the drive control unit 9 via the first high-speed off unit 6c. The first high-speed off unit 6c gives a drive signal from the driver 6d to the gate of the MOSFET 6a through the gate resistor 6e. A first high-speed gate-off path is formed by the MOSFET 6a and the first high-speed off portion 6c.

  The second gate off circuit 7 includes an N-channel type MOSFET 7a as an off MOSFET, the drain of the MOSFET 7a is connected to the terminal B, and the source is connected to the ground. The second gate-off circuit 7 combines a gate-off fixing circuit and a high-speed gate-off circuit for the IGBT 2, and the MOSFET 7a is shared.

  The gate of the MOSFET 7a is supplied with a drive signal from the drive control unit 9 via the driver 7b. MOSFET 7a and driver 7b constitute a second gate-off fixed circuit. The gate of the MOSFET 7a is supplied with a drive signal from the drive control unit 9 via the second high-speed off unit 7c. The second high-speed off unit 7c gives a drive signal from the driver 7d to the gate of the MOSFET 7a through the gate resistor 7e. The MOSFET 7a and the second high-speed off unit 7c constitute a second high-speed gate-off circuit.

  The normal gate-off circuit 8 that forms the normal gate-off path includes an N-channel MOSFET 8a, the drain of the MOSFET 8a is connected to the terminal C through the resistor 8b, and the source is connected to the ground. A drive signal is given to the gate of the MOSFET 8a from the drive control unit 9 via the driver 8c. The gates of the IGBT 1 and the IGBT 2 are connected to the terminal C through the backflow prevention unit 11. The backflow prevention unit 11 includes two backflow prevention diodes 11a and 11b, and prevents backflow of current between the gates of the IGBT1 and the IGBT2.

  The drive control unit 9 controls the driving of the IGBT 1 and the IGBT 2 based on the gate switching signal SG given from the outside and the detection signal from the detection circuit 10. The drive control unit 9 controls the first gate cutoff circuit 4, the second gate cutoff circuit 5, the first gate off circuit 6, the second gate off circuit 7, and the normal gate off circuit 8 as described later by a control circuit provided therein. A signal is given to control the drive of IGBT1 and IGBT2.

  The detection circuit 10 receives the gate voltages VG1 and VG2 of the IGBT1 and IGBT2. The detection circuit 10 receives the voltages Vse1 and Vse2 of the sense emitters of the IGBT1 and IGBT2. The detection circuit 10 converts these signals into digital signals and outputs them to the drive control unit 9. The sense voltages Vse1 and Vse2 are voltage signals corresponding to the device currents Ic1 and Ic2 of the IGBT1 and IGBT2.

Next, the operation of the above configuration will be described with reference to FIGS.
In this embodiment, when driving and controlling the IGBT 1 and IGBT 2, the two IGBT 1 and IGBT 2 are simultaneously turned on by the drive control unit 9 when the gate switching signal SG given from the outside becomes a high level, that is, an on operation instruction. Let

  Thereafter, when the device currents Ic1 and Ic2 flowing in the IGBT1 and the IGBT2 are both between the lower limit value Ithd and the upper limit value Ithu, the drive control unit 9 drives the two IGBT1 and IGBT2 as they are. State.

  Further, when the level of the device currents Ic1 and Ic2 flowing through the IGBT 1 and IGBT 2 in the on state is smaller than the lower limit value Ithd, the drive control unit 9 turns off one of them to cause loss such as switching loss and on-resistance loss. Control to minimize. At this time, for example, when the IGBT 2 is turned off, the element current Ic2 flowing through the IGBT 2 is added to the element current Ic1 of the IGBT 1 to increase, but the element current Ic1 is set to fall within the upper limit value Ithu. Has been.

  As described above, when the IGBT1 and IGBT2 are driven and controlled, when the element current Ic1 (Ic2) of one IGBT 1 or IGBT2 in operation is between the upper limit value Ithu and the lower limit value Ithd, it is kept in the ON state. The If both the IGBT1 and IGBT2 are in the on-operation and the device current Ic1 (Ic2) of the IGBT1 or IGBT2 is smaller than the lower limit value Ithd, one of them is turned off. Further, when one of the two IGBTs 1 and 2 is turned on and the element current Ic1 (Ic2) exceeds the upper limit value Ithu, the one in the off state is also turned on.

  In the case described above, in the operation of turning off one of the IGBTs, if the IGBT 2 is always turned off, the life of the IGBT 1 is reduced. Therefore, the drive control unit 9 performs control so that, for example, the IGBT 1 and the IGBT 2 are alternately turned off so that the lifetime is averaged when one of them is turned off.

  Next, the above operation will be described with reference to the flowchart of FIG. First, a case where the IGBT1 and the IGBT2 are turned on will be described. When a high-level gate switching signal SG indicating an on operation instruction is input from the outside in step A1, the drive control unit 9 proceeds to step A2 and drives IGBT1 and IGBT2 on. In this case, the drive controller 9 outputs a low-level drive signal to the first gate cutoff circuit 3 and the second gate cutoff circuit 4 so as to turn on the P-channel type MOSFETs 3a and 4a.

  As a result, the gate voltages VG1 and VG2 are applied to the gates of the IGBT1 and IGBT2, respectively, so that they are turned on, and the device currents Ic1 and Ic2 flow respectively. At this time, a sense current also flows through the sense emitters SE of the IGBT1 and IGBT2, so that sense voltages Vse1 and Vse2 corresponding to the element currents Ic1 and Ic2 are generated.

  The drive control unit 9 proceeds to step A3, and among the collector currents Ic1 and Ic2 of the IGBT1 and IGBT2 input from the detection circuit 10, is the element current Ic1 level of the IGBT1 that is the target of the holding state being lower than the lower limit value Ithd? Judge whether or not. Here, when the element current Ic1 of the IGBT 1 is greater than or equal to the lower limit value Ithd, the drive control unit 9 becomes NO and maintains the on-state of the IGBT 1 and IGBT 2 as they are.

  On the other hand, when the device current Ic1 of the IGBT 1 is lower than the lower limit value Ithd, the drive control unit 9 becomes YES in Step A3, proceeds to Step A4, and the second gate-off circuit 7 sets the second high-speed gate-off path. Then, the IGBT 2 is turned off. In this case, the drive control unit 9 first turns off the second gate cutoff circuit 5 to cut off the gate voltage VG2 of the IGBT 2. Subsequently, the drive control unit 9 drives the second high-speed off unit 7c of the second gate off circuit 7 to turn on the MOSFET 7a.

  At this time, the MOSFET 7a is supplied with a drive signal from the driver 7d to the gate via the resistor 7e. As a result, the MOSFET 7a can be turned on at high speed while avoiding breakage due to a rapid change in the gate voltage, and can turn off the IGBT 2 quickly.

  Thereafter, in step A5, the drive control unit 9 monitors the gate voltage Vg2 of the IGBT 2 that has been turned off, and determines whether or not the threshold voltage Vth has decreased. If YES in step A5, the drive control unit 9 proceeds to step A6, drives the second gate-off circuit 7 to form a gate-off fixed path, and controls the IGBT 2 to be in an off-fixed state.

  Here, the drive control unit 9 outputs an on drive signal to the driver 7b of the second gate off circuit 7 to hold the gate voltage of the MOSFET 7a to be surely in a high state, and to fix the off state.

  As described above, the drive control unit 9 holds the two ON states in accordance with the level of the element current Ic1, that is, the level of the load current, after simultaneously driving the two IGBTs 1 and 2 on. It controls whether IGBT 2 is turned off and only IGBT 1 is kept on.

  In the above control, when the load current is reduced during the on-drive, even if the drive control unit 9 continues to keep both the two IGBTs 1 and 2 on, the above-described control is performed. Steps A3 to A6 can be performed. Of the two IGBTs 1 and 2, it is assumed that the on state of the IGBT 1 is held in step A3. However, in the next operation, the IGBT 2 is set to hold the on state of the IGBT 2. This is to average the lifetimes of IGBT1 and IGBT2.

Next, with reference to FIG. 3, the operation when the external gate switching signal SG changes to the off state will be described.
In the off process, as shown in FIG. 3, when the gate control signal SG for the off operation is given from the outside, the drive controller 9 becomes YES in Step B1 and proceeds to Step B2. The drive control unit 9 outputs an off drive signal to the driver 8c of the normal gate off circuit 8 to turn on the MOSFET 8a. Thereby, the gates of IGBT1 and IGBT2 are pulled to the ground via the diodes 11a and 11b, the resistor 8b, and the MOSFET 8a, and are shifted to the off state.

  When the gate voltages Vg1 and Vg2 decrease and fall below the threshold value Vth, the drive control unit 9 becomes YES in Step B3, proceeds to Step B4, and drives the first gate-off circuit 6 and the second gate-off circuit 7. Thus, an off-fixed path is formed, and IGBT1 and IGBT2 are operated to be fixed off. In this case, the above-described control operation is performed regardless of whether both IGBT1 and IGBT2 are in the on state or only one is in the on state.

  FIG. 4 is a time chart of the operation when the off-state gate switching signal SG is input at time t2 when only one of them is in the on-state when performing the above-described off-time processing. In this case, prior to this, for example, the IGBT 2 is turned off by the drive control unit 9 at time t0.

  In the off operation of the IGBT 2, the drive control unit 9 turns off the second gate cut-off circuit 5 to turn off the MOSFET 5a to cut off the gate voltage VG2. Subsequently, the drive control unit 9 drives the second high speed off unit 7c of the second gate off circuit 7 to turn on the MOSFET 7a through the gate resistor 7e. As a result, as shown in FIG. 4D, the second high-speed gate-off path is formed by the second gate-off circuit 7.

  In this state, since the IGBT 1 is in the on operation, the generation of surge current can be reduced in the off operation of the IGBT 2, so that the off operation can be performed at high speed. Then, as shown in FIG. 4B, when the gate voltage Vg2 of the IGBT 2 decreases to the threshold voltage Vth at time t1, the drive control unit 9 outputs a drive signal to the driver 7b to turn on the MOSFET 7a. Then, as shown in FIG. 4 (f), the second gate off circuit 7 forms a second gate off fixing path to fix the IGBT 2 off.

  Since it operates as described above, the IGBT 2 is held in the off state as shown in FIG. 4 (i), and the IGBT 1 is held in the on state as shown in FIG. 4 (h). Thereafter, as shown in FIG. 4A, when a low-level gate switching signal SG for instructing an off operation is given at time t2, the drive control unit 9 drives the normal gate off circuit 8 to turn off the IGBT 1. . At this time, the MOSFET 8a of the normal gate-off circuit 8 forms a normal gate-off path at the gate of the IGBT 1 through the resistor 8b and the reverse blocking diode 11a as shown in FIG. 4 (g).

  Thereby, as shown in FIG. 4B, the gate voltage Vg1 slowly decreases in the IGBT 1, and the element current Ic1 also slowly decreases as the gate voltage Vg1 decreases as shown in FIG. 4H. Thereafter, as shown in FIG. 4B, when the gate voltage Vg1 of the IGBT 1 falls below the threshold voltage Vth at time t3, the MOSFET 6a is turned on by the first gate-off circuit 6 as shown in FIG. The first gate-off fixed path is formed by the operation, and the IGBT 1 is fixed in the off state. Further, as shown in FIG. 4C, the first high-speed off unit 6c is also driven simultaneously at time t3.

  In the case of the above operation, when the IGBT 1 is turned off while the two IGBTs 1 and 2 are turned on, the drive control unit 9 causes the first gate cutoff circuit 4 to be turned off. Subsequently, the first high-speed off portion 6c of the first gate-off circuit 6 is driven to form a first high-speed gate-off path, and the IGBT 1 can be turned off at high speed with less generation of surge current. When the gate voltage Vg1 of the IGBT 1 reaches the threshold voltage Vth, the drive control unit 9 outputs a drive signal to the driver 6b and forms a first gate off fixed path by the first gate off circuit 6 to turn off the IGBT 1. Fix it.

  Thereafter, the operation of turning off the IGBT 2 by the application of the low-level gate switching signal SG for instructing the off operation is performed by operating the normal gate off circuit 8 by the drive control unit 9 in the same manner as described above. The voltage Vg2 is slowly lowered, the device current Ic2 is also slowly reduced and turned off. Thereafter, when the gate voltage Vg2 of the IGBT 2 falls below the threshold voltage Vth, a second gate off fixing path is formed by the second gate off circuit 7, and the IGBT 2 is fixed in the off state.

  FIG. 5 is a time chart of the operation when the gate switching signal SG of the off operation is given from the state where both of the two IGBTs 1 and IGBT2 are turned on when the above-described processing at the off time is performed.

  In this case, as shown in FIG. 5 (a), when a gate switching signal SG for OFF operation is input at time t0, the drive control unit 9 drives the normal gate-off circuit 8 to perform FIG. 5 (g). A normal gate-off path is formed as shown in FIG. Thereby, both IGBT1 and IGBT2 shift to an OFF state. At this time, in the IGBT1 and IGBT2, the gate voltages Vg1 and Vg2 slowly decrease as shown in FIG. 5A, and the device currents Ic1 and Ic2 also decrease slowly as shown in FIGS. 5H and 5I. To do. After that, as shown in FIG. 5B, when the gate voltages Vg1 and Vg2 of the IGBT1 and IGBT2 fall below the threshold voltage Vth at time t1, as shown in FIGS. A gate-off fixed path is formed by the first gate-off circuit 6 and the second gate-off circuit 7, and the IGBT1 and the IGBT2 are fixed in the off state. As shown in FIGS. 5C and 5D, the first and second high-speed off units 6c and 7c are simultaneously driven at time t1.

  According to the present embodiment as described above, the first and second gate-off circuits 6 and 7 are provided and the normal gate-off circuit 8 is provided, and the drive control unit is configured to drive and control the two IGBTs 1 and 2 connected in parallel. 9 is used to control the off operation.

  As a result, in the operation of turning off one of the two IGBTs 1 and 2 while the two IGBTs 1 and 2 are both turned on, either of the first and second gate-off circuits 6 and 7 is used to form a high-speed gate-off path and quickly turn it off. Thereafter, an off-fixing path is formed and the off state is maintained, so that the off operation can be quickly performed.

  When the gate switching signal SG is an off operation instruction, the normal gate off circuit 8 forms a normal gate off path for the two IGBTs 1 and 2 that are in the on state to be turned off. As a result, the device can be reliably turned off while preventing element destruction due to the generation of a surge current.

  Further, the configuration of the first gate-off circuit 6 (second gate-off circuit 7) is such that an N-channel type MOSFET 6a (7a) as an off-MOSFET is commonly driven by the high-speed off unit 6c (7c) and the driver 6b (7b). Since it is set as the structure which carries out, it can achieve by the structure which reduced the number of elements with respect to the structure which provides an off MOSFET separately, and can attain space saving.

(Other embodiments)
In addition, this invention is not limited only to embodiment mentioned above, In the range which does not deviate from the summary, it is applicable to various embodiment, For example, it can deform | transform or expand as follows.

In the above embodiment, an example in which two IGBTs 1 and 2 are provided as semiconductor elements has been described, but the present invention can also be applied to a configuration in which three or more IGBTs are provided.
Further, when three or more IGBTs are provided, after all of the IGBTs are turned on at the same time during the on operation, when the device current value is equal to or lower than the lower limit value, the remaining elements are kept in the on state. It is possible to set not all items as targets to be turned off but some items as targets to be turned off. That is, in step A4 shown in FIG. 2, “a part of the IGBTs can be turned off by the high-speed off circuit”.

  In the above-described embodiment, an example in which two IGBTs 1 and 2 are simultaneously turned on by an on-operation gate switching signal has been described, but a method of sequentially turning on one by one may be employed. In this case, for example, the IGBT 2 is controlled to be turned on when the current when the IGBT 1 is turned on exceeds the upper limit value.

  Moreover, although the example which hold | maintains one IGBT1 in an ON state and turns off other IGBT2 when the value of element current is below a lower limit has been shown, the IGBT to be turned off can be changed and set. In this case, it may be changed and set alternately every time it is turned off. For example, the usage time may be timed and changed so that the usage time becomes average when a certain difference or more occurs. You can also.

  In the above embodiment, in the first gate-off circuit 6 and the second gate-off circuit 7, the gate-off fixed path is formed by the configuration in which signals are directly supplied to the MOSFETs 6a and 7a from the drivers 6b and 7b, but the resistance is lower than that of the gate resistors 6e and 7e. A gate resistor or a low impedance impedance element may be interposed.

An example in which an IGBT is used as the gate drive type semiconductor element has been described, but the present invention is not limited to this, and the present invention can be applied to a semiconductor element such as a MOSFET.
Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments and structures. The present disclosure includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more or less, are within the scope and spirit of the present disclosure.

  In the drawing, 1 and 2 are IGBTs (semiconductor elements), 3 is a gate drive device, 4 is a first gate cutoff circuit, 5 is a second gate cutoff circuit, and 6 is a first gate-off circuit (high-speed gate-off circuit, gate-off fixing circuit). , 6a is an N channel type MOSFET (off MOSFET), 6c is a first high speed off section, 6e is a gate resistance, 7 is a second gate off circuit (high speed gate off circuit, gate off fixing circuit), and 7a is an N channel type MOSFET ( Off MOSFET), 7c is a second high speed off section, 7e is a gate resistance, 8 is a normal gate off circuit, 9 is a drive control section (control device), 10 is a detection circuit, and 11 is a backflow prevention circuit.

Claims (5)

On-off drive control of a plurality of gate-driven semiconductor elements (1, 2) connected in parallel is performed, and based on the current flowing through the plurality of semiconductor elements, switching loss and on-loss associated with on-operation are small. In a gate drive device that sets a semiconductor device that keeps an on state among the plurality of semiconductor elements under the following conditions:
A normal gate-off circuit (8) for turning off all of the plurality of semiconductor elements;
A high-speed gate-off circuit (6a, 6c, 7a, 7c) for turning off some of the plurality of semiconductor elements in a state where there is an on-state,
The normal gate-off circuit is configured to be turned off by changing the gate voltage at a low speed so that a surge current generated when the plurality of semiconductor elements are turned off is equal to or lower than a breakdown tolerance.
The high-speed gate-off circuit is a gate drive device configured to turn off some of the plurality of semiconductor elements by changing a gate voltage at a higher speed than the normal gate-off path. The high-speed gate-off circuit (6a, 6c, 7a, 7c) is provided in a part of the plurality of semiconductor elements to be turned off,
A control device (9) for changing and setting the semiconductor element to be turned off when part of the plurality of semiconductor elements is turned off using the high-speed gate-off circuit;
The gate drive apparatus of Claim 1 provided with. A detection unit (10) for detecting whether or not a gate voltage of the semiconductor element to be turned off by the high-speed gate-off circuit is lower than a threshold voltage;
When the detection unit detects that the gate voltage of the semiconductor element to be turned off is lower than a threshold voltage, a gate-off fixing circuit (6a, 6b, 7a, 7b)
The gate drive device of Claim 1 or 2 provided with these. The high-speed gate-off circuit (6a, 6c, 7a, 7c)
Off MOSFETs (6a, 7a) for passing a current when the gate voltage of the semiconductor element is changed to an off level;
A gate resistor (6e, 7e) connected to the gate of the off MOSFET in order to pass a current within the range of the current rating of the off MOSFET;
The gate drive device according to claim 1, further comprising: The high-speed gate-off circuit (6a, 6c, 7a, 7c)
Off MOSFETs (6a, 7a) for passing a current when the gate voltage of the semiconductor element is changed to an off level;
A gate resistor (6e, 7e) connected to the gate of the off-MOSFET in order to pass a current within the range of the current rating of the off-MOSFET,
The gate-off fixing circuit (6a, 6b, 7a, 7b)
The off-MOSFET (6a, 7a) of the high-speed gate-off circuit is shared,
As a path for driving the gate of the off-MOSFET (6a, 7a) without passing through a low-resistance gate resistance or resistance having a resistance value smaller than that of the gate resistance (6e, 7e),
The gate drive apparatus as described in any one of Claim 1 to 3 provided.

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