JP2016149632A - Drive circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a drive circuit in which the occurrence of a power loss during drive can be suppressed while adverse effect of resonance is suppressed.SOLUTION: A gate drive circuit 20 driving a plurality of switches SW1 and SW2 is provided in which the plurality of switches SW1 and SW2 are connected in parallel. The gate drive circuit comprises: an OFF drive switch 22 for discharging from gates of the switches SW1 and SW2; and an ON drive switch 21 for charging to the gates of the switches SW1 and SW2. The OFF drive switch 21 and the ON drive switch 22 are each configured to simultaneously drive the plurality of switches SW1 and SW2 via a common connection point PG. Resistors R1 and R2 each with variable resistance values are provided between the connection point PG and the gate of the switch SW1 and between the connection point PG and the gate of the switch SW2, respectively. A control part 30 discriminates the occurrence of overcurrent in the switches SW1 and SW2 and increases the resistance values of the resistors R1 and R2 on the condition that the occurrence of overcurrent in the switches SW1 and SW2 is discriminated.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a drive circuit that drives a plurality of semiconductor switching elements in a configuration in which the plurality of semiconductor switching elements are connected in parallel.

  In an inverter circuit or a DCDC converter, a configuration in which output power can be increased by connecting a plurality of semiconductor switching elements (switches) in parallel is conceivable. For example, when two switches are connected in parallel, one of the two switches is a first switch and the other is a second switch. In order to suppress variations in the off-on state (open / closed state) of both switches, a configuration is known in which the control terminals of both switches are simultaneously driven using a single drive circuit. In this configuration, a connection point is provided between the drive circuit and the control terminals of both switches. The drive circuit drives the control terminals of both switches via the connection point.

  In the above circuit configuration, a closed circuit of connection point-control terminal of first switch-output terminal of first switch-output terminal of second switch-control terminal of second switch-connection point is formed. In this closed circuit, resonance occurs due to the feedback capacitance and the wiring inductance when the voltage at the control terminal rises or falls.

  In addition, a closed circuit of connection point-control terminal of first switch-input terminal of first switch-input terminal of second switch-control terminal of second switch-connection point is formed. In the above closed circuit, resonance occurs due to the input capacitance and the wiring inductance when the voltage of the control terminal rises or falls.

  Due to these resonances, there is a concern that a current larger than the allowable current of the element or wiring flows to the element or wiring, causing damage to the element or wiring. In order to suppress the resonance, a configuration is known in which a resistor is provided between the connection point and the control terminals of both switches to suppress the resonance (Non-Patent Document 1).

Fuji Electric, “IGBT Module Application Manual”, Chapter 8-8-6, [online], May 2011, [Search February 1, 2015], Internet <URL: http://www.fujielectric.co. jp / products / semiconductor / model / igbt / application / index.html>

  Here, if a resistor is provided between the connection point and the control terminal, resonance can be suppressed, while power loss occurs during driving. The present invention has been made to solve the above-described problem, and a main object of the present invention is to provide a drive circuit capable of suppressing the occurrence of power loss during driving while suppressing adverse effects due to resonance.

  The present invention is a drive circuit (20) for driving a plurality of switches (SW1, SW2) that are voltage-controlled semiconductor switching elements, wherein the plurality of switches are connected in parallel, and from the control terminal of the switch A discharge circuit (22) that switches the switch to an off state by discharging; and a charge circuit (21) that switches the switch to an on state by charging the control terminal of the switch, the discharge circuit And the charging circuit drives the plurality of switches simultaneously via a common connection point (PG), and sets a resistance value between the connection point and the control terminals of the plurality of switches. A changeable resistor (R1, R2) is provided, and an overcurrent determination unit (30) for determining that an overcurrent is generated in the switch, and the overcurrent determination The parts, on condition that it is determined that overcurrent occurs in the switch, the control unit (30) for increasing the resistance value of the resistor, characterized in that it comprises a.

  When an overcurrent occurs, there is a concern that resonance with a large amplitude occurs in the closed circuit including the path between the connection point and the control terminal, and the element and the wiring are damaged. In view of this, the resistance value of the resistor is increased on the condition that it is determined that an overcurrent is generated in the switch, thereby preventing damage to the element caused by resonance in the closed circuit. In addition, when it is not determined that an overcurrent will occur, the resistance value of the resistor is not increased, and the generation of power loss during normal driving can be reduced.

The electrical block diagram of 1st Embodiment. The figure which shows the closed circuit containing the gate and connection point of a switch. The electrical block diagram of 2nd Embodiment. The timing chart showing the change of the gate voltage at the time of normal turn-off and the turn-off at the time of implementing a slow discharge. The timing chart showing the change of output current when overcurrent arises. The electrical block diagram of 4th Embodiment. The electrical block diagram of 5th Embodiment. The electrical block diagram of 6th Embodiment. The electrical block diagram of 7th Embodiment. The timing chart showing the change of the gate voltage and the change of a sense voltage when an always-on abnormality arises in a resistor.

(First embodiment)
FIG. 1 shows an electrical configuration diagram of the first embodiment. In the present embodiment, the switches SW1 and SW2 are provided in parallel connection. Both switches SW1 and SW2 are IGBTs. The switches SW1 and SW2 are provided with free-wheeling diodes D1 and D2, respectively. The switches SW1 and SW2 operate as upper arm switches of an inverter circuit (not shown). For simplification of description, the switches SW1 and SW2 are collectively referred to as a switch SW.

  The collector of the switch SW1 and the collector of the switch SW2 are connected to a common connection point PC, and the emitter of the switch SW1 and the emitter of the switch SW2 are connected to a common connection point PE. Thus, by connecting the switches SW1 and SW2 in parallel, it is possible to improve the power that can be output compared to the case where the switches are used alone.

  The gates (control terminals) of the switches SW1 and SW2 are simultaneously driven from one gate drive circuit 20 through a common connection point PG. The gate drive circuit 20 includes an on drive switch 21, an off drive switch 22, and gate resistors 23 and 24. The on drive switch 21 is an N-channel MOSFET, and the off drive switch 22 is a P-channel MOSFET.

  The on drive switch 21 as a charging circuit applies the power supply voltage Vs as a drive voltage to the gates of the switches SW1 and SW2. The source of the on drive switch 21 is connected to the voltage source 25, and the drain is connected to the gates of the switches SW1 and SW2 via the on gate resistor 23 and the connection point PG. The on drive switch 21 is turned on when a high-state on command signal is input to the gate from the drive control unit 40, and the gates of the switches SW1 and SW2 and the voltage source 25 are brought into conduction.

  Further, the off drive switch 22 as a discharge circuit connects the gates of the switches SW1 and SW2 to the ground point, and sets the gate voltage Vge (gate-emitter voltage) to the ground voltage (emitter voltage). The source of the off drive switch 22 is connected to the ground point, and the drain is connected to the gates of the switches SW1 and SW2 via the off gate resistor 24 and the connection point PG. The off drive switch 22 is turned on when a high-state off command signal is input to the gate from the drive control unit 40, and the gates of the switches SW1 and SW2 and the grounding point are brought into conduction.

  Here, the switches SW1 and SW2 include a feedback capacitance Cres that is a gate-collector capacitance, an input capacitance Cies that is a gate-emitter capacitance, and an output capacitance Coes that is a collector-emitter capacitance. .

  As shown in FIG. 2 (a), the gate of the connection point PG-the switch SW1, the feedback capacitance Cres of the switch SW1, the collector of the switch SW1, the collector of the connection point PC, the collector of the switch SW2, the feedback capacitance Cres2-of the switch SW2. A closed circuit A1 called gate-connection point PG is generated. Further, as shown in FIG. 2B, the gate-switch SW1 input capacitance Cies1-switch SW1 emitter-connection point PE-switch SW2 emitter-switch SW2 input capacitance Cies2-switch of the connection point PG-switch SW1. A closed circuit A2 called a gate-connection point PG of SW2 is generated.

  Here, when the output currents Ice1 and Ice2 (collector-emitter current) flowing through the switches SW1 and SW2 match, no current flows through the closed circuits A1 and A2. However, it is conceivable that the switches SW1 and SW2 are turned on and off due to individual differences between the switches SW1 and SW2 and a drive signal shift caused by wiring impedance. Due to the difference between the turn-on and turn-off, differences occur in the output currents Ice1 and Ice2 of the switches SW1 and SW2, respectively, and current flows through the two closed circuits A1 and A2.

  When a current flows through the closed circuit A1, there is a concern that resonance occurs due to the feedback capacitance Cres and the inductive components of the wiring and elements. Further, when a current flows through the closed circuit A2, there is a concern that resonance occurs due to the input capacitance Cies and the inductive component of the wiring and the element.

  Returning to the description of FIG. 1, in the configuration of this embodiment, resistors R1 and R2 are provided between the connection point PG and the gates of the switches SW1 and SW2, respectively, in order to suppress resonance in the closed circuits A1 and A2. It is configured. The resonance is attenuated by the resistors R1 and R2, and it can be suppressed that a large current flows through the closed circuits A1 and A2, and that a high voltage is applied to the elements on the closed circuits A1 and A2.

  Here, when the resistors R1 and R2 are provided between the connection point PG and the gates of the switches SW1 and SW2, resonance can be suppressed, but power loss occurs when the switches SW1 and SW2 are driven. Further, when an overcurrent is generated in the switches SW1 and SW2, there is a concern that resonance with a large amplitude occurs in the closed circuits A1 and A2 and the element is damaged. In the inverter circuit, the overcurrent is generated due to an always-on abnormality in the paired lower arm switch in the leg in which the switches SW1 and SW2 are the upper arm switches.

  Therefore, on the condition that it is determined that an overcurrent is generated in the switches SW1 and SW2, the resistance values of the resistors R1 and R2 whose resistance values can be changed are increased, thereby resonating in the closed circuits A1 and A2. Damage to elements and wiring caused by the occurrence of In addition, when it is not determined that an overcurrent will occur, the power loss during driving can be reduced by not increasing the resistance values of the resistors R1 and R2.

  Specifically, the resistor R1 is configured by connecting in parallel a resistor R11 having a large resistance value and a switch SA1 and a resistor R12 having a small resistance value connected in series. Similarly, the resistor R2 is configured such that a resistor R21 having a large resistance value and a switch SA2 and a resistor R22 having a small resistance value connected in series are connected in parallel. When the switches SA1 and SA2 are turned on, the resistance values of the resistors R1 and R2 are reduced, and when the switches SA1 and SA2 are turned off, the resistance values of the resistors R1 and R2 are increased. Here, the resistance values (for example, 5Ω) of the resistor R11 and the resistor R21 are equal, and the resistance values (for example, 1Ω) of the resistor R12 and the resistor R22 are equal.

  Further, sense resistors RS1 and RS2 for current detection are provided on the emitter side of the switches SW1 and SW2. The sense resistors RS1 and RS2 are provided in parallel with the wiring connecting the emitters of the switches SW1 and SW2 and the connection point PE. The control unit 30 according to the present embodiment detects the voltage (sense voltage Vse) on the emitter side of the switches SW1 and SW2 among the terminals of the sense resistors RS1 and RS2, so that the output current Ice1 flowing in the switches SW1 and SW2 is detected. , Ice2 is acquired. That is, the sense resistors RS1 and RS2 and the control unit 30 operate as a current detection unit. When at least one of the output currents Ice1 and Ice2 exceeds the threshold value Ith (exceeds the first threshold value), it is determined that an overcurrent has occurred in the switches SW1 and SW2. In the present embodiment, when the sense voltage Vse exceeds a threshold voltage corresponding to the threshold Ith, it is determined that an overcurrent has occurred in the switches SW1 and SW2.

  Control unit 30 turns off both switches SA1 and SA2 on the condition that it is determined that an overcurrent has occurred in switches SW1 and SW2. As a result, the resistance values of the resistors R1 and R2 are increased, and resonance in the closed circuits A1 and A2 can be suppressed. Further, the control unit 30 reduces the resistance values of the resistors R1 and R2 by turning on the switches SA1 and SA2 during normal driving in which no overcurrent occurs, and the switch SW1 by the gate drive circuit 20 , SW2 when the gate is driven can be reduced.

(Second Embodiment)
FIG. 3 shows an electrical configuration diagram of the second embodiment. The same components as those in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  The gate drive circuit 20 of this embodiment includes a slow discharge switch 26 and a slow discharge resistor 27. The slow discharge switch 26 is a P-channel MOS-FET. The slow discharge switch 26 connects the gates of the switches SW1 and SW2 and the ground point, and sets the gate voltage Vge to the ground voltage. The source of the slow discharge switch 26 is connected to the ground point, and the drain is connected to the gates of the switches SW1 and SW2 via the slow discharge resistor 27 and the connection point PG. The slow discharge switch 26 is turned on when a high-level slow discharge command signal is input to the gate from the drive control unit 40, and the gates of the switches SW1 and SW2 and the grounding point are brought into conduction.

  Here, the resistance value (for example, 50Ω) of the slow discharge resistor 27 is set larger than the resistance value (for example, 1Ω) of the off-gate resistor 24. Therefore, the gate discharge of the switches SW1 and SW2 by the slow discharge switch 26 is gentler than the gate discharge of the switches SW1 and SW2 by the off drive switch 22.

  The slow discharge switch 26 as the slow discharge circuit is turned on when an overcurrent flows through the switches SW1 and SW2, and discharges from the gates of the switches SW1 and SW2 more slowly than the off drive switch 22. By discharging from the gates of the switches SW1 and SW2 more slowly than the off drive switch 22, it is possible to suppress the occurrence of surge voltage.

  The control unit 30A acquires the output currents Ice1 and Ice2 flowing through the switches SW1 and SW2 by detecting the voltage on the emitter side of the switches SW1 and SW2 among the terminals of the sense resistors RS1 and RS2. Here, the control unit 30 determines that an overcurrent has occurred on the condition that at least one of the output currents Ice1 and Ice2 has exceeded the threshold value Ith, and turns off the switches SA1 and SA2, thereby reducing the resistance. The resistance values of the resistors R1 and R2 are increased. This suppresses the occurrence of resonance.

  Furthermore, the control unit 30A of the present embodiment instructs the drive control unit 40 to turn on the slow discharge switch 26 after a predetermined time has elapsed after increasing the resistance values of the resistors R1 and R2. Then, the drive control unit 40A turns on the slow discharge switch 26 to perform the slow discharge of the switches SW1 and SW2.

  FIG. 4A shows a timing chart of the gate voltage Vge when the normal switch SW is turned off, and FIG. 4B shows a timing chart of the gate voltage Vge when the switch SW is turned off when an overcurrent is detected.

  Prior to time T1 in FIG. 4A, the power supply voltage Vs (for example, 15 V) is applied to the gate of the switch SW, and the switch SW is turned on. At time T <b> 1, a turn-off command signal is input from the drive control unit 40 to the off-drive switch 22. After the elapse of the turn-on time of the off drive switch 22 from time T1, at time T2, the off drive switch 22 is turned on, and the gate of the switch SW and the grounding point are brought into conduction. As a result, the gate voltage Vge decreases. Thereafter, after a mirror period, the gate voltage Vge is set to 0 V at time T3.

  Before time T11 in FIG. 4B, the power supply voltage Vs is applied to the gate of the switch SW, and the switch SW is turned on. At time T11, it is determined that one of the output currents Ice1 and Ice2 of the switch SW has exceeded the threshold value Ith. After the turn-off time of the switches SA1 and SA2 has elapsed from time T11, the switches SA1 and SA2 are turned off at time T12. As a result, the resistance values of the resistors R1 and R2 increase.

  Thereafter, at time T13, after a predetermined time has elapsed from time T12, the slow discharge switch 26 is turned on, and slow discharge is performed. As a result, the gate of the switch SW is slowly discharged, and the gate voltage Vge is set to 0 V at time T14 after a time longer than the turn-off time (time T2 to time T3) shown in FIG.

  If the switches SW1 and SW2 are turned off when an overcurrent is generated, a large surge current is generated. There is a concern that an excessive current flows due to the surge current and the resonance current, and the element is damaged. Thus, the slow discharge switch 26 is used to reduce the turn-off speed, thereby suppressing the surge voltage. Here, by increasing the resistance values of the resistors R1 and R2 in advance before the turn-off, the resonance at the turn-off can be suppressed, and the surge current and the adverse effect on the element due to the resonance can be effectively suppressed. can do.

(Third embodiment)
The electrical configuration of the third embodiment is the same as that of the second embodiment.

  The control unit 30A of the present embodiment acquires the output currents Ice1 and Ice2 flowing through the switches SW1 and SW2 by detecting the voltage on the emitter side of the switches SW1 and SW2 among the terminals of the sense resistors RS1 and RS2. . Here, the control unit 30A determines that an overcurrent has occurred on the condition that at least one of the output currents Ice1 and Ice2 exceeds the threshold value Ith1 (first threshold value), and sets the switches SA1 and SA2 to the off state. As a result, the resistance values of the resistors R1 and R2 are increased. This suppresses the occurrence of resonance.

  Further, the control unit 30A sets the slow discharge switch 26 to the on state on condition that at least one of the output currents Ice1 and Ice2 exceeds the threshold value Ith2 (second threshold value) for a predetermined time. Command to 40. Then, the drive control unit 40A turns on the slow discharge switch 26 to perform the slow discharge of the switches SW1 and SW2. Here, the threshold value Ith2 is set to a value larger than the threshold value Ith1. By setting the threshold values Ith1 and Ith2 in this manner, the switches SW1 and SW2 are slowly discharged after the resistance values of the resistors R1 and R2 are increased.

  FIG. 5 shows a timing chart of the output current Ice of the switch SW at the turn-off time when overcurrent is detected.

  Prior to time T21, an always-on abnormality has occurred in the lower arm switch of the inverter circuit. At time T21, the switch SW is turned on while the lower arm switch of the inverter circuit is always on, so that the output current Ice of the switch SW increases at a higher speed than normal. Go.

  At time T22, the output current Ice of the switch SW reaches the threshold value Ith1. As a result, the resistance values of the resistors R1 and R2 are increased. Thereafter, when the output current Ice of the switch SW further increases, the threshold value Ith2 is reached at time T23.

  At time T24, since the output current Ice exceeds the threshold value Ith2 over a predetermined time, the slow discharge by the slow discharge switch 26 is performed. By slow discharge, the gate voltage Vge decreases and the output current Ice decreases. Thereafter, after the tail current flows, the output current Ice becomes 0 A at time T24.

  The control unit 30A serving as an overcurrent determination unit detects the output current Ice flowing through the switch SW, and determines that an overcurrent has occurred when the detected value exceeds a predetermined threshold value Ith1. Here, compared with the threshold value Ith2 for determining the implementation of the slow discharge by the slow discharge switch 26, the threshold value Ith1 for determining the implementation of the increase in the resistance values of the resistors R1 and R2 is made smaller. With this configuration, before the turn-off is performed using the slow discharge switch 26, the resistance values of the resistors R1 and R2 can be increased in advance.

(Fourth embodiment)
FIG. 6 shows an electrical configuration diagram of the fourth embodiment. The same components as those in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted as appropriate. In the configuration of the fourth embodiment, the temperature sensitive diodes DT1 and DT2 for detecting the temperatures Th1 and Th2 of the switches SW1 and SW2 are provided, respectively. The temperature sensitive diodes DT1 and DT2 are connected to the temperature detection unit 31.

  The temperature detection unit 31 detects the temperatures Th1 and Th2 of the switches SW1 and SW2 based on the forward voltage drop of the temperature sensitive diodes DT1 and DT2, and outputs the detected values to the control unit 30B. The control unit 30B changes the resistance values of the resistors R1 and R2 at the time of overcurrent on condition that either one of the temperatures Th1 and Th2 of the switches SW1 and SW2 is lower than a threshold value Thth (predetermined temperature). .

  The switches SW1 and SW2, which are semiconductor switching elements, have a higher switching speed as the temperatures Th1 and Th2 are lower. By increasing the switching speed, the surge voltage increases and the influence of resonance increases. Therefore, the resistance values of the resistors R1 and R2 are increased at low temperatures. Thereby, the bad influence to the element by resonance can be suppressed suitably.

  Further, the higher the temperatures Th1 and Th2 of the switches SW1 and SW2, the smaller the heat generation allowable amount of the entire apparatus. In view of this, it is possible to reduce the heat generation of the entire apparatus including the switches SW1 and SW2 by preventing the resistance values of the resistors R1 and R2 from increasing at high temperatures.

(Fifth embodiment)
FIG. 7 shows an electrical configuration diagram of the fifth embodiment. The same components as those in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted as appropriate. The gate drive circuit 20C of the fifth embodiment includes a constant current drive circuit 21C as a charging circuit. The gate drive circuit 20C includes a constant current drive circuit 22C as a discharge circuit.

  The constant current drive circuit 21 </ b> C causes the gates of the switches SW <b> 1 and SW <b> 2 and the voltage source 25 to be in a conductive state by receiving a high-state ON command signal from the drive control unit 40 </ b> C. In addition, the constant current drive circuit 22C causes the gates of the switches SW1 and SW2 and the ground point to be in a conductive state when a high-state off command signal is input from the drive control unit 40C. Here, the constant current drive circuits 21C and 22C perform constant current drive.

  By providing the resistors R1 and R2 between the discharge circuit and the charging circuit and the gates of the switches SW1 and SW2, there is a concern that the switching speed of the switches SW1 and SW2 may be reduced, causing an increase in switching loss. Here, by using the constant current driving circuits 21C and 22C as the charging circuit and the discharging circuit capable of constant current driving, the switching speed of the switches SW1 and SW2 becomes constant. By making the switching speed constant, it becomes possible to reduce the switching loss accompanying the decrease in the switching speed due to the resistors R1 and R2.

(Sixth embodiment)
FIG. 8 shows an electrical configuration diagram of the sixth embodiment. The same components as those in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted as appropriate. The gate drive circuit 20D includes two on drive switches 21D1 and 21D2 as a charging circuit. The gate drive circuit 20D includes two off drive switches 22D1 and 22D2 as discharge circuits.

  The on drive switches 21D1 and 21D2 apply the power supply voltage Vs as a drive voltage to the gates of the switches SW1 and SW2. The sources of the on-drive switches 21D1 and 21D2 are connected to the voltage source 25, respectively, and the drains are connected to the gates of the switches SW1 and SW2 via the on-gate resistors 23D1 and 23D2 and the connection point PG, respectively. The on-drive switches 21D1 and 21D2 are turned on when a high-state on-command signal is input to the gate from the drive control unit 40D, and the gates of the switches SW1 and SW2 and the voltage source 25 are brought into conduction. Here, the resistance value (for example, 10Ω) of the on-gate resistor 23D2 is set to be larger than the resistance value (for example, 1Ω) of the on-gate resistor 23D1.

  The off-drive switches 22D1 and 22D2 connect the gates of the switches SW1 and SW2 to the ground point, and set the gate voltage Vge (gate-emitter voltage) to the ground voltage (emitter voltage). The sources of the off drive switches 22D1 and 22D2 are connected to the ground point, and the drains are connected to the gates of the switches SW1 and SW2 via the off gate resistors 24D1 and 24D2 and the connection point PG. The off drive switches 22D1 and 22D2 are turned on when a high-state off command signal is input to the gate from the drive control unit 40, and the gates of the switches SW1 and SW2 and the grounding point are brought into conduction. Here, the resistance value (for example, 10Ω) of the off-gate resistance 24D2 is set to be larger than the resistance value (for example, 1Ω) of the off-gate resistance 24D1.

  When the gates of the switches SW1 and SW2 are charged and discharged using the on drive switch 21D1 and the off drive switch 22D1, charging and discharging are performed through the gate resistors 23D1 and 24D1. Further, when the gates of the switches SW1 and SW2 are charged and discharged using the on drive switch 21D2 and the off drive switch 22D2, charging and discharging are performed via the gate resistors 23D2 and 24D2. The resistance values of the gate resistors 23D1 and 24D1 are “first resistance values”, and the resistance values of the gate resistors 23D2 and 24D2 are “second resistance values”.

  When charging / discharging is performed via the gate resistors 23D2 and 24D2, the surge voltage and surge current of the switches SW1 and SW2 can be effectively suppressed, while the power loss associated with driving the gates of the switches SW1 and SW2 increases. When charging / discharging is performed via the gate resistors 23D1 and 24D1, power loss due to driving of the gates of the switches SW1 and SW2 is reduced, while the effect of reducing the surge voltage and surge current of the switches SW1 and SW2 is reduced.

  Therefore, the drive control unit 40D acquires the output currents Ice1 and Ice2 flowing through the switches SW1 and SW2 from the control unit 30D. When the output currents Ice1 and Ice2 are smaller than a predetermined threshold IA (predetermined current), the drive control unit 40D outputs an on command signal and an off command signal to the on drive switch 21D1 and the off drive switch 22D1. Thereby, the power loss accompanying the drive of the gates of the switches SW1 and SW2 can be reduced.

  Further, the drive control unit 40D outputs an on command signal and an off command signal to the on drive switch 21D2 and the off drive switch 22D2 when the output currents Ice1 and Ice2 are equal to or greater than the threshold value IA. Thereby, it is possible to suppress a surge voltage when the switches SW1 and SW2 are turned on and turned off.

  Here, the threshold value IA is set to a value smaller than the threshold value Ith for increasing the resistance values of the resistors R1 and R2. When the resistance values of the resistors R1 and R2 are increased, since the gate resistors 23D2 and 24D2 are used, the resonance suppression effect and the surge voltage and surge current reduction effect can be obtained together. Thereby, the bad influence given to an element can be controlled suitably.

(Seventh embodiment)
FIG. 9 shows an electrical configuration diagram of the seventh embodiment. The same components as those in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted as appropriate. The control unit 30E acquires the detection value of the gate voltage Vge of the switches SW1 and SW2.

  As shown in FIG. 10, when one of the switches SA1 and SA2 (for example, the switch SA2) is normally off, there is a difference between the turn-on time and turn-off time of the switch SW1 and the turn-on time and turn-off time of the switch SW2. Occurs. Due to the difference between the turn-on time and the turn-off time of both switches SW1 and SW2, there is a concern that current flows in the closed circuits A1 and A2 and resonance occurs in the turn-on and turn-off of both switches SW1 and SW2.

  Therefore, the control unit 30E as a voltage detection unit detects the gate voltage Vge of the switches SW1 and SW2. Then, the control unit 30E as the abnormality determination unit determines whether the switches SA1 and SA2 are normally off based on the temporal change of the gate voltage Vge. The control unit 30E determines that a normal OFF abnormality has occurred in one of the switches SA1 and SA2, that is, if it is determined that an abnormality has occurred in one of the resistors R1 and R2, the normal resistor The resistance values of R1 and R2 are made equal to the resistance values of resistors R1 and R2 in which an abnormality has occurred. Specifically, if the switch SA2 is always turned off, control is performed so that the switch SA1 is always turned off.

  Here, the control unit 30E causes an abnormality in the resistors R1 and R2 based on a change in the collector voltage (voltage at the input terminal) at turn-on or a change in the collector voltage (voltage at the output terminal) at turn-off. It is also possible to determine whether or not there is.

  Further, for example, the sense voltage Vse of the sense resistors RS1 and RS2 used for detecting the output currents Ice1 and Ice2 changes as shown in FIG. Specifically, when the gate voltage Vge reaches the turn-on voltage Von, the output currents Ice1 and Ice2 begin to flow, and the sense voltage Vse starts to rise. Therefore, it is possible to determine the abnormality of the switches SA1 and SA2 based on the rising timing of the sense voltage Vse. Similarly, the abnormality of the switches SA1 and SA2 can be determined based on the falling timing of the sense voltage Vse.

  When an abnormality occurs in one of the resistors R1 and R2 of the switches SW1 and SW2, the resistance values between the ON drive switch 21 and the OFF drive switch 22 and the gates of the switches SW1 and SW2 are different. Due to the unbalance of the resistance values, there is a difference in the timing at which the switches SW1 and SW2 are turned on when the switches SW1 and SW2 are turned on. Similarly, at the time of turn-off, a deviation occurs in the timing at which the switches SW1 and SW2 are turned off. Since there is a concern about the occurrence of resonance due to this deviation, when one of the switches SA1 and SA2 is always off abnormally, control is performed to always turn off the other, and the resistance values of the resistors R1 and R2 are set. Make equal. By this control, it is possible to suppress the occurrence of resonance due to the abnormality of the resistors R1 and R2, and it is possible to suitably suppress the resonance when an overcurrent is generated.

(Other embodiments)
In the first to fourth and seventh embodiments, the gate resistors 23 and 24 may be omitted. Even when the gate resistors 23 and 24 are omitted, the resistors R1 and R2 can suppress the surge voltage and surge current generated between the gates of the switches SW1 and SW2 and the switches 21 and 22. is there.

  -Regarding the determination of the overcurrent of the output current Ice of the switch SW, the method of detecting the output current Ice and comparing the detected value with the threshold value Ith may be changed. For example, it may be determined that an overcurrent is generated in the switch SW as a pair of upper arm switches on the condition that it is determined that the always-on abnormality has occurred in the lower arm switch of the inverter circuit.

  Although the sense resistors RS1 and RS2 are provided on the emitter side of the switches SW1 and SW2, this may be changed and a sense resistor may be provided on the collector side of the switches SW1 and SW2. Moreover, it is good also as a structure which detects the output current Ice using Hall elements etc. instead of sense resistance RS1, RS2.

  -It is good also as a structure which changes threshold value Ith of overcurrent determination based on temperature Th1, Th2 of switch SW1, SW2. As the temperatures Th1 and Th2 of the switches SW1 and SW2 are lower, the threshold value Ith used for determining the overcurrent is preferably decreased.

  The switch SW, which is a voltage controlled semiconductor switching element, may be a MOS-FET instead of the IGBT.

  In the third embodiment, a resistance temperature detector or the like may be used instead of the temperature sensitive diodes DT1 and DT2.

  -The structure of the said embodiment is applicable also to the structure which connects three or more switches in parallel.

  A digital variable resistor that can select three or more resistance values may be used as the resistor whose resistance value can be changed.

  The above embodiments can be implemented in combination as appropriate. For example, the second and third embodiments can be combined with the fourth to seventh embodiments, respectively. The fourth embodiment can be combined with the fifth to seventh embodiments. The fifth and sixth embodiments can be combined with the seventh embodiment, respectively.

  DESCRIPTION OF SYMBOLS 20 ... Gate drive circuit, 21 ... On drive switch, 22 ... Off drive switch, 30 ... Control part (overcurrent determination part, control part), PG ... Connection point, R1, R2 ... Resistor, SW1, SW2 ... Switch.

Claims (8)

A drive circuit (20) for driving a plurality of switches (SW1, SW2) which are voltage controlled semiconductor switching elements,
The plurality of switches are connected in parallel,
A discharge circuit (22) for switching the switch to an OFF state by discharging from the control terminal of the switch;
A charging circuit (21) for switching the switch to an on state by charging the control terminal of the switch,
The discharging circuit and the charging circuit are configured to simultaneously drive the plurality of switches via a common connection point (PG),
Resistors (R1, R2) that can change resistance values are provided between the connection points and the control terminals of the plurality of switches, respectively.
An overcurrent determination unit (30) for determining that an overcurrent occurs in the switch;
A drive circuit comprising: a control unit (30) configured to increase a resistance value of the resistor on the condition that the overcurrent determination unit determines that an overcurrent is generated in the switch. Compared to the discharge circuit, comprising a slow discharge circuit (26) that slowly discharges from the control terminal of the switch,
The controller (30A) increases the resistance value of the resistor on the condition that the overcurrent determination unit determines that an overcurrent occurs in the switch, and then discharges by the slow discharge circuit. The drive circuit according to claim 1, wherein the drive circuit is implemented. The switch is provided with a current detection unit (RS1, RS2, 30) that detects an output current flowing through the switch,
The overcurrent determination unit determines that an overcurrent is generated in the switch when a detection value of the current detection unit exceeds a predetermined first threshold;
The control unit increases the resistance value of the resistor on the condition that the overcurrent determination unit determines that an overcurrent is generated in the switch, and the output current flowing through the switch is the first threshold value. It is determined whether or not a larger second threshold value is exceeded, and the discharge by the slow discharge circuit is performed on the condition that the output current flowing through the switch is determined to exceed the second threshold value. The drive circuit according to claim 2. A temperature detector (31) for detecting the temperature of the switch;
4. The control unit according to claim 1, wherein the control unit increases the resistance value of the resistor on the condition that a detected value of the temperature of the switch is lower than a predetermined temperature. 5. The drive circuit according to the item.   At least one of the discharging circuit (22C) and the charging circuit (21C) performs constant current driving using a current flowing through the control terminal of the switch as a constant current. The drive circuit according to one item. The switch is provided with a current detector (RS1, RS2) that detects an output current flowing through the switch,
The overcurrent determination unit determines that an overcurrent is generated in the switch when a detection value of the current detection unit exceeds a predetermined first threshold;
Gate resistors (23D1, 23D2, 24D1, 24D2) are provided between the discharge circuit and the charging circuit and the connection point, respectively.
When the output current of the switch is smaller than a predetermined current, the gate resistance is set to a first resistance value, and when the output current of the switch is larger than the predetermined current, the gate resistance is larger than the first resistance value. A second resistance value,
The drive circuit according to claim 1, wherein the predetermined current is smaller than the first threshold value. A voltage detection unit for detecting a voltage of at least one of the control terminal, the output terminal, and the input terminal of the switch;
The abnormality determination part (30E) which determines abnormality of the said resistor based on the difference of the detected value change of the said voltage detection part in these switches is provided, The any one of Claim 1 thru | or 6 characterized by the above-mentioned. The drive circuit according to the item.   When it is determined by the abnormality determination unit that the resistor is abnormal, the control unit (30E) sets the normal resistance value of the resistor to the resistance value of the resistor in which the abnormality has occurred. The drive circuit according to claim 7, wherein

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