JP2017120833A - Semiconductor device and manufacturing method thereof, semiconductor substrate, circuit board, and electronic device - Google Patents

Abstract

A semiconductor device or memory device having a capacitor with a large storage capacitor is provided.
A transistor, a capacitor, and an insulator are included. The transistor includes a back gate electrode and an oxide semiconductor, and the capacitor includes a first electrode and a second electrode. One of a source and a drain of the transistor is electrically connected to the first electrode, and the back gate electrode and the second electrode are provided over the surface of the insulator. The first electrode has a region overlapping with the second electrode with an insulator interposed therebetween, and the back gate electrode has a region overlapping with the oxide semiconductor with the insulator interposed therebetween. By increasing the height of the second electrode, the storage capacity of the capacitor can be increased. In addition, the manufacturing process can be simplified by forming the second electrode and the back gate electrode in the same process.
[Selection] Figure 2

Description

One embodiment of the present invention relates to a semiconductor device or a memory device.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). One embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a circuit board, an electronic device, a driving method thereof, or a manufacturing method thereof.

A DRAM (Dynamic Random Access Memory) records data by supplying charges to a capacitor. Therefore, the smaller the off-state current of the transistor that controls the supply of charge to the capacitor, the longer the period during which data is held, and the frequency of refresh operations can be reduced. Patent Document 1 describes a semiconductor device that uses an oxide semiconductor film and can hold recorded contents for a long time with a transistor with extremely low off-state current.

Patent Document 2 describes a configuration in which gate electrodes are formed above and below an active layer.

Patent Document 3 describes the configuration of a circular thin film transistor.

JP 2011-151383 A JP 2007-029394 A JP 2006-352087 A Japanese Patent Laid-Open No. 1993-082787

In Patent Document 4, the transistor included in the memory element included in the memory device and the capacitor are formed in different layers. In this case, a dedicated wiring, an interlayer film, and the like are required to form the capacitive element. As a result, an increase in manufacturing cost and an increase in thickness of a transistor, a capacitor element, and the like become problems.

An object of one embodiment of the present invention is to provide a semiconductor device or a memory device including a capacitor with a large storage capacitor. Another object of one embodiment of the present invention is to provide a semiconductor device or a memory device with high storage capacity. Another object of one embodiment of the present invention is to provide a semiconductor device or a memory device including a transistor with high on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device or a memory device including a transistor with low off-state current. Another object of one embodiment of the present invention is to provide a semiconductor device or a memory device that operates at high speed. Another object of one embodiment of the present invention is to provide a semiconductor device or a memory device in which errors in reading are reduced. Another object of one embodiment of the present invention is to provide a semiconductor device or a memory device that can be manufactured through a simple process. Another object of one embodiment of the present invention is to provide a low-cost semiconductor device or memory device. Another object of one embodiment of the present invention is to provide a semiconductor device or a memory device with low power consumption.

Another object of one embodiment of the present invention is to provide a novel semiconductor device or a memory device.

Note that one embodiment of the present invention does not necessarily have to solve all of the problems described above, and may be one that can solve at least one problem. Further, the description of the above problem does not disturb the existence of other problems. Issues other than these will be apparent from the description of the specification, drawings, claims, etc., and it is possible to extract other issues from the description of the specification, drawings, claims, etc. .

The transistor includes a transistor, a capacitor, and an insulator. The transistor includes a back gate electrode and an oxide semiconductor. The capacitor includes a first electrode and a second electrode. One of the source and the drain of the transistor is electrically connected to the first electrode, the back gate electrode is provided on the surface of the insulator, and the second electrode is provided on the surface of the insulator, The first electrode has a region overlapping with the second electrode with an insulator interposed therebetween, and the back gate electrode has a region overlapping with the oxide semiconductor with the insulator interposed therebetween, and the back gate The electrode and the second electrode are made of the same material, and the height from the surface of the insulator to the top of the back gate electrode is the same as the height from the surface of the insulator to the top of the second electrode. is there.

Further, the height from the surface of the insulator to the top of the back gate electrode and the height from the surface of the insulator to the top of the second electrode may be not less than 100 nm and not more than 500 nm.

The other of the source and the drain of the transistor is provided in a circular shape when viewed from above, and one of the source and the drain of the transistor and the first electrode included in the capacitor are connected to the source or drain of the transistor when viewed from the upper surface. It may be provided on the other outer side.

One of the source and the drain of the transistor and the first electrode included in the capacitor may be provided concentrically as viewed from above.

The oxide semiconductor may include indium, an element M (Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf), zinc, and oxygen.

A method for manufacturing a semiconductor device in which the back gate electrode of the transistor and one of the electrodes of the capacitor are formed in the same step is also one embodiment of the present invention.

A semiconductor substrate including a plurality of semiconductor devices of one embodiment of the present invention and having a dicing region is also one embodiment of the present invention.

A circuit board including an electronic component including the semiconductor device of one embodiment of the present invention and a printed board is also one embodiment of the present invention.

An electronic device including the semiconductor device of one embodiment of the present invention or the circuit board of one embodiment of the present invention and a display portion, a microphone, a speaker, or an operation key is also one embodiment of the present invention.

According to one embodiment of the present invention, a semiconductor device or a memory device including a capacitor with a large storage capacitor can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device or a memory device with a large storage capacity can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device or a memory device including a transistor with high on-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device or a memory device including a transistor with low off-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device or a memory device that operates at high speed can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device or a memory device in which errors in reading are reduced can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device or a memory device that can be manufactured through a simple process can be provided. Alternatively, according to one embodiment of the present invention, a low-cost semiconductor device or memory device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device or a memory device with low power consumption can be provided.

Alternatively, according to one embodiment of the present invention, a novel semiconductor device or memory device can be provided.

Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. It should be noted that the effects other than these are naturally obvious from the description of the specification, drawings, claims, etc., and it is possible to extract the other effects from the descriptions of the specification, drawings, claims, etc. It is.

6A and 6B are a circuit diagram and a block diagram illustrating a semiconductor device. 8A and 8B are a top view and cross-sectional views illustrating a semiconductor device. 8A and 8B are a top view and cross-sectional views illustrating a semiconductor device. FIG. 10 is a cross-sectional view illustrating a semiconductor device. FIG. 10 is a cross-sectional view illustrating a semiconductor device. FIG. 10 is a cross-sectional view illustrating a semiconductor device. 8A and 8B are a top view and cross-sectional views illustrating a semiconductor device. 8A and 8B are a top view and cross-sectional views illustrating a semiconductor device. 8A and 8B are a top view and cross-sectional views illustrating a semiconductor device. 8A and 8B are a top view and cross-sectional views illustrating a semiconductor device. 8A and 8B are a top view and cross-sectional views illustrating a semiconductor device. 8A and 8B are a top view and cross-sectional views illustrating a semiconductor device. FIG. 10 is a top view illustrating a semiconductor device. 8A and 8B are a top view and cross-sectional views illustrating a semiconductor device. FIG. 10 is a top view illustrating a semiconductor device. FIG. 10 is a top view illustrating a semiconductor device. FIG. 10 is a top view illustrating a semiconductor device. 8A and 8B are a top view and cross-sectional views illustrating a semiconductor device. 6A and 6B are a circuit diagram and a cross-sectional view illustrating a semiconductor device. 6A and 6B are a circuit diagram and a cross-sectional view illustrating a semiconductor device. 6A and 6B are a circuit diagram and a cross-sectional view illustrating a semiconductor device. The figure explaining the range of atomic ratio of the semiconductor which concerns on this invention. FIG. 6 illustrates a crystal of InMZnO ₄ . The band figure in the laminated structure of a semiconductor. FIGS. 4A to 4C illustrate structural analysis by XRD of a CAAC-OS and a single crystal oxide semiconductor, and a diagram illustrating a limited-field electron diffraction pattern of the CAAC-OS. FIGS. Sectional TEM image of CAAC-OS, planar TEM image and image analysis image thereof. The figure which shows the electron diffraction pattern of nc-OS, and the cross-sectional TEM image of nc-OS. Cross-sectional TEM image of a-like OS. FIG. 6 shows changes in crystal parts of an In—Ga—Zn oxide due to electron irradiation. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device. FIG. 10 is a block diagram illustrating a semiconductor device. FIG. 10 is a block diagram illustrating a semiconductor device. FIG. 10 is a block diagram illustrating a semiconductor device. FIG. 10 is a block diagram illustrating a semiconductor device. FIG. 10 is a block diagram illustrating a semiconductor device. FIG. 10 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. 6 is a timing chart illustrating a semiconductor device according to one embodiment of the present invention. 10A and 10B are a block diagram, a circuit diagram, and a waveform diagram illustrating a semiconductor device. 6A and 6B are a circuit diagram and a timing chart illustrating a semiconductor device. FIG. 10 is a circuit diagram illustrating a semiconductor device. FIG. 10 is a circuit diagram illustrating a semiconductor device. FIG. 10 is a circuit diagram illustrating a semiconductor device. FIG. 10 is a circuit diagram illustrating a semiconductor device. FIG. 10 is a circuit diagram illustrating a semiconductor device. 4A and 4B are a circuit diagram, a top view, and a cross-sectional view illustrating a semiconductor device. 6A and 6B are a circuit diagram and a cross-sectional view illustrating a semiconductor device. The flowchart figure which shows the manufacturing process of an electronic component, and a perspective schematic diagram. 10A and 10B each illustrate an electronic device.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the description in the following embodiments, and those skilled in the art can easily understand that the forms and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

One embodiment of the present invention includes, in its category, any device including an RF (Radio Frequency) tag, a semiconductor display device, and an integrated circuit. In addition, the display device includes a liquid crystal display device, a light emitting device including a light emitting element represented by an organic light emitting element in each pixel, electronic paper, DMD (Digital Micromirror Device), PDP (Plasma Display Panel), FED (Field Emission) A display device having an integrated circuit in a circuit such as Display) is included in the category.

Note that in describing the structure of the invention with reference to the drawings, the same reference numerals may be used in common in different drawings. In addition, when referring to the same thing, a hatch pattern is made the same and there is a case where it does not attach a code in particular.

The structures described in the following embodiments can be applied to, combined with, or replaced with the other structures described in the embodiments as appropriate, according to one embodiment of the present invention.

Note that the size, the thickness of films (layers), or regions in drawings is sometimes exaggerated for simplicity.

Note that in this specification, the expression “film” and the expression “layer” can be interchanged with each other.

The ordinal numbers attached as the first and second are used for convenience and do not indicate the order of steps or the order of lamination. Therefore, for example, the description can be made by appropriately replacing “first” with “second” or “third”. In addition, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one embodiment of the present invention.

In addition, in this specification and the like, when it is explicitly described that X and Y are connected, X and Y are electrically connected, and X and Y function. And the case where X and Y are directly connected are disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or text, and anything other than the connection relation shown in the figure or text is also described in the figure or text.

Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

As an example of the case where X and Y are directly connected, an element that enables electrical connection between X and Y (for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display, etc.) Element, light emitting element, load, etc.) are not connected between X and Y, and elements (for example, switches, transistors, capacitive elements, inductors) that enable electrical connection between X and Y X and Y are not connected via a resistor element, a diode, a display element, a light emitting element, a load, or the like.

As an example of the case where X and Y are electrically connected, an element (for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display, etc.) that enables electrical connection between X and Y is shown. More than one element, light emitting element, load, etc.) can be connected between X and Y. Note that the switch has a function of controlling on / off. That is, the switch is in a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether or not to pass a current. Alternatively, the switch has a function of selecting and switching a path through which a current flows. Note that the case where X and Y are electrically connected includes the case where X and Y are directly connected.

As an example of the case where X and Y are functionally connected, a circuit (for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.) that enables a functional connection between X and Y, signal conversion, etc. Circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit that changes signal potential level, etc.), voltage source, current source, switching Circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier, differential amplifier circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, memory circuit, control circuit, etc.) One or more can be connected between them. As an example, even if another circuit is interposed between X and Y, if the signal output from X is transmitted to Y, X and Y are functionally connected. To do. Note that the case where X and Y are functionally connected includes the case where X and Y are directly connected and the case where X and Y are electrically connected.

In addition, when it is explicitly described that X and Y are electrically connected, a case where X and Y are electrically connected (that is, there is a separate connection between X and Y). And when X and Y are functionally connected (that is, functionally connected with another circuit between X and Y) And the case where X and Y are directly connected (that is, the case where another element or another circuit is not connected between X and Y). It shall be disclosed in the document. In other words, when it is explicitly described that it is electrically connected, the same contents as when it is explicitly described only that it is connected are disclosed in this specification and the like. It is assumed that

In addition, even in the case where the components shown in the drawing are shown as being electrically connected to each other, one component may have the functions of a plurality of components. is there. For example, in the case where part of the wiring also functions as an electrode, one conductive film has both the functions of both the wiring function and the electrode function. Therefore, the term “electrically connected” in this specification includes in its category such a case where one conductive film has functions of a plurality of components.

Note that even when “semiconductor” is described, for example, when the conductivity is sufficiently low, the semiconductor device may have characteristics as an “insulator”. In addition, the boundary between “semiconductor” and “insulator” is ambiguous and may not be strictly discriminated. Therefore, a “semiconductor” in this specification can be called an “insulator” in some cases. Similarly, an “insulator” in this specification can be called a “semiconductor” in some cases.

In addition, even when “semiconductor” is described, for example, when the conductivity is sufficiently high, the semiconductor device may have characteristics as a “conductor”. In addition, the boundary between “semiconductor” and “conductor” is ambiguous, and there are cases where it cannot be strictly distinguished. Therefore, a “semiconductor” in this specification can be called a “conductor” in some cases. Similarly, a “conductor” in this specification can be called a “semiconductor” in some cases.

The term “insulator” can also be referred to as an insulating film or an insulating layer. The description of a conductor can also be referred to as a conductive film or a conductive layer. The term “semiconductor” can also be referred to as a semiconductor film or a semiconductor layer.

Note that the impurity of the semiconductor means, for example, a component other than the main component constituting the semiconductor. For example, an element having a concentration of less than 0.1 atomic% is an impurity. When impurities are included, for example, DOS (Density of State) may be formed in the semiconductor, carrier mobility may be reduced, or crystallinity may be reduced. When the semiconductor is an oxide semiconductor, examples of impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 14 elements, Group 15 elements, and transition metals other than the main component. In particular, for example, hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen and the like. In the case of an oxide semiconductor, oxygen vacancies may be formed by mixing impurities such as hydrogen, for example. In the case where the semiconductor is a silicon layer, examples of impurities that change the characteristics of the semiconductor include group 1 elements, group 2 elements, group 13 elements, and group 15 elements excluding oxygen and hydrogen.

Further, in this specification, when A is described as having a region having a size B, a length B, a thickness B, or a width B, for example, the entire region in which A is a size B, a length B, When the thickness is B or the width B, the average value in the region with A is the size B and the length B, and when the thickness is the thickness B or the width B, the median value in the region with the A is the size B and the length. If B, thickness B, or width B, the maximum value in a region of A is size B, length B, thickness B, or width B, and the minimum value in a region of A is size B, When the length B, the thickness B or the width B is a convergence value in a certain region A is the size B, the length B, the thickness B or the width B, a probable value of A itself is obtained in the measurement. The case where the region to be formed is a size B, a length B, a thickness B, or a width B is included.

Note that the channel length refers to, for example, a region where a semiconductor (or a portion where current flows in the semiconductor when the transistor is on) and a gate electrode overlap with each other in a top view of the transistor, or a region where a channel is formed The distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in FIG. Note that in one transistor, the channel length is not necessarily the same in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

The channel width is, for example, a region in which a semiconductor (or a portion in which a current flows in the semiconductor when the transistor is on) and a gate electrode overlap each other, or a source and a drain in a region where a channel is formed. This is the length of the part. Note that in one transistor, the channel width is not necessarily the same in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

Note that depending on the structure of the transistor, the channel width in a region where a channel is actually formed (hereinafter referred to as an effective channel width) and the channel width shown in a top view of the transistor (hereinafter, apparent channel width). May be different). For example, in a transistor having a three-dimensional structure, the effective channel width is larger than the apparent channel width shown in the top view of the transistor, and the influence may not be negligible. For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may be large. In that case, the effective channel width in which the channel is actually formed is larger than the apparent channel width shown in the top view.

By the way, in a transistor having a three-dimensional structure, it may be difficult to estimate an effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, it is difficult to accurately measure the effective channel width when the shape of the semiconductor is not accurately known.

Therefore, in this specification, in the top view of a transistor, an apparent channel width which is a length of a portion where a source and a drain face each other in a region where a semiconductor and a gate electrode overlap with each other is expressed as “enclosed channel width ( SCW: Surrounded Channel Width). In this specification, in the case where the term “channel width” is simply used, it may denote an enclosed channel width or an apparent channel width. Alternatively, in this specification, in the case where the term “channel width” is simply used, it may denote an effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, enclosed channel width, and the like can be determined by obtaining a cross-sectional TEM image and analyzing the image. it can.

Note that in the case where the field-effect mobility of a transistor, the current value per channel width, and the like are calculated and calculated, the calculation may be performed using the enclosed channel width. In that case, the value may be different from that calculated using the effective channel width.

(Embodiment 1)
In this embodiment, a structure of a semiconductor device according to one embodiment of the present invention will be described with reference to drawings.

<Basic configuration of semiconductor device>
A structure of a memory device is described below as an example of a semiconductor device according to one embodiment of the present invention.

FIG. 1A illustrates an example of a circuit configuration of the memory cell 11 included in the memory device of one embodiment of the present invention. The memory cell 11 includes a transistor 12, a capacitor 13, a wiring BL, a wiring WL, and a wiring PL. Note that although the transistor 12 is an n-channel transistor in FIG. 1A, it may be a p-channel transistor.

In this specification, an n-channel transistor may be referred to as an n-ch transistor, and a p-channel transistor may be referred to as a p-ch transistor.

One of the source and the drain of the transistor 12 is electrically connected to the first electrode of the capacitor 13. The other of the source and the drain of the transistor 12 is electrically connected to the wiring BL. A gate of the transistor 12 is electrically connected to the wiring WL. The second electrode of the capacitor 13 is electrically connected to the wiring PL.

The transistor 12 has a function of controlling data writing to and data reading from the capacitor 13. The capacitor 13 has a function of holding data.

The wiring BL transmits a potential corresponding to data written to the memory cell 11 (hereinafter also referred to as a write potential) or a potential corresponding to data read from the memory cell 11 (hereinafter also referred to as a read potential). As a function. The wiring WL functions as a word line for selecting the memory cell 11 from which data is written or read. The wiring PL functions as a power supply line, and can apply an L level potential, for example.

In this specification, the H level indicates a high potential, and the L level indicates a low potential. The L level can be set to, for example, a ground potential.

Here, by reducing the off-state current of the transistor 12, the retention time of data written in the capacitor 13 can be extended. Here, off-state current refers to current that flows between a source and a drain when a transistor is off. In the case where the transistor is an n-ch type, for example, if the threshold voltage is about 0 V to 2 V, the current flowing between the source and the drain when the gate voltage is negative with respect to the source voltage Can be referred to as off-current. Also, the extremely small off-state current means that, for example, the off-current per channel width of 1 μm is 100 zA (zeptoampere) or less. Since the smaller off current is more preferable, this normalized off current is preferably 10 zA / μm or less, or 1 zA / μm or less, and more preferably 10 yA (Yoctoampere) / μm or less. 1zA is 1 × 10 ⁻²¹ A and 1yA is 1 × 10 ⁻²⁴ A.

In this manner, in order to reduce off-state current extremely, a channel formation region of a transistor may be formed using a semiconductor having a wide band gap. As such a semiconductor, for example, an oxide semiconductor can be given. Since the band gap of an oxide semiconductor is 3.0 eV or more, a transistor (an OS transistor) in which an active layer or an active region is formed using an oxide semiconductor has a small leakage current due to thermal excitation and an extremely small off-state current. The channel formation region of the OS transistor is preferably an oxide semiconductor containing at least one of indium (In) and zinc (Zn). As such an oxide semiconductor, an In-M-Zn oxide (the element M is typically Al, Ga, Y, Nd, Sn, Ti, Zr, La, Ce, Hf, Si, or the like) is typical. . By reducing impurities such as moisture or hydrogen that are electron donors (donors) and reducing oxygen vacancies, an oxide semiconductor can be i-type (intrinsic semiconductor) or can be made as close to i-type as possible. . Here, such an oxide semiconductor can be referred to as a highly purified oxide semiconductor. By using the highly purified oxide semiconductor, the off-state current of the OS transistor normalized by the channel width can be reduced to about several yA / μm to several zA / μm.

In addition, an OS transistor has less temperature dependency of off-state current characteristics than a transistor in which an active layer or an active region is formed using an oxide semiconductor (hereinafter referred to as a Si transistor). Therefore, the normalized off-state current of the OS transistor can be set to 100 zA or less even at a high temperature (for example, 100 ° C. or higher). Therefore, by applying an OS transistor to the transistor 12, data written in the capacitor 13 can be held for a long time even in a high temperature environment. Therefore, a semiconductor device with high reliability can be obtained even in a high temperature environment.

FIG. 1B shows a configuration example of the cell array 10. The cell array 10 is configured by arranging the memory cells 11 in a matrix.

The memory cells 11 in the same column are electrically connected by one wiring BL and one wiring PL. The memory cells 11 in the same row are electrically connected by one wiring WL.

FIG. 2A is a top view illustrating a configuration example of the memory cell 11 illustrated in FIG. FIG. 2B is a cross-sectional view corresponding to the dashed-dotted line A1-A2 in FIG. FIG. 2C illustrates a cross-sectional view corresponding to the dashed-dotted line A3-A4 in FIG.

As described above, the memory cell 11 includes the transistor 12, the capacitor 13, the wiring BL, and the wiring WL. The memory cell 11 includes an insulator 110, a conductor 111, a conductor 112, an insulator 113, a semiconductor 114, a conductor 115, a conductor 116, an insulator 117, and a conductor 118. And an insulator 119 and an insulator 121. The insulator 119 and the insulator 121 are provided with an opening reaching the conductor 116 and an opening reaching the conductor 118. In the opening reaching the conductor 116, the wiring BL is formed. Conductors 124 are respectively provided in the openings reaching the conductor 118.

Note that a conductor is not necessarily used for the conductor 112.

In FIG. 2A, the conductor 111, the insulator 113, the semiconductor 114, the insulator 117, the insulator 119, the insulator 121, and the like are not illustrated.

As shown in FIG. 2A, the conductor 116 is provided in a circular shape, and the conductor 111, the conductor 112, the semiconductor 114, the conductor 115, and the conductor are provided outside the conductor 116 so as to surround the conductor 116. A body 118 is provided concentrically.

2B and 2C, the conductor 111 and the conductor 112 are in contact with the insulator 110, the insulator 113 is in contact with the insulator 110, the conductor 111, and the conductor 112, and the semiconductor 114 is insulated. The conductor 115 is in contact with the insulator 113 and the semiconductor 114, the conductor 116 is in contact with the semiconductor 114, the insulator 117 is in contact with the insulator 113, the semiconductor 114, the conductor 115, and the conductor 116, and the conductor 118 is in contact with the insulator 117, the insulator 119 is in contact with the insulator 117 and the conductor 118, and the insulator 121 is in contact with the insulator 119. Note that the conductor 115 has a region overlapping with the conductor 112, and the conductor 118 has a region overlapping with the conductor 111.

Note that although not illustrated, the wiring PL illustrated in FIG. 1A is electrically connected to the conductor 112. Although not illustrated, an insulator is provided between the conductor 124 and the wiring WL. The insulator is provided with an opening, and the conductor 124 and the wiring WL are electrically connected through the opening.

The conductor 111 functions as a back gate of the transistor 12. The conductor 112 functions as a second electrode of the capacitor 13. The insulator 113 functions as a gate insulating film for the back gate of the transistor 12 and a dielectric of the capacitor 13. The semiconductor 114 functions as a channel of the transistor 12. The conductor 115 functions as one of the source and the drain of the transistor 12 and the first electrode of the capacitor 13. The conductor 116 functions as the other of the source and the drain of the transistor 12.

The conductor 118 has a function as a gate of the transistor 12, and the insulator 117 has a function as a gate insulating film with respect to the gate. The insulator 119 functions as a protective insulating film for the transistor 12 and the capacitor 13.

By providing the transistor 111 with the conductor 111 functioning as a back gate, the threshold voltage of the transistor 12 can be controlled. By controlling the threshold voltage, the current flowing between the source and drain of the transistor 12 is reduced when the potential applied to the conductor 118 is low, for example, when the applied potential is 0 V or less. Can do. That is, the off-state current of the transistor 12 can be reduced.

Further, the semiconductor 114 can be electrically surrounded by the electric fields of the conductor 111 and the conductor 118. Note that a transistor structure that electrically surrounds a semiconductor with an electric field generated from a conductor is referred to as a surrounded channel (s-channel) structure. Therefore, a channel is formed in the entire semiconductor 114 (upper surface, lower surface, and side surface). In the s-channel structure, a large current can flow between the source and the drain of the transistor, and an on-current that is a current at the time of conduction can be increased.

Note that in the case where the transistor has an s-channel structure, a channel is also formed on the side surface of the semiconductor 114. Therefore, the thicker the semiconductor 114, the larger the channel region. That is, the thicker the semiconductor 114, the higher the on-state current of the transistor. In addition, the thicker the semiconductor 114, the higher the ratio of regions with high carrier controllability, so that the subthreshold swing value can be reduced. For example, the semiconductor 114 may have a region with a thickness of 10 nm or more, preferably 20 nm or more, and more preferably 30 nm or more. However, since the productivity of the semiconductor device may be reduced, for example, the semiconductor 114 having a region with a thickness of 150 nm or less may be used.

Since a high on-state current can be obtained, the s-channel structure can be said to be a structure suitable for a miniaturized transistor. Since a transistor can be miniaturized, a semiconductor device including the transistor can be a highly integrated semiconductor device with high integration. For example, the transistor has a region with a channel length of preferably 40 nm or less, more preferably 30 nm or less, more preferably 20 nm or less, and the transistor has a channel width of preferably 40 nm or less, more preferably 30 nm or less, and more. Preferably, it has a region of 20 nm or less.

The conductor 111 may be connected to a wiring or a terminal to which a predetermined potential is supplied. For example, the conductor 111 may be connected to a wiring to which a constant potential is supplied. The constant potential can be an H level potential, an L level potential, or the like. Further, the conductor 111 may be electrically connected to the conductor 118.

In one embodiment of the present invention, by increasing the height of the conductor 112, the area of the capacitor 13 in which charge can be stored can be increased. Thereby, the storage capacity of the capacitive element 13 can be increased. Note that the height of the conductor 112 is preferably higher than the height of the insulator 113, for example. Further, the height of the conductor 112 is preferably, for example, not less than 100 nm and not more than 500 nm.

In this specification, the height of the conductor 112 refers to the height from the surface of the insulator 110 to the apex of the conductor 112.

In one embodiment of the present invention, the conductor 111 and the conductor 112 can be formed in the same step by forming the transistor 12 and the capacitor 13 in the same layer. One of the source and the drain of the transistor 12 and the first electrode of the capacitor 13 can be formed as the conductor 115 at the same time. Through the above steps, the manufacturing process of the semiconductor device of one embodiment of the present invention can be simplified, and the price of the semiconductor device of one embodiment of the present invention can be reduced.

Note that since the conductor 111 and the conductor 112 are formed in the same step, the height of the conductor 111 is equal to the height of the conductor 112. The conductor 111 and the conductor 112 are made of the same material.

In this specification, the heights of X and Y being equal represent that the height of Y is 90% or more and 110% or less of the height of X. For example, in the case where the height of the conductor 111 is 150 nm, it can be said that the conductor 111 and the conductor 112 are equal in height if the height of the conductor 112 is 135 nm or more and 165 nm or less.

Note that the memory cell 11 having the structure illustrated in FIG. 2 has a structure in which one capacitor 13 has one conductor 112. However, one capacitor 13 may have two or more conductors 112. By increasing the number of conductors 112 included in one capacitor 13, the storage capacity of the capacitor 13 can be increased.

2B and 2C, each conductor and each insulator are formed substantially perpendicular to the upper surface of the insulator 110 in addition to the semiconductor 114. And may have a taper.

The wiring PL illustrated in FIG. 1A can be provided in the same layer as the wiring BL, for example, as illustrated in FIG. 3B is a cross-sectional view corresponding to the dashed-dotted line B1-B2 in the top view in FIG. 3A, and FIG. 3C is the dashed-dotted line B3 in the top view in FIG. It is sectional drawing corresponding to -B4. In the memory cell 11 having the structure, although not shown, an opening is provided in the insulator 119, and the conductor 112 and the wiring PL are electrically connected through the opening.

Note that the wiring PL may be electrically connected to the conductor 111.

Note that the wiring PL can be provided in any layer. For example, the wiring PL may be provided below the layer having the conductor 112, for example. Alternatively, the wiring BL and the wiring PL may be overlapped.

In the memory cell 11 having the structure shown in FIGS. 2B and 2C, the insulator 113 is not flattened. However, the insulator 113 may be flattened as shown in FIGS. 4A is a cross-sectional view corresponding to the dashed-dotted line A1-A2 in FIG. 2A, and FIG. 4B is a cross-sectional view corresponding to the dashed-dotted line A3-A4 in FIG. With the structure illustrated in FIGS. 4A and 4B, the semiconductor 114 can be formed flat.

Further, as illustrated in FIGS. 4C and 4D, a structure without the conductor 111 may be employed. 4C is a cross-sectional view corresponding to the dashed-dotted line A1-A2 in FIG. 2A, and FIG. 4D is a cross-sectional view corresponding to the dashed-dotted line A3-A4 in FIG. With the structure shown in FIGS. 4C and 4D, the number of necessary wirings can be reduced. Accordingly, the semiconductor device of one embodiment of the present invention can be reduced in size.

In addition, the memory cell 11 having the structure illustrated in FIGS. 2B and 2C does not have a conductor that overlaps with the conductor 116 below the conductor 116, but the memory cell 11 illustrated in FIGS. As shown, a structure having a conductor 125 may be used. 5A is a cross-sectional view corresponding to the dashed-dotted line A1-A2 in FIG. 2A, and FIG. 5B is a cross-sectional view corresponding to the dashed-dotted line A3-A4 in FIG. The conductor 116 has a region overlapping with the conductor 125. Although not shown, the conductor 125 can be electrically connected to the wiring BL, for example.

In addition, as shown in FIGS. 5C and 5D, the semiconductor 114 included in the memory cell 11 having the structure illustrated in FIGS. 2B and 2C includes three layers of an insulator 114a, a semiconductor 114b, and an insulator 114c. It is good also as a structure. 5C is a cross-sectional view corresponding to the dashed-dotted line A1-A2 in FIG. 2A, and FIG. 5D is a cross-sectional view corresponding to the dashed-dotted line A3-A4 in FIG.

Note that the insulator 114a and the insulator 114c may be formed using a substance that can function as a conductor, a semiconductor, or an insulator when used alone. However, when a transistor is formed by stacking with the semiconductor 114b, electrons flow in the vicinity of the semiconductor 114b, the interface between the semiconductor 114b and the insulator 114a, and the vicinity of the interface between the semiconductor 114b and the insulator 114c, and the insulator 114a and the insulator 114c The transistor does not function as a channel of the transistor. Therefore, in this specification, the insulator 114a and the insulator 114c are not described as semiconductors but are described as insulators. Note that the insulators 114a and 114c are described as insulators only because they have a function similar to that of an insulator in terms of function of a transistor compared to the semiconductor 114b. Therefore, a substance that can be used for the semiconductor 114b may be used for the insulator 114a and the insulator 114c.

5C and 5D, the insulator 114a is in contact with the insulator 113, the semiconductor 114b is in contact with the insulator 114a, the conductor 115 is in contact with the insulator 113 and the semiconductor 114b, and the conductor 116 is The insulator 114c is in contact with the insulator 114, the semiconductor 114b, the conductor 115, and the conductor 116, and the insulator 117 is in contact with the insulator 114c. With such a configuration, for example, the on-current of the transistor 12 can be increased, as will be described in detail later.

In addition, in the memory cell 11 having the structure shown in FIGS. 2B and 2C, the semiconductor 114 has a region overlapping with the conductor 112, but the overlapping region as shown in FIGS. 6A and 6B. May not be included. 6A is a cross-sectional view corresponding to the dashed-dotted line A1-A2 in FIG. 2A, and FIG. 6B is a cross-sectional view corresponding to the dashed-dotted line A3-A4 in FIG. With the structure shown in FIGS. 6A and 6B, the storage capacitor of the capacitor 13 can be increased.

2B and 2C has a structure in which the conductor 118 is in contact with the insulator 119. As shown in FIGS. 6C and 6D, the conductor 118 The insulator 120 may be provided between the insulator 119 and the insulator 119. 6C is a cross-sectional view corresponding to the dashed-dotted line A1-A2 in FIG. 2A, and FIG. 6D is a cross-sectional view corresponding to the dashed-dotted line A3-A4 in FIG. 6C and 6D, oxidation of the conductor 118 can be suppressed, and the reliability of the semiconductor device of one embodiment of the present invention can be improved.

2A, 2B, and 2C have a structure in which the conductor 115 and the conductor 118 do not overlap with each other. However, the memory cell 11 illustrated in FIGS. , (C), the conductor 115 and the conductor 118 may overlap each other. 7B is a cross-sectional view corresponding to the dashed-dotted line C1-C2 in the top view in FIG. 7A, and FIG. 7C is the dashed-dotted line C3 in the top view in FIG. It is sectional drawing corresponding to -C4.

In the structure illustrated in FIGS. 2A, 2B, and 2C, there is a region where the semiconductor 114 does not overlap with either the conductor 115 or the conductor 118, and the region may be a high resistance region. On the other hand, in the configuration shown in FIGS. 7A, 7B, and 7C, the region does not exist. Therefore, the on-state current of the transistor 12 can be increased.

Further, the memory cell 11 may have a structure shown in FIGS. 8A, 8B, and 8C. FIG. 8A is a top view illustrating a configuration example of the memory cell 11 illustrated in FIG. FIG. 8B is a cross-sectional view corresponding to the dashed-dotted line D1-D2 in FIG. FIG. 8C is a cross-sectional view corresponding to the dashed-dotted line D3-D4 in FIG.

When the memory cell 11 having the structure illustrated in FIGS. 8A, 8 </ b> B, and 8 </ b> C is manufactured, after the semiconductor 114 and the first conductor to be the conductor 115 and the conductor 116 are formed, An insulator 119 is formed. Then, as shown in FIGS. 8B and 8C, an opening reaching the semiconductor 114 is formed in the first conductor and the insulator 119. Next, the insulator 117 and the conductor 118 are formed in the opening. As a result, the conductor 118 and the conductor 111 have regions that overlap with each other with the insulator 113, the semiconductor 114, and the insulator 117 interposed therebetween. After that, the insulator 126 is formed.

In the memory cell having the structure illustrated in FIGS. 8A, 8 </ b> B, and 8 </ b> C, the conductor 115 and the conductor 116, the conductor 118 can be formed, and lithography can be performed once. Accordingly, the manufacturing process of the semiconductor device of one embodiment of the present invention can be simplified, and the price of the semiconductor device of one embodiment of the present invention can be reduced.

Further, the memory cell 11 may have a structure shown in FIGS. 9A, 9B, and 9C. FIG. 9A is a top view illustrating a configuration example of the memory cell 11 illustrated in FIG. FIG. 9B is a cross-sectional view corresponding to the dashed-dotted line E1-E2 in FIG. FIG. 9C is a cross-sectional view corresponding to the dashed-dotted line E3-E4 in FIG.

9A, 9B, and 9C illustrate the conductor 111, the conductor 112, the semiconductor 114, and the conductor 115 from the memory cell 11 having the structure illustrated in FIGS. 2A, 2B, and 2C. 2 is a configuration example of the memory cell 11 when a part of the conductor 118 is removed. 9B is a cross-sectional view including a portion where the above-described conductor and semiconductor 114 are removed, and FIG. 9C is a cross-sectional view including a portion where the above-described conductor and semiconductor 114 are removed.

By configuring the memory cell 11 as shown in FIGS. 9A, 9B, and 9C, the wiring BL does not overlap with the above-described other conductors, so that the parasitic capacitance of the wiring BL is reduced. Can be reduced. Accordingly, the operation of the semiconductor device of one embodiment of the present invention can be speeded up. In addition, errors in reading data held in the memory cell 11 can be reduced. Note that in the memory cell 11 having the structure illustrated in FIGS. 9A, 9 </ b> B, and 9 </ b> C, the conductor 116 and the wiring BL can be electrically connected in the same layer.

9A, 9B, and 9C show examples of the structure of the memory cell 11 in the case where both the conductor of the transistor 12 and the conductor of the capacitor 13 are removed. One aspect of this is not limited to this. For example, the conductor 112 included in the capacitor 13 and the semiconductor 114 and the conductor 115 in the region included in the capacitor 13 are removed, and the conductor 111 and the conductor 118 included in the transistor 12 and the semiconductor in the region included in the transistor 12 are removed. 114 and the conductor 115 may not be removed. For example, the conductor 111 and the conductor 118 included in the transistor 12 and only the semiconductor 114 and the conductor 115 in the region included in the transistor 12 are removed, and the conductor 112 included in the capacitor 13 and the region included in the capacitor 13 are removed. The semiconductor 114 and the conductor 115 may not be removed.

In FIG. 9A, the conductor 118, the conductor 124, and the wiring WL are formed in different layers, but the conductor 124 does not overlap with the conductor 112, the semiconductor 114, and the conductor 115. In the structure, as shown in FIG. 10A, the conductor 118, the conductor 124, and the wiring WL may be formed in the same layer. 10B is a cross-sectional view corresponding to the dashed-dotted line E1-E2 in FIG. 10A, and FIG. 10C is a cross-sectional view corresponding to the dashed-dotted line E3-E4 in FIG.

Alternatively, the conductor 118 and the conductor 124 may be formed in the same layer, and the wiring WL may be formed in a different layer from the conductor 118 and the conductor 124. With the above structure, the manufacturing process of the semiconductor device of one embodiment of the present invention can be simplified, and the price of the semiconductor device of one embodiment of the present invention can be reduced.

In the memory cell 11 having the structure shown in FIG. 9A, the conductor 111, the conductor 112, the semiconductor 114, the conductor 115, and the conductor 118 are removed one by one. As shown in FIG. Alternatively, two locations may be removed. Further, as shown in FIG. 12 (A), four portions may be removed. Further, as shown in FIG. 13, eight portions may be removed. Further, n points (n is a natural number) may be removed.

11B is a cross-sectional view corresponding to the dashed-dotted line G1-G2 in the top view in FIG. 11A, and FIG. 11C is a point in the top view in FIG. 11A. It is sectional drawing corresponding to chain line G4-G4. 12B is a cross-sectional view corresponding to the dashed-dotted line H1-H2 in the top view in FIG. 12A, and FIG. 12C is a point in the top view in FIG. It is sectional drawing corresponding to chain line H3-H4.

In the structure shown in FIG. 11A, two memory cells 11 are formed in a semicircular shape. In the configuration shown in FIG. 12A, four memory cells 11 are formed in a quadrant. In the configuration shown in FIG. 13, eight memory cells 11 are formed in an octant shape. Further, in the case of removing each of the conductor 111, the conductor 112, the semiconductor 114, the conductor 115, and the conductor 118, n pieces of sector-shaped memory cells 11 having a central angle of (360 / n) ° are formed. Is done.

Note that the memory cells 11 illustrated in FIGS. 11 to 13 are electrically connected to each other by one wiring BL. Further, when n fan-shaped memory cells 11 having a central angle of (360 / n) ° are provided, the n memory cells 11 can be electrically connected to each other by one wiring BL.

In addition, the conductor 118 included in the memory cell 11 illustrated in FIGS. 11 to 13 is electrically connected to different wirings WL through different conductors 124. That is, when n memory cells 11 are provided and they are electrically connected to each other by one wiring BL, n conductors 124 and wirings WL are provided, respectively.

With the above configuration, the memory cells 11 can be arranged more efficiently than the case where only one memory cell 11 is formed in a circular shape as shown in FIGS. That is, the degree of integration of the memory cell 11 can be increased. Accordingly, the storage capacity per unit area of the semiconductor device of one embodiment of the present invention can be increased.

11 to 13 show the case where the central angles are equal in each memory cell 11, the central angles need not be equal.

The semiconductor device of one embodiment of the present invention can have a structure in which the conductor 124 does not overlap with the conductor 111, the conductor 112, and the conductor 115. FIG. 14A shows a structure in which eight octant memory cells 11 as shown in FIG. 13 are formed, in which the conductor 124 does not overlap with the conductor 111, the conductor 112, and the conductor 115. A top view of the memory cell 11 is shown. FIG. 14B is a cross-sectional view corresponding to the dashed-dotted line I1-I2 in FIG. FIG. 14C is a cross-sectional view corresponding to the dashed-dotted line I3-I4 in FIG.

With the structure shown in FIGS. 14A and 14C, the parasitic capacitance of the conductor 124 can be reduced. Accordingly, the operation of the semiconductor device of one embodiment of the present invention can be speeded up. In addition, errors in reading data held in the memory cell 11 can be reduced.

In the memory cell 11 having the structure shown in FIGS. 2 to 14, the conductor 116 is provided in a circular shape, and the conductor 111, the conductor 112, the semiconductor 114, and the conductor are provided outside the conductor 116 so as to surround the conductor 116. 115 and the conductor 118 are concentrically arranged; however, one embodiment of the present invention is not limited thereto, and each conductor and the semiconductor 114 included in the memory cell 11 can have any shape. For example, the conductor 116 is provided in an elliptical shape, a quadrangular shape, or an m-square shape (m is an integer of 3 or more), and the conductor 111, the conductor 112, and the semiconductor 114 are provided outside the conductor 116 so as to surround the conductor 116. The conductor 115 and the conductor 118 may be provided. 2 (A), FIG. 3 (A), FIG. 7 (A), FIG. 8 (A), FIG. 9 (A), FIG. 10 (A), FIG. 11 (A), and FIG. In the memory cell 11, the conductor 116 has a square shape, and the conductor 111, the conductor 112, the semiconductor 114, the conductor 115, and the conductor 118 are provided in a trapezoid shape outside the conductor 116 so as to surround the conductor 116. FIGS. 15A, 15B, 15C, and 16D and FIGS. 16A, 16B, 16C, and 16D are respectively top views of the memory cell 11 in this case.

Note that in the memory cell 11 having the structure illustrated in FIG. 16D, the conductor 111, the conductor 112, the semiconductor 114, the conductor 115, and the conductor 118 on the straight line connecting the intersections of the square diagonal lines are removed. However, as shown in FIG. 16E, the above-described conductor and semiconductor 114 on a square diagonal may be removed.

Further, in the memory cell 11 having the structure illustrated in FIGS. 13 and 14A, the conductor 116 is square, and the conductor 111, the conductor 112, and the semiconductor 114 are formed outside the conductor 116 so as to surround the conductor 116. FIGS. 17A and 17B are top views of the memory cell 11 when the conductor 115 and the conductor 118 are provided in a trapezoidal shape.

Note that the conductor 111 and the semiconductor 114 are not shown in FIGS.

FIG. 18A illustrates an example of a top view of the capacitor 13 included in the memory cell 11 having the structure illustrated in FIGS. 2A, 2B, and 2C. FIG. 18B illustrates an example of a cross-sectional view corresponding to the dashed-dotted line J1-J2 in FIG. As shown in FIG. 18A, the conductor 112, the insulator 113, the semiconductor 114, and the conductor 115 included in the capacitor 13 can be formed in a square shape.

FIG. 18C illustrates another example of a top view of the capacitor 13 included in the memory cell 11 having the structure illustrated in FIGS. 2A, 2 </ b> B, and 2 </ b> C. FIG. 18D illustrates an example of a cross-sectional view corresponding to the dashed-dotted line K1-K2 in FIG. As shown in FIG. 18C, the conductor 112, the insulator 113, the semiconductor 114, and the conductor 115 included in the capacitor 13 can be formed concentrically. In addition, as illustrated in FIG. 18D, a mountain shape can be obtained in which the center of the circle is the top of the conductor 112, the insulator 113, the semiconductor 114, and the conductor 115 included in the capacitor 13. .

In the capacitor 13 having the structure illustrated in FIGS. 18A and 18C, the conductor 112 is surrounded by the conductor 115. With this structure, the area of the region where the conductor 112 and the conductor 115 overlap with each other is increased, so that the storage capacitor of the capacitor 13 can be increased.

Note that the shape of each element included in the capacitor 13 illustrated in FIGS. 18A to 18D is merely an example, and the shape of each element included in the capacitor 13 may be changed as long as the function is not impaired. Can do.

FIG. 19A illustrates an example of a circuit configuration in which the sense amplifier 31 is electrically connected to the memory cell 11 having the circuit configuration illustrated in FIG. The sense amplifier 31 is electrically connected to the wiring BL. The sense amplifier 31 has a function of amplifying a potential difference between a reference potential and a read potential and holding the amplified potential difference.

The memory cell 11 can be stacked on the sense amplifier 31. FIGS. 19B and 19C are examples of a stacked structure of the layer 36 including the sense amplifier 31 and the layer 16 including the memory cell 11, and a cross section when the layer 16 is provided on the layer 36. The figure is shown. Note that the sense amplifier 31 includes a transistor 35.

FIG. 19B corresponds to a channel length direction of the transistor 35 and a cross-sectional view of the memory cell 11 in the A1-A2 direction illustrated in FIG. FIG. 19C corresponds to a cross-sectional view in the channel width direction of the transistor 35 and in the A3-A4 direction of the memory cell 11 illustrated in FIG.

Note that the layer 36 may be provided above the layer 16. Further, the layer 16 and the layer 36 may be formed in the same plane without having a laminated structure.

The layer 36 includes a substrate 130 and a transistor 35, and the transistor 35 is provided over the substrate 130. The layer 36 includes an insulator 131, a low resistance region 132, a low resistance region 133, an insulator 134, an insulator 135, a conductor 136, an insulator 137, and an insulator 140.

A plurality of protrusions are formed on the substrate 130, and an insulator 131 is formed in a groove (also referred to as a trench) between the plurality of protrusions. An insulator 137 having an opening formed on the substrate 130 and the insulator 131 is provided. In the opening of the insulator 137, the insulator 134 is formed on the substrate 130 and the insulator 131, and the conductor 136 is formed on the insulator 134. An insulator 140 is formed over the conductor 136 and the insulator 137.

As shown in FIG. 19B, an opening of the insulator 137 is formed on at least a part of the convex portion of the substrate 130, and the insulator 135 is provided inside the opening of the insulator 137. An insulator 134 is provided inside the insulator 135, and a conductor 136 is provided inside the insulator 134. In addition, as illustrated in FIG. 19B, a low resistance region 133 is formed so as to overlap at least part of the insulator 135 in the convex portion of the substrate 130, and the low resistance region 132 is formed outside the low resistance region 133. It is formed. Note that the low resistance region 132 preferably has a lower resistance than the low resistance region 133.

The insulator 131 functions as an element isolation region. The low resistance region 132 functions as the source or drain of the transistor 35. The low resistance region 133 functions as an LDD (Lightly Doped Drain) region of the transistor 35. The insulator 134 functions as a gate insulating film of the transistor 35. The insulator 135 functions as a sidewall insulating film of the transistor 35. The conductor 136 has a function as a gate electrode of the transistor 35. The insulator 140 functions as an interlayer insulating film between the layer 16 and the layer 36.

In addition, a region of the convex portion of the substrate 130 that overlaps with the conductor 136 and is located between the low-resistance regions 133 functions as a channel formation region of the transistor 35.

In the transistor 35, the side and upper portions of the protrusions in the channel formation region overlap with the conductor 136 with the insulator 134 interposed therebetween, so that carriers are generated in a wide range including the side and upper portions of the channel formation region. Flowing. Therefore, the amount of carriers that move in the transistor 35 can be increased while keeping the occupied area of the transistor 35 on the substrate small. As a result, the transistor 35 has an increased on-current and increased field effect mobility. In particular, when the length in the channel width direction (channel width) of the convex portion in the channel forming region is W and the height of the convex portion in the channel forming region is T, the ratio of the convex portion height T to the channel width W (T When the aspect ratio corresponding to / W) is high, the carrier flows in a wider range, so that the on-state current of the transistor 35 can be increased and the field-effect mobility can be further increased. For example, in the case of the transistor 35 using the bulk substrate 130, the aspect ratio is preferably 0.5 or more, and more preferably 1 or more.

The transistors illustrated in FIGS. 19B and 19C illustrate an example in which element isolation is performed using a trench isolation method (STI method); however, the semiconductor device described in this embodiment is not limited to this. It is not something that can be done.

19B and 19C illustrate an example in which one transistor 35 is provided in the layer 36, the semiconductor device described in this embodiment is not limited thereto. The configuration and number of transistors provided on the substrate 130 may be set as appropriate in accordance with the configuration of the sense amplifier 31.

19B and 19C, the insulator 140 has a single-layer structure; however, a structure in which a plurality of insulators are stacked may be used. The insulator 140 may be provided with a conductor. For example, a conductor having a function of electrically connecting the wiring BL and one of the source and the drain of the transistor 35 may be provided.

The layer 16 includes an insulator 141 in contact with the upper surface of the insulator 140 and an insulator 142 in contact with the upper surface of the insulator 141. The layer 16 includes a layer including the memory cell 11 on the insulator 142.

Note that the structure above the insulator 142 is similar to that in FIG. 2B in FIG. 19B and similar to FIG. 2C in FIG. 19C, but the structure above the insulator 142 is Any configuration described herein may be employed.

The insulator 141 and the insulator 142 are provided with openings, and wirings PL are provided in the openings.

The conductor 146 is electrically connected to the conductor 111. The conductor 146 has a function of controlling the potential of the conductor 111.

Note that the stacked configuration illustrated in FIGS. 19B and 19C is merely an example, and any configuration can be employed as long as the functions of the memory cell 11 and the sense amplifier 31 can be performed. For example, the channel width direction of the transistor 35 is parallel to the A1-A2 direction of the memory cell 11 illustrated in FIG. 2B, and the channel length direction of the transistor 35 is A3-A4 of the memory cell 11 illustrated in FIG. It may be parallel to the direction. Further, for example, the wiring PL may be formed in parallel with the A3-A4 direction, and for example, the conductor 146 may be formed in parallel with the A1-A2 direction.

In FIG. 19B, the wiring BL is provided over the transistor 12 and the capacitor 13. However, as illustrated in FIG. 20B, the wiring BL is formed between the layer 36, the transistor 12, and the capacitor 13. It is good also as a structure provided in between. FIG. 20A shows an example of a circuit configuration in which a sense amplifier 31 is electrically connected to the memory cell 11 having the circuit configuration shown in FIG. 20B corresponds to a channel length direction of the transistor 35 and a cross-sectional view of the memory cell 11 in the A1-A2 direction illustrated in FIG. 2B, similarly to FIG. 19B. 20C corresponds to the channel width direction of the transistor 35 and the cross-sectional view of the memory cell 11 in the A3-A4 direction illustrated in FIG. 2C, similarly to FIG. 19C.

20B and 20C, an insulator 144 that is in contact with the upper portion of the insulator 140 and an insulator 145 that is in contact with the upper portion of the insulator 144 are provided. An opening reaching the conductor 116 is provided in the insulator 144, the insulator 145, the insulator 141, the insulator 142, the insulator 113, and the semiconductor 114, and the wiring BL is provided in the opening.

With the structure illustrated in FIG. 20B, the wiring BL and the conductor 118 can be sufficiently separated. Accordingly, parasitic capacitance generated in the wiring BL can be reduced. Accordingly, the operation of the semiconductor device of one embodiment of the present invention can be speeded up. In addition, errors in reading data held in the memory cell 11 can be reduced.

The semiconductor device of one embodiment of the present invention can also be applied to the memory cell having the structure illustrated in FIG. A memory cell 51 illustrated in FIG. 21A includes a transistor 52, a capacitor 53, and a transistor 55.

One of the source and the drain of the transistor 52 is electrically connected to the first electrode of the capacitor 53 and the gate of the transistor 55. The other of the source and the drain of the transistor 52 is electrically connected to the wiring WBL. A gate of the transistor 52 is electrically connected to the wiring WL1. The second electrode of the capacitor 53 is electrically connected to the wiring WPL. One of a source and a drain of the transistor 55 is electrically connected to the wiring RBL. The other of the source and the drain of the transistor 55 is electrically connected to the wiring RPL.

The transistor 52 has a function of controlling data writing to the capacitor 53. The capacitor 53 has a function of holding data.

The wiring WBL functions as a writing bit line for transmitting a writing potential. The wiring RBL functions as a read bit line that transmits a read potential. The wiring WPL and the wiring RPL have a function as power supply lines.

The transistor 52 and the capacitor 53 can have structures similar to those of the transistor 12 and the capacitor 13 illustrated in FIGS. 19A, 19B, and 19C. The transistor 55 can have a structure similar to that of the transistor 35 illustrated in FIGS. 19A, 19B, and 19C.

The transistor 55, the transistor 52, and the capacitor 53 can be stacked. 19B and 19C illustrate an example of a stacked structure of the layer 56 including the transistor 55 and the layer 57 including the transistor 52 and the capacitor 53, and the layer 57 is provided over the layer 56. FIG.

The insulator 150 included in the layer 56 corresponds to the insulator 140 included in the layer 36. Further, the layer 57 shown in FIGS. 21B and 21C corresponds to the layer 16 shown in FIGS. 19B and 19C. The insulator 151, the insulator 152, the insulator 153, the insulator 157, the insulator 159, and the insulator 161 included in the layer 57 are the insulator 141, the insulator 142, the insulator 113, the insulator 117, and the insulator included in the layer 16. It corresponds to the body 119 and the insulator 121, respectively.

The insulator 150, the insulator 151, the insulator 152, the insulator 153, the insulator 157, the insulator 159, and the insulator 161 are provided with openings, and the conductor 170 is provided in the openings. . One of the source and the drain of the transistor 52 and the first electrode of the capacitor 53 are electrically connected to the gate of the transistor 55 by the conductor 170.

The configurations shown in FIGS. 2 to 21 can be arbitrarily combined.

<Board>
Hereinafter, the substrate 130 will be described.

As the substrate 130, for example, a single semiconductor substrate such as silicon or germanium, or a semiconductor substrate such as silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide may be used. Preferably, a single crystal silicon substrate is used as the substrate 130. Further, as the substrate 130, a semiconductor substrate having an insulator region inside the substrate, for example, an SOI (Silicon On Insulator) substrate may be used.

As the substrate 130, for example, a semiconductor substrate having an impurity imparting p-type conductivity is used. Note that a semiconductor substrate having an impurity imparting n-type conductivity may be used as the substrate 130. Alternatively, the substrate 130 may be i-type.

The low resistance region 132 provided in the substrate 130 preferably contains an element imparting n-type conductivity such as phosphorus or arsenic or an element imparting p-type conductivity such as boron or aluminum. Similarly, the low resistance region 133 preferably includes an element imparting n-type conductivity such as phosphorus or arsenic, or an element imparting p-type conductivity such as boron or aluminum. However, since the low resistance region 133 preferably functions as an LDD, the concentration of the element imparting conductivity included in the low resistance region 133 is lower than the concentration of the element imparting conductivity included in the low resistance region 132. It is preferable. Note that the low resistance region 132 may be formed using silicide or the like.

<Conductor and wiring>
Hereinafter, a conductor and a wiring which are components of the semiconductor device of one embodiment of the present invention are described.

Examples of the conductor 111, the conductor 112, the conductor 115, the conductor 116, the conductor 118, the conductor 124, the wiring BL, the wiring WL, and the wiring PL include boron, nitrogen, oxygen, fluorine, silicon, phosphorus, and aluminum. Conductors containing one or more of titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum and tungsten are used in a single layer or in a stacked layer That's fine. For example, it may be an alloy or a compound, a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin and oxygen, a conductor containing titanium and nitrogen Etc. may be used. For example, tantalum nitrogen may be used.

As the conductor 136, it is preferable to use a metal selected from tantalum, tungsten, titanium, molybdenum, chromium, niobium, or the like, or an alloy material or a compound material containing these metals as a main component. Alternatively, polycrystalline silicon to which an impurity such as phosphorus is added can be used. Alternatively, the conductor 136 may be formed using a stacked structure of a metal nitride film and the above metal film. As the metal nitride, tungsten nitride, molybdenum nitride, or titanium nitride can be used. By providing the metal nitride film, the adhesion of the metal film can be improved and peeling can be prevented.

<Insulator>
The insulator that is a component of the semiconductor device of one embodiment of the present invention is described below.

Examples of the insulator 113, the insulator 117, and the insulator 119 include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, An insulator containing hafnium or tantalum may be used as a single layer or a stacked layer. For example, the insulator 113, the insulator 117, and the insulator 119 include aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, and lanthanum oxide. Neodymium oxide, hafnium oxide, or tantalum oxide may be used.

The insulator 113 and the insulator 117 may be insulators having excess oxygen. By providing the insulator 113 and the insulator 117 as described above, oxygen can be supplied from the insulator 113 and the insulator 117 to the semiconductor 114.

Note that in this specification and the like, excess oxygen refers to oxygen contained in excess of the stoichiometric composition, for example. Alternatively, excess oxygen refers to oxygen released from a film or layer containing the excess oxygen by heating, for example. Excess oxygen can move, for example, inside a film or layer. Excess oxygen may be moved between atoms of a film or layer, or may be moved in a rushing manner while replacing oxygen constituting the film or layer.

The insulator 113 having excess oxygen has a desorption amount of oxygen molecules in a surface temperature range of 100 ° C. or higher and 700 ° C. or lower or 100 ° C. or higher and 500 ° C. or lower by temperature programmed desorption gas spectroscopy analysis (TDS analysis). Is 1.0 × 10 ¹⁴ molecules / cm ² or more and 1.0 × 10 ¹⁶ molecules / cm ² or less, more preferably 1.0 × 10 ¹⁵ molecules / cm ² or more and 5.0 × 10 ¹⁵ molecules / cm ² or less. It becomes.

A method for measuring the amount of released molecules using TDS analysis will be described below using the amount of released oxygen as an example.

The total amount of gas released when the measurement sample is subjected to TDS analysis is proportional to the integrated value of the ionic strength of the released gas. The total amount of gas released can be calculated by comparison with a standard sample.

For example, from the TDS analysis result of a silicon substrate containing a predetermined density of hydrogen, which is a standard sample, and the TDS analysis result of the measurement sample, the amount of released oxygen molecules (N _O2 ) of the measurement sample is obtained by the following formula: Can do. Here, it is assumed that all the gases detected by the mass-to-charge ratio 32 obtained by TDS analysis are derived from oxygen molecules. The mass to charge ratio of CH ₃ OH is 32 but is not considered here as it is unlikely to exist. In addition, oxygen molecules containing oxygen atoms with a mass number of 17 and oxygen atoms with a mass number of 18 which are isotopes of oxygen atoms are not considered because the existence ratio in nature is extremely small.

N _O2 = N _H2 / S _H2 × S _O2 × α

N _H2 is a value obtained by converting hydrogen molecules desorbed from the standard sample by density. _SH2 is an integral value of ion intensity when the standard sample is subjected to TDS analysis. Here, the reference value of the standard sample is N _H2 / SH ₂ . S _O2 is an integrated value of ion intensity when the measurement sample is subjected to TDS analysis. α is a coefficient that affects the ionic strength in the TDS analysis. For details of the above formula, refer to JP-A-6-275697. The amount of released oxygen is measured using a temperature-programmed desorption analyzer EMD-WA1000S / W manufactured by Electronic Science Co., Ltd. and using a silicon substrate containing a certain amount of hydrogen atoms as a standard sample.

In TDS analysis, part of oxygen is detected as oxygen atoms. The ratio of oxygen molecules to oxygen atoms can be calculated from the ionization rate of oxygen molecules. Note that since the above α includes the ionization rate of oxygen molecules, the amount of released oxygen atoms can be estimated by evaluating the amount of released oxygen molecules.

Note that N _{2 O 2} is the amount of released oxygen molecules. The amount of release when converted to oxygen atoms is twice the amount of release of oxygen molecules.

Alternatively, the insulator from which oxygen is released by heat treatment may contain a peroxide radical. Specifically, it means that the spin density resulting from the peroxide radical is 5 × 10 ¹⁷ spins / cm ³ or more. Note that an insulator containing a peroxide radical may have an asymmetric signal with a g value near 2.01 by an electron spin resonance (ESR) method.

Examples of the insulator 120, the insulator 121, the insulator 137, the insulator 140, the insulator 141, the insulator 142, the insulator 144, and the insulator 145 include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, An insulator containing silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used as a single layer or a stacked layer.

One or more of the insulator 119, the insulator 120, the insulator 121, the insulator 140, the insulator 141, the insulator 142, the insulator 144, and the insulator 145 have a function of blocking impurities such as hydrogen and oxygen. It is preferable to have an insulator. By disposing an insulator having a function of blocking impurities such as hydrogen and oxygen below the transistor 12, electrical characteristics of the transistor 12 can be stabilized.

Examples of the insulator having a function of blocking impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, and lanthanum. An insulator containing neodymium, hafnium, or tantalum may be used as a single layer or a stacked layer.

The insulator 134 and the insulator 135 include, for example, aluminum oxide, aluminum oxynitride, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, An insulator including one or more selected from neodymium oxide, hafnium oxide, tantalum oxide, and the like can be used. Further, hafnium silicate (HfSi _x O _y (x> 0, y> 0)), hafnium silicate added with nitrogen (HfSi _x O _y N _z (x> 0, y> 0, z> 0)), nitrogen There added, hafnium aluminate _{(HfAl x O y N z (} x> 0, y> 0, z> 0)), may be used a high-k material such as hafnium oxide or yttrium oxide.

<Semiconductor>
Hereinafter, the semiconductor according to the present invention will be described.

The semiconductor preferably contains at least indium or zinc. In particular, it is preferable to contain indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, or the like is contained. Further, one kind or plural kinds selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like may be included.

Here, a case where the semiconductor includes indium, the element M, and zinc is considered. The element M is aluminum, gallium, yttrium, tin, or the like. Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, the element M may be a combination of a plurality of the aforementioned elements.

First, a preferable range of the atomic ratio of indium, element M, and zinc included in the semiconductor of the present invention will be described with reference to FIGS. 22A, 22B, and 22C. Note that FIG. 22 does not describe the atomic ratio of oxygen. The terms of the atomic ratio of indium, element M, and zinc of the semiconductor are [In], [M], and [Zn].

In FIGS. 22A, 22B, and 22C, a broken line indicates an atomic ratio of [In]: [M]: [Zn] = (1 + α) :( 1-α): 1. Line that satisfies (−1 ≦ α ≦ 1), [In]: [M]: [Zn] = (1 + α) :( 1-α): line that has an atomic ratio of 2 [In]: [M] : [Zn] = (1 + α): (1-α): a line having an atomic ratio of 3; [In]: [M]: [Zn] = (1 + α): (1-α): number of atoms of 4 A line to be a ratio and a line to have an atomic ratio of [In]: [M]: [Zn] = (1 + α) :( 1−α): 5.

A one-dot chain line is a line having an atomic ratio of [In]: [M]: [Zn] = 1: 1: β (β ≧ 0), [In]: [M]: [Zn] = 1: 2: A line with an atomic ratio of β, [In]: [M]: [Zn] = 1: 3: A line with an atomic ratio of β, [In]: [M]: [Zn] = 1: 4: Line with an atomic ratio of β, [In]: [M]: [Zn] = 2: 1: Line with an atomic ratio of β, and [In]: [M]: [Zn] = 5 : Represents a line with an atomic ratio of 1: β.

A two-dot chain line represents a line having an atomic ratio (−1 ≦ γ ≦ 1) of [In]: [M]: [Zn] = (1 + γ): 2: (1-γ). In addition, a semiconductor with an atomic ratio of [In]: [M]: [Zn] = 0: 2: 1 shown in FIG. 22 or a value close thereto tends to have a spinel crystal structure.

22A and 22B illustrate an example of a preferable range of the atomic ratio of indium, the element M, and zinc included in the semiconductor of one embodiment of the present invention.

As an example, FIG. 23 shows a crystal structure of InMZnO ₄ in which [In]: [M]: [Zn] = 1: 1: 1. FIG. 23 shows a crystal structure of InMZnO ₄ when observed from a direction parallel to the b-axis. Note that a metal element in a layer containing M, Zn, and oxygen (hereinafter referred to as an (M, Zn) layer) illustrated in FIG. 23 represents the element M or zinc. In this case, the ratio of the element M and zinc shall be equal. The element M and zinc can be substituted and the arrangement is irregular.

InMZnO ₄ has a layered crystal structure (also referred to as a layered structure). As shown in FIG. 23, a layer containing indium and oxygen (hereinafter referred to as an In layer) contains 1 element M, zinc, and oxygen. The (M, Zn) layer having 2 is 2.

Indium and element M can be substituted for each other. Therefore, the element M in the (M, Zn) layer can be replaced with indium and expressed as an (In, M, Zn) layer. In that case, a layered structure in which the In layer is 1 and the (In, M, Zn) layer is 2 is employed.

A semiconductor having an atomic ratio of [In]: [M]: [Zn] = 1: 1: 2 has a layered structure in which the In layer is 1 and the (M, Zn) layer is 3. That is, when [Zn] increases with respect to [In] and [M], when the semiconductor is crystallized, the ratio of the (M, Zn) layer to the In layer increases.

However, in the semiconductor, when the In layer is 1 and the (M, Zn) layer is a non-integer, the In layer is 1 and the (M, Zn) layer has an integer number of layers. There is. For example, when [In]: [M]: [Zn] = 1: 1: 1.5, a layered structure in which the In layer is 1 and the (M, Zn) layer is 2, and (M, Zn) ) There may be a layered structure in which a layered structure having three layers is mixed.

For example, when a semiconductor is formed using a sputtering apparatus, a film having an atomic ratio that deviates from the atomic ratio of the target is formed. In particular, depending on the substrate temperature during film formation, [Zn] of the film may be smaller than [Zn] of the target.

In addition, a plurality of phases may coexist in a semiconductor (two-phase coexistence, three-phase coexistence, etc.). For example, at an atomic ratio which is a value close to the atomic ratio of [In]: [M]: [Zn] = 0: 2: 1, two phases of a spinel crystal structure and a layered crystal structure coexist. Cheap. In addition, when the atomic ratio is a value close to the atomic ratio indicating [In]: [M]: [Zn] = 1: 0: 0, the biphasic crystal structure and the layered crystal structure have two phases. Easy to coexist. In the case where a plurality of phases coexist in a semiconductor, grain boundaries (also referred to as grain boundaries) may be formed between different crystal structures.

In addition, by increasing the indium content, the carrier mobility (electron mobility) of the semiconductor can be increased. This is because, in a semiconductor containing indium, element M and zinc, the s orbital of heavy metal mainly contributes to carrier conduction, and by increasing the indium content, the region where the s orbital overlaps becomes larger. This is because a semiconductor with a high content ratio of carrier has higher carrier mobility than a semiconductor with a low content ratio of indium.

On the other hand, when the content of indium and zinc in the semiconductor is lowered, the carrier mobility is lowered. Therefore, in the atomic number ratio indicating [In]: [M]: [Zn] = 0: 1: 0 and the atomic number ratio which is the vicinity thereof (for example, the region C shown in FIG. 22C), the insulating property Becomes higher.

Therefore, it is preferable that the semiconductor of one embodiment of the present invention have an atomic ratio shown in a region A in FIG. 22A that has a high carrier mobility and a low-boundary grain structure.

A region B shown in FIG. 22B shows [In]: [M]: [Zn] = 4: 2: 3 to 4.1 and its neighborhood values. The neighborhood value includes, for example, an atomic ratio of [In]: [M]: [Zn] = 5: 3: 4. A semiconductor having an atomic ratio indicated by the region B is an excellent semiconductor having high crystallinity and high carrier mobility.

Note that the conditions under which a semiconductor forms a layered structure are not uniquely determined by the atomic ratio. Depending on the atomic ratio, there is a difference in difficulty for forming a layered structure. On the other hand, even if the atomic ratio is the same, there may be a layered structure or a layered structure depending on the formation conditions. Therefore, the region shown in the figure is a region showing the atomic ratio in which the semiconductor has a layered structure, and the boundaries between the regions A to C are not strict.

Next, a case where the semiconductor is used for a transistor will be described.

Note that by using the semiconductor for a transistor, carrier scattering and the like at grain boundaries can be reduced; thus, a transistor with high field-effect mobility can be realized. In addition, a highly reliable transistor can be realized.

For the transistor, a semiconductor with low carrier density is preferably used. For example, the semiconductor has a carrier density of less than 8 × 10 ¹¹ / cm ³ , preferably less than 1 × 10 ¹¹ / cm ³ , more preferably less than 1 × 10 ¹⁰ / cm ³ , and 1 × 10 ⁻⁹ / cm ^3. That is all.

Note that a semiconductor with high purity intrinsic or substantially high purity intrinsic has few carrier generation sources, so that the carrier density can be lowered. In addition, since a semiconductor having high purity intrinsic or substantially high purity intrinsic has a low defect level density, the trap level density may be low.

In addition, the charge trapped in the semiconductor trap level takes a long time to disappear and may behave as if it were a fixed charge. Therefore, a transistor in which a channel region is formed in a semiconductor with a high trap state density may have unstable electrical characteristics.

Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the semiconductor. In order to reduce the impurity concentration in the semiconductor, it is preferable to reduce the impurity concentration in the adjacent film. Impurities include hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, silicon, and the like.

Here, the influence of each impurity in the semiconductor will be described.

If a semiconductor contains silicon or carbon, which is one of Group 14 elements, a defect level is formed in the semiconductor. Therefore, the concentration of silicon or carbon in the semiconductor and the concentration of silicon or carbon in the vicinity of the interface with the semiconductor (concentration obtained by secondary ion mass spectrometry (SIMS)) is 2 × 10 ¹⁸ atoms. / Cm ³ or less, preferably 2 × 10 ¹⁷ atoms / cm ³ or less.

In addition, when an alkali metal or alkaline earth metal is contained in a semiconductor, a defect level may be formed and carriers may be generated. Therefore, a transistor including a semiconductor containing an alkali metal or an alkaline earth metal is likely to be normally on. For this reason, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the semiconductor. Specifically, the concentration of alkali metal or alkaline earth metal in a semiconductor obtained by SIMS is set to 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less.

In addition, when nitrogen is contained in a semiconductor, electrons as carriers are generated, the carrier density is increased, and the semiconductor is likely to be n-type. As a result, a transistor using a semiconductor containing nitrogen as a semiconductor is likely to be normally on. Therefore, in the semiconductor, nitrogen is preferably reduced as much as possible. For example, the nitrogen concentration in the semiconductor is less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ¹⁸ atoms / cm ^{3 in} SIMS. Hereinafter, it is more preferably 1 × 10 ¹⁸ atoms / cm ³ or less, and further preferably 5 × 10 ¹⁷ atoms / cm ³ or less.

Further, since hydrogen contained in the semiconductor reacts with oxygen bonded to metal atoms to become water, oxygen vacancies may be formed in some cases. When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. In addition, a part of hydrogen may be combined with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor including a semiconductor containing hydrogen is likely to be normally on. For this reason, it is preferable that hydrogen in the semiconductor is reduced as much as possible. Specifically, in a semiconductor, the hydrogen concentration obtained by SIMS is less than 1 × 10 ²⁰ atoms / cm ³ , preferably less than 1 × 10 ¹⁹ atoms / cm ³ , more preferably less than 5 × 10 ¹⁸ atoms / cm ^3. More preferably, it is less than 1 × 10 ¹⁸ atoms / cm ³ .

By using a semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor, stable electric characteristics can be given.

Subsequently, a case where the semiconductor has a two-layer structure or a three-layer structure will be described. A band diagram of the insulator in contact with the stacked structure of the semiconductor S1, the semiconductor S2, and the semiconductor S3 and a band diagram of the insulator in contact with the stacked structure of the semiconductor S2 and the semiconductor S3 will be described with reference to FIGS.

FIG. 24A is an example of a band diagram in the film thickness direction of a stacked structure including the insulator I1, the semiconductor S1, the semiconductor S2, the semiconductor S3, and the insulator I2. FIG. 24B is an example of a band diagram in the film thickness direction of the stacked structure including the insulator I1, the semiconductor S2, the semiconductor S3, and the insulator I2. Note that the band diagram shows the energy level (Ec) at the lower end of the conduction band of the insulator I1, the semiconductor S1, the semiconductor S2, the semiconductor S3, and the insulator I2 for easy understanding.

The semiconductor S1 and the semiconductor S3 have energy levels at the lower end of the conduction band closer to the vacuum level than the semiconductor S2. The difference from the energy level at the lower end is preferably 0.15 eV or more, or 0.5 eV or more, and 2 eV or less, or 1 eV or less. That is, the difference between the electron affinity of the semiconductor S1 and the semiconductor S3 and the electron affinity of the semiconductor S2 is preferably 0.15 eV or more, or 0.5 eV or more, and 2 eV or less, or 1 eV or less.

As shown in FIGS. 24A and 24B, in the semiconductor S1, the semiconductor S2, and the semiconductor S3, the energy level at the lower end of the conduction band changes gently. In other words, it can be said that it is continuously changed or continuously joined. In order to have such a band diagram, the defect state density of the mixed layer formed at the interface between the semiconductor S1 and the semiconductor S2 or the interface between the semiconductor S2 and the semiconductor S3 is preferably low.

Specifically, the semiconductor S1 and the semiconductor S2, and the semiconductor S2 and the semiconductor S3 have a common element (main component) in addition to oxygen, so that a mixed layer with a low density of defect states can be formed. For example, in the case where the semiconductor S2 is an In—Ga—Zn semiconductor, an In—Ga—Zn semiconductor, a Ga—Zn semiconductor, gallium oxide, or the like may be used as the semiconductor S1 and the semiconductor S3.

At this time, the main path of carriers is the semiconductor S2. Since the defect level density at the interface between the semiconductor S1 and the semiconductor S2 and the interface between the semiconductor S2 and the semiconductor S3 can be reduced, the influence on the carrier conduction due to interface scattering is small, and a high on-current can be obtained.

When electrons are trapped in the trap level, the trapped electrons behave like fixed charges, so that the threshold voltage of the transistor shifts in the positive direction. By providing the semiconductor S1 and the semiconductor S3, the trap level can be moved away from the semiconductor S2. With this structure, the threshold voltage of the transistor can be prevented from shifting in the positive direction.

The semiconductor S1 and the semiconductor S3 are made of a material having sufficiently low conductivity as compared with the semiconductor S2. At this time, the semiconductor S2, the interface between the semiconductor S2 and the semiconductor S1, and the interface between the semiconductor S2 and the semiconductor S3 mainly function as a channel region. For example, as the semiconductor S1 and the semiconductor S3, a semiconductor having an atomic ratio indicated by the region C in which the insulating property is increased in FIG. Note that a region C illustrated in FIG. 22C illustrates [In]: [M]: [Zn] = 0: 1: 0 or an atomic ratio that is a value in the vicinity thereof.

In particular, when a semiconductor having an atomic ratio indicated by the region A is used for the semiconductor S2, it is preferable to use a semiconductor having [M] / [In] of 1 or more, preferably 2 or more for the semiconductor S1 and the semiconductor S3. . In addition, as the semiconductor S3, it is preferable to use a semiconductor having [M] / ([Zn] + [In]) of 1 or more that can obtain sufficiently high insulation.

<Structure of oxide semiconductor>
Hereinafter, the structure of the oxide semiconductor is described.

In this specification, “parallel” refers to a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. Further, “substantially parallel” means a state in which two straight lines are arranged at an angle of −30 ° to 30 °. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included. Further, “substantially vertical” means a state in which two straight lines are arranged at an angle of 60 ° to 120 °.

In this specification, when a crystal is trigonal or rhombohedral, it is represented as a hexagonal system.

An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. As the non-single-crystal oxide semiconductor, a CAAC-OS (c-axis-aligned crystal oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), a pseudo-amorphous oxide semiconductor (a-like oxide semiconductor) : Amorphous-like oxide semiconductor) and amorphous oxide semiconductors.

From another point of view, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxide semiconductors. Examples of a crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and an nc-OS.

Amorphous structures are generally isotropic, have no heterogeneous structure, are metastable, have no fixed atomic arrangement, have a flexible bond angle, have short-range order, but long-range order It is said that it does not have.

That is, a stable oxide semiconductor cannot be called a complete amorphous oxide semiconductor. In addition, an oxide semiconductor that is not isotropic (for example, has a periodic structure in a minute region) cannot be called a complete amorphous oxide semiconductor. On the other hand, an a-like OS is not isotropic but has an unstable structure having a void (also referred to as a void). In terms of being unstable, a-like OS is physically close to an amorphous oxide semiconductor.

<CAAC-OS>
First, the CAAC-OS will be described.

A CAAC-OS is a kind of oxide semiconductor having a plurality of c-axis aligned crystal parts (also referred to as pellets).

A case where the CAAC-OS is analyzed by X-ray diffraction (XRD: X-Ray Diffraction) is described. For example, when CAAC-OS having an InGaZnO ₄ crystal classified into the space group R-3m is subjected to structural analysis by an out-of-plane method, a diffraction angle (2θ) as illustrated in FIG. Shows a peak near 31 °. Since this peak is attributed to the (009) plane of the InGaZnO ₄ crystal, in CAAC-OS, the crystal has a c-axis orientation, and the plane on which the c-axis forms a CAAC-OS film (formation target) It can also be confirmed that it faces a direction substantially perpendicular to the upper surface. In addition to the peak where 2θ is around 31 °, a peak may also appear when 2θ is around 36 °. The peak where 2θ is around 36 ° is attributed to the crystal structure classified into the space group Fd-3m. Therefore, the CAAC-OS preferably does not show the peak.

On the other hand, when structural analysis is performed on the CAAC-OS by an in-plane method in which X-rays are incident from a direction parallel to a formation surface, a peak appears at 2θ of around 56 °. This peak is attributed to the (110) plane of the InGaZnO ₄ crystal. Even if 2θ is fixed at around 56 ° and analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis), as shown in FIG. No peak appears. On the other hand, when φ scan is performed with 2θ fixed at around 56 ° with respect to single crystal InGaZnO ₄ , six peaks attributed to a crystal plane equivalent to the (110) plane are observed as shown in FIG. Is done. Therefore, structural analysis using XRD can confirm that the CAAC-OS has irregular orientations in the a-axis and the b-axis.

Next, a CAAC-OS analyzed by electron diffraction will be described. For example, when an electron beam with a probe diameter of 300 nm is incident on a CAAC-OS including an InGaZnO ₄ crystal in parallel with a formation surface of the CAAC-OS, a diffraction pattern (restricted field of view) illustrated in FIG. Sometimes referred to as an electron diffraction pattern). This diffraction pattern includes spots caused by the (009) plane of the InGaZnO ₄ crystal. Therefore, electron diffraction shows that the pellets included in the CAAC-OS have c-axis alignment, and the c-axis is in a direction substantially perpendicular to the formation surface or the top surface. On the other hand, FIG. 25E shows a diffraction pattern obtained when an electron beam with a probe diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample surface. A ring-shaped diffraction pattern is confirmed from FIG. Therefore, it can be seen that the a-axis and the b-axis of the pellet included in the CAAC-OS have no orientation even by electron diffraction using an electron beam with a probe diameter of 300 nm. Note that the first ring in FIG. 25E is considered to originate from the (010) plane and the (100) plane of the InGaZnO ₄ crystal. Further, the second ring in FIG. 25E is considered to be due to the (110) plane or the like.

In addition, when a composite analysis image (also referred to as a high-resolution TEM image) of a bright field image and a diffraction pattern of a CAAC-OS is observed with a transmission electron microscope (TEM), a plurality of pellets are confirmed. Can do. On the other hand, even in a high-resolution TEM image, the boundary between pellets, that is, a crystal grain boundary (also referred to as a grain boundary) may not be clearly confirmed. Therefore, it can be said that the CAAC-OS does not easily lower the electron mobility due to the crystal grain boundary.

FIG. 26A illustrates a high-resolution TEM image of a cross section of the CAAC-OS which is observed from a direction substantially parallel to the sample surface. For observation of the high-resolution TEM image, a spherical aberration correction function was used. A high-resolution TEM image using the spherical aberration correction function is particularly referred to as a Cs-corrected high-resolution TEM image. The Cs-corrected high resolution TEM image can be observed, for example, with an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.

FIG. 26A shows a pellet which is a region where metal atoms are arranged in a layered manner. It can be seen that the size of one pellet is 1 nm or more and 3 nm or more. Therefore, the pellet can also be referred to as a nanocrystal (nc). In addition, the CAAC-OS can be referred to as an oxide semiconductor including CANC (C-Axis aligned nanocrystals). The pellet reflects the unevenness of the surface or top surface of the CAAC-OS film, and is parallel to the surface or top surface of the CAAC-OS.

FIGS. 26B and 26C illustrate Cs-corrected high-resolution TEM images of the plane of the CAAC-OS observed from a direction substantially perpendicular to the sample surface. FIGS. 26D and 26E are images obtained by performing image processing on FIGS. 26B and 26C, respectively. Hereinafter, an image processing method will be described. First, an FFT image is acquired by performing Fast Fourier Transform (FFT) processing on FIG. Then, relative to the origin in the FFT image acquired, for masking leaves a range between 5.0 nm ^-1 from 2.8 nm ^-1. Next, the FFT-processed mask image is subjected to an inverse fast Fourier transform (IFFT) process to obtain an image-processed image. The image acquired in this way is called an FFT filtered image. The FFT filtered image is an image obtained by extracting periodic components from the Cs-corrected high-resolution TEM image, and shows a lattice arrangement.

In FIG. 26 (D), the portion where the lattice arrangement is disturbed is indicated by a broken line. A region surrounded by a broken line is one pellet. And the location shown with the broken line is the connection part of a pellet and a pellet. Since the broken line has a hexagonal shape, it can be seen that the pellet has a hexagonal shape. In addition, the shape of a pellet is not necessarily a regular hexagonal shape, and is often a non-regular hexagonal shape.

In FIG. 26E, a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangement is aligned and a region where another lattice arrangement is aligned is indicated by a dotted line, and the change in the orientation of the lattice arrangement is shown. It is indicated by a broken line. A clear crystal grain boundary cannot be confirmed even in the vicinity of the dotted line. By connecting the surrounding lattice points around the lattice points in the vicinity of the dotted line, a distorted hexagon, pentagon, and / or heptagon can be formed. That is, it can be seen that the formation of crystal grain boundaries is suppressed by distorting the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the atomic arrangement is not dense in the ab plane direction and the bond distance between atoms changes due to substitution of metal elements. Conceivable.

As described above, the CAAC-OS has a c-axis alignment and a crystal structure in which a plurality of pellets (nanocrystals) are connected in the ab plane direction to have a strain. Therefore, the CAAC-OS can also be referred to as a CAA crystal (c-axis-aligned ab-plane-anchored crystal).

The CAAC-OS is an oxide semiconductor with high crystallinity. Since the crystallinity of an oxide semiconductor may be deteriorated by entry of impurities, generation of defects, or the like, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

Note that the impurity means an element other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element. For example, an element such as silicon, which has a stronger bonding force with oxygen than a metal element included in an oxide semiconductor, disturbs the atomic arrangement of the oxide semiconductor by depriving the oxide semiconductor of oxygen, thereby reducing crystallinity. It becomes a factor. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, and the like have large atomic radii (or molecular radii), which disturbs the atomic arrangement of the oxide semiconductor and decreases crystallinity.

<Nc-OS>
Next, the nc-OS will be described.

A case where the nc-OS is analyzed by XRD will be described. For example, when structural analysis is performed on the nc-OS by an out-of-plane method, a peak indicating orientation does not appear. That is, the nc-OS crystal has no orientation.

For example, when an nc-OS including an InGaZnO ₄ crystal is thinned and an electron beam with a probe diameter of 50 nm is incident on a region with a thickness of 34 nm in parallel with the formation surface, FIG. A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown is observed. FIG. 27B shows a diffraction pattern (nanobeam electron diffraction pattern) obtained when an electron beam with a probe diameter of 1 nm is incident on the same sample. From FIG. 27B, a plurality of spots are observed in the ring-shaped region. Therefore, nc-OS does not confirm order when an electron beam with a probe diameter of 50 nm is incident, but confirms order when an electron beam with a probe diameter of 1 nm is incident.

Further, when an electron beam having a probe diameter of 1 nm is incident on a region having a thickness of less than 10 nm, an electron diffraction pattern in which spots are arranged in a substantially regular hexagonal shape is observed as shown in FIG. There is a case. Therefore, it can be seen that the nc-OS has a highly ordered region, that is, a crystal in a thickness range of less than 10 nm. Note that there are some regions where a regular electron diffraction pattern is not observed because the crystal faces in various directions.

FIG. 27D illustrates a Cs-corrected high-resolution TEM image of a cross section of the nc-OS observed from a direction substantially parallel to the formation surface. The nc-OS has a region in which a crystal part can be confirmed, such as a portion indicated by an auxiliary line, and a region in which a clear crystal part cannot be confirmed in a high-resolution TEM image. A crystal part included in the nc-OS has a size of 1 nm to 10 nm, particularly a size of 1 nm to 3 nm in many cases. Note that an oxide semiconductor in which the size of a crystal part is greater than 10 nm and less than or equal to 100 nm is sometimes referred to as a microcrystalline oxide semiconductor. For example, the nc-OS may not be able to clearly confirm a crystal grain boundary in a high-resolution TEM image. Note that the nanocrystal may have the same origin as the pellet in the CAAC-OS. Therefore, the crystal part of nc-OS is sometimes referred to as a pellet below.

Thus, the nc-OS has a periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS has no regularity in crystal orientation between different pellets. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS may not be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method.

Note that since the crystal orientation is not regular between pellets (nanocrystals), nc-OS is an oxide semiconductor having RANC (Random Aligned Nanocrystals), or an oxide having NANC (Non-Aligned nanocrystals). It can also be called a semiconductor.

The nc-OS is an oxide semiconductor that has higher regularity than an amorphous oxide semiconductor. Therefore, the nc-OS has a lower density of defect states than an a-like OS or an amorphous oxide semiconductor. Note that the nc-OS does not have regularity in crystal orientation between different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

<A-like OS>
The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor.

FIG. 28 shows a high-resolution cross-sectional TEM image of the a-like OS. Here, FIG. 28A is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation. FIG. 28B is a high-resolution cross-sectional TEM image of the a-like OS after irradiation with electrons (e ⁻ ) of 4.3 × 10 ⁸ e ⁻ / nm ² . From FIG. 28A and FIG. 28B, it can be seen that a stripe-like bright region extending in the vertical direction is observed in the a-like OS from the start of electron irradiation. It can also be seen that the shape of the bright region changes after electron irradiation. The bright region is assumed to be a void or a low density region.

Since it has a void, the a-like OS has an unstable structure. Hereinafter, in order to show that the a-like OS has an unstable structure as compared with the CAAC-OS and the nc-OS, changes in the structure due to electron irradiation are shown.

As samples, a-like OS, nc-OS, and CAAC-OS are prepared. Each sample is an In—Ga—Zn oxide.

First, a high-resolution cross-sectional TEM image of each sample is acquired. Each sample has a crystal part by a high-resolution cross-sectional TEM image.

Note that a unit cell of an InGaZnO ₄ crystal has a structure in which three In—O layers and six Ga—Zn—O layers have a total of nine layers stacked in the c-axis direction. Are known. The spacing between these adjacent layers is about the same as the lattice spacing (also referred to as d value) of the (009) plane, and the value is determined to be 0.29 nm from crystal structure analysis. Therefore, in the following, a portion where the interval between lattice fringes is 0.28 nm or more and 0.30 nm or less is regarded as an InGaZnO ₄ crystal part. Note that the lattice fringes correspond to the ab plane of the InGaZnO ₄ crystal.

FIG. 29 is an example in which the average size of the crystal parts (22 to 30 locations) of each sample was investigated. Note that the length of the lattice stripes described above is the size of the crystal part. From FIG. 29, it can be seen that in the a-like OS, the crystal part becomes larger in accordance with the cumulative irradiation amount of electrons related to acquisition of a TEM image or the like. According to FIG. 29, the accumulated irradiation dose of electrons (e ⁻ ) is 4.2 × 10 ⁸ e ⁻ / nm in the crystal part (also referred to as initial nucleus) which was about 1.2 nm in the initial stage of observation by TEM. ^{In FIG. 2} , it can be seen that the crystal has grown to a size of about 1.9 nm. On the other hand, in the nc-OS and the CAAC-OS, there is no change in the size of the crystal part in the range of the cumulative electron dose from the start of electron irradiation to 4.2 × 10 ⁸ e ⁻ / nm ^2. I understand. FIG. 29 shows that the crystal part sizes of the nc-OS and the CAAC-OS are approximately 1.3 nm and 1.8 nm, respectively, regardless of the cumulative electron dose. Note that a Hitachi transmission electron microscope H-9000NAR was used for electron beam irradiation and TEM observation. The electron beam irradiation conditions were an acceleration voltage of 300 kV, a current density of 6.7 × 10 ⁵ e ⁻ / (nm ² · s), and an irradiation region diameter of 230 nm.

As described above, in the a-like OS, a crystal part may be grown by electron irradiation. On the other hand, in the nc-OS and the CAAC-OS, the crystal part is hardly grown by electron irradiation. That is, it can be seen that the a-like OS has an unstable structure compared to the nc-OS and the CAAC-OS.

In addition, since it has a void, the a-like OS has a lower density than the nc-OS and the CAAC-OS. Specifically, the density of the a-like OS is 78.6% or more and less than 92.3% of the density of the single crystal having the same composition. Further, the density of the nc-OS and the density of the CAAC-OS are 92.3% or more and less than 100% of the density of the single crystal having the same composition. An oxide semiconductor having a density of less than 78% of the single crystal is difficult to form.

For example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of single crystal InGaZnO ₄ having a rhombohedral structure is 6.357 g / cm ³ . Thus, for example, in an oxide semiconductor that satisfies In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of a-like OS is 5.0 g / cm ³ or more and less than 5.9 g / cm ^3. . For example, in the oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of the nc-OS and the density of the CAAC-OS is 5.9 g / cm ³ or more and 6.3 g / less than cm ³ .

Note that when single crystals having the same composition do not exist, it is possible to estimate a density corresponding to a single crystal having a desired composition by combining single crystals having different compositions at an arbitrary ratio. What is necessary is just to estimate the density corresponding to the single crystal of a desired composition using a weighted average with respect to the ratio which combines the single crystal from which a composition differs. However, the density is preferably estimated by combining as few kinds of single crystals as possible.

As described above, oxide semiconductors have various structures and various properties. Note that the oxide semiconductor may be a stacked film including two or more of an amorphous oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS, for example.

<Carrier density of oxide semiconductor>
Next, the carrier density of the oxide semiconductor is described below.

As a factor that affects the carrier density of an oxide semiconductor, oxygen vacancies (Vo) in the oxide semiconductor, impurities in the oxide semiconductor, and the like can be given.

When the number of oxygen vacancies in the oxide semiconductor increases, the density of defect states increases when hydrogen is bonded to the oxygen vacancies (this state is also referred to as VoH). Alternatively, when the number of impurities in the oxide semiconductor increases, the density of defect states increases due to the impurities. Therefore, the carrier density of an oxide semiconductor can be controlled by controlling the density of defect states in the oxide semiconductor.

Here, a transistor using an oxide semiconductor for a channel region is considered.

In the case where the object is to suppress a negative shift in the threshold voltage of the transistor or to reduce the off-state current of the transistor, it is preferable to reduce the carrier density of the oxide semiconductor. In the case of reducing the carrier density of an oxide semiconductor, the impurity concentration in the oxide semiconductor may be reduced and the defect state density may be reduced. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as high purity intrinsic or substantially high purity intrinsic. The carrier density of the high-purity intrinsic oxide semiconductor is less than 8 × 10 ¹⁵ cm ⁻³ , preferably less than 1 × 10 ¹¹ cm ⁻³ , more preferably less than 1 × 10 ¹⁰ cm ⁻³ , and 1 × 10 ^What is necessary is just to be ^-9 cm ^<-3 > or more.

On the other hand, for the purpose of improving the on-state current of the transistor or improving the field-effect mobility of the transistor, it is preferable to increase the carrier density of the oxide semiconductor. In the case of increasing the carrier density of an oxide semiconductor, the impurity concentration of the oxide semiconductor may be slightly increased or the defect state density of the oxide semiconductor may be slightly increased. Alternatively, the band gap of the oxide semiconductor is preferably made smaller. For example, an oxide semiconductor with a slightly high impurity concentration or a slightly high defect state density can be regarded as intrinsic in the range where the on / off ratio of the Id-Vg characteristics of the transistor can be obtained. In addition, an oxide semiconductor having a high electron affinity and a reduced band gap and, as a result, an increased density of thermally excited electrons (carriers) can be regarded as substantially intrinsic. Note that in the case where an oxide semiconductor having higher electron affinity is used, the threshold voltage of the transistor becomes lower.

The oxide semiconductor whose carrier density is increased is slightly n-type. Therefore, an oxide semiconductor with an increased carrier density may be referred to as “Slightly-n”.

The carrier density of the substantially intrinsic oxide semiconductor is preferably 1 × 10 ⁵ cm ⁻³ or more and less than 1 × 10 ¹⁸ cm ^−3, more preferably 1 × 10 ⁷ cm ⁻³ or more and 1 × 10 ¹⁷ cm ⁻³ or less. Preferably, 1 × 10 ⁹ cm ⁻³ or more and 5 × 10 ¹⁶ cm ⁻³ or less are more preferable, 1 × 10 ¹⁰ cm ⁻³ or more and 1 × 10 ¹⁶ cm ⁻³ or less are more preferable, and 1 × 10 ¹¹ cm ⁻³ or more. 1 × 10 ¹⁵ cm ⁻³ or less is more preferable.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 2)
In this embodiment, an example of a method for manufacturing the transistor 12 and the capacitor 13 having the structure illustrated in FIG. 2B will be described with reference to drawings.

First, the conductor 111 and the conductor 211 to be the conductor 112 are formed over the insulator 110 (FIG. 30A). As the conductor 211, a conductor that can be used for the conductor 111, the conductor 112, and the like described in Embodiment 1 may be used. The conductor 211 is formed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD: Pulsed Laser Deposition) method, or an atomic layer. It can be performed using an ALD (Atomic Layer Deposition) method or the like.

The CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, a photo CVD (Photo CVD) method using light, and the like. . Further, it can be classified into a metal CVD (MCVD: Metal CVD) method and an organic metal CVD (MOCVD: Metal Organic CVD) method depending on the source gas used.

The PECVD method can obtain a high quality film at a relatively low temperature. The TCVD method is a film formation method that can reduce plasma damage to an object to be processed because plasma is not used. For example, a wiring, an electrode, an element (a transistor, a capacitor, or the like) included in the semiconductor device may be charged up by receiving electric charge from plasma. At this time, a wiring, an electrode, an element, or the like included in the semiconductor device may be destroyed by the accumulated charge. On the other hand, in the case of a TCVD method that does not use plasma, such plasma damage does not occur, so that the yield of semiconductor devices can be increased. Further, in the TCVD method, plasma damage during film formation does not occur, so that a film with few defects can be obtained.

The ALD method is also a film forming method that can reduce plasma damage to an object to be processed. In addition, since the ALD method does not cause plasma damage during film formation, a film with few defects can be obtained.

The CVD method and the ALD method are film forming methods in which a film is formed by a reaction on the surface of an object to be processed, unlike a film forming method in which particles emitted from a target or the like are deposited. Therefore, it is a film forming method that is not easily affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, and thus is suitable for covering the surface of an opening having a high aspect ratio. This also makes it difficult to form pinholes or the like in the formed film. However, since the ALD method has a relatively low film formation rate, it may be preferable to use it in combination with another film formation method such as a CVD method with a high film formation rate.

In the CVD method and the ALD method, the composition of the obtained film can be controlled by the flow rate ratio of the source gases. For example, in the CVD method and the ALD method, a film having an arbitrary composition can be formed depending on the flow rate ratio of the source gases. Further, for example, in the CVD method and the ALD method, a film whose composition is continuously changed can be formed by changing the flow rate ratio of the source gas while forming the film. When film formation is performed while changing the flow rate ratio of the source gas, the time required for film formation can be shortened by the time required for conveyance and pressure adjustment compared to the case where film formation is performed using a plurality of film formation chambers. it can. Therefore, the productivity of the semiconductor device may be increased.

Next, a resist or the like is formed over the conductor 211 and processed using the resist, so that the conductor 111 and the conductor 112 are formed (FIG. 30B). Note that the case of simply forming a resist includes the case of forming an antireflection layer under the resist.

The resist is removed after the object is processed by etching or the like. For the removal of the resist, plasma treatment and / or wet etching is used. Note that plasma ashing is preferable as the plasma treatment. If the removal of the resist or the like is insufficient, the remaining resist or the like may be removed with hydrofluoric acid having a concentration of 0.001 volume% or more and 1 volume% or less and / or ozone water.

Next, the insulator 113 is formed (FIG. 30C). As the insulator 113, an insulator that can be used for the insulator 113 described in Embodiment 1 may be used. The insulator 113 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Alternatively, film formation may be performed while heating the substrate in order to reduce water or hydrogen contained in the insulator 113.

Further, heat treatment is preferably performed after the insulator 113 is formed. By performing the heat treatment, water or hydrogen in the insulator 113 can be further reduced. In some cases, the insulator 113 can contain excess oxygen. The heat treatment may be performed at 250 ° C to 650 ° C, preferably 450 ° C to 600 ° C, more preferably 520 ° C to 570 ° C. The heat treatment is performed in an inert gas atmosphere or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. The heat treatment may be performed in a reduced pressure state. Alternatively, the heat treatment may be performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more in order to supplement the desorbed oxygen after the heat treatment in an inert gas atmosphere. By heat treatment, impurities such as hydrogen and water can be removed. For the heat treatment, an RTA apparatus using lamp heating can also be used. The heat treatment by the RTA apparatus is effective for improving productivity because it takes a shorter time than a furnace.

Next, a semiconductor to be the semiconductor 114 is formed. As the semiconductor to be the semiconductor 114, a semiconductor that can be used for the semiconductor described in Embodiment 1 may be used. A semiconductor to be the semiconductor 114 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Further, it is preferable that the semiconductor to be the semiconductor 114 be formed while the substrate is heated.

Next, it is preferable to perform a heat treatment. By performing the heat treatment, the hydrogen concentration of the semiconductor 114 may be reduced. In some cases, oxygen vacancies in the semiconductor 114 can be reduced. The heat treatment may be performed at 250 ° C to 650 ° C, preferably 450 ° C to 600 ° C, more preferably 520 ° C to 570 ° C. The heat treatment is performed in an inert gas atmosphere or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. The heat treatment may be performed in a reduced pressure state. Alternatively, the heat treatment may be performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more in order to supplement the desorbed oxygen after the heat treatment in an inert gas atmosphere. By the heat treatment, the crystallinity of the semiconductor 114 can be increased, impurities such as hydrogen and water can be removed, and the like. For the heat treatment, an RTA apparatus using lamp heating can also be used. The heat treatment by the RTA apparatus is effective for improving productivity because it takes a shorter time than a furnace. In the case where the CAAC-OS described in Embodiment 1 is used as the semiconductor 114, the peak intensity is increased and the full width at half maximum is decreased by performing heat treatment. That is, the crystallinity of the CAAC-OS is increased by heat treatment.

Through the heat treatment, oxygen can be supplied from the insulator 113 to the semiconductor to be the semiconductor 114. By performing heat treatment on the insulator 113, oxygen can be supplied to the semiconductor to be the semiconductor 114 very easily.

In this manner, by supplying oxygen to the semiconductor to be the semiconductor 114 and reducing oxygen vacancies, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor with a low density of defect states can be obtained.

Further, high-density plasma treatment or the like may be performed. The high density plasma may be generated using microwaves. In the high-density plasma treatment, for example, an oxidizing gas such as oxygen or nitrous oxide may be used. Alternatively, a mixed gas of an oxidizing gas and a rare gas such as He, Ar, Kr, or Xe may be used. In high-density plasma processing, a bias may be applied to the substrate. Thereby, oxygen ions or the like in the plasma can be drawn to the substrate side. The high density plasma treatment may be performed while heating the substrate. For example, when high-density plasma treatment is performed instead of the heat treatment, the same effect can be obtained at a temperature lower than the temperature of the heat treatment. The high density plasma treatment may be performed before the insulator 113 is formed, may be performed after the semiconductor 114 is formed, or may be performed after an insulator 119 described later is formed.

Next, a resist or the like is formed over the semiconductor to be the semiconductor 114 and processed using the resist, so that the semiconductor 114 is formed (FIG. 30D).

Next, the conductor 115 and the conductor 215 to be the conductor 116 are formed (FIG. 31A). As the conductor 215, a conductor that can be used as the conductor 115 and the conductor 116 described in Embodiment 1 may be used. The conductor 215 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, a resist or the like is formed over the conductor 215 and processed using the resist, so that the conductor 115 and the conductor 116 are formed (FIG. 31B).

Next, an insulator 117 is formed (FIG. 31C). As the insulator 117, an insulator that can be used as the insulator 117 described in Embodiment 1 may be used. The insulator 117 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, a conductor 218 to be the conductor 118 is formed (FIG. 31D). As the conductor 218, a conductor that can be used as the conductor 118 described in Embodiment 1 may be used. The conductor 218 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Note that the formation of the insulator 117 and the conductor 218 are continuously performed without being exposed to the air, whereby contamination of impurities into the film and at the interface can be reduced.

Next, a resist or the like is formed over the conductor 218 and processed using the resist, so that the conductor 118 is formed (FIG. 32A).

Next, an insulator 119 is formed. After that, the insulator 120 is formed (FIG. 32B). As the insulator 119 and the insulator 120, an insulator that can be used as the insulator 119 and the insulator 120 described in Embodiment 1 may be used. The insulator 119 and the insulator 120 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, a resist or the like is formed over the insulator 120, and openings are formed in the insulator 120, the insulator 119, and the insulator 117. After that, a conductor to be the wiring BL is formed so as to fill the opening (FIG. 32C). As a conductor to be the wiring BL, a conductor that can be used as the wiring BL described in Embodiment 1 may be used. The conductor to be the wiring BL can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Through the above process, the semiconductor device illustrated in FIG. 2B can be manufactured.

Note that heat treatment was performed a plurality of times in the above manufacturing steps, but these heat treatments are performed at a lower temperature as the subsequent steps are performed, thereby reducing the influence of thermal diffusion of impurities due to the heat treatment performed in the later steps. Can do.

In the semiconductor device described in this embodiment, when a wiring or the like is formed using a low-resistance material such as copper, a metal having a low melting point such as copper may be melted by high-temperature heat treatment. Is preferably suppressed to about 400 ° C. to 450 ° C. Thus, the signal transmission speed can be improved by reducing the wiring resistance. Thus, the semiconductor device described in this embodiment can be used for a memory device functioning as a cache memory (for example, a memory device having a function equivalent to that of a built-in DRAM of a CPU chip).

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 3)
In the present embodiment, the sense amplifier 31 will be described in detail with reference to the drawings.

<Configuration example of memory circuit>
FIG. 33 shows a configuration example of the memory circuit 40 using the memory cell 11 and the sense amplifier 31 shown in FIG. The memory circuit 40 includes a plurality of memory cells 11 a and 11 b provided in the cell array 10 and a plurality of sense amplifiers 31 provided in the sense amplifier circuit 30. A top view of the memory circuit 40 in FIG. 33 is shown in FIG. Here, the memory cell 11 a and the memory cell 11 b can have the same configuration as the memory cell 11.

The memory cell 11a is connected to the wiring WLa and the wiring BLa. The memory cell 11a is selected by the potential supplied to the wiring WLa, and data is written to the memory cell 11a by supplying the writing potential to the wiring BLa. Similarly, the memory cell 11b is connected to the wiring WLb and the wiring BLb.

The sense amplifier circuit 30 includes a plurality of sense amplifiers 31 and is connected to the wiring BLa, the wiring BLb, the wiring GBLa, and the wiring GBLb. Here, a configuration example is shown in which one sense amplifier 31 is connected to one wiring BLa and one wiring BLb. The sense amplifier 31 is connected to the wiring GBLa and the wiring GBLb.

The sense amplifier circuit 30 has a function of amplifying an input signal and a function of controlling the output of the amplified signal. Specifically, the read potential is amplified and output to the wiring GBLa or the wiring GBLb at a predetermined timing. By amplifying the read potential by the sense amplifier circuit 30, data can be reliably read even when the potential read from the memory cell 11a or the memory cell 11b is weak. Further, by controlling the output of the amplified potential to the wiring GBLa or the wiring GBLb, the plurality of sense amplifiers 31 can be connected by one wiring GBLa and one wiring GBLb.

In the memory circuit 40 shown in FIGS. 33 and 34, a set of one sense amplifier 31 and a plurality of memory cells 11a and a plurality of memory cells 11b stacked on the one sense amplifier 31 is four. The case where one is provided is illustrated. However, in the memory circuit 40 according to one embodiment of the present invention, the set may be singular or plural other than four.

In FIGS. 33 and 34, the region 15a in which the plurality of memory cells 11a are provided and the region 15b in which the plurality of memory cells 11b are provided include the plurality of memory cells 11a and the plurality of memory cells. It overlaps with one sense amplifier 31 connected to 11b.

33 and 34, the sense amplifier 31 is connected to the wiring BLa and the wiring BLb. The plurality of memory cells 11a provided in one region 15a are connected to the same wiring BLa. A plurality of memory cells 11b provided in one region 15b are connected to the same wiring BLb.

The four regions 15a share a plurality of wirings WLa, and the four regions 15b share a plurality of wirings WLb. Specifically, one wiring WLa is connected to four memory cells 11a, and one wiring WLb is connected to four memory cells 11b.

Since the cell array 10 illustrated in FIGS. 33 and 34 is an open type, the wiring BLa does not intersect with the wiring WLb, and the wiring BLb does not intersect with the wiring WLa.

Each sense amplifier 31 is connected to the wiring GBLa and the wiring GBLb.

Such a cell array layout method is sometimes referred to as an open type. When the open type is applied, the density of the memory cells can be increased and the area of the cell array 10 can be reduced as compared with a folded layout described later. Therefore, the area of the memory circuit 40 can be reduced, and the memory capacity per unit area of the memory circuit 40 can be increased.

In one embodiment of the present invention, the memory circuit 40 has a structure in which the cell array 10 is stacked over the sense amplifier 31. In the region 15a, at least one or more memory cells 11a are arranged so as to have a region overlapping with the sense amplifier 31, and in the region 15b, at least one or more memory cells 11b are arranged so as to have a region overlapping with the sense amplifier 31. Has been. Thereby, the area of the memory circuit 40 can be reduced as compared with the case where the cell array 10 and the sense amplifier 31 are provided in the same layer. Therefore, the storage capacity per unit area of the storage circuit 40 can be increased. Note that the memory cell 11 a and the memory cell 11 b may be arranged so as to have a region overlapping with one sense amplifier 31, or may be arranged so as to have a region overlapping with a plurality of different sense amplifiers 31. The number of memory cells 11a and memory cells 11b stacked on one sense amplifier 31, that is, the number of memory cells 11a and memory cells 11b included in one set of region 15a and region 15b is freely set. be able to. For example, the number of memory cells 11a and memory cells 11b stacked on one sense amplifier 31, in other words, the total number of memory cells 11a and memory cells 11b included in one set of region 15a and region 15b is 512. Hereinafter, the total number is preferably 256 or less, and can be at least 2 or more in total.

In order to reduce power consumption in the memory circuit 40, it is preferable to reduce the number of memory cells 11a included in the region 15a and the number of memory cells 11b included in the region 15b. However, if the number of memory cells 11a included in the region 15a and the number of memory cells 11b included in the region 15b are reduced, it is necessary to increase the number of sense amplifiers 31 in order to maintain the storage capacity. Here, when the cell array 10 and the sense amplifier 31 are provided in the same layer, an increase in the number of sense amplifiers 31 directly leads to an increase in the area of the memory circuit 40. Therefore, it is difficult to reduce the number of memory cells included in the region 15a and the region 15b below a certain level.

On the other hand, since the cell array 10 and the sense amplifier 31 are stacked in one embodiment of the present invention, an increase in the area of the memory circuit 40 can be suppressed even if the number of the sense amplifiers 31 is increased. Therefore, it is easy to reduce the power consumption in the memory circuit 40 by reducing the number of memory cells 11a included in the region 15a and the number of memory cells 11b included in the region 15b. Specifically, the total number of memory cells 11a and memory cells 11b stacked on one sense amplifier 31, in other words, the total number of memory cells 11a and memory cells 11b included in one set of region 15a and region 15b. It can be 64 or less, preferably a total of 32 or less, more preferably a total of 16 or less, and even more preferably a total of 8 or less. Note that although the total area of the sense amplifiers 31 is preferably suppressed to be equal to or less than the area of the cell array 10, an increase in the area of the memory circuit 40 can be reduced even if the total area is equal to or greater than the area of the cell array 10.

Further, by stacking the cell array 10 and the sense amplifier 31, the lengths of the wiring BLa and the wiring BLb that connect the cell array 10 and the sense amplifier 31 can be shortened. Furthermore, by reducing the number of memory cells 11a and memory cells 11b stacked on one sense amplifier 31, in other words, the number of memory cells 11a and memory cells 11b included in one set of region 15a and region 15b. The lengths of the wiring BLa and the wiring BLb connecting the cell array 10 and the sense amplifier 31 can be further shortened. Therefore, the wiring resistance and parasitic capacitance of the wiring BLa and the wiring BLb can be reduced, and the power consumption and the operation speed of the memory circuit 40 can be reduced. In addition, since noise in the read potential can be reduced, errors in the read operation can be reduced.

FIG. 35A illustrates a modification of the memory circuit 40 illustrated in FIG. FIG. 35B shows a top view of the memory circuit 40 having the structure shown in FIG. The memory circuit 40 having the configuration shown in FIGS. 35A and 35B has a structure in which the memory cell 11 is stacked on the sense amplifier 31. The memory circuit 40 having the configuration shown in FIG. 33 has an open layout type for the cell array 10, whereas the memory circuit 40 having the configuration shown in FIGS. 35A and 35B has a folded layout type for the cell array 10. It is.

In the memory circuit 40 having the configuration shown in FIGS. 35A and 35B, two sets of one sense amplifier 31 and a plurality of memory cells 11 stacked on the one sense amplifier 31 are provided. The case where it is provided is illustrated. Note that in the memory circuit 40 according to one embodiment of the present invention, the above set may be a single set or a plurality of three or more sets.

In FIGS. 35A and 35B, four memory cells 11 overlap one sense amplifier 31 connected to the plurality of memory cells 11. Note that in the memory circuit 40 according to one embodiment of the present invention, the number of the memory cells 11 overlapping with one sense amplifier 31 may be one or more than four.

35A and 35B, the sense amplifier 31 is connected to a certain wiring BL and one wiring BL adjacent to the wiring BL. Each sense amplifier 31 is connected to the wiring GBLa and the wiring GBLb.

Since the cell array 10 shown in FIGS. 35A and 35B is a folded type, the memory cell 11 connected to a certain wiring BL, and the memory cell 11 connected to the wiring BL adjacent to the wiring BL However, they are not connected to the same wiring WL.

With such a configuration, when data is read by one sense amplifier 31, it is possible to reduce the influence of noise of the two wirings BL connected to the sense amplifier. Therefore, in the memory circuit 40, errors during reading can be reduced.

<Structure Example of Semiconductor Device Using Memory Circuit>
Next, a configuration example of a semiconductor device using the memory circuit 40 will be described with reference to FIG.

The semiconductor device illustrated in FIG. 36 includes a memory circuit 40, a main amplifier 80, and an input / output circuit 90. Here, a configuration in which the semiconductor device includes k (k is a natural number of 2 or more) memory circuits 40 (memory circuits 40-1 to 40-n) is shown. A memory circuit 40 illustrated in FIG. 36 includes a cell array 10 including a plurality of memory cells 11a and memory cells 11b and a sense amplifier circuit 30 including a plurality of sense amplifiers 31 as in FIG. Note that FIG. 36 illustrates a configuration in which the memory circuit 40-1 includes the cell array 10 and the sense amplifier circuit 30, but the memory circuits 40-2 to 40-n are configured similarly to the memory circuit 40-1. Can do. Further, in the memory circuit 40-1 illustrated in FIG. 36, the wiring BLb, the wiring WLb, the memory cell 11b, and the like illustrated in FIG. 33 are omitted in order to prevent the diagram from becoming complicated. In the sense amplifier circuit 30 illustrated in FIG. 36, the wiring GBLa and the wiring GBLb are provided one by one. However, the configuration is not limited thereto, and a plurality of wirings GBLa and GBLb may be provided.

The main amplifier 80 is connected to the storage circuit 40 and the input / output circuit 90. The main amplifier 80 has a function of amplifying the input signal. Specifically, it has a function of amplifying the potential of the wiring GBLa or the wiring GBLb and outputting the amplified potential to the input / output circuit 90. The main amplifier 80 can be omitted.

The input / output circuit 90 has a function of outputting the potential of the wiring GBLa, the potential of the wiring GBLb, or the potential output from the main amplifier 80 to the outside as read data.

Here, when the wirings BLa are connected to different wirings GBLa and the wirings BLb are connected to different wirings GBLb, it is necessary to provide the same number of wirings GBLa as the wirings BLa. It is necessary to provide the same number of wirings GBLb. Furthermore, all of the wiring GBLa and the wiring GLBb are connected to the main amplifier 80. In this case, the main amplifier 80 needs to amplify all of the signals supplied to the same number of wires GBLa as the wires BLa and all of the signals supplied to the same number of wires GBLb as the wires BLb. The electric power for driving will increase. Further, when the interval between the wirings GBLa and the wirings GBLb is narrowed, the parasitic capacitance generated in the wirings GBLa and GBLb increases. For this reason, it is necessary to supply signals to the wiring GBLa and the wiring GBLb in consideration of signal attenuation and delay due to parasitic capacitance by means such as increasing the amplification factor in the sense amplifier circuit 30. Therefore, the power required for reading and writing data increases.

On the other hand, in one embodiment of the present invention, the wiring GBLa is shared by the plurality of wirings BLa, and the sense amplifier circuit 30 selects a predetermined wiring BLa from among the plurality of wirings BLa and selects the selected wiring BLa. Has a function of outputting the potential to the wiring GBLa. Further, the wiring GBLb is shared by the plurality of wirings BLb, and the sense amplifier circuit 30 selects a predetermined wiring BLb among the plurality of wirings BLb and outputs the potential of the selected wiring BLb to the wiring GBLb. It has a function. As a result, the number of wiring GBLa and wiring GBLb connected to the main amplifier 80 can be reduced, so that the number of signals to be amplified in the main amplifier 80 can be reduced. Therefore, power consumption in the main amplifier 80 can be reduced. In addition, since the number of the wiring GBLa and the wiring GBLb can be reduced and the distance between the wirings GBLa and the wiring GBLb can be increased, the parasitic capacitance generated in the wiring GBLa and the wiring GBLb can be reduced, and the wiring GBLa and the wiring GBLb The attenuation of the supplied signal can be suppressed. Therefore, the burden of signal amplification by the sense amplifier circuit 30 and the main amplifier 80 can be reduced, and power consumption of the semiconductor device of one embodiment of the present invention can be reduced.

Further, by reducing the number of the wiring GBLa and the wiring GBLb to reduce the parasitic capacitance, a configuration in which the signals of the wiring GBLa and the wiring GBLb are directly output to the input / output circuit 90 without being amplified can be employed. In this case, the main amplifier 80 can be omitted, and the power consumption and area of the semiconductor device can be reduced.

Note that the number of wirings GBLa is not particularly limited, and can be any number smaller than the number of wirings BLa. Further, the number of wirings GBLb is not particularly limited, and may be any number smaller than the number of wirings BLb.

Here, the configuration in which the data stored in the memory cell 11a and the memory cell 11b is output from the input / output circuit 90 to the outside has been described. However, the operation for writing the data to the memory cell 11a and the memory cell 11b is also based on the same principle. It can be carried out. Specifically, write data input from the outside is output from the input / output circuit 90 to the main amplifier 80, and the potential amplified by the main amplifier 80 is input to the sense amplifier circuit 30. Then, the potential amplified by the sense amplifier circuit 30 is supplied to the wiring BLa or the wiring BLb as a writing potential. Note that the timing of outputting the writing potential to the wiring BLa or the wiring BLb can be controlled by the sense amplifier circuit 30. The above effect can also be obtained in data writing.

The wiring WLa and the wiring WLb are connected to the drive circuit 70. The driver circuit 70 has a function of supplying a signal (hereinafter also referred to as a write word signal) for selecting the memory cell 11a or the memory cell 11b to which data is written to the predetermined wiring WLa or the wiring WLb. The drive circuit 70 can be configured by a decoder or the like.

The sense amplifier 31 is connected to the memory cell 11a via the wiring BLa and is connected to the memory cell 11b via the wiring BLb. The sense amplifier 31 includes an amplifier circuit 32 and a switch circuit 33.

The amplifier circuit 32 has a function of amplifying the potentials of the wiring BLa and the wiring BLb. Specifically, the amplifier circuit 32 has a function of amplifying a difference between the potential of the wiring BLa or the wiring BLb and the reference potential and holding the amplified potential difference. For example, in the case of amplifying the potential of the wiring BLa, the potential difference between the wiring BLa and the wiring BLb is amplified using the potential of the wiring BLb as a reference potential. Further, in the case of amplifying the potential of the wiring BLb, the potential difference between the wiring BLb and the wiring BLa is amplified using the potential of the wiring BLa as a reference potential.

The switch circuit 33 has a function of selecting whether or not to output the amplified potential of the wiring BLa to the wiring GBLa and selecting whether or not to output the amplified potential of the wiring BLb to the wiring GBLb. Specifically, it has a function of controlling the conductive state between the wiring BLa and the wiring GBLa and the conductive state between the wiring BLb and the wiring GBLb.

The switch circuit 33 is connected to any one of the plurality of wirings CSEL, and the operation of the switching circuit 33 is controlled based on a signal supplied from the drive circuit 70 to the wiring CSEL. Specifically, the conduction state between the wiring BLa and the wiring GBLa and the conduction state between the wiring BLb and the wiring GBLb are controlled. Accordingly, the wiring BLa that supplies a potential to the wiring GBLa among the plurality of wirings BLa can be selected. In addition, the wiring BLb that supplies a potential to the wiring GBLb among the plurality of wirings BLb can be selected. Thus, the wiring BLa can be shared and the wiring BLb can be shared. Accordingly, the number of the wiring GBLa and the wiring GBLb can be reduced.

Here, in one embodiment of the present invention, of the signals output from the wiring BLa and the wiring BLb, the signal output to the outside from the input / output circuit 90 can be selected using the switch circuit 33 and the wiring CSEL. it can. Therefore, it is not necessary for the input / output circuit 90 to perform an operation of selecting some of the plurality of signals using a multiplexer or the like. Therefore, the configuration of the input / output circuit 90 can be simplified and the area can be reduced.

Further, in the above structure, as shown in FIG. 36, the switch circuit 33 and the wiring CSEL are preferably arranged so as to have a region overlapping with the cell array 10. Specifically, the switch circuit 33 and the wiring CSEL are preferably provided so as to have a region overlapping with the memory cell 11a and / or the memory cell 11b. Thereby, it is possible to add a function of selecting an output signal to the sense amplifier circuit 30 while suppressing an increase in the area of the memory circuit 40.

Note that although the wiring WLa, the wiring WLb, and the wiring CSEL are connected to the driving circuit 70 here, the wiring WLa, the wiring WLb, and the wiring CSEL are connected to separate driving circuits. Also good. In this case, the potentials of the wiring WLa and the wiring WLb and the potential of the wiring CSEL are controlled by separate driving circuits.

Next, an example of the arrangement of the sense amplifier 31 and the wiring CSEL in the sense amplifier circuit 30 will be described.

In FIG. 37A, four sense amplifiers 31 (sense amplifiers 31a to 31d) are periodically arranged in one column, and each sense amplifier 31 is connected to one of four wirings CSEL (wirings CSELa to d). Is shown. Specifically, the sense amplifier 31a is connected to the wiring CSELa, the sense amplifier 31b is connected to the wiring CSELb, the sense amplifier 31c is connected to the wiring CSELc, and the sense amplifier 31d is connected to the wiring CSELd. Each sense amplifier 31 is connected to the wiring GBLa and the wiring GBLb.

A part of the wiring CSEL may be provided on the opposite side of the sense amplifier 31. For example, as illustrated in FIG. 37B, a structure in which a sense amplifier 31 is provided between the wiring CSELa and the wiring CSELb and the wiring CSELc and the wiring CSELd can be employed.

As shown in FIG. 37C, the sense amplifier 31 may be arranged on a zigzag line. In this case, a part of the sense amplifier 31 may be arranged so as to overlap a part of the adjacent sense amplifier 31. For example, the sense amplifier 31b is arranged so as to overlap a part of the sense amplifier 31a and a part of the sense amplifier 31c. This makes it possible to shorten the length of the sense amplifier circuit 30 in the width direction (left and right direction on the paper) as compared with FIGS. 37 (A) and (B).

The sense amplifiers 31 may be provided in a plurality of rows. For example, two rows can be provided as shown in FIG. Here, a configuration is shown in which sense amplifiers 31a to 31d arranged in two rows and two columns are periodically arranged.

<Configuration example of sense amplifier>
Next, a specific configuration example of the sense amplifier 31 according to one embodiment of the present invention is described.

FIG. 38 shows an example of a circuit configuration of the memory cell 11a and the memory cell 11b and the sense amplifier 31 electrically connected to the memory cell 11a and the memory cell 11b. The memory cell 11a is connected to the sense amplifier 31 via the wiring BLa, and the memory cell 11b is connected to the sense amplifier 31 via the wiring BLb.

Note that FIG. 38 illustrates a configuration in which one memory cell 11a is connected to one wiring BLa and one memory cell 11b is connected to one wiring BLb. A plurality of memory cells 11 a may be connected to the sense amplifier 31. A plurality of memory cells 11b may be connected to the sense amplifier 31 on the wiring BLb.

The sense amplifier 31 includes an amplifier circuit 32, a switch circuit 33, and a precharge circuit 34.

The amplifier circuit 32 includes a p-channel transistor 91 and a transistor 92, and an n-channel transistor 93 and a transistor 94. One of a source and a drain of the transistor 91 is connected to the wiring SP, and the other of the source and the drain is connected to the gate of the transistor 92, the gate of the transistor 94, and the wiring BLa. One of a source and a drain of the transistor 93 is connected to the gate of the transistor 92, the gate of the transistor 94, and the wiring BLa, and the other of the source and the drain is connected to the wiring SN. One of a source and a drain of the transistor 92 is connected to the wiring SP, and the other of the source and the drain is connected to the gate of the transistor 91, the gate of the transistor 93, and the wiring BLb. One of a source and a drain of the transistor 94 is connected to the gate of the transistor 91, the gate of the transistor 93, and the wiring BLb, and the other of the source and the drain is connected to the wiring SN. The amplifier circuit 32 has a function of amplifying the potential of the wiring BLa and a function of amplifying the potential of the wiring BLb. Note that the sense amplifier 31 including the amplifier circuit 32 illustrated in FIG. 38 functions as a latch-type sense amplifier.

The switch circuit 33 includes an n-channel transistor 95 and a transistor 96. The transistors 95 and 96 may be p-channel type. One of a source and a drain of the transistor 95 is connected to the wiring BLa, and the other of the source and the drain is connected to the wiring GBLa. One of a source and a drain of the transistor 96 is connected to the wiring BLb, and the other of the source and the drain is connected to the wiring GBLb. The gate of the transistor 95 and the gate of the transistor 96 are connected to the wiring CSEL. The switch circuit 33 has a function of controlling a conduction state between the wiring BLa and the wiring GBLa and a conduction state between the wiring BLb and the wiring GBLb based on a potential supplied to the wiring CSEL.

The precharge circuit 34 includes an n-channel transistor 97, a transistor 98, and a transistor 99. The transistors 97 to 99 may be p-channel types. One of a source and a drain of the transistor 97 is connected to the wiring BLa, and the other of the source and the drain is connected to the wiring Pre. One of a source and a drain of the transistor 98 is connected to the wiring BLb, and the other of the source and the drain is connected to the wiring Pre. One of a source and a drain of the transistor 99 is connected to the wiring BLa, and the other of the source and the drain is connected to the wiring BLb. The gate of the transistor 97, the gate of the transistor 98, and the gate of the transistor 99 are connected to the wiring PCL. The precharge circuit 34 has a function of initializing the potentials of the wiring BLa and the wiring BLb.

Note that the amplifier circuit 32, the switch circuit 33, and the precharge circuit 34 are preferably arranged so as to have a region overlapping with the memory cell 11.

<Operation example of sense amplifier>
Next, an example of operations of the memory cell 11a and the memory cell 11b and the sense amplifier 31 illustrated in FIG. 38 at the time of data reading will be described with reference to a timing chart illustrated in FIG.

First, in the period T1, the transistors 97 to 99 included in the precharge circuit 34 are turned on to initialize the potentials of the wiring BLa and the wiring BLb. Specifically, an H level potential VH_PL is applied to the wiring PCL, and the transistors 97 to 99 are turned on in the precharge circuit 34. Thus, the potential Vpre of the wiring Pre is supplied to the wiring BLa and the wiring BLb. Note that the potential Vpre can be set to, for example, (VH_SP + VL_SN) / 2.

Note that in the period T1, the L-level potential VL_CSEL is supplied to the wiring CSEL, and the transistor 95 and the transistor 96 in the switch circuit 33 are off. Further, the L-level potential VL_WL is applied to the wiring WLa, and the transistor 12 is off in the memory cell 11a. Similarly, although not illustrated in FIG. 39, the L-level potential VL_WL is applied to the wiring WLb, and the transistor 12 is off in the memory cell 11b. Further, the potential Vpre is applied to the wiring SP and the wiring SN, and the amplifier circuit 32 is in an off state.

Next, the L-level potential VL_PL is applied to the wiring PCL, and the transistors 97 to 99 are turned off in the precharge circuit 34. Then, in the period T2, the wiring WLa is selected. Specifically, in FIG. 39, the wiring WLa is selected by applying the H-level potential VH_WL to the wiring WLa, and the transistor 12 is turned on in the memory cell 11a. With the above structure, the wiring BLa and the capacitor 13 are brought into conduction through the transistor 12. When the wiring BLa and the capacitor 13 are brought into conduction, the potential of the wiring BLa varies according to the amount of charge held in the capacitor 13.

In the timing chart shown in FIG. 39, a case where the amount of charge accumulated in the capacitor 13 is large is illustrated. Specifically, when the amount of charge accumulated in the capacitor 13 is large, charge is released from the capacitor 13 to the wiring BLa, so that the potential of the wiring BLa is increased by ΔV1 from the potential Vpre. On the other hand, when the amount of charge accumulated in the capacitor 13 is small, the charge flows into the capacitor 13 from the wiring BLa, so that the potential of the wiring BLa drops by ΔV2.

Note that in the period T2, the L-level potential VL_CSEL is still applied to the wiring CSEL, and the transistor 95 and the transistor 96 are kept off in the switch circuit 33. In addition, the potential Vpre remains applied to the wiring SP and the wiring SN, and the amplifier circuit 32 maintains an off state.

Next, in the period T <b> 3, the amplifier circuit 32 is turned on by applying the H level potential VH_SP to the wiring SP and the L level potential VL_SN to the wiring SN. The amplifier circuit 32 has a function of amplifying a potential difference (ΔV1 in the case of FIG. 39) between the wiring BLa and the wiring BLb. Accordingly, in the timing chart illustrated in FIG. 39, when the amplifier circuit 32 is turned on, the potential of the wiring BLa approaches the potential VH_SP of the wiring SP from the potential Vpre + ΔV1. In addition, the potential of the wiring BLb approaches the potential VL_SN of the wiring SN from the potential Vpre.

Note that when the potential of the wiring BLa is the potential Vpre−ΔV2 at the beginning of the period T3, the amplifier circuit 32 is turned on, so that the potential of the wiring BLa is changed from the potential Vpre−ΔV2 to the potential VL_SN of the wiring SN. Approaching. In addition, the potential of the wiring BLb approaches the potential VH_SP of the wiring SP from the potential Vpre.

In the period T3, the L-level potential VL_PL is still applied to the wiring PCL, and the transistors 97 to 99 are kept off in the precharge circuit 34. In addition, the L-level potential VL_CSEL is still applied to the wiring CSEL, and the transistor 95 and the transistor 96 are kept off in the switch circuit 33. The H-level potential VH_WL is still applied to the wiring WLa, and the transistor 12 is kept on in the memory cell 11a. Therefore, in the memory cell 11a, electric charge corresponding to the potential VH_SP of the wiring BLa is accumulated in the capacitor 13.

Next, in the period T4, the switch circuit 33 is turned on by controlling the potential applied to the wiring CSEL. Specifically, in FIG. 39, the H level potential VH_CSEL is applied to the wiring CSEL, and the transistor 95 and the transistor 96 are turned on in the switch circuit 33. Accordingly, the potential of the wiring BLa is supplied to the wiring GBLa, and the potential of the wiring BLb is supplied to the wiring GBLb.

Note that in the period T4, the L-level potential VL_PL is still applied to the wiring PCL, and the transistors 97 to 99 in the precharge circuit 34 are kept off. Further, the H-level potential VH_WL is still applied to the wiring WLa, and the transistor 12 is kept on in the memory cell 11a. The wiring SP remains supplied with the H level potential VH_SP, and the wiring SN remains supplied with the L level potential VL_SP, so that the amplifier circuit 32 is kept on. Therefore, in the memory cell 11a, the charge corresponding to the potential VH_SP of the wiring BLa is still accumulated in the capacitor 13.

When the period T4 ends, the switch circuit 33 is turned off by controlling the potential applied to the wiring CSEL. Specifically, in FIG. 39, the L-level potential VL_CSEL is applied to the wiring CSEL, and the transistor 95 and the transistor 96 are turned off in the switch circuit 33.

In addition, when the period T4 ends, the selection of the wiring WLa ends. Specifically, in FIG. 39, by applying the L-level potential VL_WL to the wiring WLa, the wiring WLa is deselected, and the transistor 12 is turned off in the memory cell 11a. Through the above operation, charge corresponding to the potential VH_SP of the wiring BLa is held in the capacitor 13; thus, the data is held in the memory cell 11a even after data is read.

Data is read from the memory cell 11a by the operations in the above-described periods T1 to T4. Data can be read from the memory cell 11b in the same manner.

Note that data can be written to the memory cell 11a and the memory cell 11b on the same principle as described above. Specifically, as in the case of reading data, first, the transistors 97 to 99 included in the precharge circuit 34 are temporarily turned on to initialize the potentials of the wiring BLa and the wiring BLb. Next, the wiring WLa connected to the memory cell 11a to which data is to be written or the wiring WLb connected to the memory cell 11b is selected, and the transistor 12 is turned on in the memory cell 11a or the memory cell 11b. Through the above operation, the wiring BLa or the wiring BLb and the capacitor 13 are brought into conduction through the transistor 12. Next, the amplifier circuit 32 is turned on by applying the H level potential VH_SP to the wiring SP and the L level potential VL_SN to the wiring SN. Next, the switch circuit 33 is turned on by controlling the potential applied to the wiring CSEL. Specifically, the H level potential VH_CSEL is applied to the wiring CSEL, and the transistor 95 and the transistor 96 are turned on in the switch circuit 33. With the above structure, the wiring BLa and the wiring GBLa are brought into conduction, and the wiring BLb and the wiring GBLb are brought into conduction. Then, by applying a writing potential to each of the wiring GBLs and the wiring GBLb, the writing potential is applied to the wiring BLa and the wiring BLb through the switch circuit 33. Through the above operation, electric charge is accumulated in the capacitor 13 in accordance with the potential of the wiring BLa or the wiring BLb, and data is written in the memory cell 11a or the memory cell 11b.

Note that after the potential of the wiring GBLa is applied to the wiring BLa and the potential of the wiring GBLb is applied to the wiring BLb, even if the transistor 95 and the transistor 96 are turned off in the switch circuit 33, the sense amplifier 31 is turned on. If there is, the relationship between the potential of the wiring BLa and the potential of the wiring BLb is held by the amplifier circuit 32. Therefore, the timing at which the transistor 95 and the transistor 96 are changed from on to off in the switch circuit 33 may be before or after the wiring WLa is selected.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 4)
In this embodiment, an example of a semiconductor device including a plurality of circuits each including the OS transistor described in the above embodiment will be described with reference to FIGS.

FIG. 40A is a block diagram of the semiconductor device 900. FIG. The semiconductor device 900 includes a power supply circuit 901, a circuit 902, a potential generation circuit 903, a circuit 904, a potential generation circuit 905, and a circuit 906.

The power supply circuit 901 is a circuit that generates a reference potential V _ORG . The potential V _ORG may be a plurality of potentials instead of a single potential. The potential V _ORG can be generated based on the potential V ₀ supplied from the outside of the semiconductor device 900. The semiconductor device 900 can generate the potential V _ORG based on a single power supply potential given from the outside. Therefore, the semiconductor device 900 can operate without applying a plurality of power supply potentials from the outside.

The circuits 902, 904, and 906 are circuits that operate with different power supply potentials. For example, the power supply potential of the circuit 902 is a potential applied by the potential V _ORG and the potential V _SS (V _ORG > V _SS ). For example, the power supply potential of the circuit 904 is a potential applied by the potential V _POG and the potential V _SS (V _POG > V _ORG ). For example, the power supply potential of the circuit 906 is a potential applied by the potential V _ORG and the potential V _NEG (V _ORG > V _SS > V _NEG ). Note that if the potential _VSS is a ground potential, the types of potentials generated by the power supply circuit 901 can be reduced.

The potential generation circuit 903 is a circuit that generates a potential _VPOG . The potential generation circuit 903 can generate the potential V _POG based on the potential V _{ORG supplied} from the power supply circuit 901. Therefore, the semiconductor device 900 including the circuit 904 can operate based on a single power supply potential supplied from the outside.

The potential generation circuit 905 is a circuit that generates a potential V _NEG . The potential generation circuit 905 can generate the potential V _NEG based on the potential V _{ORG supplied} from the power supply circuit 901. Therefore, the semiconductor device 900 including the circuit 906 can operate based on a single power supply potential supplied from the outside.

FIG. _40B illustrates an example of a circuit 904 that operates at the potential V _POG , and FIG. 40C illustrates an example of a waveform of a signal for operating the circuit 904.

In FIG. 40B, the transistor 911 is illustrated. Signal applied to the gate of the transistor 911 is generated, for example, based on the potential _{V POG} and the potential _{V SS.} The signal is set to a potential V _SS during operation of the conductive state of transistor 911 potential V _POG, during operation of the non-conductive state. The potential V _POG is higher than the potential V _ORG as illustrated in FIG. Therefore, the transistor 911 can more reliably perform an operation of bringing the source (S) and the drain (D) into conduction. As a result, the circuit 904 can be a circuit in which malfunctions are reduced.

FIG. _40D illustrates an example of a circuit 906 that operates at the potential V _NEG , and FIG. _40E illustrates an example of a waveform of a signal for operating the circuit 906.

In FIG. 40D, the transistor 912 is illustrated. Signal applied to the gate of the transistor 912, for example, generated based on the potential _{V ORG} and the potential _{V SS.} The signal is set to a potential V _SS during operation of the transistor 911 in a conducting state potential V _ORG, during operation of the non-conductive state. The potential applied to the back gate of the transistor 912 is generated based on the potential V _NEG . Potential _{V NEG,} as shown in FIG. 40 (E), less than the potential _{V SS.} Therefore, the threshold potential of the transistor 912 can be controlled to shift positively. Therefore, the transistor 912 can be more reliably turned off, and the current flowing between the source (S) and the drain (D) can be reduced. As a result, the circuit 906 can be a circuit in which malfunctions are reduced and power consumption is reduced.

Note that the potential V _NEG may be directly applied to the back gate of the transistor 912. Alternatively, a signal to be _supplied to the gate of the transistor 912 may be generated based on the potential V _ORG and the potential V _NEG and the signal may be supplied to the back gate of the transistor 912.

41A and 41B show modifications of FIGS. 40D and 40E.

In the circuit diagram illustrated in FIG. 41A, a transistor 922 whose conduction state can be controlled by the control circuit 921 between the potential generation circuit 905 and the circuit 906 is illustrated. The transistor 922 is an n-channel OS transistor. Control signal _{S BG} control circuit 921 is output a signal for controlling the conduction state of the transistor 922. A transistor 912a and a transistor 912b included in the circuit 906 are the same OS transistors as the transistor 922.

The timing chart of FIG. 41 (B) shows a control signal _{S BG,} the state of the potential of the back gate of the transistor 912a and the transistor 912b by a change in the potential of the node _{N BG.} Control signal _{S BG} is transistor 922 in a conducting state at the high level, the node _{N BG} is a potential _{V NEG.} Thereafter, when the control signal _SBG is at a low level, the node _NBG becomes electrically floating. Since the transistor 922 is an OS transistor, the off-state current is small. Therefore, even if the node _NBG is electrically floating, the potential V _NEG once applied can be held.

FIG. 42A illustrates an example of a circuit configuration which can be applied to the potential generation circuit 903 described above. A potential generation circuit 903 illustrated in FIG. 42A is a five-stage charge pump including diodes D1 to D5, capacitors C1 to C5, and an inverter INV. The clock signal CLK is supplied to the capacitor C1 to the capacitor C5 directly or via the inverter INV. When the power supply potential of the inverter INV is a potential applied by the potential V _ORG and the potential V _SS , the potential V _POG that is boosted to a positive potential five times the potential V _ORG can be obtained by the clock signal CLK. The forward potential of the diodes D1 to D5 is 0V. In addition, a desired potential V _POG can be obtained by changing the number of stages of the charge pump.

FIG. 42B illustrates an example of a circuit configuration that can be applied to the potential generation circuit 905 described above. A potential generation circuit 905 illustrated in FIG. 42B is a four-stage charge pump including diodes D1 to D5, capacitors C1 to C5, and an inverter INV. The clock signal CLK is supplied to the capacitor C1 to the capacitor C5 directly or via the inverter INV. When the power supply potential of the inverter INV is a potential applied by the potential V _ORG and the potential V _SS , a potential V _NEG that is stepped down from the potential V _SS to a negative potential four times the potential V _ORG is obtained by the clock signal CLK. be able to. The forward potential of the diodes D1 to D5 is 0V. Further, a desired potential V _NEG can be obtained by changing the number of stages of the charge pump.

Note that the circuit configuration of the above-described potential generation circuit 903 is not limited to the configuration of the circuit diagram illustrated in FIG. Modified examples of the potential generation circuit 903 are illustrated in FIGS. 43A, 43B, and 43, and FIG.

A potential generation circuit 903a illustrated in FIG. 43A includes transistors M1 to M10, capacitors C11 to C14, and an inverter INV1. The clock signal CLK is supplied directly to the gates of the transistors M1 to M10 or via the inverter INV1. With the clock signal CLK, a potential V _POG boosted to a positive potential four times the potential V _ORG can be obtained. Note that a desired potential V _POG can be obtained by changing the number of stages. The potential generation circuit 903a illustrated in FIG. 43A can reduce off-state current by using the transistors M1 to M10 as OS transistors, and can suppress leakage of charges held in the capacitors C11 to C14. Therefore, it is possible to efficiently boost the potential V _ORG to the potential V _POG .

A potential generation circuit 903b illustrated in FIG. 43B includes transistors M11 to M14, a capacitor C15, a capacitor C16, and an inverter INV2. The clock signal CLK is supplied directly to the gates of the transistors M11 to M14 or via the inverter INV2. With the clock signal CLK, a potential V _POG that is boosted to a positive potential that is twice the potential V _ORG can be obtained. The potential generation circuit 903b illustrated in FIG. 43B can reduce off-state current by using the transistors M11 to M14 as OS transistors, and can suppress leakage of charges held in the capacitor C15 and the capacitor C16. Therefore, it is possible to efficiently boost the potential V _ORG to the potential V _POG .

A potential generation circuit 903c illustrated in FIG. 43C includes an inductor IND1, a transistor M15, a diode D6, and a capacitor C17. The conduction state of the transistor M15 is controlled by the control signal EN. A potential V _POG obtained by boosting the potential V _ORG can be obtained by the control signal EN. Since the potential generation circuit 903c illustrated in FIG. 43C uses the inductor IND1 to increase the potential, the potential generation circuit 903c can increase the potential with high conversion efficiency.

A potential generation circuit 903d illustrated in FIG. 44 corresponds to a structure in which the diodes D1 to D5 of the potential generation circuit 903 illustrated in FIG. 42A are replaced with diode-connected transistors M16 to M20. The potential generation circuit 903d illustrated in FIG. 44 can reduce off-state current by using the transistors M16 to M20 as OS transistors, and can suppress leakage of charge held in the capacitors C1 to C5. Therefore, it is possible to efficiently boost the potential V _ORG to the potential V _POG .

Note that a modification of the potential generation circuit 903 can be applied to the potential generation circuit 905 illustrated in FIG. The structure of the circuit diagram in this case is shown in FIGS. 45 (A), (B), (C) and FIG. Potential generating circuit 905a shown in FIG. 45 (A) is the clock signal CLK, and it is possible to obtain the potential _{V NEG} stepped down from the potential _{V SS} to 3 times the negative potential of _{V ORG.} The potential generating circuit 905b which shown in FIG. 36 (B) is the clock signal CLK, and it is possible to obtain the potential _{V NEG} stepped down from the potential _{V SS} to twice the negative potential of _{V ORG.}

In the potential generation circuits 905a to 905d shown in FIGS. 45 (A), (B), (C) and FIG. 46, the potential generation circuits shown in FIGS. 43 (A), (B), (C) and FIG. This corresponds to a structure in which the potential applied to each wiring is changed or the arrangement of elements is changed in 903a to 903d. 45A, 45B, 46C, and 46, as in the case of the potential generation circuits 905a to 905d, can be efficiently reduced from the potential V _ORG to the potential V _NEG .

As described above, in the structure of this embodiment mode, a potential necessary for a circuit included in the semiconductor device can be generated internally. Therefore, the semiconductor device can reduce the type of power supply potential applied from the outside.

The structures and methods described in this embodiment can be combined as appropriate with any of the structures and methods described in the other embodiments.

(Embodiment 5)
In this embodiment, a display device using a transistor or the like according to one embodiment of the present invention will be described with reference to FIGS.

<Configuration of display device>
As a display element used for the display device, a liquid crystal element (also referred to as a liquid crystal display element), a light-emitting element (also referred to as a light-emitting display element), or the like can be used. The light-emitting element includes, in its category, an element whose luminance is controlled by current or voltage, and specifically includes inorganic EL (Electroluminescence), organic EL, and the like. Hereinafter, a display device using an EL element (an EL display device) and a display device using a liquid crystal element (a liquid crystal display device) will be described as examples of the display device.

Note that a display device described below includes a panel in which a display element is sealed, and a module in which an IC or the like including a controller is mounted on the panel.

The display device described below refers to an image display device or a light source (including a lighting device). The display device includes all connectors, for example, a module to which FPC and TCP are attached, a module having a printed wiring board at the end of TCP, or a module in which an IC (integrated circuit) is directly mounted on a display element by a COG method.

FIG. 47 illustrates an example of an EL display device according to one embodiment of the present invention. FIG. 47A shows a circuit diagram of a pixel of an EL display device. FIG. 47B is a top view showing the entire EL display device. FIG. 47C is an MN cross section corresponding to part of the dashed-dotted line MN in FIG.

FIG. 47A is an example of a circuit diagram of a pixel used in the EL display device.

Note that in this specification and the like, a person skilled in the art can connect all terminals of an active element (a transistor, a diode, etc.), a passive element (a capacitor element, a resistance element, etc.) without specifying connection destinations. Thus, it may be possible to constitute an aspect of the invention. That is, it can be said that one aspect of the invention is clear without specifying the connection destination. And, when the content specifying the connection destination is described in this specification etc., it is possible to determine that one aspect of the invention that does not specify the connection destination is described in this specification etc. There is. In particular, when a plurality of locations are assumed as the connection destination of the terminal, it is not necessary to limit the connection destination of the terminal to a specific location. Therefore, it is possible to constitute one embodiment of the present invention by specifying connection destinations of only some terminals of active elements (transistors, diodes, etc.) and passive elements (capacitance elements, resistance elements, etc.). There are cases.

Note that in this specification and the like, it may be possible for those skilled in the art to specify the invention when at least the connection portion of a circuit is specified. Alternatively, it may be possible for those skilled in the art to specify the invention when at least the function of a circuit is specified. That is, if the function is specified, it can be said that one aspect of the invention is clear. Then, it may be possible to determine that one embodiment of the invention whose function is specified is described in this specification and the like. Therefore, if a connection destination is specified for a certain circuit without specifying a function, the circuit is disclosed as one embodiment of the invention, and can constitute one embodiment of the invention. Alternatively, if a function is specified for a certain circuit without specifying a connection destination, the circuit is disclosed as one embodiment of the invention, and can constitute one embodiment of the invention.

An EL display device illustrated in FIG. 47A includes a switch element 743, a transistor 741, a capacitor 742, and a light-emitting element 719.

Note that FIG. 47A and the like illustrate an example of a circuit configuration, and thus transistors can be added. On the other hand, it is also possible not to add a transistor, a switch, a passive element, or the like at each node in FIG.

A gate of the transistor 741 is electrically connected to one end of the switch element 743 and one electrode of the capacitor 742. A source of the transistor 741 is electrically connected to the other electrode of the capacitor 742 and electrically connected to one electrode of the light-emitting element 719. The source of the transistor 741 is supplied with the power supply potential VDD. The other end of the switch element 743 is electrically connected to the signal line 744. A constant potential is applied to the other electrode of the light-emitting element 719. Note that the constant potential is set to the ground potential GND or lower.

As the switch element 743, a transistor is preferably used. By using a transistor, the area of a pixel can be reduced and an EL display device with high resolution can be obtained. In addition, when a transistor manufactured through the same process as the transistor 741 is used as the switch element 743, the productivity of the EL display device can be increased. Note that as the transistor 741 and / or the switch element 743, for example, the above-described transistor can be used.

FIG. 47B is a top view of the EL display device. The EL display device includes a substrate 700, a substrate 750, a sealant 734, a driver circuit 735, a driver circuit 736, a pixel 737, and an FPC 732. The sealant 734 is disposed between the substrate 700 and the substrate 750 so as to surround the pixel 737, the drive circuit 735, and the drive circuit 736. Note that the drive circuit 735 and / or the drive circuit 736 may be disposed outside the sealant 734.

FIG. 47C is a cross-sectional view of the EL display device corresponding to part of the dashed-dotted line MN in FIG.

A transistor having a structure similar to that of the transistor 12 can be used as the transistor 741. As the capacitor 742, a capacitor having a structure similar to that of the capacitor 13 can be used.

An insulator 720 is provided over the transistor 741 and the capacitor 742. A conductor 781 is provided over the insulator 720. The conductor 781 is electrically connected to the transistor 741 through the opening of the insulator 720.

A partition 784 having an opening reaching the conductor 781 is provided over the conductor 781. A light-emitting layer 782 that is in contact with the conductor 781 through the opening of the partition 784 is provided over the partition 784. A conductor 783 is provided over the light-emitting layer 782. A region where the conductor 781, the light emitting layer 782, and the conductor 783 overlap with each other serves as the light emitting element 719.

Up to this point, an example of an EL display device has been described. Next, an example of a liquid crystal display device will be described.

FIG. 48A is a circuit diagram illustrating a configuration example of a pixel of a liquid crystal display device. The pixel shown in FIG. 48 includes a transistor 751, a capacitor 752, and an element (liquid crystal element) 753 filled with liquid crystal between a pair of electrodes.

As the transistor 751, a transistor having a structure similar to that of the transistor 12 can be used. As the capacitor 752, a capacitor having a structure similar to that of the capacitor 13 can be used.

In the transistor 751, one of a source and a drain is electrically connected to the signal line 755, and a gate is electrically connected to the scan line 754.

In the capacitor 752, one electrode is electrically connected to the other of the source and the drain of the transistor 751, and the other electrode is electrically connected to a wiring for supplying a common potential.

In the liquid crystal element 753, one electrode is electrically connected to the other of the source and the drain of the transistor 751, and the other electrode is electrically connected to a wiring for supplying a common potential. Note that the common potential applied to the wiring to which the other electrode of the capacitor 752 is electrically connected may be different from the common potential applied to the other electrode of the liquid crystal element 753.

Note that the top view of the liquid crystal display device is the same as that of the EL display device. A cross-sectional view of the liquid crystal display device corresponding to the dashed-dotted line MN in FIG. 47B is illustrated in FIG. In FIG. 48B, the FPC 732 is connected to a wiring 733a through a terminal 731. Note that the wiring 733a may be formed using the same kind of conductor or semiconductor as the conductor or semiconductor included in the transistor 751.

The description of the transistor 741 is referred to for the transistor 751. For the capacitor 752, the description of the capacitor 742 is referred to. Note that FIG. 48B illustrates a structure of the capacitor 752 corresponding to the capacitor 742 in FIG. 47C; however, the structure is not limited thereto.

Note that in the case where an oxide semiconductor is used for the semiconductor of the transistor 751, a transistor with extremely low off-state current can be obtained. Therefore, the charge held in the capacitor 752 is unlikely to leak, and the voltage applied to the liquid crystal element 753 can be maintained for a long time. Therefore, when a moving image or a still image with little movement is displayed, the transistor 751 is turned off, so that power for the operation of the transistor 751 is not necessary and a liquid crystal display device with low power consumption can be obtained. In addition, since the area occupied by the capacitor 752 can be reduced, a liquid crystal display device with a high aperture ratio or a liquid crystal display device with high definition can be provided.

An insulator 720 is provided over the transistor 751 and the capacitor 752. A conductor 791 is provided over the insulator 720. The conductor 791 is electrically connected to the transistor 751 through the opening of the insulator 720.

An insulator 792 functioning as an alignment film is provided over the conductor 791. A liquid crystal layer 793 is provided over the insulator 792. An insulator 794 functioning as an alignment film is provided over the liquid crystal layer 793. A spacer 795 is provided over the insulator 794. A conductor 796 is provided over the spacer 795 and the insulator 794. A substrate 797 is provided over the conductor 796.

Liquid crystal driving methods include a TN (Twisted Nematic) mode, an STN (Super Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, and an MVA (Multi-Antential Switching). Mode, PVA (Patterned Vertical Alignment) mode, ASV (Advanced Super View) mode, ASM (Axial Symmetrically Coated MicroBell) mode, OCB (Optically Compensated BEC) mode ntrapped birefringence (FLC) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (Antiferroelectric Liquid Crystal) mode, PDLC (Polymer Dispersed Liquid Crystal) mode, guest h mode, blue mode However, the present invention is not limited to this, and various driving methods can be used.

With the above structure, a display device including a capacitor with a small occupied area can be provided, or a display device with high display quality can be provided. Alternatively, a high-definition display device can be provided.

For example, in this specification and the like, a display element, a display device that is a device including a display element, a light-emitting element, and a light-emitting device that is a device including a light-emitting element have various forms or have various elements. Can do. A display element, a display device, a light-emitting element, or a light-emitting device includes, for example, white, red, green, or blue light-emitting diodes (LEDs), transistors (transistors that emit light in response to current), electron-emitting devices, and liquid crystals Element, electronic ink, electrophoretic element, grating light valve (GLV), plasma display (PDP), display element using MEMS (micro electro mechanical system), digital micromirror device (DMD), DMS (digital Micro shutter), IMOD (interference modulation) element, shutter type MEMS display element, optical interference type MEMS display element, electrowetting element, piezoelectric ceramic display, carbon It has at least one of a display element using a tube. In addition to these, a display medium in which contrast, luminance, reflectance, transmittance, or the like is changed by an electric or magnetic action may be included.

An example of a display device using an EL element is an EL display. As an example of a display device using an electron-emitting device, there is a field emission display (FED), an SED type flat display (SED), or the like. As an example of a display device using a liquid crystal element, there is a liquid crystal display (a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct view liquid crystal display, a projection liquid crystal display) and the like. An example of a display device using electronic ink or an electrophoretic element is electronic paper. Note that in the case of realizing a transflective liquid crystal display or a reflective liquid crystal display, part or all of the pixel electrode may have a function as a reflective electrode. For example, part or all of the pixel electrode may have aluminum, silver, or the like. Further, in that case, a memory circuit such as an SRAM can be provided under the reflective electrode. Thereby, power consumption can be further reduced.

In addition, when using LED, you may arrange | position graphene or graphite under the electrode and nitride semiconductor of LED. Graphene or graphite may be a multilayer film in which a plurality of layers are stacked. Thus, by providing graphene or graphite, a nitride semiconductor such as an n-type GaN semiconductor having a crystal can be easily formed thereon. Furthermore, a p-type GaN semiconductor having a crystal or the like can be provided thereon to form an LED. Note that an AlN layer may be provided between graphene or graphite and an n-type GaN semiconductor having a crystal. Note that the GaN semiconductor included in the LED may be formed by MOCVD. However, by providing graphene, the GaN semiconductor included in the LED can be formed by a sputtering method.

The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 6)
In this embodiment, an example in which the semiconductor device or the memory circuit described in the above embodiment is applied to an electronic component, and an example in which the semiconductor device or the memory circuit is applied to an electronic device including the electronic component are described with reference to FIGS. explain.

FIG. 49A illustrates an example in which the semiconductor device or the memory circuit described in the above embodiment is applied to an electronic component. Note that the electronic component is also referred to as a semiconductor package or an IC package. This electronic component has a plurality of standards and names depending on the terminal take-out direction and the shape of the terminal. Therefore, in this embodiment, an example will be described.

A circuit portion including a transistor as described in the above embodiment is completed by combining a plurality of detachable components with a printed circuit board through an assembly process (post-process).

The post-process can be completed through each process shown in FIG. Specifically, after the element substrate obtained in the previous process is completed (step S1), the back surface of the substrate is ground (step S2). This is because by reducing the thickness of the substrate at this stage, it is possible to reduce the warpage of the substrate in the previous process and to reduce the size of the component.

FIG. 49B shows the structure of the semiconductor substrate after step S2. A substrate 1000 illustrated in FIG. 49B includes a plurality of circuit portions 1013 and a dicing region 1020. The circuit portion 1013 includes the semiconductor device of one embodiment of the present invention.

After grinding the back surface of the substrate, a dicing process is performed to separate the substrate into a plurality of chips. Then, a die bonding process is performed in which the separated chips are individually picked up and mounted on the lead frame and bonded (step S3). For the bonding between the chip and the lead frame in this die bonding process, a suitable method is appropriately selected according to the product, such as bonding with a resin or bonding with a tape. The die bonding step may be mounted on the interposer and bonded.

Next, wire bonding is performed in which the lead of the lead frame and the electrode on the chip are electrically connected by a thin metal wire (wire) (step S4). A silver wire or a gold wire can be used as the metal thin wire. For wire bonding, ball bonding or wedge bonding can be used.

The wire-bonded chip is sealed with an epoxy resin or the like and subjected to a molding process (step S5). By performing the molding process, the inside of the electronic component is filled with resin, which can reduce damage to the built-in circuit part and wires due to mechanical external force, and can reduce deterioration of characteristics due to moisture and dust. it can.

Next, the lead of the lead frame is plated. Then, the lead is cut and molded (step S6). By this plating treatment, rusting of the lead can be prevented, and soldering when mounting on a printed circuit board can be performed more reliably.

Next, a printing process (marking) is performed on the surface of the package (step S7). An electronic component is completed through a final inspection process (step S8) (step S9).

The electronic component described above can include the semiconductor device or the memory circuit described in the above embodiment. Therefore, an electronic component with reduced power consumption can be realized.

FIG. 49C is a schematic perspective view of the completed electronic component. FIG. 49C shows a schematic perspective view of a QFP (Quad Flat Package) as an example of an electronic component. An electronic component 1010 shown in FIG. 49C shows a lead 1011 and a circuit portion 1013. An electronic component 1010 shown in FIG. 49C is mounted on a printed board 1012, for example. A plurality of such electronic components 1010 are combined and each is electrically connected on the printed circuit board 1012 so that the electronic component 1010 can be mounted inside the electronic device. The completed circuit board 1014 is provided inside an electronic device or the like.

In addition, a semiconductor device, a memory circuit, and an electronic component according to one embodiment of the present invention can reproduce a recording medium such as a display device, a computer, and a recording medium (typically, a DVD: Digital Versatile Disc, It can be used for a device having a display capable of displaying the image. Here, the computer includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system. In addition, the semiconductor device described in any of the above embodiments can be used for a memory chip, and can be packaged to be a main memory module (for example, one having a function that can replace the DRAM module).

In addition, as an electronic device in which the semiconductor device according to one embodiment of the present invention can be used, a mobile phone, a game machine including a portable type, a portable information terminal, an electronic book terminal, a video camera, a digital still camera, or the like, goggles Type display (head-mounted display), navigation system, sound playback device (car audio, digital audio player, etc.), copier, facsimile, printer, printer multifunction device, automatic teller machine (ATM), vending machine, medical equipment Etc. Specific examples of these electronic devices are shown in FIGS.

FIG. 50A illustrates a portable game machine including a housing 2001, a housing 2002, a display portion 2003, a display portion 2004, a microphone 2005, a speaker 2006, operation keys 2007, a stylus 2008, and the like. The semiconductor device according to one embodiment of the present invention can be used for various integrated circuits of a portable game machine. Note that although the portable game machine illustrated in FIG. 50A includes the two display portions 2003 and 2004, the number of display portions included in the portable game device is not limited thereto.

FIG. 50B illustrates a portable information terminal which includes a first housing 2601, a second housing 2602, a first display portion 2603, a second display portion 2604, a connection portion 2605, operation keys 2606, and the like. The semiconductor device according to one embodiment of the present invention can be used for various integrated circuits of a portable information terminal. The first display portion 2603 is provided in the first housing 2601, and the second display portion 2604 is provided in the second housing 2602. The first housing 2601 and the second housing 2602 are connected by a connection portion 2605, and the angle between the first housing 2601 and the second housing 2602 can be changed by the connection portion 2605. is there. The video on the first display portion 2603 may be switched according to the angle between the first housing 2601 and the second housing 2602 in the connection portion 2605. Further, a display device to which a function as a position input device is added to at least one of the first display portion 2603 and the second display portion 2604 may be used. Note that the function as a position input device can be added by providing a touch panel on the display device. Alternatively, the function as a position input device can be added by providing a photoelectric conversion element called a photosensor in a pixel portion of a display device.

FIG. 50C illustrates a laptop personal computer, which includes a housing 2401, a display portion 2402, a keyboard 2403, a pointing device 2404, and the like. The semiconductor device according to one embodiment of the present invention can be used for various integrated circuits of a notebook personal computer.

FIG. 50D illustrates an electric refrigerator-freezer which includes a housing 2301, a refrigerator door 2302, a freezer door 2303, and the like. The semiconductor device according to one embodiment of the present invention can be used for various integrated circuits of an electric refrigerator-freezer.

FIG. 50E illustrates a video camera, which includes a first housing 2801, a second housing 2802, a display portion 2803, operation keys 2804, a lens 2805, a connection portion 2806, and the like. The semiconductor device according to one embodiment of the present invention can be used for various integrated circuits of a video camera. The operation key 2804 and the lens 2805 are provided in the first housing 2801, and the display portion 2803 is provided in the second housing 2802. The first housing 2801 and the second housing 2802 are connected by a connection portion 2806, and the angle between the first housing 2801 and the second housing 2802 can be changed by the connection portion 2806. is there. The video on the display portion 2803 may be switched according to the angle between the first housing 2801 and the second housing 2802 in the connection portion 2806.

FIG. 50F illustrates a passenger car that includes a car body 2101, wheels 2102, a dashboard 2103, lights 2104, and the like. The semiconductor device according to one embodiment of the present invention can be used for various integrated circuits of a passenger car.

The structures and methods described in this embodiment can be combined as appropriate with any of the structures and methods described in the other embodiments.

The structures and methods described in this embodiment can be combined as appropriate with any of the structures and methods described in the other embodiments.

10 cell array 11 memory cell 11a memory cell 11b memory cell 12 transistor 13 capacitor 15a region 15b region 16 layer 30 sense amplifier circuit 31 sense amplifier 31a sense amplifier 31b sense amplifier 31c sense amplifier 31d sense amplifier 32 amplifier circuit 33 switch circuit 34 precharge Circuit 35 Transistor 36 Layer 40 Memory circuit 51 Memory cell 52 Transistor 53 Capacitor 55 Transistor 56 Layer 57 Layer 70 Drive circuit 80 Main amplifier 90 Input / output circuit 91 Transistor 92 Transistor 93 Transistor 94 Transistor 95 Transistor 96 Transistor 97 Transistor 98 Transistor 99 Transistor 110 Insulator 111 Conductor 112 Conductor 113 Insulator 114 Semiconductor 114a Insulator 1 4b Semiconductor 114c Insulator 115 Conductor 116 Conductor 117 Insulator 118 Conductor 119 Insulator 120 Insulator 121 Insulator 124 Conductor 125 Conductor 126 Insulator 130 Substrate 131 Insulator 132 Low resistance region 133 Low resistance region 134 Insulation Body 135 Insulator 136 Conductor 137 Insulator 140 Insulator 141 Insulator 142 Insulator 144 Insulator 145 Insulator 146 Conductor 150 Insulator 151 Insulator 152 Insulator 153 Insulator 157 Insulator 159 Insulator 161 Insulator 170 Conductor 211 Conductor 215 Conductor 218 Conductor 700 Substrate 719 Light emitting element 720 Insulator 731 Terminal 732 FPC
733a wiring 734 sealant 735 drive circuit 736 drive circuit 737 pixel 741 transistor 742 capacitor element 743 switch element 744 signal line 750 substrate 751 transistor 752 capacitor element 753 liquid crystal element 754 scan line 755 signal line 781 conductor 782 light emitting layer 783 conductor 784 Partition 791 Conductor 792 Insulator 793 Liquid crystal layer 794 Insulator 795 Spacer 796 Conductor 797 Substrate 900 Semiconductor device 901 Power supply circuit 902 Circuit 903 Potential generation circuit 903a Potential generation circuit 903b Potential generation circuit 903c Potential generation circuit 903d Potential generation circuit 904 circuit 905 potential generation circuit 905a potential generation circuit 905b potential generation circuit 905d potential generation circuit 906 circuit 911 transistor 912 transistor 912a transistor 912b Transistor 921 Control circuit 922 Transistor 1000 Board 1010 Electronic component 1011 Lead 1012 Printed board 1013 Circuit part 1014 Circuit board 1020 Dicing area 2001 Case 2002 Case 2003 Display part 2004 Display part 2005 Microphone 2006 Speaker 2007 Operation key 2008 Stylus 2101 Car body 2102 Wheel 2103 Dashboard 2104 Light 2301 Case 2302 Refrigerating room door 2303 Freezing room door 2401 Case 2402 Display unit 2403 Keyboard 2404 Pointing device 2601 Case 2602 Case 2603 Display unit 2604 Display unit 2605 Connection unit 2606 Operation key 2801 Case 2802 Housing 2803 Display unit 2804 Operation key 2805 Lens 2806 Connection unit

Claims (9)

A transistor, a capacitor, and an insulator;
The transistor includes a back gate electrode and an oxide semiconductor,
The capacitive element has a first electrode and a second electrode,
One of a source and a drain of the transistor is electrically connected to the first electrode;
The back gate electrode is provided on a surface of the insulator;
The second electrode is provided on a surface of the insulator;
The first electrode has a region overlapping the second electrode with the insulator interposed therebetween,
The back gate electrode has a region overlapping with the oxide semiconductor with the insulator interposed therebetween,
The back gate electrode and the second electrode are made of the same material,
The height from the surface of the insulator to the top of the back gate electrode is equal to the height from the surface of the insulator to the top of the second electrode. In claim 1,
The height from the surface of the insulator to the top of the back gate electrode and the height from the surface of the insulator to the top of the second electrode are 100 nm to 500 nm. In claim 1 or 2,
The other of the source and the drain of the transistor is provided in a circular shape when viewed from above,
One of the source and the drain of the transistor and the first electrode of the capacitor are provided outside the other of the source and the drain of the transistor as viewed from above. In claim 3,
One of the source and the drain of the transistor and the first electrode of the capacitor are provided concentrically as viewed from above. In any one of Claims 1 thru | or 4,
The oxide semiconductor is a semiconductor device including indium, element M (Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf), zinc, and oxygen.   A method for manufacturing a semiconductor device, wherein a back gate electrode of a transistor and one of electrodes of a capacitor are formed in the same step. A plurality of the semiconductor devices according to claim 1;
A semiconductor substrate having an area for dicing.   A circuit board comprising: an electronic component having the semiconductor device according to claim 1; and a printed board.   An electronic apparatus comprising the semiconductor device according to claim 1 or the circuit board according to claim 8, and a display unit, a microphone, a speaker, or an operation key.