JP2017084979A - Wiring formation method and wiring structure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form the wiring with higher accuracy compared with before, when forming multiple types of wiring of different wiring widths by electroplating process.SOLUTION: A wiring formation method includes a step of forming a conductive seed layer on an insulator film, a step of making the electrical resistance of a seed layer in a region where first wiring having a width larger than a predetermined value is formed, higher than the electrical resistance of a seed layer in a region where second wiring having a width of a predetermined value or less is formed, a step of forming a mask layer, having a first opening where the first wiring is formed and a second opening where the second wiring is formed, on the seed layer, a step of performing electroplating by using the seed layer as an electrode, and forming the first wiring and second wiring in the first opening and second opening, a step of removing the mask layer after forming the first wiring and second wiring, and a step of removing the seed layer not covered with the first wiring and second wiring, after the mask layer is removed.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a wiring formation method and a wiring structure.

  A semi-additive method is known as a method for forming wiring on a substrate such as a printed board or an interposer. In the semi-additive method, after a seed layer (conductive thin film) is formed on an electrically insulating substrate, a photoresist is selectively formed in a region where no wiring is formed, and a seed layer not covered with the photoresist is formed. In this method, wiring is formed by electroplating as an electrode. For example, when a positioning mark is formed on a printed circuit board, a region where a seed layer is not formed is provided around the region where the mark is to be formed, and the amount of current supplied to the region where the mark is formed during electroplating is reduced. A technique for reducing the number has been proposed (see, for example, Patent Document 1). By reducing the amount of current supplied to the seed layer exposed in the region where the mark is to be formed, the mark is formed thinner than when the amount of current supplied is not reduced. As a result, the inclination around the mark becomes inconspicuous, and a decrease in the recognition accuracy of the positioning mark is suppressed.

  In addition, if the thickness of the wiring formed by the semi-additive method does not reach the specified value, there is a technique in which a mask having a through hole having a size corresponding to the thickness of the wiring is arranged on the wiring region and electroplating is performed again. It has been proposed (see, for example, Patent Document 2). In this method, the thinner the wiring with respect to the specified value, the larger the through hole is formed, and the electrolytic solution for electroplating easily flows through the through hole to the region where the thickness of the wiring is insufficient. Thickness is aligned.

JP 2010-182749 A JP 2014-86714 A

  A power supply wiring (power supply line and ground line) having a width wider than the width of the signal wiring is formed along with the signal wiring on a substrate such as a printed board and an interposer. In recent years, along with miniaturization of elements mounted on LSI (Large Scale Integration), signal wirings formed on substrates such as printed boards and interposers tend to be miniaturized. For example, when signal wiring is formed by electroplating using the semi-additive method, the thinner the opening of the photoresist that forms the signal wiring, the more difficult it is to circulate the electrolyte for electroplating. It becomes thinner than the thickness of the power supply wiring. The thickness of the photoresist used as a mask during electroplating is determined according to the maximum thickness of the wiring formed by electroplating. When matching the thickness of the photoresist with the thickness of the power supply wiring formed by electroplating, the aspect ratio of the opening of the photoresist for signal wiring is when matching the thickness of the photoresist with the thickness of the signal wiring. Larger than Here, the aspect ratio is indicated by the ratio (depth / inner diameter) between the depth and the inner diameter of the opening of the photoresist. As the aspect ratio increases, it becomes more difficult to form the photoresist opening with high accuracy, and it becomes difficult to form the wiring formed in the opening with high accuracy.

  In one aspect, the wiring forming method and the wiring structure disclosed in the present disclosure are intended to form a wiring with higher accuracy than in the past when a plurality of types of wiring having different wiring widths are formed by electroplating. And

  According to one aspect, a method for forming a wiring includes a step of forming a conductive seed layer on an insulating film, and an electrical resistance of the seed layer in a region where a first wiring having a width larger than a predetermined value is formed. Is higher than the electrical resistance of the seed layer in the region where the second wiring having a width equal to or less than a predetermined value is formed, the first opening in which the first wiring is formed, and the second wiring Forming a mask layer having a second opening to be formed on the seed layer; performing electroplating using the seed layer as an electrode; forming a first wiring in the first opening; Forming the second wiring in the two openings, forming the first wiring and the second wiring, then removing the mask layer, removing the mask layer, And a step of removing the seed layer not covered with the two wirings.

  According to another aspect, there is provided a wiring structure in which a first wiring having a width larger than a predetermined value and a second wiring having a width equal to or smaller than a predetermined value are formed on an insulating film. A first metal film in contact with the insulating film side; and a second metal film in contact with the insulating film side of the second wiring and having a lower electrical resistance than the first metal film.

  The wiring forming method and wiring structure disclosed in the present disclosure can form wirings with higher accuracy than conventional methods when a plurality of types of wirings having different wiring widths are formed by electroplating.

It is a figure which shows one Embodiment of the formation method and wiring structure of wiring. It is a figure which shows another example of the formation method of wiring. It is a figure which shows another embodiment of the formation method of wiring, and wiring structure. It is a figure which shows an example of the electronic device containing the wiring structure formed in another another embodiment of the formation method of wiring. It is a figure which shows another embodiment of the formation method of wiring, and wiring structure. It is a figure which shows the continuation of FIG. It is a figure which shows the continuation of FIG. It is a figure which shows the continuation of FIG. It is a figure which shows the continuation of FIG. FIG. 10 is a diagram showing a continuation of FIG. 9. It is a figure which shows the continuation of FIG. It is a figure which shows the continuation of FIG. It is a figure which shows the continuation of FIG. It is a figure which shows the continuation of FIG. It is a figure which shows the continuation of FIG. It is a figure which shows the continuation of FIG. It is a figure which shows another embodiment of the formation method of wiring, and wiring structure. It is a figure which shows the continuation of FIG. It is a figure which shows the continuation of FIG. FIG. 20 is a diagram showing a continuation of FIG. 19. It is a figure which shows the continuation of FIG. It is a figure which shows the continuation of FIG.

  Hereinafter, embodiments will be described with reference to the drawings.

  FIG. 1 shows an embodiment of a wiring formation method and a wiring structure. FIG. 1 is a sectional view showing a manufacturing process for forming wiring on a substrate such as a printed circuit board and an interposer. The interposer is built in a package such as Fan Out WLP (Wafer Level Package) or MCP (Multi Chip Package), and connects the LSI chip and the substrate to each other or connects a plurality of LSI chips to each other. In the interposer, for example, glass or resin is used as a base material. For easy understanding, in FIG. 1 and other drawings, the thickness and aspect ratio of each element are different from the thickness and aspect ratio of an element formed on an actual substrate.

  In FIG. 1, a wiring having a width (for example, 10 microns) larger than a predetermined value (for example, 5 microns) and a wiring having a width not larger than a predetermined value (for example, 2 microns) are formed on the insulating film 10. The For example, a wiring having a width larger than a predetermined value is a power wiring that is supplied with a power supply voltage or a ground voltage, and a wiring having a width equal to or smaller than a predetermined value is a signal wiring through which a signal is transmitted. The power supply wiring and the signal wiring are formed on the insulating film 10 by performing the following steps.

  First, in FIG. 1A, a metal film 12 such as Cu (copper) is formed on the insulating film 10 by sputtering or the like. For example, the thickness of the metal film 12 is 100 nm. The insulating film 10 is formed using an organic material such as polyimide resin or phenol resin. The insulating film 10 may be formed using an inorganic material such as a silicon substrate.

  Next, in FIG. 1B, NiCu (nickel copper; for example, Ni: Cu = 1: 1 alloy) having a higher electrical resistance than Cu is formed in the power supply wiring region where the power supply wiring is formed on the metal film 12. The metal film 14 is formed. For example, the thickness of the metal film 14 is 50 nm. The metal film 14 is formed by using a photolithography method to cover the signal wiring region with a photoresist, sputtering NiCu, and removing the photoresist. Then, a seed layer SL made of a Cu film is formed in the signal wiring region, and a seed layer SL in which the Cu film and the NiCu film are stacked is formed in the power supply wiring region. The seed layer SL functions as an electrode for depositing metal during electroplating. The metal film 14 may be formed by sputtering the metal film 14 over the entire surface of the metal film 12 and then selectively removing the metal film 14 located in the signal wiring region using a photolithography method. .

  By forming the NiCu film on the Cu film, the resistance component in the thickness direction of the Cu film and the resistance component in the thickness direction of the NiCu film are connected in series in the power supply wiring region. Thereby, the electrical resistance of the seed layer SL by the Cu film and the NiCu film becomes higher than the electrical resistance of the seed layer SL by the Cu film formed in the signal wiring region. Here, since the electrical resistance determines the current that flows to deposit the metal on the seed layer SL during the electroplating process, the higher the electrical resistance, the more difficult the metal is deposited on the seed layer SL.

  Next, in FIG. 1C, a mask layer MSK having an opening OPa in which the metal film 14 is exposed in the power supply wiring region and an opening OPb in which the metal film 12 is exposed in the signal wiring region is a photoresist 16. It is formed using. For example, the thickness of the mask layer MSK is 2.5 microns. For example, the mask layer MSK is positioned on the openings OPb and OPa by forming a photoresist 16 on the metal films 12 and 14 and then selectively irradiating the photoresist 16 with light using the photomask (exposure). It is formed by removing the photoresist 16 by development. The photoresist 16 may be formed by applying a liquid photoresist, or may be formed by applying a film-like photoresist.

  Next, in FIG. 1D, electroplating is performed using the seed layer SL as an electrode, and a power wiring 18a such as Cu is formed in the opening OPa, and a signal wiring 18b such as Cu is formed in the opening OPb. It is formed. Here, since the groove formed by the opening OPb for the signal wiring 18b is narrower than the groove formed by the opening OPa for the power supply wiring 18a, the electrolytic solution for electroplating is difficult to circulate. For this reason, Cu is hard to precipitate in opening part OPb compared with opening part OPa. For example, when the width of the opening OPb is 5 microns or less, the metal is less likely to be deposited by the electroplating process than when the width is larger than 5 microns.

  In addition, the electrical resistance of the seed layer SL (metal film 12) exposed in the opening OPb is lower than the electrical resistance of the seed layer SL (laminated film formed of the metal films 12 and 14) exposed in the opening OPa. For this reason, from the viewpoint of the electrical resistance of the electrode, Cu is more likely to be deposited in the opening OPb than in the opening OPa. The film of the power supply wiring 18a and the signal wiring 18b respectively formed in the openings OPa and OPb having different widths by compensating the difficulty of deposition of Cu by the opening OPb having a narrow width by reducing the resistance of the seed layer SL. The thickness (that is, the height of the wiring) can be made equal to each other. In other words, the film thickness of the power supply wiring 18a and the signal wiring 18b can be made equal to each other by supplementing the ease of Cu deposition by the wide opening OPa by increasing the resistance of the seed layer SL. For example, the optimum value of the thickness of the metal film 14 is obtained by preparing a sample having an opening OPb from which the metal film 12 is exposed and a plurality of openings OPa from which the metal film 14 having various thicknesses is exposed, and performing electroplating. Evaluation is made by depositing Cu in the opening OPa and the plurality of openings OPb by the treatment.

  Next, in FIG. 1E, the photoresist 16 is removed.

  Next, in FIG. 1F, the metal films 12 and 14 not covered with the power supply wiring 18a and the signal wiring 18b are removed. For example, the metal films 12 and 14 are simultaneously removed by performing wet etching using the power supply wiring 18a and the signal wiring 18b as a mask. Then, a laminated film including the metal films 12 and 14 is formed between the power supply wiring 18 a and the insulating film 10, and a wiring structure including the metal film 12 is formed between the signal wiring 18 b and the insulating film 10. Note that the power supply wiring 18a and the signal wiring 18b extend in the depth direction of FIG. 1, and the wiring width of the power supply wiring 18a and the signal wiring 18b is the cross section (transverse cross section of the wiring) shown in FIG. It is indicated by the length in the horizontal direction.

  In the wiring structure shown in FIG. 1F, the line L / space S, which is the ratio of the width (L) of each signal wiring 18b and the interval (S) between the adjacent signal wirings 18b, is 2 microns / 2 microns. It is. In the first experiment for manufacturing the wiring structure shown in FIG. 1, the thickness of the power supply wiring 18a formed by electroplating is 2.8 microns, and the thickness of the signal wiring 18b is 2.0 microns. Met. Thereafter, the difference in thickness between the power supply wiring 18a and the signal wiring 18b was reduced by further increasing the electrical resistance of the laminated film formed of the metal films 12 and 14.

  1 shows an example in which the metal film 14 is stacked on the metal film 12 so that the electrical resistance of the seed layer SL exposed in the opening OPa is higher than the electrical resistance of the seed layer SL exposed in the opening OPb. Is shown. However, by forming single metal films having different electrical resistances in the power supply wiring region and the signal wiring region, respectively, the electrical resistance of the seed layer SL exposed in the opening OPa becomes the seed layer exposed in the opening OPb. It may be higher than the electrical resistance of SL. Further, by forming a plurality of metal films 14 having different thicknesses on the metal film 12, three or more types of seed layers SL having different electrical resistances may be formed. In this case, the film thicknesses of the wirings corresponding to the three or more kinds of wiring widths can be made equal to each other.

  FIG. 2 shows another example of a wiring formation method. Detailed descriptions of the same elements and steps as those in FIG. 1 are omitted. In FIG. 2, the wiring is formed without forming the metal film 14 such as NiCu shown in FIG. 1 in the power supply wiring region.

  First, in FIG. 2A, a metal film 12 such as Cu (seed layer SL) is formed on the insulating film 10 as in FIG.

  Next, in FIG. 2B, as in FIG. 1C, the opening OPa from which the metal film 12 is exposed is provided in the power supply wiring region, and the opening OPb from which the metal film 12 is exposed is provided as the signal wiring region. A mask layer MSK having the same is formed using the photoresist 16. Here, the mask layer MSK is formed to have a thickness about twice that of the mask layer MSK shown in FIG. 1, for example. The reason why the mask layer MSK is thicker than that in FIG. 1 will be described with reference to FIG.

  When the mask layer MSK is thick, the aspect ratio of the opening OPb (ratio between depth and inner diameter (depth / inner diameter)) is increased. Therefore, the mask layer MSK can be formed more accurately than the opening OPb shown in FIG. And the formation accuracy of the signal wiring 18b shown in FIG. For example, when the mask layer MSK is thick, in the signal wiring region, the photoresist 16 has a tapered shape that becomes wider toward the insulating film 10 side, and the width of the opening OPb on the insulating film 10 side becomes narrower. In this case, the signal wiring 18b having a desired width is not formed by the electroplating process.

  Next, in FIG. 2C, electroplating is performed using the seed layer SL as an electrode, and a power wiring 18a such as Cu is formed in the opening OPa, and a signal wiring 18b such as Cu is formed in the opening OPb. It is formed. Here, compared with the opening OPb, the opening OPa is easier to circulate the electrolytic solution for electroplating, and the electrical resistance of the seed layer SL exposed to the openings OPa and OPb is the same. Therefore, Cu is more likely to precipitate in the opening OPa than in the opening OPb, and the thickness of the power supply wiring 18a is about twice the thickness of the power supply wiring 18a shown in FIG. Since the conditions of the electroplating process in the opening OPb are the same as in FIG. 1, the thickness of the signal wiring 18b formed by Cu deposited in the opening OPb is equal to the thickness of the signal wiring 18b shown in FIG. is there. In the experiment for manufacturing the wiring structure shown in FIG. 2, when the thickness of the signal wiring 18b was 2.0 microns, the thickness of the power supply wiring 18a exceeded 4 microns.

  The thickness of the mask layer MSK is approximately twice the thickness of the mask layer MSK shown in FIG. 1 (for example, in accordance with the thickness of the power supply wiring 18a formed when the signal wiring 18b having a prescribed thickness is formed (for example, 5 microns). If the mask layer MSK has the same thickness as that of the mask layer MSK in FIG. 1 (for example, 2.5 microns), Cu deposited in the opening OPa by the electroplating process is removed from the upper surface of the mask layer MSK. It overflows and the normal power supply wiring 18a is not formed.

  Next, in FIG. 2D, the photoresist 16 is removed as in FIG.

  Next, in FIG. 2E, as in FIG. 1F, the metal film 12 that is not covered by the power supply wiring 18a and the signal wiring 18b is removed.

  FIG. 2F shows an example in which the insulating film 20 is formed so as to cover the power supply wiring 18a and the signal wiring 18b. When the power supply wiring 18a is thicker than the signal wiring 18b, a step is generated on the surface of the insulating film 20, so that it is difficult to form the next wiring layer on the power supply wiring 18a and the signal wiring 18b with high accuracy by photolithography. There is a fear.

  As described above, in the embodiment shown in FIG. 1, the film thicknesses of the power supply wiring 18a and the signal wiring 18b formed in the openings OPa and OPb having different widths can be made equal to each other. In other words, by making the electrical resistance of the seed layer SL exposed in the opening OPa higher than the electrical resistance of the seed layer SL exposed in the opening OPb, the deposition rate of Cu in the opening OPa is increased in the electroplating process. It can be made slow in accordance with the deposition rate of Cu in the part OPb. As a result, even when the line L / space S of the signal wiring 18b is about 2 microns / 2 microns which is thinner than the conventional one, the film thickness of the power wiring 18a and the signal wiring 18b can be made equal to each other.

  Further, as shown in FIG. 2, it is possible to prevent the power supply wiring 18a from being thicker than the signal wiring 18b, so that the mask layer MSK (photoresist 16) is matched to the signal wiring 18b. It can be formed to a different thickness. As a result, it is possible to prevent the aspect ratio of the opening OPb forming the signal wiring 18b from becoming high as shown in FIG. As a result, even when the line L / space S of the signal wiring 18b is about 2 microns / 2 microns, a mask pattern made of the photoresist 16 can be formed with higher accuracy than in the past, and the signal wiring 18b It can be formed with high accuracy.

  Further, since the thickness of the power supply wiring 18a can be formed to be equal to the thickness of the signal wiring 18b, the mask layer MSK is deposited in the opening OPa even when the thickness of the mask layer MSK is reduced compared to FIG. Cu can be prevented from overflowing from the upper surface of the mask layer MSK. As a result, a wiring structure having a normal power supply wiring 18a can be formed.

  FIG. 3 shows another embodiment of a wiring formation method and a wiring structure. Detailed descriptions of the same elements and similar steps as those in FIG. 1 are omitted. The dimensions of each element shown in FIG. 3 are the same as the dimensions described in FIG. In FIG. 3, the wiring is formed without forming the metal film 14 such as NiCu shown in FIG. 1 in the power supply wiring region.

  First, in FIG. 3A, a metal film 12 such as Cu is formed on the insulating film 10 as in FIG.

  Next, in FIG. 3B, similarly to FIG. 1C, the opening OPa from which the metal film 12 is exposed is provided in the power supply wiring region, and the opening OPb from which the metal film 12 is exposed is provided as the signal wiring region. A mask layer MSK having the same is formed using the photoresist 16. Since the thickness of the mask layer MSK is the same as that in FIG. 1, the problem of the aspect ratio of the opening OPb described in FIG. 2 does not occur, and the signal wiring 18b (FIG. 3D) is equivalent to that in FIG. It can be formed with the accuracy of

  Next, in FIG. 3C, the metal film 12 exposed in the openings OPa and OPb is dry-etched with an inert gas such as Ar. The inert gas ionized at the time of dry etching is less likely to enter the narrow groove formed by the opening OPb than the wide groove formed by the opening OPa. For this reason, the etching rate of the metal film 12 exposed in the opening OPb is lower than the etching rate of the metal film 12 exposed in the opening OPa.

  For example, when the aspect ratio of the opening OPb having a width of 2 microns exceeds “1”, the metal film 12 exposed to the opening OPb is hardly etched. On the other hand, since the metal film 12 exposed in the opening OPa is normally etched, the thickness of the metal film 12 exposed in the opening OPa is equal to the thickness of the metal film 12 exposed in the opening OPb. It will be thinner. Here, when the seed layer SL is formed by one metal film 12, the electrical resistance of the seed layer SL is represented by a resistance component in a direction along the surface of the substrate 10. For this reason, the electrical resistance of the relatively thin seed layer SL exposed in the opening OPa is higher than the electrical resistance of the relatively thick seed layer SL exposed in the opening OPb.

  Next, in FIG. 3D, similarly to FIG. 1D, electroplating is performed using the seed layer SL as an electrode, and a power wiring 18a such as Cu is formed in the opening OPa, and Cu or the like is formed. The signal wiring 18b is formed in the opening OPb. As in FIG. 1, the electrical resistance of the seed layer SL exposed at the opening OPa is higher than the electrical resistance of the seed layer SL exposed at the opening OPb. In addition, the groove formed by the opening OPb is less likely to circulate the electrolytic solution for electroplating than the groove formed by the opening OPa, as in FIG. Therefore, as in FIG. 1, the film thicknesses (that is, the heights of the wirings) of the power supply wiring 18a and the signal wiring 18b formed in the openings OPa and OPb having different widths can be made equal to each other. Note that the optimum value of the etching amount of the metal film 12 in the power supply wiring region is evaluated by creating a plurality of samples having different processing times of the dry etching described with reference to FIG.

  Next, in FIG. 3E, the photoresist 16 is removed as in FIG.

  Next, in FIG. 3F, as in FIG. 1F, the metal film 12 not covered with the power supply wiring 18a and the signal wiring 18b is removed. Then, a wiring structure in which the metal film 12 between the power supply wiring 18 a and the insulating film 10 is thinner than the metal film 12 between the signal wiring 18 b and the insulating film 10 is formed.

  In the wiring structure shown in FIG. 3F, as in FIG. 1F, the line L /, which is the ratio between the width (L) of each signal wiring 18b and the interval (S) between the adjacent signal wirings 18b. The space S is 2 microns / 2 microns. In the first experiment for manufacturing the wiring structure shown in FIG. 3, the thickness of the power supply wiring 18a formed by electroplating is 2.2 microns, and the thickness of the signal wiring 18b is 2.0 microns. Met. Thereafter, the difference between the thickness of the power supply wiring 18a and the thickness of the signal wiring 18b was reduced by further increasing the electric resistance of the metal film 12 in the power supply wiring region.

  After the metal film 12 having a predetermined thickness is formed, the metal film 12 is further formed selectively in the signal wiring region by using a photolithography method, so that the thickness of the metal film 18 in the power supply wiring region is increased. May be made relatively thinner than the thickness of the metal film 12 in the signal wiring region.

  As described above, in the embodiment shown in FIG. 3, as in the embodiment shown in FIG. 1, the film thicknesses of the power supply wiring 18a and the signal wiring 18b formed in the openings OPa and OPb having different widths are made equal to each other. be able to. Further, since the aspect ratio of the opening OPb for the signal wiring 18b can be prevented from being increased as shown in FIG. 2, the mask pattern made of the photoresist 16 can be formed with higher accuracy than in the prior art. The signal wiring 18b can be formed with high accuracy. Furthermore, since Cu deposited on the opening OPa by the electroplating process can be prevented from overflowing from the upper surface of the mask layer MSK, a wiring structure having a normal power supply wiring 18a can be formed.

  Further, in the embodiment shown in FIG. 3, the Cu film in the power supply wiring region is selectively etched without selectively forming the NiCu film in the power supply wiring region, so that it is exposed to the opening 18 a in the power supply wiring region. The resistance of the seed layer SL is increased. Thus, the steps of forming, exposing, developing and removing the photoresist 16 for forming the NiCu film can be omitted, and the number of steps for forming the wiring structure shown in FIG. Can be reduced compared to As a result, the manufacturing cost of the wiring structure can be reduced compared to the manufacturing cost of the wiring structure shown in FIG.

  FIG. 4 shows an example of an electronic device 100 including a wiring structure formed in still another embodiment of a wiring forming method. FIG. 4 shows a cross section of the electronic device 100. The electronic device 100 shown in FIG. 4 is formed by connecting a plurality of LSI chips 110 a and 110 b and a printed circuit board 120 to each other via an interposer 130. A substrate for ensuring the rigidity of the interposer 130 may be provided on the surface of the interposer 130 on the printed circuit board 120 side. Also, the electronic device 100 shown in FIG. 4 may be provided in the form of an MCP.

  The pad (not shown) of the LSI chip 110a is connected to the electrode (pad) of the interposer 130 via the bump BP1a, and the pad (not shown) of the LSI chip 110b is connected to the electrode (pad) of the interposer 130 via the bump BP1b. Pad). The terminal TM of the printed circuit board 120 is connected to the electrode (pad) of the interposer 130 through the bump BP2. The LSI chips 110a and 110b and the printed circuit board 120 are connected to each other via wiring formed in the interposer 130. In the example shown in FIG. 4, the interposer 130 includes an electrode layer E1 on which an electrode connected to the terminal TM of the printed circuit board 120 is formed, and an electrode layer E2 on which an electrode connected to the pads of the LSI chips 110a and 110b is formed. Have. The interposer 130 includes wiring layers W1 and W2 that are provided between the electrode layers E1 and E2 and in which signal wirings and power supply wirings are formed.

  5 to 16 show a method for manufacturing the interposer 130 shown in FIG. That is, FIGS. 5 to 16 show another embodiment of the wiring formation method and wiring structure. Detailed descriptions of the same elements and similar steps as those in FIG. 1 are omitted. For easy understanding, the wiring structure in the interposer 130 manufactured by the processes in FIGS. 5 to 16 is different from that in FIG.

  First, in FIG. 5A, a metal film 32 such as Ni is formed on an electrically insulating base substrate 30 by sputtering or the like. Next, in FIG. 5B, the photoresist 16 is formed, exposed and developed by photolithography, and a photo is applied to the portion corresponding to the electrode connected to the terminal TM of the printed circuit board 120 shown in FIG. A mask layer MSK leaving the resist 16 is formed. The photoresist 16 may be formed by applying a liquid photoresist, or may be formed by applying a film-like photoresist.

  Next, in FIG. 5C, the metal film 32 not covered with the photoresist 16 is removed by wet etching or the like, and electrodes EL1, EL2, and EL3 connected to the terminals TM of the printed circuit board 120 are formed. For example, the electrodes EL1 and EL2 are formed for a power supply, and the electrode EL3 is formed for a signal. Next, in FIG. 5D, the photoresist 16 is removed, and an electrode layer E1 is formed.

  Next, in FIG. 6A, a photosensitive insulating film 34 is formed over the base substrate 30 so as to cover the electrodes EL1 to EL3. The photosensitive insulating film 34 may be formed by applying a liquid material onto the base substrate 30, or may be formed by attaching a film-like material onto the base substrate 30. Since the photosensitive insulating film 34 remains in the interposer 130 after the interposer 130 is manufactured, it is also referred to as a permanent resist.

  Next, in FIG. 6B, exposure and development are performed by a photolithography method, and openings OP1, OP2, and OP3 are formed over the electrodes EL1, EL2, and EL3. Next, in FIG. 6C, a metal film 36 of Cu or the like is formed on the insulating film 34 and inside the openings OP1-OP3 by sputtering or the like, and the metal film 36 is exposed to the openings OP1-OP3. Connected to electrodes EL1-EL3.

  Next, in FIG. 7A, a photoresist 16 is formed, exposed, and developed by photolithography, and a mask layer MSK having an opening OP4 in a region including the power supply electrodes EL1 and EL2 is formed. It is formed. Next, in FIG. 7B, a metal film 38 such as NiCu (for example, an alloy of Ni: Cu = 1: 1) is formed on the photoresist 16 and inside the opening OP4 by sputtering or the like. Thereby, a laminated film of the Cu film (metal film 36) and the NiCu film (metal film 38) is formed inside the opening OP4.

  Next, in FIG. 7C, the photoresist 16 is removed. The metal film 38 sputtered on the photoresist 16 is removed together with the photoresist 16. Then, a seed layer SL made of a Cu film (metal film 36) and a NiCu film (metal film 38) is formed in the power supply wiring region corresponding to the electrodes EL1 and EL2, and Cu is formed in the signal wiring region corresponding to the electrode EL3. A seed layer SL is formed from the film (metal film 36). As described with reference to FIG. 1, the electrical resistance of the seed layer SL formed by the Cu film and the NiCu film formed in the power supply wiring region is higher than the electrical resistance of the seed layer SL formed by the Cu film formed in the signal wiring region.

  Next, in FIG. 8A, a mask having openings OP5 where the metal film 38 is exposed in the power supply wiring region and openings OP6 and OP7 where the metal film 36 is exposed is formed in the signal wiring region by photolithography. Layer MSK is formed using photoresist 16. Note that the opening OP7 is formed for a signal wiring extending in the horizontal direction of FIG. For this reason, the width of the opening OP7 (that is, the width of the wiring) in the cross-sectional direction of the signal wiring (the depth direction in FIG. 8A) is the opening for the via (contact) exposed to the electrode EL3 in the opening OP6. The same width as 2 microns.

  Next, in FIG. 8B, electroplating is performed using the seed layer SL as an electrode, and a power wiring 18a such as Cu is formed in the opening OP5, and signal wirings 18b and 18c such as Cu are formed in the opening. It is formed in OP6 and OP7, respectively. Here, since the electrical resistance of the seed layer SL exposed in the wide opening OP5 is higher than the electrical resistance of the seed layer SL exposed in the narrow openings OP6 and OP7, as described with reference to FIG. The wiring 18a and the signal wirings 18b and 18c can have the same film thickness.

  Further, in the power supply wiring 18a and the signal wirings 18b and 18c, the wiring (via) formed in the insulating film 34 and connected to the electrodes EL1 to EL3 is independent of the width of the power supply wiring 18a and the signal wiring 18b and 18c. They are the same size. For this reason, the electrolytic solution for electroplating circulates to the same degree in the openings for vias (openings OP1, OP2, OP3 shown in FIG. 6B), and Cu is supplied to the via openings. The deposition rate is determined depending on the electric resistance of the seed layer SL. Therefore, the deposition rate of Cu in the via for the power supply wiring 18a is slower than the deposition rate of Cu in the via for the signal wiring 18b. Thereby, compared with the case where the metal film 38 made of NiCu is not formed in the via, the metal film 38 can be made thinner and the electric resistance in the thickness direction of the NiCu film can be lowered. As a result, the NiCu sputtering time can be shortened, and NiCu used for sputtering can be saved.

  Next, in FIG. 8C, the photoresist 16 is removed. Next, in FIG. 9A, the metal film 36 (Cu film) and the metal film 38 (NiCu film) which are not covered with the power supply wiring 18a and the signal wirings 18b and 18c are replaced with the power supply wiring 18a and the signal wiring 18b. , 18c as a mask and removed by wet etching or the like. Then, the wiring layer W1 is formed. The wirings 18a and 18b formed on the insulating film 34 extend in the depth direction of FIG. 9A, and the wiring 18c formed on the insulating film 34 extends in the horizontal direction of FIG. 9A. To do. For example, the width of the wiring 18a formed on the insulating film 34 is 10 microns, and the width of the wirings 18b and 18c formed on the insulating film 34 is 2.5 microns and 2 microns, respectively. In the wirings 18a and 18b, the width of the wiring (via) formed in the insulating film 34 and connected to the electrodes EL1 to EL3 is 2 microns.

  Next, in FIG. 9B, as in FIG. 6A, a photosensitive insulating film 34 is formed so as to cover the power supply wiring 18a and the signal wirings 18b and 18c. Next, in FIG. 9C, similarly to FIG. 6B, the insulating film 34 is exposed and developed, and openings OP8, OP9, and OP10 are formed on the power supply wiring 18a and the signal wiring 18b. . Note that when the new power supply wiring formed over the power supply wiring 18a is not connected to the power supply wiring 18a in the cross section shown in FIG. 9C, the openings OP8 and OP9 are not formed.

  Next, in FIG. 10A, a metal film 36 (Cu film) is formed as in FIG. 6C, and in FIG. 10B, in the power supply wiring region as in FIG. 7A. A mask layer MSK having an opening OP11 is formed from the resist 16. Next, in FIG. 10C, a metal film 38 (NiCu film) is formed as in FIG. 7B.

  Next, in FIG. 11A, the photoresist 16 is removed as in FIG. 7C, and in FIG. 11B, the opening for forming the power supply wiring is formed as in FIG. 8A. A mask layer MSK having a portion OP12 and a plurality of openings OP13 for forming signal wirings is formed.

  Next, in FIG. 12A, as in FIG. 8B, electroplating is performed using the seed layer SL as an electrode, and a power wiring 18a such as Cu is formed in the opening OP12, and Cu or the like is formed. The signal wirings 18b and 18d are formed in the opening OP13. In the cross section shown in FIG. 12A, the signal wiring 18d is not connected to the signal wiring formed in the wiring layer W1, and thus has no via (contact) connected to the wiring layer W1. Next, in FIG. 12B, the photoresist 16 is removed as in FIG. 8C.

  Next, in FIG. 13A, as in FIG. 9A, the metal films 36 and 38 that are not covered with the power supply wiring 18a and the signal wirings 18b and 18d are replaced with the power supply wiring 18a and the signal wirings 18b and 18d. Are removed by wet etching or the like. Then, the wiring layer W2 is formed. Wirings 18a, 18b, and 18d formed on the insulating film 34 extend in the depth direction of FIG. For example, the width of the wiring 18a formed on the insulating film 34 is 10 microns, and the width of the wirings 18b and 18d formed on the insulating film 34 is 2.5 microns and 2 microns, respectively. In the wirings 18a and 18b, the width of the wiring (via) formed in the insulating film 34 and connected to the wiring layer W1 is 2 microns. Next, in FIG. 13B, as in FIG. 9B, a photosensitive insulating film 34 is formed to cover the power supply wiring 18a and the signal wirings 18b and 18d.

  Next, in FIG. 14A, similarly to FIG. 9C, the insulating film 34 is exposed and developed, and openings OP14, OP15, and OP16 are formed on the power supply wiring 18a and the signal wiring 18b. . Next, in FIG. 14B, a metal film 36 (Cu film) is formed as in FIG.

  Next, in FIG. 15A, as in FIG. 10B, a mask layer MSK having a photoresist 16 is formed in a region excluding the openings OP14, OP15, and OP16. Next, in FIG. 15B, electroplating is performed using the seed layer SL as an electrode, and a metal film 40 such as Cu, a metal film 42 such as Ni, and a metal film 44 such as Cu are formed in the openings OP14 and OP15. , OP16. The laminated film formed of the metal films 40, 42, 44 is formed as an electrode connected to the pads of the LSI chips 110a, 110b shown in FIG. The sizes of the electrodes connected to the pads of the LSI chips 110a and 110b are the same regardless of the signal and the power source. For this reason, in the process of laminating the metal films 40, 42, and 44, unlike the process of forming the wiring layers W1 and W2, the NiCu film that increases the resistance of the seed layer SL is not formed.

  Next, in FIG. 16A, as in FIG. 12B, the photoresist 16 is removed, and the electrodes EL4, EL5, EL6 connected to the pads of the LSI chips 110a, 110b are exposed on the insulating film. To do.

  Next, in FIG. 16B, as in FIG. 13A, the metal film 36 not covered with the electrodes EL4, EL5, and EL6 is removed by wet etching or the like using the electrodes EL4, EL5, and EL6 as a mask. The Then, the electrode layer E2 is formed. Thereafter, the laminated structure including the electrode layer E1, the wiring layers W1 and W2, and the electrode layer E2 is peeled off from the base substrate 30, and the interposer 130 shown in FIG. 4 is completed.

  As described above, also in the embodiment shown in FIGS. 5 to 16, as in the embodiment shown in FIG. 1, the power supply wiring 18 a and the signal wirings 18 b, 18 c, and 18 d having different widths can have the same film thickness. . Further, it is possible to prevent the aspect ratio of the openings OP6, OP7, and OP13 of the photoresist 16 for the signal wirings 18b, 18c, and 18d from increasing as shown in FIG. Therefore, the mask pattern made of the photoresist 16 can be formed with higher accuracy than in the prior art, and the signal wirings 18b, 18c, and 18d can be formed with higher accuracy. Furthermore, since Cu deposited on the openings OP5 and OP12 by electroplating can be prevented from overflowing from the upper surface of the mask layer MSK, a wiring structure having a normal power supply wiring 18a can be formed.

  Furthermore, in the embodiment shown in FIGS. 5 to 16, the NiCu sputtering time can be shortened by forming the NiCu film in the via opening (OP1 in FIG. 6B) of the power supply wiring 18a. NiCu used for sputtering can be saved.

  17 to 22 show another example of a method for manufacturing the interposer 130 shown in FIG. That is, FIG. 17 to FIG. 22 show another embodiment of a wiring formation method and a wiring structure. Detailed descriptions of the same elements and similar steps as those in FIGS. 3 and 5 to 16 are omitted. The structure of the interposer 130 formed by the steps shown in FIGS. 17 to 22 is the same as the structure of the interposer 130 formed in the steps shown in FIGS. 5 to 16 except that the structure of the seed layer SL is different.

  The process of forming the Cu film shown in FIG. 17A is the same as that in FIG. 6C, and the manufacturing process until the structure of FIG. 17A is obtained is shown in FIGS. ). Next, in FIG. 17B, as in FIG. 8A, the opening OP5 from which the metal film 36 is exposed is provided in the power supply wiring region, and the openings OP6 and OP7 from which the metal film 36 is exposed are provided as signal wiring. A mask layer MSK included in the region is formed using the photoresist 16.

  Next, in FIG. 17C, as in FIG. 3C, the metal film 36 exposed in the openings OP5, OP6, OP7 is dry-etched with an inert gas such as Ar (argon). At this time, the metal film 36 formed on the surface of the insulating film 34 in the openings OP6 and OP7 having a relatively high aspect ratio is hardly etched. On the other hand, the metal film 36 formed on the surface of the insulating film 34 in the opening OP5 having a relatively low aspect ratio is etched to reduce the film thickness.

  As described in FIG. 8, the opening OP7 extends in the horizontal direction of FIG. 17C, and the width of the opening OP7 is the width of the via opening exposed to the electrode EL3 in the opening OP6. Same as 2 microns. The width of the opening OP6 on the insulating film 34 is 2.5 microns, and the width of the opening OP5 on the insulating film 34 is 10 microns. For this reason, the aspect ratio of the openings OP6 and OP7 is “1” or more. As described above, the electrical resistance of the seed layer SL exposed in the opening OP5 where the wide power supply wiring is formed is equal to the electrical resistance of the seed layer SL exposed in the openings OP6 and OP7 where the narrow signal wiring is formed. Compared to higher.

  Next, in FIG. 18A, as in FIG. 8B, electroplating is performed using the seed layer SL as an electrode, and a power wiring 18a such as Cu is formed in the opening OP5, while Cu or the like is formed. Signal wirings 18b and 18c are formed in the openings OP6 and OP7, respectively. Here, the electrical resistance of the seed layer SL exposed to the opening OP5 where the electroplating electrolyte is easy to circulate is higher than the electrical resistance exposed to the openings OP6 and OP7 where the electroplating electrolyte is difficult to circulate. Therefore, as described with reference to FIG. 3D, the film thickness (that is, the wiring) of the power supply wiring 18a and the signal wirings 18b and 18c formed in the opening OP5 and the openings OP6 and OP7 having different widths, respectively. Can be made equal to each other.

  Next, after the photoresist 16 is removed, in FIG. 18B, as in FIG. 3F, the metal film 36 (Cu film) not covered with the power supply wiring 18a and the signal wirings 18b and 18c. Are removed by wet etching or the like to form the wiring layer W1. Next, after the openings OP8, OP9, and OP10 are formed using the photosensitive insulating film 34, in FIG. 18C, the metal film 36 (Cu film) is formed as in FIG. It is formed.

  Next, in FIG. 19A, as in FIG. 11B, a mask layer MSK having an opening OP12 for forming a power supply wiring and a plurality of openings OP13 for forming a signal wiring is formed. It is formed. Next, in FIG. 19B, as in FIGS. 3C and 17C, the metal film 36 exposed in the openings OP12 and OP13 is dry-etched, and the insulating film 34 in the opening OP12 is removed. The metal film 36 formed on the surface is etched to reduce the film thickness. The metal film 36 formed on the surface of the insulating film 34 in the opening OP13 is hardly etched.

  Next, in FIG. 20A, as in FIG. 12A, electroplating is performed using the seed layer SL as an electrode, and a power wiring 18a such as Cu is formed in the opening OP12, and Cu or the like is formed. The signal wirings 18b and 18d are formed in the opening OP13. Next, after the photoresist 16 is removed, in FIG. 20B, as in FIGS. 3F and 18B, the metal that is not covered with the power supply wiring 18a and the signal wirings 18b and 18d. The film 36 is removed by wet etching or the like, and the wiring layer W2 is formed.

  Next, in FIG. 21A, after the openings OP14, OP15, OP16 are formed using the photosensitive insulating film 34, the metal film 36 (Cu film) is formed as in FIG. 14B. It is formed. Next, after the mask layer MSK having the photoresist 16 is formed in the region excluding the openings OP14, OP15, and OP16, in FIG. 21B, as in FIG. 40, 42, and 44 are formed in order in each opening OP14-OP16.

  Next, after the photoresist 16 is removed, in FIG. 22A, as in FIG. 16B, the metal film 36 not covered with the electrodes EL4, EL5, EL6 becomes the electrodes EL4, EL5, EL6. Is removed by wet etching or the like using as a mask. Then, the electrode layer E2 is formed. Thereafter, the laminated structure including the electrode layer E1, the wiring layers W1 and W2, and the electrode layer E2 is peeled off from the base substrate 30, and the interposer 130 shown in FIG. 4 is completed.

  As described above, also in the embodiment shown in FIGS. 17 to 22, the film thicknesses of the power supply wiring 18a and the signal wirings 18b, 18c, and 18d having different widths can be made equal to each other as in the embodiment shown in FIG. . Further, it is possible to prevent the aspect ratio of the openings OP6, OP7, and OP13 of the photoresist 16 for the signal wirings 18b, 18c, and 18d from increasing as shown in FIG. Therefore, the mask pattern made of the photoresist 16 can be formed with higher accuracy than in the prior art, and the signal wirings 18b, 18c, and 18d can be formed with higher accuracy. Furthermore, since Cu deposited on the openings OP5 and OP12 by electroplating can be prevented from overflowing from the upper surface of the mask layer MSK, a wiring structure having a normal power supply wiring 18a can be formed. Further, as in the embodiment shown in FIG. 3, the steps of forming, exposing, developing and removing the photoresist 16 for forming the NiCu film can be omitted. For this reason, the number of steps for forming the wiring structure shown in FIG. 22 can be reduced compared to the number of steps shown in FIGS. 5 to 16, and the manufacturing cost of the wiring structure shown in FIG. The manufacturing cost of the wiring structure shown can be reduced.

The invention described in the above embodiments is organized and disclosed as an appendix.
(Appendix 1)
Forming a conductive seed layer on the insulating film;
The electrical resistance of the seed layer in the region where the first wiring having a width larger than a predetermined value is formed is made higher than the electrical resistance of the seed layer in the region where the second wiring having a width smaller than the predetermined value is formed. Process,
Forming a mask layer having a first opening in which the first wiring is formed and a second opening in which the second wiring is formed on the seed layer;
Performing electroplating using the seed layer as an electrode, forming the first wiring in the first opening and forming the second wiring in the second opening;
Removing the mask layer after forming the first wiring and the second wiring;
And a step of removing a seed layer not covered with the first wiring and the second wiring after removing the mask layer.
(Appendix 2)
The seed layer formed on the insulating film includes a first metal;
In the step of increasing the electric resistance of the seed layer, before forming the mask layer, a second metal film having an electric resistance higher than that of the first metal is formed in a region where the first wiring is formed. By forming the first metal film on the formed first metal film, the electric resistance of the seed layer in the region where the first wiring is formed is set to the electric resistance of the seed layer in the region where the second wiring is formed. The method for forming a wiring according to appendix 1, wherein the wiring height is higher.
(Appendix 3)
Forming a third opening in the insulating film for connecting the first wiring to a third wiring formed under the insulating film before forming the seed layer on the insulating film; Have
The first opening is formed at a position including the third opening,
The wiring forming method according to claim 2, wherein the first metal film and the second metal film are formed in the first opening and the third opening.
(Appendix 4)
In the step of increasing the electrical resistance of the seed layer, the thickness of the seed layer exposed in the first opening is made smaller than the thickness of the seed layer exposed in the second opening by an etching process. The method of forming a wiring according to claim 1, wherein the electrical resistance of the seed layer in the region where the first wiring is formed is higher than the electrical resistance of the seed layer in the region where the second wiring is formed. .
(Appendix 5)
5. The wiring according to claim 4, wherein in the etching process, dry etching using an inert gas is performed in a state where the seed layer is exposed in the first opening and the second opening. Forming method.
(Appendix 6)
The first wiring is a power supply wiring to which a power supply voltage or a ground voltage is supplied,
6. The method of forming a wiring according to claim 1, wherein the second wiring is a signal wiring through which a signal is transmitted.
(Appendix 7)
A wiring structure in which a first wiring having a width larger than a predetermined value and a second wiring having a width equal to or smaller than the predetermined value are formed on an insulating film,
A first metal film in contact with the insulating film side of the first wiring;
A wiring structure comprising: a second metal film in contact with the insulating film side of the second wiring and having an electric resistance lower than that of the first metal film.
(Appendix 8)
The first metal film includes a film containing a first metal and a film containing a second metal having a higher electric resistance than the first metal,
The wiring structure according to appendix 7, wherein the second metal film contains the first metal.
(Appendix 9)
The first metal film and the second metal film contain the same metal as each other,
The first metal film has a first thickness;
The wiring structure according to appendix 7, wherein the second metal film is thicker than the first thickness.

  From the above detailed description, features and advantages of the embodiments will become apparent. This is intended to cover the features and advantages of the embodiments described above without departing from the spirit and scope of the claims. Also, any improvement and modification should be readily conceivable by those having ordinary knowledge in the art. Therefore, there is no intention to limit the scope of the inventive embodiments to those described above, and appropriate modifications and equivalents included in the scope disclosed in the embodiments can be used.

  DESCRIPTION OF SYMBOLS 10 ... Insulating film; 12, 14 ... Metal film; 16 ... Photoresist; 18a ... Power supply wiring; 18b, 18c, 18d ... Signal wiring; 20 ... Insulating film; 30 ... Base substrate; 36, 38, 40, 42, 44 ... metal film; 100 ... electronic device; 110a, 110b ... LSI chip; 120 ... printed circuit board; 130 ... interposer; BP1a, BP1b ... bump; E1, E2 ... electrode layer; EL2, EL3, EL4, EL5, EL6 ... electrode; MSK ... mask layer; OPa, OPb ... opening; OP1, OP2, OP3, OP4, OP5, OP6, OP7, OP8, OP9, OP10, OP11, OP12, OP13, OP14, OP15, OP16 ... opening; SL ... seed layer; TM ... terminal; W1, W2 ... wiring layer

Claims (8)

Forming a conductive seed layer on the insulating film;
The electrical resistance of the seed layer in the region where the first wiring having a width larger than a predetermined value is formed is made higher than the electrical resistance of the seed layer in the region where the second wiring having a width smaller than the predetermined value is formed. Process,
Forming a mask layer having a first opening in which the first wiring is formed and a second opening in which the second wiring is formed on the seed layer;
Performing electroplating using the seed layer as an electrode, forming the first wiring in the first opening and forming the second wiring in the second opening;
Removing the mask layer after forming the first wiring and the second wiring;
And a step of removing a seed layer not covered with the first wiring and the second wiring after removing the mask layer. The seed layer formed on the insulating film includes a first metal;
In the step of increasing the electric resistance of the seed layer, before forming the mask layer, a second metal film having an electric resistance higher than that of the first metal is formed in a region where the first wiring is formed. By forming the first metal film on the formed first metal film, the electric resistance of the seed layer in the region where the first wiring is formed is set to the electric resistance of the seed layer in the region where the second wiring is formed. 2. The method of forming a wiring according to claim 1, wherein the height is higher. Forming a third opening in the insulating film for connecting the first wiring to a third wiring formed under the insulating film before forming the seed layer on the insulating film; Have
The first opening is formed at a position including the third opening,
3. The method of forming a wiring according to claim 2, wherein the first metal film and the second metal film are formed in the first opening and the third opening.   In the step of increasing the electrical resistance of the seed layer, the thickness of the seed layer exposed in the first opening is made smaller than the thickness of the seed layer exposed in the second opening by an etching process. 2. The formation of a wiring according to claim 1, wherein the electrical resistance of the seed layer in the region where the first wiring is formed is higher than the electrical resistance of the seed layer in the region where the second wiring is formed. Method.   5. The wiring according to claim 4, wherein, in the etching process, dry etching using an inert gas is performed in a state where the seed layer is exposed in the first opening and the second opening. Forming method. A wiring structure in which a first wiring having a width larger than a predetermined value and a second wiring having a width equal to or smaller than the predetermined value are formed on an insulating film,
A first metal film in contact with the insulating film side of the first wiring;
A wiring structure comprising: a second metal film in contact with the insulating film side of the second wiring and having an electric resistance lower than that of the first metal film. The first metal film includes a film containing a first metal and a film containing a second metal having a higher electric resistance than the first metal,
The wiring structure according to claim 6, wherein the second metal film contains the first metal. The first metal film and the second metal film contain the same metal as each other,
The first metal film has a first thickness;
The wiring structure according to claim 6, wherein the second metal film is thicker than the first thickness.

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