JP2017022889A - Power circuit and control method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power circuit and a control method therefor, having excellent controllability according to a load.SOLUTION: The power circuit turns on a switching transistor connected between an input terminal to which an input voltage is applied and an output node, to supply a current through an inductor to a capacitor connected to the output node, so as to obtain an output voltage from an output terminal connected to the capacitor. The power circuit includes at least either of a detection circuit which outputs an output signal according to the state of a current which flows through the inductor, and a comparison circuit which outputs an output signal depending on whether the voltage of the output terminal is higher or lower than a predetermined reference voltage. The power circuit further includes a control circuit which controls the ON time of the switching transistor, according to the output signal of either the detection circuit or the comparison circuit at predetermined timing.SELECTED DRAWING: Figure 1

Description

  The present embodiment relates to a power supply circuit and a control method thereof.

  The power supply circuit is desirably configured to supply an output voltage corresponding to the characteristics of the load. Conventionally, a technique of a single inductor multiple output (SIMO) type power supply circuit capable of obtaining a plurality of outputs via one inductor has been disclosed. In the SIMO type power supply circuit, independent output voltages are supplied to a plurality of loads. A power supply circuit excellent in controllability according to the state of a load to which an output voltage is supplied and a control method thereof are desired.

JP 2014-93863 A

  An object of one embodiment is to provide a power supply circuit excellent in controllability according to the state of a load to which an output voltage is supplied, and a control method therefor.

  According to one embodiment, the power supply circuit turns on the switching transistor connected between the input terminal to which the input voltage is applied and the output node, and supplies a current to the capacitor connected to the output node via the inductor. And an output voltage is obtained from an output terminal connected to the capacitor. A power supply circuit is a detection circuit that outputs an output signal corresponding to a state of a current flowing through the inductor, or a comparison circuit that outputs an output signal according to whether the voltage at the output terminal is higher or lower than a predetermined reference voltage. At least one is provided. A control circuit that controls an on-time of the switching transistor in accordance with an output signal of the detection circuit or the comparison circuit at a predetermined timing;

FIG. 1 is a diagram illustrating a configuration of a power supply circuit according to the first embodiment. FIG. 2 is a diagram for explaining the basic operation of the power supply circuit. FIG. 3 is a diagram for explaining a control method of the power supply circuit according to the second embodiment. FIG. 4 is a diagram illustrating the configuration of the power supply circuit according to the third embodiment. FIG. 5 is a diagram for explaining a control method of the power supply circuit according to the fourth embodiment. FIG. 6 is a diagram illustrating a configuration of a power supply circuit according to the fifth embodiment. FIG. 7 is a diagram for explaining a control method of the power supply circuit according to the sixth embodiment. FIG. 8 is a diagram illustrating a configuration of a power supply circuit according to the seventh embodiment. FIG. 9 is a diagram for explaining a control method of the power supply circuit according to the eighth embodiment. FIG. 10 is a diagram illustrating the configuration of the power supply circuit according to the ninth embodiment. FIG. 11 is a diagram for explaining a control method of the power supply circuit according to the tenth embodiment. FIG. 12 is a diagram illustrating the configuration of the power supply circuit according to the eleventh embodiment. FIG. 13 is a diagram for explaining a control method of the power supply circuit according to the twelfth embodiment. FIG. 14 is a diagram illustrating the configuration of the power supply circuit according to the thirteenth embodiment. FIG. 15 is a diagram for explaining a method of controlling the power supply circuit according to the fourteenth embodiment. FIG. 16 is a diagram illustrating the configuration of the power supply circuit according to the fifteenth embodiment. FIG. 17 is a diagram for explaining a control method of the power supply circuit according to the sixteenth embodiment. FIG. 18 is a diagram illustrating a configuration of a power supply circuit according to the seventeenth embodiment. FIG. 19 is a diagram for explaining the control method of the power supply circuit according to the eighteenth embodiment. FIG. 20 is a diagram illustrating the configuration of the power supply circuit according to the nineteenth embodiment. FIG. 21 is a diagram for explaining the control method of the power supply circuit according to the twentieth embodiment. FIG. 22 is a diagram for explaining the control method of the power supply circuit according to the twenty-first embodiment. FIG. 23 is a diagram illustrating the configuration of the power supply circuit according to the twenty-second embodiment. FIG. 24 is a diagram for explaining the control method of the power supply circuit according to the twenty-third embodiment. FIG. 25 is a diagram illustrating a configuration of a power supply circuit according to the twenty-fourth embodiment. FIG. 26 is a diagram for explaining a control method of the power supply circuit according to the twenty-fifth embodiment. FIG. 27 is a diagram for explaining a control method of the power supply circuit according to the twenty-sixth embodiment. FIG. 28 is a diagram illustrating a configuration of a power supply circuit according to a twenty-seventh embodiment. FIG. 29 is a diagram for explaining the control method of the power circuit according to the twenty-eighth embodiment. FIG. 30 is a diagram for explaining the control method of the power supply circuit according to the twenty-ninth embodiment. FIG. 31 is a diagram for explaining the control method of the power supply circuit according to the thirtieth embodiment. FIG. 32 is a diagram for explaining the control method of the power circuit according to the thirty-first embodiment. FIG. 33 is a diagram for explaining the control method of the power supply circuit according to the thirty-second embodiment. FIG. 34 is a diagram for explaining the control method of the power circuit according to the thirty-third embodiment. FIG. 35 is a diagram for explaining the control method of the power circuit according to the thirty-fourth embodiment. FIG. 36 is a diagram showing the configuration of the power supply circuit of the 35th embodiment. FIG. 37 is a diagram showing the configuration of the power supply circuit according to the thirty-sixth embodiment. FIG. 38 is a diagram for explaining the control method of the power supply circuit according to the thirty-seventh embodiment. FIG. 39 is a diagram for explaining the control method of the power circuit according to the thirty-eighth embodiment. FIG. 40 is a diagram for explaining the control method of the power supply circuit according to the thirty-ninth embodiment. FIG. 41 is a diagram for explaining the control method for the power supply circuit according to the fortieth embodiment. FIG. 42 is a diagram for explaining the control method for the power supply circuit according to the forty-first embodiment. FIG. 43 is a diagram for explaining the control method of the power supply circuit according to the forty-second embodiment. FIG. 44 is a diagram showing the configuration of the power supply circuit of the forty-third embodiment. FIG. 45 is a diagram for explaining the control method of the power supply circuit according to the forty-fourth embodiment.

  Exemplary embodiments of a power supply circuit and its control method will be explained below in detail with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments.

(First embodiment)
FIG. 1 is a diagram illustrating a configuration of a power supply circuit according to the first embodiment. The power supply circuit of this embodiment includes an input terminal 10 to which an input voltage Vin is applied. The source of the PMOS switching transistor 12 on the high side is connected to the input terminal 10, and the drain is connected to the output node 13. The drain of the NMOS switching transistor 14 on the low side is connected to the output node 13, and the ground potential is supplied to the source.

  One end of an inductor 16 is connected to the output node 13. The other end of the inductor 16 is connected to the output terminal 20. The output terminal 20 supplies the output voltage Vout to a load (not shown). One end of the capacitor 18 is connected to the output terminal 20, and the other end is supplied with a ground potential.

  The output terminal 20 is supplied to the feedback comparator 24 and compared with the reference voltage Vref. The feedback comparator 24 is supplied with a clock signal CLK. The feedback comparator 24 performs a comparison operation of the output voltage Vout and the reference voltage Vref discretely in synchronization with the clock signal CLK, outputs the output signal FBCMP_out, and supplies it to the on-time control circuit 40. For example, when the feedback comparator 24 performs a discrete operation in which the clock signal CLK is in a high level period, power consumption associated with the operation of the feedback comparator 24 is reduced.

  When the output voltage Vout is lower than the reference voltage Vref, the output signal FBCMP_out of the feedback comparator 24 is at a high level, and when the reference voltage Vref is lower than the output voltage Vout, the output signal FBCMP_out is at a low level. That is, when the output voltage Vout is higher than the reference voltage Vref, the output signal FBCMP_out becomes a low level, and a state in which the output signal FBCMP_out is not output, so-called pulse skip occurs.

The output node 13 is connected to one input terminal of the comparison circuit 22. A ground potential is supplied to the other input terminal of the comparison circuit 22. Depending on the state of the inductor current, a current discontinuous state (DCM: Discontinuous Conduction Mode) (hereinafter referred to as a DCM state) and other states, that is, a continuous current state (CCM: Continuous Conduit Mode) (hereinafter, referred to as a DCM). CCM state). The voltage V _{LX at the} output node 13 changes according to the direction in which the inductor current flows. Therefore, by comparing the voltage V _LX of the output node 13 with the ground potential by the comparison circuit 22, the output signal ZCC_out corresponding to the direction in which the inductor current Iind flowing in the inductor 16 flows can be obtained.

  The power supply circuit of this embodiment includes an on-time control circuit 40 that adjusts the on-time of the PMOS switching transistor 12. The on-time control circuit 40 includes a DCM / CCM detection circuit 42 that detects the output signal ZCC_out from the comparison circuit 22. When the output signal ZCC_out is at a high level, that is, in the DCM state, a control signal for increasing the on-time of the PMOS switching transistor 12 is supplied to the drive circuit 30. In the first control mode, that is, the mode in which the on-time is controlled according to the inductor current Iind, the on-time is controlled according to the output signal of the DCM / CCM detection circuit 42.

  The on-time control circuit 40 includes a pulse skip detection circuit 41 that receives the output signal FBCMP_out from the feedback comparator 24 and detects the presence or absence of pulse skip. When the pulse skip detection circuit 41 detects the pulse skip, the pulse skip detection circuit 41 supplies a control signal for reducing the ON time of the PMOS switching transistor 12 to the drive circuit 30. In the second control mode, that is, a mode in which the on-time is controlled according to the comparison result between the output voltage Vout synchronized with the clock signal CLK and the reference voltage Vref, the on-time is determined according to the output signal of the pulse skip detection circuit 41. Be controlled.

  The drive circuit 30 has a pulse generation circuit 32. The pulse generation circuit 32 generates a pulse signal having a predetermined time width in response to the signal from the on-time control circuit 40. The pulse width of the pulse signal generated by the pulse generation circuit 32 is controlled by a signal from the on-time control circuit 40. For example, the time width of the high level of the pulse signal can be adjusted by adjusting the rising and falling timings of the pulse signal. By synchronizing the rising edge of the pulse signal with the clock signal CLK and adjusting the falling timing with the signal from the on-time control circuit 40, the time width of the high level of the pulse signal can be adjusted.

  For example, it can be configured to generate a pulse signal that falls after a predetermined delay time from the rise of the pulse signal. The delay circuit (not shown) for generating the delay time is configured by an inverter having a predetermined number of stages, and the time width of the high level of the pulse signal can be adjusted by adjusting the number of inverter stages. By increasing the number of stages of delay circuits (not shown) to increase the delay time, the time width of the high level of the pulse signal can be increased and the on-time of the high-side PMOS switching transistor 12 can be increased. Conversely, the on-time of the PMOS switching transistor 12 can be reduced by reducing the number of inverter stages and shortening the delay time. The on-time of the PMOS switching transistor 12 can be adjusted by adjusting the time width of the high level of the pulse signal. A series of controls for adjusting the ON time of the PMOS switching transistor 12 by adjusting the time width of the high level of the pulse signal generated by the pulse generation circuit 32 is hereinafter referred to as ON time control.

  The output of the pulse generation circuit 32 is supplied to the drive circuit 34. The drive circuit 34 has buffers (36, 38). The drive signal from the buffer 36 is supplied to the gate of the PMOS switching transistor 12, and the drive signal from the buffer circuit 38 is supplied to the gate of the NMOS switching transistor 14. On / off of the PMOS switching transistor 12 and the NMOS switching transistor 14 is controlled by drive signals from the buffer 36 and the buffer 38. For example, in order to avoid a situation in which the PMOS switching transistor 12 and the NMOS switching transistor 14 are simultaneously turned on and a through current is generated between the input terminal 10 and the ground potential, a predetermined dead time is generated in the pulse generation circuit 32.

The output signal ZCC_out of the comparison circuit 22 is supplied to the buffer 38. The buffer 38 is controlled in response to the output signal ZCC_out of the comparison circuit 22 that is output at the timing when the voltage V _LX of the output node 13 becomes lower than the ground potential, and the NMOS switching transistor 14 is turned off, so that the inductor current Iind becomes the ground potential. A so-called reverse flow state of the inductor current Iind flowing to the side can be avoided, and a decrease in conversion efficiency can be avoided.

  In the present embodiment, the on-time control circuit 40 is supplied with a mode switching signal mode for switching the control mode. A first control mode for controlling the on-time of the high-side PMOS switching transistor 12 by adjusting the high level time width of the pulse signal according to the output signal of the DCM / CCM detection circuit 42 by the mode switching signal mode. Then, the high-level time width of the pulse signal is adjusted in accordance with the output signal of the pulse skip detection circuit 41 to switch to the second control mode in which the on-time of the PMOS switching transistor 12 is adjusted.

  Next, a method for controlling the power supply circuit according to the first embodiment will be described with reference to FIG. FIG. 2A is a diagram for explaining the first control mode. In the first control mode, a pulse signal (not shown) output from the pulse generation circuit 32 rises at the rising timing t0 of the clock signal CLK. The pulse generation circuit 32 generates a pulse signal (not shown) that turns on the NMOS switching transistor 14 after a predetermined dead time, and supplies the pulse signal to the NMOS switching transistor 14 via the buffer 38.

  In the first control mode, the inductor current Iind is applied to the inductor 16 over the period from the rising timing t0 of the clock signal CLK to the rising timing t1 of the next clock signal CLK, that is, over one cycle of the clock signal CLK. And the capacitor 18 connected to the output terminal 20 is charged. That is, control is performed to charge the capacitor 18 and increase the output voltage Vout by making maximum use of one cycle of the clock signal CLK from timing t0 to timing t1. Since the inductor current Iind flows during the period from the timing t0 to the timing t1, the charge accumulated in the capacitor 18 connected to the output terminal 20 is increased by the inductor current Iind, and the output voltage Vout is increased to the maximum. Thereby, the frequency | count that the output voltage Vout becomes lower than the reference voltage Vref can be reduced. Therefore, it is possible to reduce the switching frequency of the switching transistors (12, 14) for charging the capacitor 18, and it is possible to reduce the loss of power consumption accompanying the switching operation of the switching transistors (12, 14). Hereinafter, this first control mode is also referred to as a maximum Ton control mode.

  FIG. 2B is a diagram for explaining the second control mode. In the second control mode, a pulse signal (not shown) generated by the pulse generation circuit 32 rises at the rising timing t10 of the clock signal CLK, and thereafter, the clock signal CLK that is continuously supplied becomes the timing (t11 to t11). The switching operation of the switching transistors (12, 14) is performed every time when rising at t13), and the inductor current Iind is supplied to the capacitor 18. That is, this is a control mode in which the switching operation of the switching transistors (12, 14) is performed in response to the rise of each clock signal CLK. In such a control mode, the capacitor 18 is charged while the maximum value of the inductor current Iind is suppressed in order to charge the capacitor 18 by switching the switching transistors 12 and 14 each time the clock signal CLK is received. The output voltage Vout can be maintained at a desired voltage. Hereinafter, this control mode is also referred to as a minimum Ton control mode. In addition, since the switching frequency of the switching transistors (12, 14) is controlled to match the frequency of the clock signal CLK, the switching frequency of the switching transistors (12, 14) can be easily controlled.

(Second Embodiment)
FIG. 3 is a diagram for explaining a control method for switching between the maximum Ton control mode that is the first control mode and the minimum Ton control mode that is the second control mode. It is determined whether it is necessary to increase the switching frequency of the switching transistors (12, 14) (S301). When increasing the switching frequency, the mode is switched to the minimum Ton control mode (S302). In the minimum Ton control mode, for example, the switching operation of the switching transistors (12, 14) is performed every time the clock signal CLK rises, the inductor current Iind is supplied to the capacitor 18, and the output voltage Vout increases. That is, since the switching frequency is controlled to coincide with the frequency of the clock signal CLK, it can be used to increase the switching frequency.

  If there is no need to increase the switching frequency, the mode is switched to the maximum Ton control mode (S303). In the maximum Ton control mode, since the inductor voltage Iind having a high peak value can be supplied to the capacitor 18 to increase the output voltage Vout, the state where the output voltage Vout is higher than the reference voltage Vref can be maintained for a long time. It becomes. As a result, the pulse skip that occurs when the output voltage Vout is higher than the reference voltage Vref can be increased, so that the switching frequency can be suppressed.

  By adopting a configuration of a power supply circuit having a minimum Ton control mode and a maximum Ton control mode, the switching frequency can be easily controlled in accordance with the load characteristics or specifications. For example, when the output voltage Vout is supplied to a load (not shown) having a function of receiving an RF signal, the switching transistor (12 14) The noise interference between the noise generated by the switching operation and the output signal of the load can be avoided. When adjusting the switching frequency, if the switching frequency is increased to avoid noise interference, control is performed in the minimum Ton control mode, and if the switching frequency is suppressed to avoid noise interference, control in the maximum Ton control mode is performed. I can do it.

(Third embodiment)
FIG. 4 is a diagram illustrating the configuration of the power supply circuit according to the third embodiment. Constituent elements corresponding to the above-described embodiment are denoted by the same reference numerals. This embodiment shows one embodiment in the case of the first control mode, that is, the maximum Ton control mode. Since the first control mode is selected, the mode switching signal mode supplied to the on-time control circuit 40 is omitted. It should be noted that a configuration having only the first control mode is also possible. In this case, the mode switching signal mode becomes unnecessary.

The output signal ZCC_out of the comparison circuit 22 that compares the voltage V _LX of the output node 13 connected to the drain of the PMOS switching transistor 12 and the drain of the NMOS switching transistor 14 with the ground potential is the DCM / CCM detection circuit 42 of the on-time control circuit 40. To be supplied.

  The pulse generation circuit 32 generates a pulse signal in response to the signal supplied from the on-time control circuit 40. The DCM / CCM detection circuit 42 detects the output signal ZCC_out of the comparison circuit 22 in response to the clock signal CLK. When the operation state is the CCM state, a control signal that shortens the high-level time width of the pulse signal generated by the pulse generation circuit 32 and reduces the on-time of the PMOS switching transistor 12 is supplied to the pulse generation circuit 32. When the operation state is the DCM operation, the control signal for increasing the ON time by increasing the time width of the high level of the pulse signal is supplied to the pulse generation circuit 32.

(Fourth embodiment)
FIG. 5 shows one example of the control method of the power supply circuit of the third embodiment described above. The output signal ZCC_out of the comparison circuit 22 is detected at timing t51 when the clock signal CLK rises. FIG. 5A shows a case where the operating state is the CCM state and the inductor current Iind flows to the output voltage side. In the CCM state as indicated by the dotted circle (i), that is, when the inductor current Iind flows to the inductor 16 side at the timing t51, the voltage V _LX of the output node 13 becomes lower than the ground potential. In this case, since the output signal ZCC_out of the comparison circuit 22 is at the low level, it is possible to detect the CCM state or the DCM state by detecting the output signal ZCC_out of the comparison circuit 22. In the CCM state, control is performed to reduce the on-time.

  FIG. 5B shows control when the operating state of the power supply circuit is in the DCM state. In the DCM state as indicated by the dotted circle (ii), the output signal ZCC_out of the comparison circuit 22 becomes High level at the rising timing t52 of the clock signal CLK in a state where the inductor current Iind does not flow. It is possible to detect the CCM state or the DCM state by detecting the output signal ZCC_out. In the DCM state, control is performed to increase the on-time. As a result, the control for increasing the output voltage Vout by supplying the inductor current Iind to the capacitor 18 by utilizing the period of one cycle of the clock signal CLK to the maximum, that is, the control in the maximum Ton control mode is maintained.

  In the control method of the power supply circuit according to the present embodiment, the pulse signal generated by the pulse generation circuit 32 depending on whether the state at the end timing (t51, t52) of the clock signal CLK is the DCM state or the CCM state. The on-time of the switching transistor is adjusted by adjusting the time width of the high level. Thereby, it is possible to maintain the control in which the inductor current Iind is supplied to the capacitor 18 and the output voltage Vout is raised by utilizing the period of one cycle of the clock signal CLK, that is, the control in the maximum Ton control mode.

(Fifth embodiment)
FIG. 6 shows the configuration of the power supply circuit of the fifth embodiment. Constituent elements corresponding to the above-described embodiment are denoted by the same reference numerals. In the present embodiment, a plurality of output terminals (20-1 to 20-n) connected to the common inductor 16 in a time division manner are provided. Each output terminal (20-1 to 20-n) is connected to one end 200 of the inductor 16 via a switch (19-1 to 19-n), respectively. Capacitors (18-1 to 18-n) are connected to the output terminals (20-1 to 20-n). In each switch (19-1 to 19-n), on / off of each switch (19-1 to 19-n) is controlled, and each output terminal (20-1 to 20-n) is connected to the inductor 16. Slot assignment signals (φ1 to φn) for assigning the time to be transmitted are supplied from the on-time control circuit 40.

  Feedback comparators (24-1 to 24-n) are connected to the output terminals (20-1 to 20-n). Each feedback comparator (24-1 to 24-n) compares each output voltage (Vout1 to Voutn) with a predetermined reference voltage (Vref1 to Vrefn) in synchronization with the clock signal CLK, and outputs an output signal (FBCMP_out1 to FBCMP_outn). Is supplied to the on-time control circuit 40. The predetermined reference voltages (Vref1 to Vrefn) may be the same voltage or different depending on a load (not shown) connected to each output terminal (20-1 to 20-n). May be.

  By connecting the inductor 16 to each output terminal (20-1 to 20-n) by switches (19-1 to 19-n) in a time-sharing manner, the inductor 16 is independent from each output terminal (20-1 to 20-n). Output voltages (Vout1 to Voutn) can be obtained.

(Sixth embodiment)
One embodiment of the control method for the power supply circuit according to the fifth embodiment described above will be described with reference to FIG. For convenience of explanation, an example of controlling output voltages (Vout1, Vout2) from the output terminal 20-1 and the output terminal 20-2 will be described. The path reaching the load (not shown) via the output terminal 20-1 is channel 1, and the path reaching the load (not shown) via the output terminal 20-2 is channel 2. In addition, a period in which each output terminal (20-1, 20-2) is assigned to the inductor 16 in a time division manner and the corresponding capacitor (18-1, 18-2) is charged is also called a slot. The switches (19-1, 19-2) are sequentially turned on by the slot assignment signals (φ1, φ2), and the capacitors (18-1, 18-2) are charged with the inductor current Iind.

In the present embodiment, the channel is switched by switching the slot allocation signal φ1 and the slot allocation signal φ2. That is, at time t71 when the clock signal CLK rises, the slot assignment signal φ2 rises and is applied to the switch 19-2, whereby the channel connected to the inductor 16 is switched to the channel 2 of the output terminal 20-2. In this embodiment, it is detected whether the operation state at the timing t71 when the channel is switched is the CCM state or the DCM state. The CCM state or the DCM state can be determined by detecting the voltage V _LX of the output node 13 as described in the above-described embodiment.

  As shown in FIG. 6A, for example, when the state at timing t71 is the CCM state as indicated by a dotted circle (iii), the output signal ZCC_out of the comparison circuit 22 is at the low level. In this case, control is performed to shorten the high-level time width of the pulse signal and shorten the ON time of the high-side PMOS switching transistor 12. By this control, the peak value of the inductor current Iind becomes small, and the timing at which the inductor current Iind becomes zero becomes early, so that it is possible to shift to the DCM state.

  When the channel is switched in the CCM state, the energy remaining in the inductor 16 is released to the load connected to another channel in the next switching cycle, and the output voltage rises unintentionally. That is, cross regulation occurs. For this reason, in order to avoid cross regulation, it is necessary to make the inductor current Iind flowing through the inductor 16 zero before the channel is switched by the slot assignment signals (φ1, φ2).

  Therefore, when the operation state at the timing t71 is the CCM state, the high-level time width of the pulse signal generated by the pulse generation circuit 32 when the next slot assignment signal φ1 is supplied is shortened, and the PMOS switching transistor 12 Control to shorten the on-time of. Thus, the operation state of channel 1 when the next slot assignment signal φ1 is applied can be shifted to the DCM state. The fact that the operation state at the timing t71 is the CCM state is stored in a storage circuit (not shown) provided in the on-time control circuit 40, and the slot assignment signal φ1 is next applied to the channel 1 Used when adjusting the on-time.

  FIG. 5B shows a case where the operation state at the timing t72 at the time of channel switching is the DCM state. As indicated by the dotted circle (iv), when the state at the timing t72 is the DCM state, the output signal ZCC_out of the comparison circuit 22 is at the high level. In this case, when the next slot assignment signal φ1 is supplied to the channel 1, control is performed to increase the ON time by increasing the high level time width of the pulse signal generated by the pulse generation circuit 32. By increasing the on-time, the slot period can be utilized to the maximum extent to charge the capacitor 18 with the inductor current Iind, thereby increasing the output voltage Vout.

  According to the present embodiment, when the operation state at the time of channel switching is the CCM state, control is performed to reduce the on-time at the next slot assignment and shift to the DCM state. Thereby, cross regulation can be avoided. When the operation state at the time of channel switching is the DCM state, control is performed to increase the on-time when a slot is assigned to the channel next time. By increasing the ON time, the slot period can be utilized to the maximum extent, and the capacitor 18 can be charged by the inductor current Iind to increase the output voltage Vout.

(Seventh embodiment)
FIG. 8 is a diagram illustrating a configuration of a power supply circuit according to the seventh embodiment. Constituent elements corresponding to the above-described embodiment are denoted by the same reference numerals. In the present embodiment, the high-speed clock signal high-speed CLK having a high frequency is supplied to the on-time control circuit 40. For example, by detecting the output signal ZCC_out of the comparison circuit 22 at the rising timing of the high-speed clock signal high-speed CLK, it can be determined whether the DCM state or the CCM state with a predetermined margin. In the CCM state, there is a problem of cross regulation. For this reason, it is possible to more reliably avoid the cross regulation by giving a margin to the determination of the DCM state or the CCM state, and performing the control to reduce the on-time when it is determined to be the CCM state.

(Eighth embodiment)
FIG. 9 is a diagram for explaining one embodiment of the control method of the power supply circuit according to the seventh embodiment described above. In the control method of this embodiment, the high-speed clock signal high-speed CLK having a higher frequency than the clock signal CLK is supplied to the on-time control circuit 40. The output signal ZCC_out is detected at each rising timing of the high-speed clock signal high-speed CLK. The state of the output signal ZCC_out detected at the rising timing of the high-speed clock signal high-speed CLK is latched in, for example, a latch circuit (not shown) and the channel is switched by the slot assignment signal φ2, that is, the timing t91 of the clock signal CLK. To detect the latched signal. If the high-level output signal ZCC_out of the comparison circuit 22 is detected at the timing t92 of the high-speed clock signal high-speed CLK, it is determined that the current state is the DCM state. In the DCM state, control is performed to increase the on-time. When the output signal ZCC_out of the comparison circuit 22 is not detected at the timing t92 of the high-speed clock signal high-speed CLK, it is determined that the CCM state is set, and control is performed to reduce the ON time.

  In the present embodiment, the timing of detecting whether the state is the DCM state or the CCM state is advanced not to the timing t91 at the time of channel switching but to the rising timing t92 of the high-speed clock signal high-speed CLK, and the CCM state is provided with a margin. Or the DCM state. When the CCM state is determined, the control to shift to the DCM state with the margin can be performed by performing the control to reduce the on-time.

  When the direction of the inductor current Iind changes to the DCM state, the comparison circuit 22 outputs a high level output signal ZCC_out. In the present embodiment, even if the channel is in the DCM state at the channel switching timing t91, the high-level clock signal high-speed CLK is detected by the detection operation using the high-speed clock signal until the channel switching timing t91. When the output signal ZCC_out cannot be detected, it is determined that the output signal ZCC_out is in the CCM state, and control is performed to reduce the ON time. By controlling the ON time with a margin with respect to the timing t91 at the time of channel switching, it is possible to more reliably avoid the occurrence of cross regulation that causes channel switching in the CCM state.

(Ninth embodiment)
FIG. 10 is a diagram illustrating the configuration of the power supply circuit according to the ninth embodiment. Constituent elements corresponding to the above-described embodiment are denoted by the same reference numerals. In the present embodiment, the feedback comparators (24-1 to 24-n) that compare the output voltages (Vout1 to Voutn) and the reference voltages (Vref1 to Vrefn) have a delayed clock signal CLK obtained by delaying the clock signal CLK. -Dly is supplied. That is, the feedback comparators (24-1 to 24-n) perform a comparison operation in synchronization with the delayed clock signal CLK-dly. The on-time control circuit 40 is supplied with a clock signal CLK and a delayed clock signal CLK_dly.

(Tenth embodiment)
FIG. 11 is a diagram for explaining one embodiment of the control method of the power supply circuit according to the ninth embodiment already described. A delayed clock signal CLK_dly delayed by a predetermined time with respect to the clock signal CLK is used. Slot assignment signals (φ1, φ2) are generated from the delayed clock signal CLK_dly and supplied to the switches (19-1 to 19-n). The output signal ZCC_out of the comparison circuit 22 that compares the voltage V _LX of the output node 13 with the reference potential is detected at the rising timing of the clock signal CLK.

  Slot assignment to each channel is controlled by slot assignment signals (φ1, φ2) generated from the delayed clock signal CLK_dly. In the detection using the rising timing t111 of the clock signal CLK, if the high level output signal ZCC_out is not detected at the timing t112 when the channel is switched, it is determined as the CCM state, and the on-time is controlled to be reduced. . By latching the signal detected at timing t111 of the clock signal CLK and detecting the signal at timing t112, the comparison circuit 22 outputs the high-level output signal ZCC_out and the timing t112 at the time of channel switching. It is possible to detect the CCM state or the DCM state with a margin between them. Cross regulation can be more reliably avoided by giving a margin to the determination of the DCM state or the CCM state and performing control to reduce the on-time when it is determined that the state is the CCM state.

(Eleventh embodiment)
FIG. 12 is a diagram illustrating the configuration of the power supply circuit according to the eleventh embodiment. Constituent elements corresponding to the above-described embodiment are denoted by the same reference numerals. In the present embodiment, the clock signal CLK is supplied to the feedback comparators (24-1 to 24-n) that compare the output voltages (Vout1 to Voutn) and the reference voltages (Vref1 to Vrefn). That is, the feedback comparators (24-1 to 24-n) perform a comparison operation in synchronization with the clock signal CLK. The on-time control circuit 40 is supplied with a delayed clock signal CLK_dly obtained by delaying the clock signal CLK. The output signal ZCC_out of the comparison circuit 22 that compares the voltage V _LX of the output node 13 with the reference potential is detected at the timing of the delayed clock signal CLK_dly.

(Twelfth embodiment)
FIG. 13 is a diagram for explaining one embodiment of the power supply circuit control method according to the eleventh embodiment already described. A delayed clock signal CLK_dly delayed by a predetermined time with respect to the clock signal CLK is generated. Slot assignment signals (φ1, φ2) are generated from the clock signal CLK and supplied to the switches (19-1 to 19-n). The output signal ZCC_out of the comparison circuit 22 that compares the voltage V _LX of the output node 13 with the reference potential is detected at the rising timing of the delayed clock signal CLK_dly.

  Slot assignment to each channel, that is, channel switching is performed at the timing of the slot assignment signals (φ1, φ2) generated from the clock signal CLK, that is, the rising timing t131 of the clock signal CLK.

  In the present embodiment, the output signal ZCC_out of the comparison circuit 22 is detected at the rising timing t132 of the delayed clock signal CLK_dly. That is, with respect to the rising timing t131 of the clock signal CLK that is the channel switching timing, it is determined whether the DCM state or the CCM state has a margin between the timing t132 and the timing t131. In the detection using the rising edge timing t132 of the delayed clock signal CLK_dly, if the high level output signal ZCC_out is not detected at the timing t132, it is determined as the CCM state, and the on-time is controlled to be reduced. By providing a margin for the determination of the DCM state or the CCM state, and performing control to reduce the on-time when it is determined to be the CCM state, cross regulation can be avoided more reliably.

(13th Embodiment)
FIG. 14 is a diagram illustrating the configuration of the power supply circuit according to the thirteenth embodiment. Constituent elements corresponding to the above-described embodiment are denoted by the same reference numerals. In the present embodiment, the delay circuit 23 is connected to the output terminal of the comparison circuit 22 that compares the voltage V _LX of the output node 13 with the ground potential. The delayed output signal ZCC_out_dly delayed by the delay circuit 23 is supplied to the on-time control circuit 40.

(Fourteenth embodiment)
FIG. 15 is a diagram for explaining one embodiment of the control method of the power supply circuit according to the thirteenth embodiment described above. Slot assignment signals (φ1, φ2) are generated from the clock signal CLK and supplied to the switches (19-1 to 19-n). A delayed output signal ZCC_out_dly obtained by delaying the output signal ZCC_out of the comparison circuit 22 that compares the voltage V _LX of the output node 13 with the reference potential for a predetermined time is detected at a timing t151 of the clock signal CLK. When the delayed output signal ZCC_out_dly is not detected by the timing t151 of the clock signal CLK, control is performed to reduce the on-time. That is, it is determined whether the current state is the DCM state or the CCM state with a margin between the timing t152 and the timing t151. Cross regulation can be more reliably avoided by giving a margin to the determination of the DCM state or the CCM state and performing control to reduce the on-time when it is determined that the state is the CCM state.

(Fifteenth embodiment)
FIG. 16 is a diagram illustrating the configuration of the power supply circuit according to the fifteenth embodiment. Constituent elements corresponding to the above-described embodiment are denoted by the same reference numerals. In the present embodiment, the delay circuit 23 is connected to the output terminal of the comparison circuit 22 that compares the voltage V _LX of the output node 13 with the ground potential. The delayed output signal ZCC_out_dly delayed by the delay circuit 23 is supplied to the on-time control circuit 40. The on-time control circuit 40 is supplied with a high-speed clock signal high-speed CLK.

(Sixteenth embodiment)
FIG. 17 is a diagram for explaining one embodiment of the control method of the power circuit according to the fifteenth embodiment described above. A slot assignment signal is generated from the clock signal CLK. In FIG. 17, two slot assignment signals (φ1, φ2) are shown for convenience. Each slot assignment signal (φ1, φ2) is supplied to the corresponding switch (19-1 to 19-n).

The delay output signal ZCC_out_dly delayed by a predetermined time from the rising timing t171 of the output signal ZCC_out of the comparison circuit 22 that compares the voltage V _LX of the output node 13 with the ground potential that is the reference potential is the rising timing of each high-speed clock signal high-speed CLK. Detected at t173. For example, the state of the delayed output signal ZCC_out_dly is detected by latching it in a latch circuit (not shown) provided separately at each rising timing of the high-speed clock signal high-speed CLK. The state of the delayed output signal ZCC_out_dly latched by the latch circuit is detected at a timing t171 at the time of channel switching.

  If the delayed output signal ZCC_out_dly is not detected by the timing t171 of the clock signal CLK, it is determined that the state is the CCM state and control is performed to reduce the on-time. That is, the timing for detecting whether the state is the CCM state or the DCM state, that is, the timing for detecting the delayed output signal ZCC_out_dly is advanced from the timing t171 at which the output terminal is switched, so that the CCM state is determined with a margin. By providing a margin for the determination of the CCM state and performing control to reduce the on-time when it is determined to be the CCM state, cross regulation can be avoided more reliably.

(Seventeenth embodiment)
FIG. 18 is a diagram illustrating a configuration of a power supply circuit according to the seventeenth embodiment. Constituent elements corresponding to the above-described embodiment are denoted by the same reference numerals. In the present embodiment, the feedback comparators (24-1 to 24-n) that compare the output voltages (Vout1 to Voutn) and the reference voltages (Vref1 to Vrefn) have a delayed clock signal CLK_dly obtained by delaying the clock signal CLK. Is supplied. That is, the feedback comparators (24-1 to 24-n) perform a comparison operation in synchronization with the delayed clock signal CLK_dly. The on-time control circuit 40 is supplied with a clock signal CLK and a delayed clock signal CLK_dly obtained by delaying the clock signal CLK. Slot assignment signals (φ1, φ2) are generated from the delayed clock signal CLK_dly and supplied to the switches (19-1 to 19-n).

(Eighteenth embodiment)
FIG. 19 is a diagram for explaining one embodiment of the power circuit control method of the seventeenth embodiment already described. Slot assignment signals (φ1, φ2) are generated from the delayed clock signal CLK_dly and supplied to the switches (19-1 to 19-n). A delayed output signal ZCC_out_dly obtained by delaying the output signal ZCC_out of the comparison circuit 22 that compares the voltage V _LX of the output node 13 with the reference potential for a predetermined time is detected at a timing t193 at which the clock signal CLK rises. When the delayed output signal ZCC_out_dly is not detected by timing t193, control is performed to reduce the on-time. That is, it is determined whether the current state is the DCM state or the CCM state with a margin between the timing t192 at which the output signal ZCC_out of the comparison circuit 22 is output and the timing t191 of the delayed clock signal CLK_dly that is the channel switching timing. If the CCM state is determined, control is performed to reduce the on-time. By this control, the occurrence of cross regulation can be avoided more reliably.

(Nineteenth embodiment)
FIG. 20 is a diagram illustrating the configuration of the power supply circuit according to the nineteenth embodiment. Constituent elements corresponding to the above-described embodiment are denoted by the same reference numerals. In the present embodiment, the clock signal CLK is supplied to the feedback comparators (24-1 to 24-n) that compare the output voltages (Vout1 to Voutn) and the reference voltages (Vref1 to Vrefn). That is, the feedback comparators (24-1 to 24-n) perform a comparison operation in synchronization with the clock signal CLK. The on-time control circuit 40 is supplied with a delayed output signal ZCC_out_dly obtained by delaying the output signal ZCC_out of the comparison circuit 22 that compares the voltage V _LX of the output node 13 with the reference potential for a predetermined time. The on-time control circuit 40 is supplied with a clock signal CLK and a delayed clock signal CLK_dly obtained by delaying the clock signal CLK.

(20th embodiment)
FIG. 21 is a diagram for explaining one embodiment of the control method of the power circuit according to the nineteenth embodiment already described. Slot assignment signals (φ1, φ2) are generated from the clock signal CLK and supplied to the switches (19-1 to 19-n). The delayed output signal ZCC_out_dly obtained by delaying the output signal ZCC_out of the comparison circuit 22 that compares the voltage V _LX of the output node 13 with the reference potential for a predetermined time is detected at the rising timing t213 of the delayed clock signal CLK_dly obtained by delaying the clock signal CLK. The When the delayed output signal ZCC_out_dly is not detected by timing t213, control is performed to reduce the on-time. That is, it is determined whether the current state is the DCM state or the CCM state with a margin between the timing t212 at which the output signal ZCC_out of the comparison circuit 22 is output and the timing t211 of the clock signal CLK that is the channel switching timing. When it is determined that the state is on, control is performed to reduce the on-time. By controlling the on-time with a margin, it is easy to avoid cross regulation.

(21st Embodiment)
FIG. 22 is a diagram for explaining another embodiment of the method for controlling the power supply circuit. In the present embodiment, slot assignment signals (φ1, φ2) are generated from the clock signal CLK. Before the channel is switched, that is, at the timing t222 before the timing t221 at which the next clock signal CLK rises, the low-side NMOS switching transistor 14 is turned off. For example, a signal PWSW_off that turns off the NMOS switching transistor 14 is generated using a high-speed clock signal (not shown), and the NMOS switching transistor 14 is controlled by controlling the buffer circuit 38 that supplies a drive signal to the NMOS switching transistor 14. Can be turned off.

A control method when the inductor current Iind flows to the output voltage side when the NMOS switching transistor 14 is turned off will be described with reference to FIG. When the inductor current Iind flows to the output voltage side when the NMOS switching transistor 14 is turned off, the voltage V _LX at the output node 13 becomes lower than the ground potential, as shown by the dotted circle (v). In this case, control to reduce the ON time is performed, and at the timing when the slot assignment signal φ1 is next supplied, control is performed so that the channel is switched at the timing when the inductor current Iind becomes zero. This is to avoid cross regulation.

A control method in the case where the inductor current Iind flows from the output voltage side to the NMOS switching transistor 14 when the NMOS switching transistor 14 is turned off will be described with reference to FIG. When the inductor current Iind flows from the output voltage side to the NMOS switching transistor 14 when the NMOS switching transistor 14 is turned off, the voltage V _{LX at the} output node 13 becomes higher than the ground potential. That is, as indicated by the dotted ellipse (vi), ringing occurs in the voltage V _LX of the output node 13, and the voltage becomes higher than the ground potential. In this case, control for increasing the on-time of the PMOS switching transistor 12 is performed. By increasing the on-time, the inductor current Iind can be supplied to the capacitor 18 and the output voltage Vout can be increased by making maximum use of the slot period.

In the present embodiment, the low-side NMOS switching transistor 14 is forcibly turned off at a timing t222 before the high-side PMOS switching transistor 12 is turned on, and the voltage V _LX of the output node 13 at the timing t221 at which the channel is switched is set. By detecting the direction in which the inductor current Iind flows and determining the ON time, the occurrence of cross regulation can be avoided without using the comparison circuit 22.

(Twenty-second embodiment)
FIG. 23 is a diagram illustrating the configuration of the power supply circuit according to the twenty-second embodiment. Constituent elements corresponding to the above-described embodiment are denoted by the same reference numerals. In the present embodiment, a predetermined reference voltage Vref is applied to the other input terminal of the comparison circuit 22 that detects the voltage V _LX of the output node 13 instead of the ground potential. An embodiment in the case of so-called pseudoDCM is shown. For example, when the voltage V _{LX at} the output node 13 becomes higher than the reference voltage Vref, the comparison circuit 22 outputs a high-level output signal CMP_out.

  A switch 160 is connected to both ends of the inductor 16. The switch 160 is supplied with a control signal pwsw_off, and its on / off is controlled. That is, the current that has been flowing through the inductor 16 when the NMOS switching transistor 14 on the low side is turned off is circulated.

(23rd embodiment)
FIG. 24 is a diagram for explaining one embodiment of the control method of the power circuit according to the twenty-second embodiment described above. In the present embodiment, slot assignment signals (φ1, φ2) are generated from the clock signal CLK. The output signal CMP_out of the comparison circuit 22 is detected at the timing when the channel is switched, that is, at the timing t241 when the next clock signal CLK rises. As shown in FIG. 6A, when the output signal CMP_out of the comparison circuit 22 is not detected at the timing t241, it is determined that the inductor current Iind larger than the reference current Aref flows, and control is performed to reduce the on-time. . This is to shift to the DCM state and avoid cross regulation.

  As shown in FIG. 5B, when the output signal CMP_out of the comparison circuit 22 is detected at the timing when the channel is switched, that is, at the timing t241 at which the next clock signal CLK rises, the inductor current Iind becomes the reference current Aref. It determines that it is below, and performs control which increases ON time. By increasing the on-time, the inductor period Iind can be supplied to the capacitor by making maximum use of the slot period, and the output voltage can be increased.

  Also in the case of pseudoDCM of this embodiment, the operation state at the channel switching timing is detected, and when the inductor current Iind is equal to or less than the reference current Aref, control is performed to increase the on-time. As a result, the control for increasing the output voltage (Vout1 to Voutn) by supplying the inductor current Iind to the capacitors (18-1 to 18-n) by making the maximum use of the period of one cycle of the clock signal CLK, that is, the maximum Control by the Ton control mode can be maintained. When the inductor current Iind larger than the reference current Aref is flowing, the on-time is reduced to perform control to avoid the occurrence of cross regulation.

(24th Embodiment)
FIG. 25 is a diagram illustrating a configuration of a power supply circuit according to the twenty-fourth embodiment. Constituent elements corresponding to the above-described embodiment are denoted by the same reference numerals. In the present embodiment, a current sensor 251 and a DCM trigger circuit 250 are provided. In this embodiment, instead of the configuration of detecting the voltage V _LX of the output node 13, the inductor current Iind is detected to detect the DCM state or the CCM state.

  The current sensor 251 includes, for example, a comparator (not shown) having inputs connected to both ends of a resistor (not shown) connected in series to the inductor 16. When the direction in which the inductor current Iind flows changes, the magnitude relationship of the voltage input to the comparator changes. Since the output of the comparator is switched by changing the magnitude relation of the voltage, it is possible to detect the DCM state or the CCM state by detecting the change in the output of the comparator.

  For example, the DCM trigger circuit 250 supplies the trigger signal DCM trigger signal to the on-time control circuit 40 in response to a change in the output of the comparator. In response to the DCM trigger signal, the DCM / CCM detection circuit 42 of the on-time control circuit 40 supplies the pulse generation circuit 32 with a signal for adjusting the high level period of the pulse signal.

  In this embodiment, by detecting the change in the direction of the current of the inductor current Iind, it is detected whether it is in the DCM state or the CCM state, and the time width of the high level of the pulse signal is adjusted to adjust the ON time. Can be controlled.

(25th Embodiment)
FIG. 26 is a diagram illustrating an embodiment of a control method for controlling the timing for adjusting the on-time. In the present embodiment, slot assignment signals (φ1, φ2) are generated from the clock signal CLK. For convenience of explanation, only the control for the channel 1 to which the slot assignment signal φ1 is supplied will be described. In the control method of the present embodiment, when the DCM state is determined, the on-time is adjusted at the timing when the next slot assignment signal φ1 is supplied to the channel 1. That is, when the DCM state is determined at timing t261, control is performed to increase the on-time at the timing when the next slot assignment signal φ1 is supplied, and the on-time is increased to Ton + α. This is because the on-time adjustment is reflected at an early timing.

  When the CCM state is determined at the timing t262 of the clock signal CLK, the on-time is reduced at the time of slot assignment when the next slot assignment signal φ1 is supplied to the channel 1, and control is performed to return to the original time Ton.

  By immediately reflecting the detection result of the DCM state / CCM state in the adjustment of the on-time at the time of the next slot assignment, the output voltage can be quickly controlled according to the load state. When the CCM state is determined, the on-time is quickly reduced to shift to the DCM state, thereby avoiding the occurrence of cross regulation.

(26th Embodiment)
FIG. 27 is a diagram illustrating another embodiment of a control method for controlling the timing for adjusting the on-time. In the present embodiment, slot assignment signals (φ1, φ2) are generated from the clock signal CLK. For convenience of explanation, only the control for the channel 1 to which the slot assignment signal φ1 is supplied will be described. In the control method according to the present embodiment, when the DCM state is determined at the timing t271 when the channel is switched, the on-time is adjusted when the third slot is allocated from the determined slot. That is, the control for increasing the ON time is delayed by a predetermined time, not the timing at which the next slot assignment signal φ1 is supplied, and the ON time is increased to Ton + α. At this time, power consumption can be reduced by stopping the operation of the circuit related to the determination of the on-time control between the slot to be determined and the slot for adjusting the time. Also, it is possible to perform control to increase the on-time only when it is determined that the DCM state is continuous for three slots.

  When the CCM state is determined at the timing t272 at the time of channel switching, control to reduce the on-time is performed. Control for reducing the ON time is performed at the timing when the next slot assignment signal φ1 is supplied. That is, at the timing when the next slot assignment signal φ1 is applied, for example, control is performed to return the on time to the original time Ton. In the control method of the present embodiment, when the CCM state is determined at the timing t272 when the channel is switched, the on-time is adjusted when the third slot is allocated from the determined slot. That is, the control to reduce the on time is delayed by a predetermined time, not the timing at which the next slot assignment signal φ1 is supplied, to reduce the on time. At this time, power consumption can be reduced by stopping the operation of the circuit related to the determination of the on-time control between the slot to be determined and the slot for adjusting the time. Also, it is possible to perform control to reduce the on-time only when it is determined that the CCM state is continuous for three slots.

  In this embodiment, the control for increasing the on-time when it is determined as the DCM state is performed at a timing delayed by a predetermined time, and the control for decreasing the on-time when it is determined as the CCM state is performed at the timing of the next slot allocation. Do. When the CCM state is determined, the occurrence of cross regulation can be avoided by reducing the on-time at an early timing. That is, it is possible to make the control within different times by changing the timing for performing the control for reducing the ON time by determining the CCM state and the control for increasing the ON time by determining the DCM state. By delaying the control to increase the on-time, the frequency of the on-time control is reduced, so that the circuit operation is stabilized. The adjustment of the timing of the control for increasing the on-time and the control for decreasing the on-time is performed, for example, by providing a storage circuit (not shown) for storing the detection result of the CCM state and the detection of the DCM state. The on-time can be controlled after a predetermined timing based on the stored information.

(Twenty-seventh embodiment)
FIG. 28 is a diagram illustrating a configuration of a power supply circuit according to a twenty-seventh embodiment. Constituent elements corresponding to the above-described embodiment are denoted by the same reference numerals. This embodiment shows one embodiment in the case of the second control mode, that is, the minimum Ton control mode. Since the second control mode is selected, the mode switching signal mode supplied to the on-time control circuit 40 is omitted.

  The power supply circuit of this embodiment includes a feedback comparator 24 that compares the output voltage Vout of the output terminal 20 and the reference voltage Vref1 in synchronization with the clock signal CLK. The output signal FBCMP_out of the feedback comparator 24 is supplied to the on-time control circuit 40. The on-time control circuit 40 has a pulse skip detection circuit 41 that detects the output signal FBCMP_out of the feedback comparator 24 and detects the presence or absence of a pulse skip. For example, when the output voltage Vout is lower than the reference voltage Vref1, the feedback comparator 24 outputs a high-level output signal FBCMP_out.

(Twenty-eighth embodiment)
FIG. 29 is a diagram for explaining one embodiment of the control method of the power circuit according to the 27th embodiment described above. In the present embodiment, the output signal FBCMP_out of the feedback comparator 24 is detected in synchronization with the clock signal CLK. In a state where the output signal FBCMP_out of the feedback comparator 24 is not detected, that is, in the case of pulse skip, control is performed to reduce the on-time. For example, control for reducing the on-time to Ton-α is performed. The state in which pulse skip occurs is that the charge supplied in one pulse is larger than the charge consumed in one clock period, so supply by one pulse by reducing the on-time and reducing the inductor current Iind. The charge to be reduced can be made to coincide with the charge consumed in one clock period. Further, it is possible to perform frequency control to make the switching frequency of the switching transistor coincide with the clock signal CLK by avoiding pulse skip by reducing the ON time.

(Twenty-ninth embodiment)
FIG. 30 is a diagram illustrating a flow of a method for controlling the power supply circuit. The output voltage Vout is compared with the reference voltage Vref in synchronization with the clock signal CLK (S311). It is checked whether or not there is a pulse skip (S312). When there is a pulse skip, that is, when the output signal FBCMP_out of the feedback comparator 24 is not detected, the ON time is decreased (S313). This is because the output voltage Vout is maintained at a high level, so that the output voltage Vout is lowered so that there is no pulse skip. If there is no pulse skip, the on-time is not adjusted and the same on-time is maintained (S314).

  In the present embodiment, control is performed to detect the presence or absence of pulse skip and adjust the on-time. By controlling so that no pulse skip occurs, the output voltage Vout can be controlled in the minimum Ton control mode in which the switching transistor performs a switching operation at a frequency matching the frequency of the clock signal CLK and charges the capacitor 18.

(Thirty embodiment)
FIG. 31 is a diagram showing a flow of another control method of the power supply circuit. The output voltage Vout is compared with the reference voltage Vref in synchronization with the clock signal CLK (S321). It is checked whether or not there is a pulse skip (S322). When there is a pulse skip, it is detected whether or not the pulse skip has occurred continuously (S323). If pulse skips occur continuously, control is performed to reduce the on-time (S324). When pulse skip does not occur continuously, the on-time is not adjusted and the current on-time is maintained (S325). When there is no pulse skip, that is, when the output signal FBCMP_out of the feedback comparator 24 is detected in synchronization with the clock signal CLK, the current on-time is maintained (S325).

  In the present embodiment, it is detected whether or not pulse skips are continued, and control is performed to reduce the on-time when pulse skips occur continuously. It is possible to reduce the frequency of control and stabilize the circuit operation by adjusting the on-time only when pulse skips occur continuously instead of adjusting the on-time each time a pulse skip occurs. .

(Thirty-first embodiment)
FIG. 32 is a diagram illustrating a flow of another control method of the power supply circuit. The output voltage Vout is compared with the reference voltage Vref in synchronization with the clock signal CLK (S331). The presence or absence of pulse skip is detected (S332). In the detection performed continuously, it is detected whether or not the pulse skip has occurred a predetermined number of times (S333). When the pulse skip occurs a predetermined number of times in the continuous detection, the ON time is decreased (S334). For example, the ON time is decreased when N pulse skips are detected in M detections that are continuously performed. M and N can be set arbitrarily. If the pulse skip does not occur a predetermined number of times, the on time is maintained (S335). Even when the pulse skip does not occur, the on-time is maintained (S335).

  In this embodiment, in the detection performed continuously, when the pulse skip occurs a predetermined number of times, control is performed to reduce the on-time. Frequency of on-time control by controlling the on-time only when a predetermined number of pulse skips occur in the continuous detection of a predetermined number of times, rather than controlling the on-time each time a pulse skip occurs And the circuit operation can be stabilized.

(Thirty-second embodiment)
FIG. 33 is a diagram illustrating a flow of another control method of the power supply circuit. The output voltage Vout is compared with the reference voltage Vref in synchronization with the clock signal CLK (S341). The presence or absence of pulse skip is detected (S342). It is detected whether or not a state without pulse skip occurs continuously (S343). When the state without pulse skip occurs continuously, the ON time is increased (S344). If the state without pulse skip does not occur continuously, the on-time is not adjusted and the current on-time is maintained (S345). If pulse skip occurs, the on-time is decreased (S346).

  In the present embodiment, control is performed to increase the on-time when a state without pulse skip occurs continuously. When there is a state in which there is no pulse skip continuously, there is a possibility that the amount of current supplied to the channel may be insufficient. Therefore, the output voltage Vout is increased by supplementing the current with a longer on-time. The decrease can be suppressed.

(Thirty-third embodiment)
FIG. 34 is a diagram showing a flow of another control method of the power supply circuit. The output voltage Vout is compared with the reference voltage Vref in synchronization with the clock signal CLK (S351). The presence or absence of pulse skip is detected (S352). If there is no pulse skip, it is detected whether a state without pulse skip has occurred continuously (S353). When the state without pulse skip occurs continuously, the ON time is increased (S354). If the state without pulse skip does not occur, the on-time is not adjusted and the current on-time is maintained (S355).

  In the present embodiment, control is performed to increase the on-time when a state without pulse skip occurs continuously. When a state without pulse skip occurs continuously, there is a possibility that the amount of current supplied to the channel may be insufficient. Therefore, the output voltage Vout is increased by replenishing the current by extending the ON time. The decrease can be suppressed.

(Thirty-fourth embodiment)
FIG. 35 is a diagram showing a flow of another control method of the power supply circuit. The output voltage Vout is compared with the reference voltage Vref in synchronization with the clock signal CLK (S361). The presence or absence of pulse skip is detected (S362). When there is no pulse skip, it is detected whether or not a state without pulse skip has occurred a certain number of times (S363). When the state without pulse skip occurs a certain number of times, the on-time is increased (S364). If the state without pulse skip does not occur, the on-time is not adjusted and the current on-time is maintained (S365).

  In the present embodiment, control is performed to increase the on-time when a state without pulse skip occurs a certain number of times. When a state without pulse skip occurs a certain number of times, there is a possibility that the amount of current supplied to the channel may be insufficient. Therefore, by reducing the output voltage Vout by increasing the ON time and replenishing the current. I can do it. In addition, when there is a pulse skip, or when the pulse skip occurs continuously or occurs a certain number of times, it is possible to perform a control combined with a control for reducing the ON time.

(Thirty-fifth embodiment)
FIG. 36 is a diagram showing the configuration of the power supply circuit of the 35th embodiment. Constituent elements corresponding to the above-described embodiment are denoted by the same reference numerals. In the present embodiment, one end 200 of the inductor 16 is connected to a plurality of output terminals (20-1 to 20-n) in a time division manner. That is, each output terminal (20-1 to 20-n) is connected to the inductor 16 when each switch (19-1 to 19-n) is on. Each switch (19-1 to 19-n) is controlled to be turned on / off by the supplied slot assignment signal (φ1 to φn). Each output terminal (20-1 to 20-n) supplies an independent output voltage (Vout1 to Voutn) to each load (not shown).

  Feedback comparators (24-1 to 24-n) that compare the output voltages (Vout1 to Voutn) and the reference voltages (Vref1 to Vrefn) in synchronization with the clock signal CLK are provided. Each food back comparator outputs an output signal (FBCMP_out1 to FBCMP_outn) corresponding to the comparison result between the output voltage (Vout1 to Voutn) and each reference voltage (Vref1 to Vrefn), and supplies the output signal to the on-time control circuit 40.

  The power supply circuit of this embodiment is a SIMO type power supply circuit that supplies independent output voltages (Vout1 to Voutn) from a plurality of output terminals (20-1 to 20-n) connected to a common inductor 16 in a time division manner. Configure. Presence / absence of pulse skipping by the output signals (FBCMP_out1 to FBCMP_outn) indicating the comparison results of the output voltages (Vout1 to Voutn) and the reference voltages (Vref to Vrefn) in each channel in a state where the slot assignment signals (φ1 to φn) are supplied. Detecting and controlling the on-time at the time of slot assignment to each channel using the control method described above. By this control, the output voltage (Vout1 to Voutn) can be controlled in the SIMO type power supply circuit in the minimum Ton control mode.

(Thirty-sixth embodiment)
FIG. 37 is a diagram showing the configuration of the power supply circuit according to the thirty-sixth embodiment. Constituent elements corresponding to the above-described embodiment are denoted by the same reference numerals. In this embodiment, in addition to the feedback comparator 24-1 that compares the output voltage Vout1 of the output terminal 20-1 with the reference voltage Vref1 in synchronization with the clock signal CLK, the output voltage Vout1 is synchronized with the high-speed clock signal high-speed CLK. A second feedback comparator 24-1-2 that compares with the reference voltage Vref1-2 is included. For example, the reference voltage Vref1-2 is set to a value lower than the reference voltage Vref1. The high-speed clock signal high-speed CLK has a higher frequency than the clock signal CLK. Similarly, two feedback comparators are connected to each of the other output terminals (20-2 to 20-n), but are omitted.

  In the power supply circuit of the present embodiment, the presence or absence of pulse skip is detected by detecting the output signal FBCMP_out1 of the feedback comparator 24-1. By detecting the output signal FBCMP_out1-2 of the second feedback comparator 24-1-2 to which the high-speed clock signal high-speed CLK is applied, it is detected whether or not the output voltage Vout1 is lower than the reference voltage Vref1-2. That is, in addition to detecting the presence or absence of pulse skip, the degree of decrease in the output voltage Vout1 is detected. For example, even when there is no pulse skipping, when the output voltage Vout1 is lower than the reference voltage Vref1-2, the on-time is increased to increase the supply amount of the inductor current Iind, thereby increasing the output voltage Vout1. I do.

  In this embodiment, even when pulse skip does not occur, if the output voltage Vout is greatly reduced, it is possible to perform control to increase the on-time in the channel. It can respond quickly.

(Thirty-seventh embodiment)
FIG. 38 is a diagram for explaining one embodiment of the power supply circuit control method according to the thirty-sixth embodiment described above. Slot assignment signals (φ1, φ2) are generated from the clock signal CLK. The output signal FBCMP_out1 of the feedback comparator 24-1 is detected in synchronization with the clock signal CLK. In the case shown in FIG. 38, since the output signal FBCMP_out1 of the feedback comparator 24-1 exists at the rising timing t363 of the slot assignment signal φ1, there is no pulse skipping.

  In synchronization with the high-speed clock signal high-speed CLK, the second feedback comparator 24-1-2 compares the output voltage Vout1 with the reference voltage Vref1-2. At timing t361 of the high-speed clock signal high-speed CLK, the output voltage Vout1 is lower than the reference voltage Vref1-2. That is, the output voltage Vout is reduced. For this reason, control is performed to increase the ON time to Ton + α by increasing the ON time.

  In the control method of the present embodiment, in addition to detecting the presence or absence of pulse skip, the state of decrease in the output voltage Vout is detected. When the decrease in the output voltage Vout is large, even when there is no pulse skipping, it is possible to respond quickly to load fluctuations by performing control to increase the on-time and increase the output voltage Vout.

(Thirty-eighth embodiment)
FIG. 39 is a diagram illustrating a flow of the control method according to the thirty-eighth embodiment. In synchronization with the clock signal CLK, the feedback comparator 24-1 compares the output voltage Vout1 with the reference voltage Vref1 (S371). The output signal FBCMP_out1 of the feedback comparator 24-1 is detected to detect whether or not pulse skip has occurred (S372). If there is a pulse skip, the on-time is decreased (S373).

  If there is no pulse skip, the output voltage Vout1 is compared with the reference voltage Vref1-2 in synchronization with the high-speed clock signal high-speed CLK (S374). It is detected whether or not the output voltage Vout1 is lower than the reference voltage Vref1-2 (S375). When the output voltage Vout1 is lower than the reference voltage Vref1-2, the on-time is increased (S376). When there is no voltage drop until the output voltage Vout1 falls below the reference voltage Vref1-2, the on-time is not adjusted and Ton is maintained (S377).

  In the control method of the present embodiment, in addition to detecting the presence or absence of pulse skip, the state of decrease in the output voltage Vout is detected. When the decrease in the output voltage Vout is large, even when there is no pulse skipping, it is possible to respond quickly to load fluctuations by performing control to increase the on-time and increase the output voltage Vout.

(39th Embodiment)
FIG. 40 is a diagram for explaining the control method of the power supply circuit according to the thirty-ninth embodiment. In the control method of the present embodiment, for example, in the configuration of a single channel power supply circuit as shown in FIG. 1, one input terminal is connected to the common output terminal 20-1 as in the configuration of the power supply circuit shown in FIG. One input terminal is connected to the first feedback comparator 24-1 to which the first reference voltage Vref is applied to the other input terminal and the output terminal 20-1, and the second input terminal is connected to the second input terminal. This is achieved by a configuration including a second feedback comparator 24-1-2 to which the reference voltage Vref-2 is applied. For example, the first reference voltage Vref is set to a voltage higher than the second reference voltage Vref-2.

  At the rising timing (t401 to t405) of the clock signal CLK supplied to the first and second feedback comparators (24-1, 24-1-2), the first feedback comparator 24-1 sets the output voltage Vout. The first reference voltage Vref is compared. When the output voltage Vout is lower than the first reference voltage Vref, a drive signal for driving the PMOS switching transistor 12 is generated. In the illustrated example, at each timing (t401 to t405), since the output voltage Vout is lower than the first reference voltage Vref, a drive signal for driving the PMOS transistor 12 is generated.

  At the rising timing (t401, t403, t405) of the clock signal CLK, the second feedback comparator 24-1-2 compares the output voltage Vout with the second reference voltage Vref-2. For example, when the output voltage Vout is lower than the second reference voltage Vref-2, the H-level output signal FBCMP-2_out is output. In response to the H level output signal FBCMP-2_out, the on-time control circuit 40 performs control to increase the on-time from Ton to Ton + α.

  At the rising timing (t402, t404) of the clock signal CLK, the comparison operation between the output voltage Vout and the second reference voltage Vref-2 by the second feedback comparator 24-1-2 is not performed. For example, at the timing (t402, t404), the operation of the second feedback comparator 24-1-2 can be stopped by performing control so that the clock signal CLK is not supplied to the second feedback comparator.

  At timing t403 of the clock signal CLK, the output voltage Vout and the second reference voltage Vref-2 are compared. When the output voltage Vout is lower than the second reference voltage Vref-2, an H-level output signal FBCMP-2_out is output. The on-time control circuit 40 performs control to increase the on-time from Ton + α to Ton + 2α.

  In the power supply circuit control method of this embodiment, two feedback comparators having one input terminal connected to a common output terminal are provided, and a drive signal is supplied to the PMOS switching transistor 12 by the output signal of one feedback comparator. For example, control is performed to adjust the on-time based on the output signal of the second feedback comparator that compares the lower second reference voltage with the output voltage Vout. The operation of the second feedback comparator for adjusting the on-time is not an operation synchronized with the rising of each time of the clock signal CLK, for example, a comparison operation once every two times, thereby consuming the feedback comparator. Electric power can be reduced. Further, the circuit operation can be stabilized by reducing the number of times of on-time control.

(40th embodiment)
FIG. 41 is a diagram for explaining the control method for the power supply circuit according to the fortieth embodiment. In the control method of this embodiment, for example, as shown in FIG. 1, in the configuration of a single-channel power supply circuit, one input terminal is connected to the output terminal 20, and the first reference voltage Vref and the first input terminal are connected to the other input terminal. This is achieved by a configuration including a feedback comparator 24 to which two reference voltages Vref-2 are switched and supplied. For example, the second reference voltage Vref-2 is set to a voltage lower than the first reference voltage Vref.

  At every other rising timing (t411, t413, t415, t417) of the high-speed clock signal high-speed CLK supplied to the feedback comparator 24, the feedback comparator 24 compares the output voltage Vout with the first reference voltage Vref. When the output voltage Vout is lower than the first reference voltage Vref, a drive signal for driving the PMOS switching transistor 12 is generated. In the case of the illustrated example, the output voltage Vout is lower than the first reference voltage Vref at each timing (t411, t413, t415, t417), so that a drive signal for driving the PMOS switching transistor 12 is generated.

  At every other rising timing (t412, t414, t416) of the high-speed clock signal high-speed CLK, the reference voltage supplied to the feedback comparator 24 is changed from the first reference voltage Vref to the second reference voltage Vre-2. The output voltage Vout is compared with the second reference voltage Vref-2 by switching. For example, when the output voltage Vout is lower than the second reference voltage Vref-2 as at the timing t412 of the high-speed clock signal high-speed CLK, the H-level output signal FBCMP_out is output. The on-time control circuit 40 performs control to increase the on-time from Ton to Ton + α in response to the H-level output signal FBCMP_out.

  In the control method of the power supply circuit according to the present embodiment, every other reference voltage supplied to one feedback comparator 24 to which the high-speed clock signal high-speed CLK is supplied is the first reference voltage Vref and the second reference voltage Vref. -2 is switched to determine whether to supply a drive signal to the PMOS switching transistor 12 by comparing the first reference voltage Vref and the output voltage Vout, and the second reference voltage Vref-2 and the output voltage Vout The ON time can be controlled by comparing the two. Since the number of feedback comparators can be reduced by sharing one feedback comparator, power consumption can be reduced.

(41st embodiment)
FIG. 42 is a diagram for explaining the control method for the power supply circuit according to the forty-first embodiment. In the control method of the present embodiment, for example, in the configuration of a single channel power supply circuit as shown in FIG. 1, one input terminal is connected to the common output terminal 20-1 as in the configuration of the power supply circuit shown in FIG. The first feedback comparator 24-1 connected to the other input terminal and the reference voltage Vref applied to the other input terminal, one input terminal connected to the output terminal 20-1, and the reference voltage Vref applied to the other input terminal. This is achieved by a configuration including the second feedback comparator 24-1-2. The first feedback comparator 24-1 operates in synchronization with the clock signal CLK, and the second feedback comparator 24-1-2 operates in synchronization with the delayed clock signal CLK_dly delayed with respect to the clock signal CLK.

  At the rising timing (t421, t423, t425, t427) of the clock signal CLK supplied to the first feedback comparator 24-1, the output voltage Vout and the reference voltage Vref are compared by the first feedback comparator 24-1. . When the output voltage Vout is lower than the reference voltage Vref, a drive signal for driving the PMOS switching transistor 12 is generated. In the case of the illustrated example, the output voltage Vout is lower than the reference voltage Vref at each timing (t421, t423, t425, t427), so that a drive signal for driving the PMOS transistor 12 is generated.

  At the rising timing (t422, t424, t426) of the delayed clock signal CLK_dly, the second feedback comparator 24-1-2 compares the output voltage Vout with the reference voltage Vref. When the output voltage Vout is lower than the reference voltage Vref at the rising timing of the delayed clock signal CLK_dly, the H-level output signal FBCMP-2_out is output from the second feedback comparator 24-1-2, and the on-time control circuit 40 Performs control to increase the ON time in response to the H level output signal FBCMP-2_out. For example, since the output voltage Vout is lower than the reference voltage Vref at the timing t422 of the delayed clock signal CLK_dly, control is performed to increase the on time from Ton to Ton + α. In addition, since the output voltage Vout is lower than the reference voltage at the timing t424 of the delayed clock signal CLK_dly, the H-level output signal FBCMP-2_out is output from the second feedback comparator 24-1-2, and the on-time control circuit 40 Increases the on-time to Ton + 2α in response to the H level output signal FBCMP-2_out.

  In the control method of the power supply circuit of the present embodiment, two feedback comparators connected to a common output terminal are provided, and the PMOS is generated by the output signal of the first feedback comparator 24-1 operating in synchronization with the clock signal CLK. It is determined whether or not to supply a drive signal to the switching transistor 12, and the reference voltage Vref and the output voltage at the timing of the delayed clock signal CLK_dly delayed with respect to the clock signal CLK supplied to the first feedback comparator 24-1. It is possible to control to adjust the on-time by comparing Vout and detecting the degree of decrease of the output voltage Vout. Note that the operation of the second feedback comparator 24-1-2 for adjusting the on-time is not an operation synchronized with the rising of the delayed clock signal CLK_dly every time, but is performed, for example, once every two times of the delayed clock signal CLK_dly. By performing the comparison operation with the frequency of times, the power consumption of the second feedback comparator 24-1-2 can be reduced. Further, the circuit operation can be stabilized by reducing the number of times of on-time control.

(Forty-second embodiment)
FIG. 43 is a diagram for explaining the control method of the power supply circuit according to the forty-second embodiment. In the control method of the present embodiment, for example, in the configuration of a single channel power supply circuit as shown in FIG. 1, one input terminal is connected to the common output terminal 20-1 as in the configuration of the power supply circuit shown in FIG. A first feedback comparator 24-1 to which the reference voltage Vref is applied to the other input terminal, one input terminal connected to the output terminal 20-1, and a second reference voltage Vref to the other input terminal. -2 is achieved by a configuration including a second feedback comparator 24-1-2. For example, the second reference voltage Vref-2 is set to a voltage lower than the first reference voltage Vref. The first feedback comparator 24-1 operates in synchronization with the clock signal CLK, and the second feedback comparator 24-1-2 operates in synchronization with the delayed clock signal CLK_dly delayed with respect to the clock signal CLK.

  At the rising timing (t431, t433, t435, t437) of the clock signal CLK supplied to the first feedback comparator 24-1, the first feedback comparator 24-1 compares the output voltage Vout with the reference voltage Vref. . When the output voltage Vout is lower than the reference voltage Vref, a drive signal for driving the PMOS switching transistor 12 is generated. In the case of the illustrated example, the output voltage Vout is lower than the reference voltage Vref at each timing (t431, t433, t435, t437), so that a drive signal for driving the PMOS switching transistor 12 is generated.

  At the rising timing (t432, t434, t436) of the delayed clock signal CLK_dly, the second feedback comparator 24-1-2 compares the output voltage Vout with the second reference voltage Vref-2. When the output voltage Vout is lower than the second reference voltage Vref-2 at the rising timing of the delayed clock signal CLK_dly, the H-level output signal FBCMP-2_out is output from the second feedback comparator 24-1-2, The on-time control circuit 40 performs control to increase the on-time in response to the H-level output signal FBCMP-2_out. For example, since the output voltage Vout is lower than the second reference voltage Vref−2 at the timing t432 of the delayed clock signal CLK_dly, control is performed to increase the on time from Ton to Ton + α. At the rising timings t434 and t436 of the delayed clock signal CLK_dly, since the output voltage Vout is higher than the second reference voltage Vref-2, no H level signal is output from the second feedback comparator 24-1-2. Therefore, the on-time is maintained at Ton + α.

  In the control method for the power supply circuit of the present embodiment, two feedback comparators connected to a common output terminal are provided. It is determined whether or not a drive signal is supplied to the PMOS switching transistor 12 based on an output signal of the first feedback comparator 24-1 that operates in synchronization with the clock signal CLK, and is supplied to the first feedback comparator 24-1. The second reference voltage Vref-2 lower than the first reference voltage Vref is compared with the output voltage Vout at the timing of the delayed clock signal CLK_dly delayed with respect to the clock signal CLK to detect the degree of decrease in the output voltage Vout Thus, control for adjusting the on-time can be performed. Note that the operation of the second feedback comparator 24-1-2 for adjusting the on-time is not an operation synchronized with the rising of the delayed clock signal CLK_dly every time, but is performed, for example, once every two times of the delayed clock signal CLK_dly. By performing the control for performing the comparison operation at the frequency of times, the power consumption of the second feedback comparator 24-1-2 can be reduced. Further, the circuit operation can be stabilized by reducing the number of times of on-time control.

  The embodiment described with reference to FIGS. 40 to 43 can also be applied to a SIMO type power supply circuit having a plurality of output terminals.

(43rd embodiment)
FIG. 44 is a diagram showing the configuration of the power supply circuit of the forty-third embodiment. Constituent elements corresponding to the above-described embodiment are denoted by the same reference numerals. In the present embodiment, the on-time control circuit 40 includes a channel selection circuit 44. The channel selection circuit 44 arbitrarily selects a channel for performing a comparison operation between the output voltage (Vout1 to Voutn) and the reference voltage Vref.

  In the present embodiment, in addition to the operation of detecting the presence or absence of pulse skip by comparing the output voltages (Vout1 to Voutn) and the reference voltages (Vref1 to Vrefn) by the feedback comparators (24-1 to 24-n), any The output voltages (Vout1 to Voutn) of the selected channels and the reference voltages (Vref1 to Vrefn) can be compared using the feedback comparators (24-1 to 24-n) at an arbitrary timing. That is, there is a configuration in which the operation of detecting the presence or absence of pulse skipping in the selected channel and the state of decrease in the output voltage (Vout1 to Voutn) is performed in parallel. Thus, in addition to the on-time control based on the presence / absence of pulse skip, the second feedback comparator (24-1-2) adjusts the on-time in the channel when a decrease in the output voltage (Vout1 to Voutn) is detected. Without using the feedback comparator (24-1 to 24-n).

(44th Embodiment)
FIG. 45 is a diagram for explaining one embodiment of the power circuit control method of the forty-fourth embodiment described above. In the present embodiment, slot assignment signals (φ1, φ2) are generated from the clock signal CLK. The feedback comparator 24-1 compares the output voltage Vout1 with the reference voltage Vrfef1 at the timings t391 and t393 for assigning the slot to the channel 1, and detects the presence or absence of pulse skipping. When the output voltage Vout1 is lower than the reference voltage Vref1, a high level output signal FBCMP_out1 is output from the feedback comparator 24-1, and a pulse skip is detected. When the pulse skip is detected, control to increase the on-time is performed.

  In the control method of this embodiment, the operation of comparing the output voltage Vout1 with the reference voltage Vref1 is performed at the timing of slot allocation to the channel 1, that is, at the timing t392 when the slot allocation signal φ1 is not supplied. When the output signal FBCMP_out1 of the feedback comparator 24-1 is detected in this comparison operation, control is performed to increase the ON time. That is, in addition to the on-time control based on the presence / absence of pulse skip, it is possible to perform a control for detecting a decrease in the output voltage Vout and adjusting the on-time using the feedback comparator 24-1. For example, the channel selection circuit 44 can arbitrarily select the slot allocation timing at which the drop in the output voltage Vout is detected.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  10 input terminal, 12 PMOS switching transistor, 13 output node, 14 NMOS switching transistor, 22 comparison circuit, 24 feedback comparator, 30 drive circuit, 32 pulse generation circuit, 34 drive circuit, 40 on-time control circuit, 41 pulse skip detection circuit 42 DCM / CCM detection circuit.

Claims (18)

An output terminal connected to the capacitor by turning on a switching transistor connected between an input terminal to which an input voltage is applied and an output node to supply current to the capacitor connected to the output node via an inductor A power supply circuit for obtaining an output voltage from the power supply circuit,
At least one of a detection circuit that outputs an output signal according to a state of a current flowing through the inductor, or a comparison circuit that outputs an output signal according to whether the voltage of the output terminal is higher or lower than a predetermined reference voltage;
A power supply circuit comprising: a control circuit that controls an on-time of the switching transistor in accordance with an output signal of the detection circuit or the comparison circuit at a predetermined timing.   The power supply circuit according to claim 1, wherein the power supply circuit has a plurality of output terminals connected to the inductor in a time division manner.   The power supply circuit according to claim 1, wherein the detection circuit includes a second comparison circuit that compares a voltage of the output node with a predetermined reference voltage.   The power supply circuit according to claim 1, wherein the detection circuit includes a current sensor that detects a direction of a current flowing through the inductor.   The comparison circuit includes a first comparison circuit that compares the voltage at the output terminal with the predetermined reference voltage, and a second comparison that compares the voltage at the output terminal with a second reference voltage different from the reference voltage. The power supply circuit according to claim 1, further comprising a circuit.   The first comparison circuit operates in response to a clock signal having a predetermined frequency, and the second comparison circuit operates in response to a second clock signal having a higher frequency than the clock signal. The power supply circuit according to claim 5.   The control circuit includes both the detection circuit and the comparison circuit, and selects one of the detection circuit and the comparison circuit according to a switching frequency of the switching transistor to control an on-time of the switching transistor. The power supply circuit according to 1. The switching transistor connected between the input terminal to which the input voltage is applied and the output node is turned on, current is supplied to the capacitor connected to the switching transistor via the inductor, and the output connected to the capacitor A method for controlling a power supply circuit that obtains an output voltage from a terminal, the method for controlling the power supply circuit comprising:
A method for controlling a power supply circuit, comprising: detecting a change in a current flowing through the inductor at a predetermined timing; and adjusting an ON time of the switching transistor according to a detection result.   The power supply circuit includes a plurality of output terminals connected to the inductor in a time division manner, and the predetermined timing for detecting a change in the current flowing through the inductor is a timing for switching the output terminal connected to the inductor. The method for controlling a power supply circuit according to claim 8, wherein:   Detection of a change in the current flowing through the inductor is performed by comparing the voltage of the output node with a predetermined reference potential, and when the voltage of the output node is lower than the predetermined reference potential in the detection, 10. The method for controlling a power supply circuit according to claim 8, wherein the on-time of the switching transistor is reduced.   The power supply circuit includes a plurality of output terminals connected to the inductor in a time-sharing manner, and the predetermined timing for detecting a change in the current flowing through the inductor is predetermined than the timing for switching the output terminal connected to the inductor. 9. The method of controlling a power supply circuit according to claim 8, wherein the timing is earlier by time.   The time from the timing when the current change is detected to the control for decreasing the on-time of the switching transistor is shorter than the time from the timing when the current change is detected to the control for increasing the on-time of the switching transistor. The method for controlling a power supply circuit according to any one of claims 8 to 11, wherein: The switching transistor connected between the input terminal to which the input voltage is applied and the output node is turned on, current is supplied to the capacitor connected to the switching transistor via the inductor, and the output connected to the capacitor A method for controlling a power supply circuit that obtains an output voltage from a terminal, the method for controlling the power supply circuit comprising:
A power supply circuit comprising: comparing the output voltage with a predetermined reference voltage in synchronization with a clock signal; and adjusting an ON time of the switching transistor according to a comparison result between the output voltage and the predetermined reference voltage. Control method.   14. The method of controlling a power supply circuit according to claim 13, wherein when a state in which the output voltage is higher than the predetermined reference voltage is continuously detected, an ON time of the switching transistor is decreased.   The power supply circuit includes a plurality of output terminals connected to the inductor in a time division manner, and the output terminals are connected to the inductor in a time division manner by a slot assignment signal having a time width corresponding to one period of the clock signal. 15. The method for controlling a power supply circuit according to claim 13 or 14, wherein:   The method of controlling the power supply circuit according to claim 15, wherein the comparison between the output voltage and the predetermined reference voltage is performed at a timing of switching an output terminal connected to the inductor.   The output voltage is compared with a second reference voltage in synchronization with a high-speed clock signal having a frequency higher than that of the clock signal, and when the output voltage is lower than the second reference voltage, the switching transistor The method for controlling a power supply circuit according to any one of claims 13 to 16, wherein the on-time is increased. Compare the output voltage of the output terminal not connected to the inductor with the predetermined reference voltage,
When the output voltage of the output terminal not connected to the inductor is lower than the predetermined reference voltage, the output terminal is connected to the inductor by the slot assignment signal supplied next. 18. The method for controlling a power supply circuit according to claim 15, wherein control is performed to increase an on time of the switching transistor.

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