JP2015198131A - Method for manufacturing silicon carbide semiconductor device - Google Patents

Abstract

To provide a method for manufacturing a silicon carbide semiconductor device capable of forming an ohmic electrode that exhibits good ohmic characteristics and does not cause peeling.
First, an n ⁻ type drift layer 2 is epitaxially grown on a (000-1) plane of an n ⁺ type silicon carbide substrate 1. Next, a predetermined element structure is formed inside the n ⁻ type drift layer 2. Next, a nickel layer is formed on the (0001) plane of n ⁺ type silicon carbide substrate 1. Next, the ohmic electrode 7 is formed at the interface between the n ⁺ type silicon carbide substrate 1 and the nickel layer by reacting the nickel layer with the n ⁺ type silicon carbide substrate 1 by silicidation by heat treatment. The thickness of the ohmic electrode 7 is 100 nm or more. In the heat treatment for forming the ohmic electrode 7, the peak value of the atomic concentration distribution in the thickness direction of the ohmic electrode 7 of carbon atoms diffused inside the ohmic electrode 7 is set to 51 atm% or more and less than 60 atm%.
[Selection] Figure 4

Description

  The present invention relates to a method for manufacturing a silicon carbide semiconductor device.

  Conventionally, for the purpose of controlling high frequency and high power, the performance of power devices (hereinafter referred to as silicon semiconductor devices) using a semiconductor substrate made of silicon (Si) has been improved. However, since a silicon semiconductor device cannot be used at a high temperature, application of a new semiconductor material is being studied for the demand for a high-performance power device that can be used at a higher temperature.

  Silicon carbide (SiC) is excellent in controllability of electrical conductivity at high temperatures because it has a wide forbidden band that is about three times that of silicon. Silicon carbide is applicable as a substrate material for high breakdown voltage devices because it has a breakdown voltage that is about an order of magnitude higher than that of silicon. Furthermore, since silicon carbide has an electron saturation drift velocity that is about twice that of silicon, it can be applied to devices intended for high-frequency and high-power control.

  The present invention relates to a technology for forming a back electrode of a power device (hereinafter referred to as a silicon carbide semiconductor device) using a semiconductor substrate made of silicon carbide (hereinafter referred to as a silicon carbide substrate). And forming a nickel silicide layer formed by a reaction between the silicon carbide substrate and the nickel film by high-temperature heat treatment to obtain ohmic characteristics at the electrical contact portion (contact) between the silicon carbide substrate and the nickel layer. Are known.

  However, when a nickel silicide layer (hereinafter referred to as an ohmic electrode) is formed as an ohmic contact by this method, surplus carbon atoms (hereinafter referred to as free carbon) released from the silicon carbide substrate on the surface of the ohmic electrode due to the formation of nickel silicide. And by-products containing) are segregated. Due to the by-product containing free carbon, there is a problem that the adhesion with the wiring metal layer formed on the ohmic electrode is lowered, and the wiring metal layer is easily peeled off.

  As a method of solving this problem, a second metal film made of a metal that generates carbide such as titanium, tantalum, or tungsten is formed on a nickel film formed as a first metal film on the surface of a silicon carbide substrate. A method of performing heat treatment has been proposed (see, for example, Patent Document 1 below). In Patent Document 1 below, free carbon generated by the formation of nickel silicide reacts with the second metal film to generate carbide. For this reason, it can prevent that the by-product containing free carbon segregates on the surface of an ohmic electrode, and can prevent that a wiring metal layer peels from an ohmic electrode.

However, in the following Patent Document 1, the effect of preventing the peeling of the wiring metal layer cannot be stably obtained. As a method of solving this problem, a second metal film made of a metal that generates carbide such as titanium, tantalum, or tungsten is formed on a nickel film formed as a first metal film on the surface of a silicon carbide substrate. A method of performing a heat treatment for cleaning the surface of the ohmic electrode by exposing it to oxygen (O ₂ ) plasma or argon (Ar) plasma after forming an ohmic electrode formed by a reaction between the silicon carbide substrate and the nickel film by heat treatment Has been proposed (see, for example, Patent Document 2 below).

JP 2006-344688 A JP 2012-248729 A

  However, by-products containing free carbon generated by the formation of nickel silicide may be segregated not only on the surface of the ohmic electrode but also inside the ohmic electrode. The by-product containing free carbon segregated inside the ohmic electrode causes embrittlement of the film quality of the ohmic electrode and partial peeling of the ohmic electrode. As a result of repeated researches by the inventors, in the techniques of Patent Documents 1 and 2, the by-product containing free carbon segregates inside the ohmic electrode, and suddenly starts from the location where this by-product segregates. It has been found that the ohmic electrode is cracked and the ohmic electrode and the wiring metal layer formed on the ohmic electrode may be peeled off.

  An object of the present invention is to provide a method for manufacturing a silicon carbide semiconductor device capable of forming an ohmic electrode that exhibits good ohmic characteristics and does not cause peeling in order to eliminate the above-described problems caused by the prior art. To do.

  In order to solve the above-described problems and achieve the object of the present invention, a method for manufacturing a silicon carbide semiconductor device according to the present invention has the following characteristics. First, a metal layer forming step of forming a metal layer made of nickel on the surface of a semiconductor substrate made of silicon carbide is performed. Next, a heat treatment step is performed in which the metal layer and the semiconductor substrate are reacted by heat treatment to form an electrode exhibiting ohmic characteristics at the interface between the metal layer and the semiconductor substrate. At this time, the thickness of the electrode is 100 nm or more. In the heat treatment step, the peak value of the atomic concentration distribution in the thickness direction of the electrode of carbon atoms diffused from the semiconductor substrate into the electrode when forming the electrode is set to 51 atm% or more and less than 60 atm%. .

  In the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-described invention, in the heat treatment step, a peak value of an atomic concentration distribution in the thickness direction of the electrode of carbon atoms diffused inside the electrode. Is 55 atm% or more and less than 58 atm%.

  The method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above-described invention, the metal layer is formed on a (0001) plane of the semiconductor substrate in the metal layer forming step.

  The method for manufacturing a silicon carbide semiconductor device according to the present invention further has the following features in the above-described invention. In the metal layer forming step, first, a step of forming a first metal layer made of nickel on the surface of the semiconductor substrate is performed. Next, the first metal layer and the second metal layer are formed by forming a second metal layer made of one or more of molybdenum, tantalum, titanium, and chromium on the surface of the first metal layer. Are formed in order to form the metal layer.

  According to the method for manufacturing a silicon carbide semiconductor device according to the present invention, it is possible to form a good ohmic electrode having a low contact resistance, and to prevent the free carbon from increasing on the surface and inside of the ohmic electrode. Generation or segregation of by-products containing free carbon on the surface and inside of the substrate can be suppressed. For this reason, there exists an effect that the ohmic electrode which shows a favorable ohmic characteristic and does not produce peeling can be formed.

It is sectional drawing which shows the state in the middle of manufacture of the silicon carbide semiconductor device concerning Embodiment 1. FIG. It is sectional drawing which shows the state in the middle of manufacture of the silicon carbide semiconductor device concerning Embodiment 1. FIG. It is sectional drawing which shows the state in the middle of manufacture of the silicon carbide semiconductor device concerning Embodiment 1. FIG. It is sectional drawing which shows the state in the middle of manufacture of the silicon carbide semiconductor device concerning Embodiment 1. FIG. It is sectional drawing which shows the state in the middle of manufacture of the silicon carbide semiconductor device concerning Embodiment 1. FIG. It is sectional drawing which shows the state in the middle of manufacture of the silicon carbide semiconductor device concerning Embodiment 1. FIG. FIG. 6 is a characteristic diagram showing a relationship between a forward voltage and a thickness of an ohmic electrode of a silicon carbide semiconductor device manufactured by the method for manufacturing a silicon carbide semiconductor device according to the first embodiment.

  Exemplary embodiments of a method for manufacturing a silicon carbide semiconductor device according to the present invention will be described below in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + and − attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region where it is not attached. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted. Also, in this specification, in the Miller index notation, “−” means a bar attached to the index immediately after that, and “−” is added before the index to indicate a negative index.

(Embodiment 1)
A method for manufacturing a silicon carbide semiconductor device according to the first embodiment will be described by taking as an example the case of manufacturing (manufacturing) a Schottky Barrier Diode (SBD). FIGS. 1-6 is sectional drawing which shows the state in the middle of manufacture of the silicon carbide semiconductor device concerning Embodiment 1. FIGS. FIGS. 1-6 shows the state in the middle of manufacture of the area | region used as one effective chip among the several semiconductor chips built on one silicon carbide wafer. First, as shown in FIG. 1, an n ⁻ type drift layer 2 is formed on the front surface of an n ⁺ type silicon carbide substrate (silicon carbide wafer) 1 made of, for example, silicon carbide four-layer periodic hexagonal crystal (4H—SiC). A silicon carbide epitaxial layer is deposited.

the front surface of the n ⁺ -type silicon carbide substrate 1 may be, for example, n ⁺ -type silicon carbide substrate 1 (000-1) plane (the so-called C plane). The n ⁺ -type (000) plane of silicon carbide substrate 1, the carbon atom tends to precipitate as compared with the crystal plane having other plane orientations. For this reason, in Embodiment 1, for example, the front surface of the substrate on which an ohmic electrode to be described later is not formed is the (000-1) surface. The n ⁺ type silicon carbide substrate 1 is doped with nitrogen (N) at an impurity concentration of 1.0 × 10 ¹⁸ / cm ³ , for example. The thickness of n ⁺ type silicon carbide substrate 1 may be 350 μm, for example. The n ⁻ type drift layer 2 is doped with nitrogen at an impurity concentration of, for example, 1.8 × 10 ¹⁶ / cm ³ . The thickness of the n ⁻ type drift layer 2 may be 6 μm, for example.

Next, as shown in FIG. 2, the surface layer of the n ⁻ type drift layer 2 opposite to the n ⁺ type silicon carbide substrate 1 side is implanted by ion implantation of an n type impurity such as phosphorus (P). The n-type region 3 for channel stopper is selectively formed. The n-type region 3 is disposed so as to surround the active region at a termination structure portion surrounding the active region. Next, as shown in FIG. 3, the n ⁻ type drift layer 2 is opposite to the n ⁺ type silicon carbide substrate 1 side in the termination structure by ion implantation of a p-type impurity such as aluminum (Al). A p-type region 4 for a termination structure and one or more p-type regions 5 having a floating potential for an FLR (Field Limiting Ring) structure are selectively formed in the surface layer on the side.

The active region is a region through which current flows in the on state. The termination structure is a region that relaxes the electric field of the n ⁻ -type drift layer 2 and maintains a withstand voltage. The p-type region 4 is disposed in the vicinity of the boundary between the active region and the termination structure portion so as to extend from the active region to the termination structure portion and surround the active region. The p-type region 5 is arranged between the n-type region 3 and the p-type region 4 and separated from the n-type region 3 and the p-type region 4. The p-type region 5 is arranged so as to surround the active region (that is, so as to surround the p-type region 4, and inside the p-type region 4 and itself when a plurality of p-type regions 5 are arranged. Arranged so as to surround the p-type region 5). Next, the impurities implanted to form the n-type region 3 and the p-type regions 4 and 5 are activated by, for example, a heat treatment for 240 seconds at a temperature of 1650 ° C. in an argon (Ar) gas atmosphere.

Next, as shown in FIG. 4, for example, the surface of n ⁻ type drift layer 2 opposite to the n ⁺ type silicon carbide substrate 1 side is thermally oxidized by a heat treatment at a temperature of 1100 ° C., for example, and field oxide film 6 Form. Next, a silicon carbide epitaxial substrate (silicon carbide epitaxial wafer) composed of n ⁺ type silicon carbide substrate 1 and n ⁻ type drift layer 2 is inserted into a processing furnace (chamber) of a sputtering apparatus, for example, and the substrate temperature is maintained at 250 ° C. To do. In this state, by performing magnetron sputtering in an argon gas atmosphere at a pressure of 0.2 Pa, n ⁺ -type silicon carbide substrate 1 (0001) plane, that is, the back surface of the n ⁺ -type silicon carbide substrate 1, for example, 100nm approximately For example, a nickel (Ni) layer of a thickness is deposited.

Next, the silicon carbide epitaxial substrate on which the nickel layer is deposited is inserted into a reaction furnace of, for example, a rapid thermal annealing (RTA) apparatus, and the silicon carbide epitaxial substrate (entire element) is heated. At this time, for example, the heating temperature of the silicon carbide epitaxial substrate is raised until it reaches 1100 ° C. at a heating rate of 1 ° C./second, and then held at that temperature for 2 minutes. By this heat treatment, the nickel layer reacts with the n ⁺ type silicon carbide substrate 1 to be silicided, and low resistance nickel that exhibits ohmic characteristics at the electrical contact portion (contact) between the n ⁺ type silicon carbide substrate 1 and the nickel layer. A silicide layer (hereinafter referred to as an ohmic electrode) 7 is formed. FIG. 4 shows a case where the entire nickel layer becomes a nickel silicide layer. The peak value of the atomic concentration distribution of the carbon atoms diffused inside the ohmic electrode 7 in the thickness direction of the ohmic electrode 7 (hereinafter referred to as the peak atomic concentration of carbon atoms in the ohmic electrode 7) is, for example, less than 60 atm%. And

Next, the silicon carbide epitaxial substrate in which the ohmic electrode 7 is formed is inserted into, for example, a processing furnace of a sputtering apparatus. Then, 200 W of high frequency (RF: Radio Frequency) power is applied to the silicon carbide epitaxial substrate, and reverse sputtering (cleaning treatment) is performed in an oxygen (O ₂ ) gas atmosphere or an argon gas atmosphere at a pressure of 0.3 Pa. As a result, the surface of the ohmic electrode 7 is cleaned by being exposed to oxygen plasma or argon plasma. Next, the field oxide film 6 is selectively removed by photolithography and etching to expose a portion of the n ⁻ type drift layer 2 corresponding to the active region. Next, for example, a titanium (Ti) layer is deposited on the surface of the n ⁻ -type drift layer 2 exposed at the opening of the field oxide film 6 by, for example, vapor deposition.

Next, the silicon carbide epitaxial substrate on which the titanium layer is deposited is inserted into, for example, a reactor of an RTA apparatus, and the silicon carbide epitaxial substrate (entire element) is heated. At this time, the heating temperature of the silicon carbide epitaxial substrate is raised to, for example, 500 ° C. at a heating rate of 8 ° C./second, and then held for 5 minutes. By this heat treatment, Schottky electrode 8 made of a titanium layer is formed on the surface of n ⁻ type drift layer 2. Schottky electrode 8 is arranged so as to extend from the surface of n ⁻ type drift layer 2 to the surface of p type region 4 in order to operate the Schottky barrier diode as a high breakdown voltage element. That is, the end of Schottky electrode 8 is located on the surface of p-type region 4.

  Next, as shown in FIG. 5, a bonding electrode pad 9 made of, for example, aluminum-silicon (Al—Si) is formed to a thickness of 5 μm so as to contact the Schottky electrode 8. Next, a passivation film 10 made of, for example, polyimide is formed from the surface of the field oxide film 6 to the end of the electrode pad 9. Next, as shown in FIG. 6, a wiring metal layer 11 for connection to an external device is formed on the surface of the ohmic electrode 7. The wiring metal layer 11 is formed, for example, by sequentially depositing a titanium layer having a thickness of 70 nm, a nickel layer having a thickness of 400 nm, and a gold (Au) layer having a thickness of 200 nm. Thereafter, the semiconductor chip according to the first embodiment is completed by cutting (dicing) the semiconductor chips formed on the silicon carbide epitaxial substrate (silicon carbide epitaxial wafer) into individual chips.

  Next, a method for suppressing the peak atom concentration of carbon atoms in the ohmic electrode 7 will be described. By balancing the material and thickness of the ohmic electrode 7 and the heat treatment conditions for forming the ohmic electrode 7, the peak atom concentration of carbon atoms in the ohmic electrode 7 can be suppressed to less than 60 atm%. This has been confirmed by the present inventors. The heat treatment conditions for forming the ohmic electrode 7 and the material and thickness of the ohmic electrode 7 influence each other. For this reason, for example, even if only the thickness of the ohmic electrode 7 is limited, the peeling of the wiring metal layer 11 cannot be sufficiently suppressed. In addition, the peak atoms of carbon atoms in the ohmic electrode 7 are adjusted by adjusting the heat treatment conditions. It is important to control the concentration range.

  Further, as another method for suppressing the peak atom concentration of carbon atoms in the ohmic electrode 7, for example, by increasing the heat treatment temperature for forming the ohmic electrode 7 and lengthening the heat treatment time, it is released from the silicon carbide epitaxial substrate. There is a method for easily diffusing the surplus carbon atoms (free carbon), but in this case, the peak atom concentration of the carbon atoms in the ohmic electrode 7 may be too low. Lowering the peak atomic concentration of carbon atoms in the ohmic electrode 7 means that free carbon diffusing to the outside of the ohmic electrode 7 is increased, and free carbon deposited on the surface of the ohmic electrode 7 is greatly increased. Will do. For example, when the peak atomic concentration of carbon atoms in the ohmic electrode 7 is less than 51 atm%, even if the surface of the ohmic electrode 7 is cleaned by exposure to oxygen plasma or argon plasma, the ohmic electrode 7 and the wiring metal layer It has been confirmed by the inventors that this results in facilitating the peeling of 11. Therefore, by balancing the material and thickness of the ohmic electrode 7 and the heat treatment conditions for forming the ohmic electrode 7, the peak atomic concentration of carbon atoms in the ohmic electrode 7 is within a range of 51 atm% or more and less than 60 atm%. It is better to control. Preferably, the peak atom concentration of carbon atoms in the ohmic electrode 7 is controlled within the range of 55 atm% or more and less than 58 atm%.

  The thickness of the ohmic electrode 7 is preferably 100 nm or more. The reason is as follows. FIG. 7 is a characteristic diagram showing the relationship between the forward voltage and the ohmic electrode thickness of the silicon carbide semiconductor device manufactured by the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. The thickness of the ohmic electrode 7 is preferably not less than a certain thickness in order to reduce the contact resistance. As shown in FIG. 7, as a result of measuring the forward voltage (ON voltage) Vf of the Schottky barrier diode manufactured by variously changing the thickness of the ohmic electrode 7, the thickness of the ohmic electrode 7 is 100 nm or more. In this case, it was confirmed that the forward voltage Vf becomes small and a good contact resistance value is obtained. In FIG. 7, the voltage characteristic changes when the ohmic electrode 7 has a thickness of 100 nm, and the voltage characteristics are good when the ohmic electrode 7 has a thickness of 100 nm or more.

  Moreover, when the thickness of the ohmic electrode 7 is too thick, free carbon is locally unevenly distributed inside the ohmic electrode 7 and the ohmic electrode 7 is peeled off. Specifically, when the thickness of the ohmic electrode 7 is 300 nm at which the contact resistance does not change, a part of the ohmic electrode 7 and the wiring metal layer 11 are likely to be peeled off from a predetermined position inside the ohmic electrode 7. It has been confirmed by the inventors that there is a tendency. Therefore, preferably, the thickness of the ohmic electrode 7 is low in contact resistance, exhibits good ohmic characteristics, and prevents the ohmic electrode 7 and the wiring metal layer 11 from peeling in consideration of preventing the occurrence of peeling due to manufacturing variations. It is good that it is 105 nm or more and 280 nm or less, which can be hardly generated. More preferably, the thickness of the ohmic electrode 7 is 110 nm or more and 150 nm or less so that the above effect can be obtained more stably.

(Example)
In accordance with the method for manufacturing the silicon carbide semiconductor device according to the first embodiment described above, a Schottky barrier diode was produced in each effective chip region of the silicon carbide wafer (silicon carbide epitaxial wafer) under the above-described various conditions (hereinafter, referred to as the following). Example). And the peak atom concentration of the carbon atom in three places in the ohmic electrode 7 was measured in the Example by the profile analysis of the depth direction by an Auger Electron Spectroscopy (AES: Auger Electron Spectroscopy) method, respectively. As a result, in the examples, the peak atomic concentrations of carbon atoms at three locations in the ohmic electrode 7 are 56.8 atm%, 57.3 atm%, and 57.1 atm%, respectively, and the average is 57.1 atm%. Was confirmed.

(Comparative example)
For comparison, a Schottky barrier diode in which the ohmic electrode 7 was formed in each effective chip region of the silicon carbide wafer under the heat treatment conditions different from those of the example was prepared (hereinafter referred to as a comparative example). In the comparative example, in order to form the ohmic electrode 7, the heating temperature of the comparative example was raised until reaching 1000 ° C. at a heating rate of 1.5 ° C./second, and then held at that temperature for 3 minutes. . The manufacturing method of the comparative example other than the heat treatment conditions for forming the ohmic electrode 7 is the same as that of the example. In the comparative example, the peak atom concentrations of carbon atoms at three locations in the ohmic electrode 7 measured by the same method as in the examples are 61.0 atm%, 61.7 atm%, and 61.8 atm%, respectively, and the average is 61 0.5 atm%.

(Verification 1)
In the above-described examples and comparative examples, each semiconductor chip formed on a silicon carbide wafer was cut into individual chips, and each 100 semiconductor chips were arbitrarily picked up. In both the example and the comparative example, out of the 100 semiconductor chips picked up, the ratio of the number of semiconductor chips where the wiring metal layer 11 is peeled off the ohmic electrode 7 and the area ratio of the peeling portion of the wiring metal layer 11 And measured. The area ratio of the peeling portion of the wiring metal layer 11 is the area ratio of the peeling portion of the wiring metal layer 11 to the total area of the wiring metal layer 11 for each semiconductor chip where the peeling of the wiring metal layer 11 occurs (= wiring metal). The area of the peeled portion of the layer 11 / the total area of the wiring metal layer 11).

  Thus, as a result of verifying the presence or absence of peeling of the wiring metal layer 11 for each semiconductor chip, there was no semiconductor chip in which the entire surface of the wiring metal layer 11 was peeled off when the semiconductor chip was picked up in both the examples and the comparative examples. In both the example and the comparative example, the part where the wiring metal layer 11 was peeled was around the dicing line. However, in the comparative example, the wiring metal layer 11 was peeled off by 23 semiconductor chips out of 100 semiconductor chips. In the 23 semiconductor chips in which the wiring metal layer 11 was peeled off, the area ratio of the peeling portions of the wiring metal layer 11 of each semiconductor chip was in the range of 2% to 10% of the total area of the wiring metal layer 11. It was distributed in.

  On the other hand, in the example, the wiring metal layer 11 was peeled off by three semiconductor chips out of 100 semiconductor chips. However, in the three semiconductor chips where the wiring metal layer 11 was peeled off, It was confirmed that the area ratio of the peeled portion of the wiring metal layer 11 of each semiconductor chip was smaller than that of the comparative example and was within 2% of the total area of the wiring metal layer 11.

(Verification 2)
Next, in all of the semiconductor chips in which the wiring metal layer 11 was peeled off in both the examples and the comparative examples, the portions where the wiring metal layer 11 was peeled off were observed in detail with an optical microscope. As a result, in the comparative example, it was confirmed that the wiring metal layer 11 was peeled off at the following three locations. The first location is the interface between the ohmic electrode 7 and the wiring metal layer 11. The second location is inside the ohmic electrode 7. That is, the wiring metal layer 11 is peeled off together with a part of the ohmic electrode 7 which is the lower layer of the wiring metal layer 11. The third portion is, for example, a chip end portion resulting from chip chipping (chipping) during dicing. That is, the wiring metal layer 11 is missing together with the chip.

  Of the 23 semiconductor chips in which the wiring metal layer 11 has been peeled off, the number of semiconductor chips in which the wiring metal layer 11 has been peeled off in the first to third locations is as follows. The separation of the wiring metal layer 11 at the first location was confirmed with seven semiconductor chips. The peeling of the wiring metal layer 11 at the second location was confirmed with 12 semiconductor chips. The peeling of the wiring metal layer 11 at the third location was confirmed with four semiconductor chips. In the comparative example, since the peak atomic concentration of carbon atoms in the ohmic electrode 7 is 60 atm% or more (see Verification 1), the first location or the second location is caused by free carbon on the surface or inside of the ohmic electrode 7. Separation of the wiring metal layer 11 occurs at a location.

  On the other hand, in the example, in all the three semiconductor chips, the wiring metal layer 11 was peeled off at the chip end due to chip chipping during dicing, and in the first and second locations as in the comparative example. The wiring metal layer 11 was not peeled off. Thus, by setting the peak atom concentration of carbon atoms in the ohmic electrode 7 to less than 60 atm% (see Verification 1), the first location or the above-mentioned first cause caused by free carbon segregating on the surface or inside of the ohmic electrode 7 or It was confirmed that no peeling of the wiring metal layer 11 occurred at the second location.

  In addition, the heat treatment conditions for forming the ohmic electrode 7 are different between the example and the comparative example. However, as described in the verifications 1 and 2, the effect of the present invention is obtained only in the example. Different verification results were obtained. Therefore, the factors involved in setting the heat treatment conditions for forming the ohmic electrode 7, that is, the material and thickness of the ohmic electrode 7 and the heat treatment conditions for forming the ohmic electrode 7 should be balanced. Thus, it can be seen that the peak atom concentration of carbon atoms in the ohmic electrode 7 can be made less than 60 atm%.

  As described above, according to the first embodiment, the peak atomic concentration of carbon atoms in the ohmic electrode is made less than 60 atm%, so that when the ohmic electrode is formed, it is released on the surface and inside of the ohmic electrode. An increase in carbon can be prevented. Thereby, generation or segregation of by-products containing free carbon on the surface and inside of the ohmic electrode can be prevented, and embrittlement and peeling of the ohmic electrode can be prevented. Further, according to the first embodiment, by setting the thickness of the ohmic electrode 7 to 100 nm or more, a good ohmic electrode having a low contact resistance can be formed. Accordingly, it is possible to form an ohmic electrode that exhibits good ohmic characteristics and does not cause peeling.

(Embodiment 2)
Next, a method for manufacturing the semiconductor device according to the second embodiment will be described. The semiconductor device manufacturing method according to the second embodiment is different from the semiconductor device manufacturing method according to the first embodiment in that a nickel layer formed as a first metal layer on the back surface of the n ⁺ -type silicon carbide substrate 1, The ohmic electrode 7 is formed by silicidizing a laminated film including a second metal layer formed using an electrode material different from the first metal layer on the first metal layer. The second metal layer may be, for example, a metal layer made of molybdenum (Mo), tantalum (Ta), titanium, or chromium (Cr), or a metal compound layer containing one or more of these metals.

In the second embodiment, the heat treatment, the nickel atoms in the first metal layer (nickel layer) is bonded to the silicon atoms of the n ⁺ -type silicon carbide substrate 1 (reaction between nickel layer and the n ⁺ -type silicon carbide substrate 1 As in the first embodiment, the ohmic electrode 7 made of nickel silicide is formed. At this time, surplus carbon atoms (free carbon) liberated from the n ⁺ -type silicon carbide substrate 1 diffuse into the ohmic electrode 7, and the carbon atoms diffused into the ohmic electrode 7 are separated from the metal atoms in the second metal layer. Combined to form metal carbide. That is, free carbon in the ohmic electrode 7 can be reduced by forming the ohmic electrode 7 by siliciding a laminated film in which the first metal layer and the second metal layer are sequentially laminated. Thereby, embrittlement and peeling of the ohmic electrode 7 can be prevented more reliably.

  As described above, according to the second embodiment, the same effect as in the first embodiment can be obtained.

  As described above, the present invention can be variously changed. In each of the above-described embodiments, for example, the dimensions and surface concentration of each part are variously set according to required specifications. Further, in each of the above-described embodiments, a case where a silicon carbide epitaxial substrate in which a silicon carbide epitaxial layer is deposited on a silicon carbide substrate is described as an example. However, the present invention is not limited to this. For example, a device is configured. All the regions may be ion-implanted regions formed inside the silicon carbide substrate. In each of the above-described embodiments, the case where the (000-1) plane of the silicon carbide substrate is used as the front surface is described as an example. However, the (0001) plane of the silicon carbide substrate is used as the front surface. It may be a surface. Further, in each of the above-described embodiments, the case where the ohmic electrode is formed by furnace annealing is described as an example. However, the present invention is not limited to this. For example, the ohmic electrode is formed by laser annealing, lamp annealing, or induction heating. Also good.

  In each of the above-described embodiments, a case where a Schottky barrier diode is manufactured is described as an example. However, the present invention is not limited to this, and a MOSFET (Metal Oxide Field Effect Transistor) or an insulated gate field effect transistor is used. IGBT (Insulated Gate Bipolar Transistor) can be manufactured. That is, the present invention is applicable also when an ohmic electrode is formed on the front surface of a silicon carbide substrate. Further, the present invention is similarly established even when the conductivity type is reversed.

  As described above, the method for manufacturing a silicon carbide semiconductor device according to the present invention is useful for a semiconductor device having an ohmic electrode on the surface of a silicon carbide substrate, and in particular, a power semiconductor having an ohmic electrode on the back surface of the silicon carbide substrate. Suitable for equipment.

1 n ⁺ type silicon carbide substrate 2 n ⁻ type drift layer 3 n type region for channel stopper 4 p type region for termination structure 5 p type region for FLR structure 6 field oxide film 7 ohmic electrode 8 Schottky electrode 9 electrode Pad 10 Passivation film 11 Wiring metal layer

Claims (4)

A metal layer forming step of forming a metal layer made of nickel on the surface of a semiconductor substrate made of silicon carbide;
A heat treatment step of reacting the metal layer with the semiconductor substrate by heat treatment to form an electrode exhibiting ohmic characteristics at an interface between the metal layer and the semiconductor substrate;
Including
The electrode has a thickness of 100 nm or more;
In the heat treatment step, the peak value of the atomic concentration distribution in the thickness direction of the electrode of carbon atoms diffused from the semiconductor substrate into the electrode when forming the electrode is set to 51 atm% or more and less than 60 atm%. A method for manufacturing a silicon carbide semiconductor device.   2. The peak value of the atomic concentration distribution in the thickness direction of the electrode of carbon atoms diffused inside the electrode is set to 55 atm% or more and less than 58 atm% in the heat treatment step. A method for manufacturing a silicon carbide semiconductor device.   3. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein in the metal layer forming step, the metal layer is formed on a (0001) plane of the semiconductor substrate. The metal layer forming step includes
Forming a first metal layer made of nickel on a surface of the semiconductor substrate;
Forming a second metal layer made of at least one of molybdenum, tantalum, titanium, and chromium on the surface of the first metal layer, and the first metal layer and the second metal layer The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the metal layer is formed by sequentially depositing layers.

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