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JP2014187137A - Method for producing electronic device - Google Patents

Method for producing electronic device Download PDF

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JP2014187137A
JP2014187137A JP2013060324A JP2013060324A JP2014187137A JP 2014187137 A JP2014187137 A JP 2014187137A JP 2013060324 A JP2013060324 A JP 2013060324A JP 2013060324 A JP2013060324 A JP 2013060324A JP 2014187137 A JP2014187137 A JP 2014187137A
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wire
solder
plating layer
soldering
heating
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JP6011408B2 (en
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Hiroshi Kasugai
浩 春日井
Yasuo Yamamoto
康雄 山本
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Denso Corp
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Denso Corp
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    • H01L24/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
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  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent the separation of wire due to heating after wire bonding as much as possible in a method for producing an electronic device which is formed by wire-bonding and soldering to a power chip provided with a wire pad composed of an Au-plated layer on an undercoat whose surface is a Ni-plated layer and a solder land for soldering.SOLUTION: The method for producing an electronic device comprises a soldering step of soldering a terminal 50, a wire-bonding step of joining a wire 40 to a wire pad 21 thereafter, a heating step of heating a power chip 20 thereafter. Then, a Ni diffusion step in which Ni is diffused from a Ni-plated layer 211 to the surface of an Au-plated layer 212 in the wire pad 21 is carried out by heating the prepared power chip 20 before the soldering step.

Description

本発明は、ワイヤパッドとはんだランドとを両備する電子部品を有する電子装置の製造方法に関する。   The present invention relates to a method for manufacturing an electronic device having an electronic component having both wire pads and solder lands.

従来、一般に、ワイヤボンディング用のワイヤパッドを有する電子部品と、当該ワイヤパッド上にワイヤボンディングされたアルミニウムよりなるワイヤとを備える電子装置が知られている。ここで、ワイヤパッドは、通常、表面がNiめっき層を下地とするAuめっき層、すなわちNi/Auめっき層よりなる。   2. Description of the Related Art Conventionally, an electronic device is generally known that includes an electronic component having a wire pad for wire bonding and a wire made of aluminum wire-bonded on the wire pad. Here, the wire pad is usually composed of an Au plating layer whose surface is a Ni plating layer, that is, a Ni / Au plating layer.

このようなものにおいては、ワイヤボンディング後の電子装置には、たとえば、更なる他部品の接続やモールド封止前の密着性付与剤の塗布、乾燥等のための加熱が、後工程として行われるのが通常である。   In such a case, for the electronic device after wire bonding, for example, heating for further connection of other components, application of an adhesion imparting agent before mold sealing, drying, etc. is performed as a post-process. It is normal.

そのため、たとえば特許文献1に記載のように、Auめっき層が厚いと(たとえば500nm以上)、当該加熱工程によって電子部品が高温となり(たとえば150℃以上)、Auめっき層中にボイドが発生し、ボンディングワイヤの剥がれが生じやすいことが知られている。   Therefore, for example, as described in Patent Document 1, when the Au plating layer is thick (for example, 500 nm or more), the electronic component becomes high temperature (for example, 150 ° C. or more) by the heating process, and voids are generated in the Au plating layer. It is known that the bonding wire is easily peeled off.

特開2003−59962号公報JP 2003-59962 A

これに対して、本発明者は、Auめっき層をたとえば20nm〜50nmと薄くすることで当該Auめっき層中のボイド発生を抑制できることを実験的に確認した。   On the other hand, this inventor confirmed experimentally that the void generation | occurrence | production in the said Au plating layer can be suppressed by making Au plating layer thin, for example with 20 nm-50 nm.

さらに、本発明者は、電子部品がワイヤパッドに追加して、さらにSnを含むはんだによるはんだ付け用のはんだランドを有する構成である場合について、検討を行った。以下、この構成を、「ワイヤ−はんだ両備構成」ということにする。   Furthermore, the present inventor has studied the case where the electronic component has a configuration in which a solder land for soldering with a solder containing Sn is further added to the wire pad. Hereinafter, this configuration is referred to as a “wire-solder dual configuration”.

このワイヤ−はんだ両備構成は、通常、はんだ付けを行った後、ワイヤボンディングを行うことで形成される。そして、本発明者の検討の結果、この場合においては、Auめっき層を薄くしても、上記した電子装置への加熱によって、ワイヤの剥がれが発生することがわかった。   This wire-solder dual arrangement is usually formed by performing wire bonding after soldering. As a result of the study by the present inventor, in this case, it was found that even if the Au plating layer was made thin, peeling of the wire occurred due to heating to the electronic device described above.

本発明は、上記問題に鑑みてなされたものであり、表面がNiめっき層を下地とするAuめっき層よりなるワイヤパッドとはんだ付け用のはんだランドとを備える電子部品に、ワイヤボンディングおよびはんだ付けを行って形成される電子装置の製造方法において、ワイヤボンディング後の加熱によるワイヤ剥がれを極力防止することを目的とする。   The present invention has been made in view of the above problems, and wire bonding and soldering are performed on an electronic component including a wire pad made of an Au plating layer whose surface is a Ni plating layer and a solder land for soldering. In the manufacturing method of the electronic device formed by performing the above, the object is to prevent wire peeling due to heating after wire bonding as much as possible.

上記目的を達成するため、本発明者は、鋭意検討を行い、ワイヤ−はんだ両備構成の電子装置におけるワイヤ剥がれの発生メカニズムを、以下のように推定した。この推定メカニズムについて、図7を参照して述べる。図7では、表面がNiめっき層211を下地とするAuめっき層212よりなるワイヤパッド21の概略断面が示されている。   In order to achieve the above object, the present inventor has intensively studied and estimated the occurrence mechanism of the wire peeling in the electronic device having both the wire-solder configuration as follows. This estimation mechanism will be described with reference to FIG. FIG. 7 shows a schematic cross section of the wire pad 21 whose surface is made of the Au plating layer 212 with the Ni plating layer 211 as a base.

まず、ワイヤボンディング前に、電子部品上の図示しないはんだランドに対してSnを含むはんだによって、はんだ付けを行う。すると、図7(a)、(b)に示されるように、当該はんだのリフローによって、電子部品上のはんだからワイヤパッド21上に、Sn1(図中では点ハッチングの丸で示す)が、飛散してAuめっき層212表面に付着する。   First, before wire bonding, a solder land (not shown) on the electronic component is soldered with solder containing Sn. Then, as shown in FIGS. 7A and 7B, Sn1 (indicated by a dot-hatched circle in the figure) is scattered from the solder on the electronic component onto the wire pad 21 by the reflow of the solder. Then, it adheres to the surface of the Au plating layer 212.

また、はんだリフローの熱によって、このSn1がAuめっき層212内に拡散し、下地のNiめっき層211から拡散してくるNiと反応し、図7(c)に示されるように、Auめっき層212内にてSn−Ni合金(たとえばNiSn、図中では片側斜線ハッチングの丸で示す)2を形成する。 Further, this Sn1 diffuses into the Au plating layer 212 due to the heat of the solder reflow, reacts with Ni diffused from the underlying Ni plating layer 211, and as shown in FIG. 7C, the Au plating layer An Sn—Ni alloy (for example, Ni 3 Sn, indicated by a hatched circle on one side in the figure) 2 is formed in 212.

そして、この状態のワイヤパッド21に対して、ワイヤボンディングを行うことにより、図7(d)に示されるように、Auめっき層212上にAlよりなるワイヤ40が接続される。このワイヤボンディング後、電子装置に対して、上記した後工程としての加熱が施される。   Then, by performing wire bonding to the wire pad 21 in this state, the wire 40 made of Al is connected on the Au plating layer 212 as shown in FIG. After the wire bonding, the electronic device is heated as a post-process described above.

このとき当該加熱工程では、図7(e)、(f)に示されるように、ワイヤパッド21においてAuめっき層212のAuとワイヤ40のAlとで相互拡散が起こり、Niめっき層211とワイヤ40との間にAu−Al合金層213が形成され、薄いAuめっき層212は実質的に消滅していく。   At this time, in the heating step, as shown in FIGS. 7E and 7F, mutual diffusion occurs between the Au of the Au plating layer 212 and the Al of the wire 40 in the wire pad 21, and the Ni plating layer 211 and the wire 40, the Au—Al alloy layer 213 is formed, and the thin Au plating layer 212 substantially disappears.

しかし、このAu−Al合金層213の形成において、Auめっき層212内にSn−Ni合金2が存在すると、Auの拡散がSi−Ni合金2に邪魔されて、Sn−Ni合金2の存在部分では拡散が遅く、存在しない部分では拡散が速くなることから、Auの拡散速度が不均一となる。そのため、図7(e)、(f)に示されるように、ワイヤパッド21内にて、Sn−Ni合金2の部分でボイドBが生じる。   However, in the formation of the Au—Al alloy layer 213, if the Sn—Ni alloy 2 exists in the Au plating layer 212, the diffusion of Au is obstructed by the Si—Ni alloy 2, and the existing portion of the Sn—Ni alloy 2 is present. In this case, the diffusion is slow and the diffusion is fast in the non-existing portion, so that the diffusion rate of Au becomes non-uniform. Therefore, as shown in FIGS. 7E and 7F, void B is generated in the portion of the Sn—Ni alloy 2 in the wire pad 21.

そのため、ワイヤパッド21においては、このボイドBの部分で強度が低下し、これによってワイヤ40の剥離が発生しやすくなる。以上が、本発明者の検討による推定メカニズムである。これについては、顕微鏡観察や元素分析等により確認している。   Therefore, the strength of the wire pad 21 is reduced at the void B portion, and the wire 40 is easily peeled off. The above is the presumed mechanism by examination of this inventor. This is confirmed by microscopic observation and elemental analysis.

そこで、このメカニズムに鑑み、本発明者は、このはんだリフロー時において、ワイヤパッドのAuめっき層表面に付着したSnが、Auめっき層内に拡散するのを抑制してやれば、Auめっき層内においてSn−Ni合金が形成されるのを極力防止できると考えた。本発明は、この点に着目して創出されたものである。   Therefore, in view of this mechanism, the present inventor can prevent Sn adhering to the Au plating layer surface of the wire pad from diffusing into the Au plating layer at the time of the solder reflow. It was thought that the formation of the Ni alloy could be prevented as much as possible. The present invention has been created by focusing on this point.

すなわち、請求項1に記載の発明では、ワイヤボンド用のワイヤパッド(21)およびはんだ付け用のはんだランド(22)を有する電子部品(20)と、ワイヤパッドにワイヤボンディングされたアルミニウムよりなるワイヤ(40)と、はんだランドにSnを含むはんだ(70)を介してはんだ付けされた接合部材(50)と、を備える電子装置の製造方法であって、
電子部品として、ワイヤパッドの表面が、Niめっき層(211)を下地とするAuめっき層(212)よりなるものを用意する用意工程と、はんだランドにはんだを配置し、はんだ上に接合部材を搭載した状態ではんだをリフローさせることにより、接合部材をはんだ付けするはんだ付け工程と、はんだ付け工程の後、ワイヤボンディングを行ってワイヤパッドにワイヤを接合するワイヤボンディング工程と、ワイヤボンディング工程の後、電子部品を加熱する加熱工程と、を備え、
はんだ付け工程の前に、用意された電子部品を加熱することにより、ワイヤパッドにおいてAuめっき層の表面にNiめっき層からNiを拡散させるNi拡散工程を行うことを特徴とする。
That is, according to the first aspect of the present invention, an electronic component (20) having a wire pad (21) for wire bonding and a solder land (22) for soldering, and a wire made of aluminum wire-bonded to the wire pad (40) and a joining member (50) soldered to a solder land via a solder (70) containing Sn,
As an electronic component, a preparation process for preparing the surface of the wire pad consisting of an Au plating layer (212) with the Ni plating layer (211) as a base, solder is disposed on the solder land, and a joining member is provided on the solder After reflowing the solder in the mounted state, a soldering process for soldering the joining member, a wire bonding process for bonding the wire to the wire pad by performing wire bonding after the soldering process, and after the wire bonding process A heating process for heating the electronic component,
Before the soldering step, the prepared electronic component is heated to perform a Ni diffusion step of diffusing Ni from the Ni plating layer on the surface of the Au plating layer in the wire pad.

それによれば、Ni拡散工程によって、はんだリフロー前に予め、Auめっき層表面にNiが拡散されるから、はんだリフロー時にAuめっき層表面にSn(1)が付着しても、このSnのAuめっき層内への拡散は、同じ表面に存在するNi(3)によって阻害される。   According to this, since Ni is diffused in advance on the surface of the Au plating layer by the Ni diffusion step before the solder reflow, even if Sn (1) adheres to the surface of the Au plating layer during the solder reflow, the Au plating of this Sn Diffusion into the layer is inhibited by Ni (3) present on the same surface.

そのため、Auめっき層内にてSn−Ni合金(2)の形成が抑制されるので、ワイヤボンディング後に加熱されることでNiめっき層とAlワイヤとの間にAu−Al合金層(213)が形成されても、ワイヤパッド内におけるボイド(B)の発生を抑制できる。よって、本発明によれば、ワイヤボンディング後の加熱によるワイヤ剥がれを極力防止することができる。   Therefore, since the formation of the Sn—Ni alloy (2) is suppressed in the Au plating layer, the Au—Al alloy layer (213) is formed between the Ni plating layer and the Al wire by heating after wire bonding. Even if formed, generation of voids (B) in the wire pad can be suppressed. Therefore, according to the present invention, it is possible to prevent wire peeling due to heating after wire bonding as much as possible.

また、請求項2に記載の発明では、請求項1に記載の電子装置の製造方法において、はんだ付け工程では、はんだは、フラックスを含むはんだペーストとして、はんだランドに配置することを特徴とする。特に、はんだペーストの場合は、Snの付着が多いので、上記Ni拡散工程による効果が有効に発揮される。   According to a second aspect of the present invention, in the method of manufacturing an electronic device according to the first aspect, in the soldering step, the solder is disposed on the solder land as a solder paste containing a flux. In particular, in the case of a solder paste, since there is much adhesion of Sn, the effect by the Ni diffusion step is effectively exhibited.

なお、特許請求の範囲およびこの欄で記載した各手段の括弧内の符号は、後述する実施形態に記載の具体的手段との対応関係を示す一例である。   In addition, the code | symbol in the bracket | parenthesis of each means described in the claim and this column is an example which shows a corresponding relationship with the specific means as described in embodiment mentioned later.

(a)は、本発明の実施形態にかかる電子装置の概略断面図であり、(b)は、(a)中の電子部品におけるワイヤボンディング直後のワイヤパッドとはんだランドの詳細を示す拡大図であり、(c)は、(b)においてワイヤボンディング後に行った加熱後の状態を示す図である。(A) is a schematic sectional drawing of the electronic device concerning embodiment of this invention, (b) is an enlarged view which shows the detail of the wire pad and solder land immediately after the wire bonding in the electronic component in (a). (C) is a figure which shows the state after the heating performed after the wire bonding in (b). 図1に示される電子装置の製造方法を示す工程図である。It is process drawing which shows the manufacturing method of the electronic device shown by FIG. 図2に示される製造工程の進行に伴うワイヤパッドの状態変化を示す概略断面図である。It is a schematic sectional drawing which shows the state change of the wire pad accompanying progress of the manufacturing process shown by FIG. 上記実施形態におけるワイヤ剥がれ発生防止の推定メカニズムを示す図である。It is a figure which shows the presumed mechanism of wire peeling generation | occurrence | production prevention in the said embodiment. 上記実施形態における作用効果の一例を示す図である。It is a figure which shows an example of the effect in the said embodiment. 上記実施形態における作用効果の一例を示す図である。It is a figure which shows an example of the effect in the said embodiment. 本発明者の試作検討によるワイヤ剥がれ発生の推定メカニズムを示す図である。It is a figure which shows the presumed mechanism of wire peeling generation | occurrence | production by the inventor's trial manufacture examination.

以下、本発明の実施形態について図に基づいて説明する。なお、以下の各実施形態相互において、互いに同一もしくは均等である部分には、説明の簡略化を図るべく、図中、同一符号を付してある。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other are given the same reference numerals in the drawings in order to simplify the description.

(第1実施形態)
本発明の第1実施形態にかかる電子装置S1について、図1、図2を参照して述べる。この電子装置S1は、たとえば自動車などの車両に搭載され、車両用の各種装置の駆動、制御等を行うための装置として適用されるものである。
(First embodiment)
The electronic device S1 according to the first embodiment of the present invention will be described with reference to FIGS. The electronic device S1 is mounted on a vehicle such as an automobile and is applied as a device for driving, controlling, etc. various devices for the vehicle.

本実施形態の電子装置S1は、大きくは、基板10と、基板10上に搭載されたパワーチップ20および他の搭載部品30と、基板10上にてこれら基板10、各部品20、30の各間を電気的に接続するボンディングワイヤ40およびターミナル50と、を備えて構成されている。   The electronic device S1 of the present embodiment is broadly divided into a substrate 10, a power chip 20 and other mounted components 30 mounted on the substrate 10, and each of the substrate 10, each component 20, 30 on the substrate 10. A bonding wire 40 and a terminal 50 that are electrically connected to each other are provided.

基板10は、表裏の板面をそれぞれ一面11、他面12とする板状をなすものである。本実施形態の基板10は、Cu等よりなるリードフレームであるが、その他にも基板10としては、たとえばセラミック基板、プリント基板などが挙げられる。図1では、基板10の板厚方向に沿った電子装置S1の断面が示されている。   The substrate 10 has a plate shape in which the front and back plate surfaces are one surface 11 and the other surface 12, respectively. The substrate 10 of the present embodiment is a lead frame made of Cu or the like, but other examples of the substrate 10 include a ceramic substrate and a printed circuit board. In FIG. 1, a cross section of the electronic device S <b> 1 along the thickness direction of the substrate 10 is shown.

パワーチップ20は、ワイヤボンド用のワイヤパッド21およびはんだ付け用のはんだランド22を有する電子部品20として構成される。このようなパワーチップ20としては、たとえばパワーMOSトランジスタやIGBT等が挙げられる。   The power chip 20 is configured as an electronic component 20 having wire pads 21 for wire bonding and solder lands 22 for soldering. Examples of such a power chip 20 include a power MOS transistor and an IGBT.

他の搭載部品30は、たとえばマイコンなどの制御IC等である。これらパワーチップ20および他の搭載部品30は、はんだや導電性接着剤等のマウント材60を介して基板10の一面11上に接続されている。   The other mounted component 30 is a control IC such as a microcomputer. The power chip 20 and other mounting components 30 are connected to the one surface 11 of the substrate 10 via a mounting material 60 such as solder or a conductive adhesive.

パワーチップ20におけるワイヤパッド21およびはんだランド22は、基板10の一面11側にアルミニウム(Al)よりなるアルミ層210、220を有し、その上に各層が積層された構成を有する。   The wire pad 21 and the solder land 22 in the power chip 20 have aluminum layers 210 and 220 made of aluminum (Al) on the one surface 11 side of the substrate 10, and each layer is laminated thereon.

ここで、ボンディングワイヤ40の接続直後までのワイヤパッド21、および、はんだ70接続前のはんだランド22は、図1(b)および後述の図2(b)に示されるように、共に表面が、Niめっき層211、221を下地とするAuめっき層212、222よりなる。限定するものではないが、Auめっき層212、222の厚さは、たとえば20nm〜50nm程度のものとする。   Here, as shown in FIG. 1B and FIG. 2B to be described later, the surfaces of both the wire pad 21 immediately after the bonding wire 40 and the solder land 22 before the solder 70 are connected are as follows. It consists of Au plating layers 212 and 222 with Ni plating layers 211 and 221 as bases. Although not limited, the thickness of the Au plating layers 212 and 222 is, for example, about 20 nm to 50 nm.

つまり、これらワイヤパッド21およびはんだランド22は、当初では、ともに表面が「Ni/Auめっき」よりなるものとされている。そして、ボンディングワイヤ40接続後のワイヤパッド21に対する加熱、および、はんだランド22へのはんだ付けにより、図1(b)、(c)に示されるように、ワイヤパッド21およびはんだランド22の表面部分は、当初の状態から変化し、最終的には図1(c)の状態となっている。   That is, both the wire pad 21 and the solder land 22 are initially made of “Ni / Au plating”. Then, by heating the wire pad 21 after the bonding wire 40 is connected and soldering to the solder land 22, as shown in FIGS. 1B and 1C, surface portions of the wire pad 21 and the solder land 22. Changes from the initial state, and finally becomes the state of FIG.

この状態変化も含めて、ワイヤパッド21およびはんだランド22の各接続構成について述べる。ボンディングワイヤ40は、Alよりなるもので、通常のワイヤボンディング法により形成されている。このワイヤ40によって、パワーチップ20のワイヤパッド21と他の搭載部品30とが結線され、これらが電気的に接続されている。   Including this state change, each connection configuration of the wire pad 21 and the solder land 22 will be described. The bonding wire 40 is made of Al and is formed by a normal wire bonding method. With this wire 40, the wire pad 21 of the power chip 20 and the other mounting component 30 are connected, and these are electrically connected.

そして、このボンディングワイヤ40のワイヤパッド21への接続直後では、図1(b)に示されるように、ワイヤパッド21の表面は当初の「Ni/Auめっき」となっている。   Immediately after the bonding wire 40 is connected to the wire pad 21, the surface of the wire pad 21 is initially “Ni / Au plated” as shown in FIG.

ここで、ワイヤボンディング後には、たとえば更なる他部品の基板10への搭載や、モールド封止前の密着性付与剤の塗布、乾燥等のための加熱、あるいは、電子部品S1と他の部材との接続等、ワイヤボンディングの後工程としての加熱工程が行われる。   Here, after wire bonding, for example, mounting of another component on the substrate 10, application of an adhesion-imparting agent before mold sealing, heating for drying, etc., or electronic component S 1 and other members A heating process as a post-process of wire bonding, such as connection, is performed.

そうすると、この後工程としての加熱工程によって、ワイヤパッド21の表面におけるAuめっき層212とワイヤ40のアルミとが拡散し合うことにより、薄いAuめっき層212は実質的に消滅し、図1(c)に示されるように、Au−Al合金層213が形成される。   Then, the Au plating layer 212 on the surface of the wire pad 21 and the aluminum of the wire 40 are diffused by the heating process as a subsequent process, so that the thin Au plating layer 212 substantially disappears, and FIG. ), An Au—Al alloy layer 213 is formed.

つまり、最終的(つまり、製品として使用される時)には、本実施形態の電子装置S1におけるワイヤパッド21は、図1(c)に示されるようなアルミ層210、Niめっき層211、Au−Al合金層213が、基板10側から順次積層された構成となる。   That is, finally (that is, when used as a product), the wire pad 21 in the electronic device S1 of the present embodiment includes the aluminum layer 210, the Ni plating layer 211, and the Au as shown in FIG. The Al alloy layer 213 is sequentially stacked from the substrate 10 side.

一方、はんだランド22にはんだ付けされる接合部材としてのターミナル50は、Cuや鉄系金属等よりなるもので、図1に示されるように折り曲げられた板状のものである。このターミナル50によって、パワーチップ20のはんだランド22と基板10とが、はんだ70を介してはんだ付けされ、これらが電気的に接続されている。ここで、はんだ70は、Sn(すず)を含む鉛フリーはんだや共晶はんだ等である。   On the other hand, the terminal 50 as a joining member to be soldered to the solder land 22 is made of Cu, iron-based metal, or the like, and has a plate shape bent as shown in FIG. With this terminal 50, the solder land 22 of the power chip 20 and the substrate 10 are soldered via the solder 70, and these are electrically connected. Here, the solder 70 is a lead-free solder or eutectic solder containing Sn (tin).

このターミナル50のはんだ付けによって、はんだランド22の表面に当初存在していたAuめっき層222(図2(b)参照)は、はんだ70に吸収されて消滅する。そして、最終的には、本実施形態の電子装置S1におけるはんだランド22は、図1(b)、(c)に示されるようなアルミ層220、Niめっき層221が、基板10側から順次積層された構成になる。   By the soldering of the terminal 50, the Au plating layer 222 (see FIG. 2B) originally present on the surface of the solder land 22 is absorbed by the solder 70 and disappears. Finally, the solder land 22 in the electronic device S1 of the present embodiment has an aluminum layer 220 and a Ni plating layer 221 as shown in FIGS. 1B and 1C sequentially stacked from the substrate 10 side. It becomes the composition which was done.

次に、図2を参照して、本実施形態の電子装置S1の製造方法について述べる。なお、図2では、(b)においてワイヤパッド21およびはんだランド22の当初の状態を詳細に示してあるが、これら各部21、22の製造工程に伴う状態変化については、上記した通りであるため、(c)および(d)では、ワイヤパッド21、はんだランド22を簡略化して示してある。   Next, a method for manufacturing the electronic device S1 of the present embodiment will be described with reference to FIG. In FIG. 2, the initial state of the wire pad 21 and the solder land 22 is shown in detail in (b), but the state change accompanying the manufacturing process of these parts 21 and 22 is as described above. , (C) and (d), the wire pads 21 and the solder lands 22 are simplified.

まず、用意工程では、図2(a)、(b)に示されるように基板10を用意する。また、電子部品として、ワイヤパッド21の表面がNiめっき層211を下地とするAuめっき層212よりなるもの、つまり上記「Ni/Auめっき」であるパワーチップ20を用意する。   First, in the preparation step, the substrate 10 is prepared as shown in FIGS. 2 (a) and 2 (b). Further, as an electronic component, a power chip 20 is prepared in which the surface of the wire pad 21 is made of an Au plating layer 212 with a Ni plating layer 211 as a base, that is, the “Ni / Au plating”.

ここでは、用意されるパワーチップ20におけるはんだランド22も、表面が上記「Ni/Auめっき」とされている。このようなワイヤパッド21およびはんだランド22は、アルミの蒸着、スパッタや電気めっき、無電解めっき等により形成される。ここまでが用意工程である。   Here, the surface of the solder land 22 in the prepared power chip 20 is also the above-mentioned “Ni / Au plating”. Such wire pads 21 and solder lands 22 are formed by aluminum deposition, sputtering, electroplating, electroless plating, or the like. This is the preparation process.

次に、図2(b)に示されるように、基板10の一面11上に、マウント材60を介して、パワーチップ20および他の搭載部品30を搭載し、接合する(部品搭載工程)。   Next, as shown in FIG. 2B, the power chip 20 and other mounting components 30 are mounted and bonded to the one surface 11 of the substrate 10 via the mounting material 60 (component mounting step).

次に、図2(c)に示されるはんだ付け工程では、はんだランド22にはんだ70を配置し、このはんだ70上に接合部材としてのターミナル50を搭載した状態ではんだ70をリフローさせることにより、ターミナル50をはんだ付けする。本実施形態では、はんだ70は、はんだペーストの状態で印刷等により塗布する。   Next, in the soldering process shown in FIG. 2C, the solder 70 is disposed on the solder land 22, and the solder 70 is reflowed in a state where the terminal 50 as a joining member is mounted on the solder 70. The terminal 50 is soldered. In the present embodiment, the solder 70 is applied by printing or the like in a solder paste state.

このはんだ付け工程の後、図2(d)に示されるように、アルミのワイヤボンディングを行ってワイヤパッド21にワイヤ40を接合するワイヤボンディング工程を行う。   After this soldering step, as shown in FIG. 2D, a wire bonding step of bonding the wire 40 to the wire pad 21 by performing aluminum wire bonding is performed.

この後、必要に応じて、基板10に更に他部品を搭載する工程や、モールド樹脂で封止する場合にはポリアミド等の密着性付与剤(プライマー)の塗布、乾燥工程や、他の部材との接続工程等の、後工程としての加熱工程を行う。この後工程としての加熱工程により、電子部品は加熱される。こうして電子装置S1ができあがる。   Thereafter, if necessary, a process of mounting other components on the substrate 10, an application of an adhesion imparting agent (primer) such as polyamide, a drying process, and other members when sealing with mold resin A heating process as a post-process such as a connecting process is performed. The electronic component is heated by a heating process as a subsequent process. Thus, the electronic device S1 is completed.

このような製造方法において、本実施形態では、更に、はんだ付け工程の前に、用意されたパワーチップ20を加熱することにより、ワイヤパッド21においてAuめっき層212の表面にNiめっき層211からNiを拡散させるNi拡散工程を行う。   In such a manufacturing method, in the present embodiment, the prepared power chip 20 is further heated before the soldering step, whereby the Ni plating layer 211 to the Ni plating layer 211 are formed on the surface of the Au plating layer 212 in the wire pad 21. A Ni diffusion step for diffusing is performed.

このNi拡散工程は、用意されたパワーチップ20単体を加熱することで行ってもよいし、部品搭載工程によって基板10に搭載された状態のものを加熱することで行ってもよい。このときのパワーチップの加熱条件は、たとえば280℃以上、180秒以上の条件とする。   The Ni diffusion step may be performed by heating the prepared power chip 20 alone, or may be performed by heating the component mounted on the substrate 10 in the component mounting step. The heating conditions of the power chip at this time are, for example, 280 ° C. or higher and 180 seconds or longer.

このように本実施形態の製造方法においては、はんだ付け工程の前に、Ni拡散工程を行うが、これは、上記した後工程としての加熱工程によるワイヤ40の剥がれを抑制するために行うものである。このNi拡散工程について図3、図4を参照して具体的に述べる。なお、図3、図4に示されるワイヤパッドの状態変化やメカニズムについては、顕微鏡観察や元素分析等により確認した結果に基づくものである。   As described above, in the manufacturing method of the present embodiment, the Ni diffusion process is performed before the soldering process, which is performed in order to suppress the peeling of the wire 40 due to the heating process as the subsequent process described above. is there. The Ni diffusion process will be specifically described with reference to FIGS. In addition, about the state change and mechanism of a wire pad shown by FIG. 3, FIG. 4, it is based on the result confirmed by microscope observation, elemental analysis, etc. FIG.

Ni拡散工程前では、図3(a)、図4(a)に示されるように、ワイヤパッド21は、表面が、下地のNiめっき層211とその上のAuめっき層212とよりなる。そして、Ni拡散工程を行う。   Before the Ni diffusion step, as shown in FIGS. 3A and 4A, the surface of the wire pad 21 is composed of the underlying Ni plating layer 211 and the Au plating layer 212 thereon. Then, a Ni diffusion process is performed.

このNi拡散工程の加熱により、図3(b)、図4(a)に示されるように、下地のNiめっき層211中のNi3(図中では白丸で示す)が、Auめっき層212の表面まで拡散する。そして、この状態で、はんだ付け工程を行うと、はんだリフローの熱によって、はんだランド上のはんだからワイヤパッド21上に、Sn1(図中では点ハッチングの丸で示す)が飛散してAuめっき層212の表面に付着する。   Due to the heating in the Ni diffusion step, as shown in FIGS. 3B and 4A, Ni3 (shown by white circles in the figure) in the underlying Ni plating layer 211 becomes the surface of the Au plating layer 212. To spread. Then, when the soldering process is performed in this state, Sn1 (indicated by a dot-hatched circle in the figure) scatters from the solder on the solder land onto the wire pad 21 due to the heat of the solder reflow. It adheres to the surface of 212.

ここで、はんだリフローの熱によって、このAuめっき層212に付着したSn1は、Auめっき層212内に拡散しようとするが、既に同じAuめっき層212の表面に存在しているNi3によってブロックされるため、当該Sn1のAuめっき212層内への拡散が抑制される(図4(b)参照)。そのため、本実施形態では、図4(c)に示されるように、Auめっき層212内におけるSn−Ni合金2の形成は極力抑制される。   Here, Sn1 adhering to the Au plating layer 212 due to the heat of solder reflow attempts to diffuse into the Au plating layer 212, but is blocked by Ni3 already present on the surface of the same Au plating layer 212. Therefore, diffusion of the Sn1 into the Au plating 212 layer is suppressed (see FIG. 4B). Therefore, in this embodiment, as shown in FIG. 4C, the formation of the Sn—Ni alloy 2 in the Au plating layer 212 is suppressed as much as possible.

そして、図3(c)、図4(d)に示されるように、この状態のワイヤパッド21に対して、ワイヤボンディングが行われることにより、Auめっき層212上にAlよりなるボンディングワイヤ40が接続される。   3 (c) and 4 (d), wire bonding is performed on the wire pad 21 in this state, so that the bonding wire 40 made of Al is formed on the Au plating layer 212. Connected.

このワイヤボンディング後、電子装置S1には上記した加熱が施される。このとき当該加熱工程では、図3(d)、図4(e)、図4(f)に示されるように、ワイヤパッド21においてAuめっき層212のAuとワイヤ40のAlとで相互拡散が起こり、Niめっき層211とワイヤ40との間にAu−Al合金層213が形成される。   After the wire bonding, the electronic device S1 is heated as described above. At this time, in the heating process, as shown in FIGS. 3D, 4E, and 4F, mutual diffusion occurs between the Au of the Au plating layer 212 and the Al of the wire 40 in the wire pad 21. As a result, an Au—Al alloy layer 213 is formed between the Ni plating layer 211 and the wire 40.

ここで、本実施形態のAu−Al合金層213の形成においては、Auめっき層212内に存在し上記相互拡散を阻害するSn−Ni合金2の量が大幅に低減されるので、上記図7にて述べたようなAuの拡散速度の不均一が極力解消される。そのため、ワイヤパッド21内に生じるボイドBの発生を大幅に抑制できる。   Here, in the formation of the Au—Al alloy layer 213 of the present embodiment, the amount of the Sn—Ni alloy 2 present in the Au plating layer 212 and hindering the mutual diffusion is greatly reduced. The non-uniformity of Au diffusion rate as described in (1) is eliminated as much as possible. Therefore, generation of void B generated in the wire pad 21 can be greatly suppressed.

このように、本実施形態によれば、後工程としての加熱工程に供され、Niめっき層211とAlワイヤ40との間にAu−Al合金層213が形成されても、ワイヤパッド21内におけるボイドBの発生を抑制できる。よって、本実施形態によれば、ワイヤボンディング後の加熱によるワイヤ剥がれを極力防止することができる。   Thus, according to the present embodiment, even if the Au—Al alloy layer 213 is formed between the Ni plating layer 211 and the Al wire 40 in the heating process as a post process, Generation of void B can be suppressed. Therefore, according to this embodiment, it is possible to prevent wire peeling due to heating after wire bonding as much as possible.

また、本実施形態では、はんだ付け工程では、はんだ70は、フラックスを含むはんだペーストとして、はんだランド22に配置している。はんだペーストの場合は、Snの付着が顕著となるので、上記Ni拡散工程による効果が有効に発揮される。   In the present embodiment, in the soldering process, the solder 70 is disposed on the solder land 22 as a solder paste containing flux. In the case of the solder paste, since the adhesion of Sn becomes remarkable, the effect by the Ni diffusion step is effectively exhibited.

ここで、本実施形態による上記作用効果についての一具体例について、図5、図6を参照して述べる。図5は、Ni拡散工程によってワイヤパッド21のAuめっき層212表面へNiが拡散する効果を、実験的に確認したものである。   Here, a specific example of the above-described effect according to the present embodiment will be described with reference to FIGS. FIG. 5 shows experimentally confirmed effects of Ni diffusing to the surface of the Au plating layer 212 of the wire pad 21 by the Ni diffusion process.

具体的には、Ni拡散工程後のAuめっき層212の表面かから厚さ方向へエッチングを行い、各エッチング深さにおけるNi存在量をオージェ電子分光法(Auger Electron Spectroscopy:AES)により求めた。図5において、縦軸はエッチング時間(単位:分)であり、Auめっき層212の厚さ方向に相当し、横軸はNi強度であり、Ni存在量に相当する。   Specifically, etching was performed in the thickness direction from the surface of the Au plating layer 212 after the Ni diffusion step, and the Ni abundance at each etching depth was obtained by Auger Electron Spectroscopy (AES). In FIG. 5, the vertical axis represents the etching time (unit: minutes) and corresponds to the thickness direction of the Au plating layer 212, and the horizontal axis represents Ni strength and corresponds to the amount of Ni present.

図5に示されるように、Ni拡散工程ありの場合とNi拡散工程なしの場合とでは、「あり」の方が、エッチング時間0すなわちAuめっき層212の表面におけるNi存在量が約2倍に増えている。つまり、本実施形態におけるNi拡散工程によるNiの拡散効果が確認された。   As shown in FIG. 5, the etching time is 0, that is, the amount of Ni present on the surface of the Au plating layer 212 is approximately doubled when “Yes” is present when the Ni diffusion step is performed and when the Ni diffusion step is not performed. is increasing. That is, the Ni diffusion effect by the Ni diffusion process in this embodiment was confirmed.

図6は、Ni拡散工程における加熱温度を280℃として、アニール時間(加熱時間、単位:秒)によるボイド発生防止の効果を調べた結果を示している。図6によれば、おおよそ加熱時間は180秒以上でボイド率の低減度合が飽和している。このことから、Ni拡散工程によるNiの拡散効果を適切に発揮するためには、加熱温度が280℃の場合、180秒以上加熱することが望ましい。   FIG. 6 shows the results of examining the effect of preventing void generation by the annealing time (heating time, unit: second) at a heating temperature of 280 ° C. in the Ni diffusion step. According to FIG. 6, the heating time is approximately 180 seconds or more, and the degree of reduction in the void ratio is saturated. For this reason, in order to appropriately exhibit the Ni diffusion effect by the Ni diffusion step, when the heating temperature is 280 ° C., it is desirable to heat for 180 seconds or more.

(他の実施形態)
なお、電子部品20としては、Alワイヤ40がワイヤボンディングされるワイヤパッド21と、はんだランド22とを両備するものであればよく、上記パワーチップ20に限定されるものではない。たとえば、その他、電子部品としては、各種の表面実装部品、回路基板、各種のセンサチップ等であってもよい。
(Other embodiments)
The electronic component 20 is not limited to the power chip 20 as long as it has both the wire pad 21 to which the Al wire 40 is wire-bonded and the solder land 22. For example, as other electronic components, various surface mount components, circuit boards, various sensor chips, and the like may be used.

また、電子部品20としては、はんだランド22の表面も、ワイヤパッド21と同様の「Ni/Auめっき」の構成であったが、これは、電子部品の製造工程上、はんだランド22の表面をAu/Niめっきとすると、ワイヤパッド21も同一表面構成とするのが通常であることによる。   Moreover, as for the electronic component 20, the surface of the solder land 22 has the same “Ni / Au plating” configuration as that of the wire pad 21, but this is because the surface of the solder land 22 is formed in the manufacturing process of the electronic component. In the case of Au / Ni plating, the wire pad 21 is usually of the same surface configuration.

ただし、はんだランド22は、Snはんだ70ではんだ付けされるものであればよく、はんだ付けが可能なものならば、上記実施形態のようなワイヤパッド21と同一の表面構成、すなわち「Ni/Auめっき」以外のものであってもよい。   However, the solder land 22 only needs to be soldered with the Sn solder 70. If the solder land 22 can be soldered, the same surface configuration as that of the wire pad 21 as in the above embodiment, that is, “Ni / Au It may be other than “plating”.

また、基板10上には、ワイヤパッド21とはんだランド22とを両備する電子部品20が複数個搭載されていてもよい。この場合も、各電子部品20について、はんだ付け工程の前にNi拡散工程を実施すればよい。   Further, a plurality of electronic components 20 having both wire pads 21 and solder lands 22 may be mounted on the substrate 10. Also in this case, the Ni diffusion process may be performed on each electronic component 20 before the soldering process.

また、接合部材としては、はんだランドにはんだ付けされるものであればよく、上記ターミナル50以外のものであってもよい。また、はんだ70の配置については、はんだペーストの塗布以外にも、はんだボール等による配置でもよい。   Moreover, as a joining member, what is soldered to a solder land is sufficient, and things other than the said terminal 50 may be sufficient. Further, the solder 70 may be arranged by solder balls or the like in addition to the application of the solder paste.

また、本発明は上記した実施形態に限定されるものではなく、特許請求の範囲に記載した範囲内において適宜変更が可能である。また、上記実施形態は、上記の図示例に限定されるものではない。また、上記実施形態において、実施形態を構成する要素は、特に必須であると明示した場合および原理的に明らかに必須であると考えられる場合等を除き、必ずしも必須のものではないことは言うまでもない。また、上記実施形態において、実施形態の構成要素の個数、数値、量、範囲等の数値が言及されている場合、特に必須であると明示した場合および原理的に明らかに特定の数に限定される場合等を除き、その特定の数に限定されるものではない。また、上記実施形態において、構成要素等の形状、位置関係等に言及するときは、特に明示した場合および原理的に特定の形状、位置関係等に限定される場合等を除き、その形状、位置関係等に限定されるものではない。   Further, the present invention is not limited to the above-described embodiment, and can be appropriately changed within the scope described in the claims. Moreover, the said embodiment is not limited to said example of illustration. Further, in the above-described embodiment, it is needless to say that elements constituting the embodiment are not necessarily indispensable except for the case where it is clearly indicated that the element is essential and the case where the element is clearly considered to be essential in principle. . Further, in the above embodiment, when numerical values such as the number, numerical value, quantity, range, etc. of the constituent elements of the embodiment are mentioned, it is particularly limited to a specific number when clearly indicated as essential and in principle. The number is not limited to a specific number except for cases. In the above embodiment, when referring to the shape, positional relationship, etc. of components, the shape, position, etc., unless otherwise specified and in principle limited to a specific shape, positional relationship, etc. It is not limited to relationships.

10 基板
20 電子部品としてのパワーチップ
21 ワイヤパッド
22 はんだランド
40 ボンディングワイヤ
50 接合部材としてのターミナル
70 はんだ
211 ワイヤパッドのNiめっき層
212 ワイヤパッドのAuめっき層
DESCRIPTION OF SYMBOLS 10 Board | substrate 20 Power chip as an electronic component 21 Wire pad 22 Solder land 40 Bonding wire 50 Terminal as a joining member 70 Solder 211 Ni plating layer of wire pad 212 Au plating layer of wire pad

Claims (3)

ワイヤボンド用のワイヤパッド(21)およびはんだ付け用のはんだランド(22)を有する電子部品(20)と、
前記ワイヤパッドにワイヤボンディングされたアルミニウムよりなるワイヤ(40)と、
前記はんだランドにSnを含むはんだ(70)を介してはんだ付けされた接合部材(50)と、を備える電子装置の製造方法であって、
前記電子部品として、前記ワイヤパッドの表面が、Niめっき層(211)を下地とするAuめっき層(212)よりなるものを用意する用意工程と、
前記はんだランドに前記はんだを配置し、前記はんだ上に前記接合部材を搭載した状態で前記はんだをリフローさせることにより、前記接合部材をはんだ付けするはんだ付け工程と、
前記はんだ付け工程の後、ワイヤボンディングを行って前記ワイヤパッドに前記ワイヤを接合するワイヤボンディング工程と、
前記ワイヤボンディング工程の後、前記電子部品を加熱する加熱工程と、を備え、
前記はんだ付け工程の前に、前記用意された前記電子部品を加熱することにより、前記ワイヤパッドにおいて前記Auめっき層の表面に前記Niめっき層からNiを拡散させるNi拡散工程を行うことを特徴とする電子装置の製造方法。
An electronic component (20) having a wire pad (21) for wire bonding and a solder land (22) for soldering;
A wire (40) made of aluminum wire-bonded to the wire pad;
A joining member (50) soldered to the solder land via a solder (70) containing Sn, and an electronic device manufacturing method comprising:
A preparation step of preparing an electronic component having a surface of the wire pad made of an Au plating layer (212) based on a Ni plating layer (211);
A soldering step of soldering the joining member by placing the solder on the solder land and reflowing the solder in a state where the joining member is mounted on the solder;
After the soldering step, wire bonding is performed to bond the wire to the wire pad by performing wire bonding;
A heating step of heating the electronic component after the wire bonding step,
Before the soldering step, performing the Ni diffusion step of diffusing Ni from the Ni plating layer on the surface of the Au plating layer in the wire pad by heating the prepared electronic component. A method for manufacturing an electronic device.
前記はんだ付け工程では、前記はんだは、フラックスを含むはんだペーストとして、前記はんだランドに配置することを特徴とする請求項1に記載の電子装置の製造方法。   2. The method of manufacturing an electronic device according to claim 1, wherein in the soldering step, the solder is disposed on the solder land as a solder paste containing a flux. 前記用意工程では、前記電子部品として、前記はんだランドの表面も、前記ワイヤパッドと同様の材質を用いたNiめっき層(221)を下地とするAuめっき層(222)よりなるものを用意することを特徴とする請求項1または2に記載の電子装置の製造方法。   In the preparation step, as the electronic component, the surface of the solder land is also made of an Au plating layer (222) based on a Ni plating layer (221) using the same material as the wire pad. The method for manufacturing an electronic device according to claim 1, wherein:
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