JP2014157909A - Method of manufacturing semiconductor device - Google Patents

Abstract

Disclosed is a semiconductor substrate having a reduced thickness that can be prevented from being damaged when it is divided by dicing.
A support substrate is attached to an adhesive layer, and then a substrate is thinned from the back surface side to form a substrate through-via in the substrate, and a back surface wiring patterning is formed on the back surface of the substrate. Then, the substrate 101 is diced from the back surface of the thinned substrate 101 and divided into a plurality of chips 105. After the dicing, the back surfaces of the plurality of chips 105 that are divided on the support substrate 104 through the adhesive layer 103 are attached to the adhesive tape 106, and then the support substrate 104 is released. For example, the adhesiveness of the adhesive tape 106 is assumed to be lower than the bending strength of the substrate 101.
[Selection] Figure 1E

Description

  The present invention relates to a method of manufacturing a semiconductor device in which a semiconductor substrate is thinned and then made into individual chips.

  With the recent increase in communication speed, there has been a demand for microwave / millimeter-wave monolithic integrated circuits (MMIC) that meet the required characteristics and performance. In this high-speed IC, a compound semiconductor having high physical properties is often used, and in particular, a transistor such as HEMT or HBT using InP is often used. Conventionally, in high-speed ICs targeting up to 50 GHz even in the microwave band, increasing the operating frequency mainly by miniaturizing transistors has been the basis of manufacturing technology.

  However, in an IC that handles higher frequencies, in addition to miniaturization of transistors, a new device for propagating ultra-high frequency signals losslessly is required. At this time, the most serious problem is that the high-frequency signal propagating through the wiring on the substrate radiates and resonates to the substrate having a high dielectric constant, thereby destabilizing the IC operation.

  In order to suppress such substrate resonance, the following two measures are effective.

Countermeasure 1: Resonance mode in the substrate thickness direction is suppressed by thinning the substrate.
Countermeasure 2: Resonance modes in the substrate surface direction are suppressed by forming ground vias that penetrate the substrate at narrow intervals.

  Here, the thinner the substrate is, the easier it is to process the via that penetrates the substrate, so that the substantial countermeasures are concentrated in the countermeasure 1 thinning of the substrate. Therefore, first, a technique for forming a chip in a state in which the substrate is thinned and chips and cracks are suppressed from the thinned substrate is important.

  In the thinning of the substrate, for example, there is a technique in which a silicon substrate on which a through via is formed is thinned by grinding from the back surface, and then dicing is performed to divide into individual chips (see Patent Document 1).

  In such chip division by dicing, generally, first, as shown in FIG. 2A, a glass substrate 203 is attached to a semiconductor substrate 201 via an adhesive layer 202, and this is attached to a dicing tape 205. wear. Next, as illustrated in FIG. 2B, the adhesive layer 202 is peeled off from the semiconductor substrate 201 to separate the glass substrate 203.

  Next, as shown in FIG. 2C, the rotating dicing blade 251 is relatively moved along a cutting line (not shown), so that the semiconductor substrate 201 is cut and the chip 204 is manufactured. After the separation into all the chips 204 in this way, as shown in FIG. 2D, each chip 204 is released from the dicing tape 205 and supplied to the subsequent mounting process.

Japanese Patent No. 4800898

  However, since the substrate is thinned, breakage such as chipping and cracking is likely to occur. When chipping and cracking occur in this way, the expected performance on the chip cannot be achieved, and in some cases it may be defective. There is a problem of becoming. For example, after attaching a semiconductor substrate to a dicing tape, chipping / cracking occurs due to stress at the time of peeling the support substrate or dicing. Further, in the above-described technique, the dicing tape has high adhesive strength so that the chip is not peeled off during dicing, and peeling (separation) of the thinned chip after dicing becomes difficult.

  For example, when the semiconductor is a substrate having a certain degree of rigidity such as silicon or GaAs, the above-described problem can be suppressed to some extent. However, in the case of an InP substrate, since InP is a mechanically fragile material, the above is a big problem. Even if the substrate is somewhat rigid such as silicon or GaAs, the same problem occurs when the substrate is made thinner.

  The present invention has been made in order to solve the above-described problems, and an object of the present invention is to make it possible to suppress breakage at the time of division by dicing even for a thinned semiconductor substrate. To do.

  The method for manufacturing a semiconductor device according to the present invention includes a first step of forming a wiring on a main surface of a substrate made of a semiconductor, and a support substrate is attached to the main surface on which the wiring of the substrate is formed via an adhesive layer. A second step, a third step of thinning the substrate from the back side, a fourth step of dicing the substrate from the back side of the thinned substrate and dividing it into a plurality of chips, and bonding onto the support substrate A fifth step of attaching the back surfaces of the plurality of chips divided in a state of being pasted through the layers to the adhesive tape, and a sixth step of releasing the support substrate by separating the adhesive layer from the plurality of chips; A seventh step of releasing the chip from the adhesive tape, and in the seventh step, the adhesive tape has a lower adhesive strength than the bending strength of the substrate.

  In the manufacturing method of the semiconductor device, the adhesiveness of the adhesive tape may be lower than the bending strength of the substrate as long as the support substrate can be released with the chip attached to the adhesive tape. Further, in the seventh step, the chip may be released by reducing the adhesiveness of the adhesive tape below the bending strength of the substrate by irradiation with ultraviolet rays. Further, in the seventh step, the adhesive tape may be expanded to lower the adhesiveness of the adhesive tape below the bending strength of the substrate, thereby releasing the chip.

  In the semiconductor device manufacturing method, in the first step, an element may be formed on the main surface of the substrate in addition to the wiring.

  As described above, according to the present invention, it is an object of the present invention to prevent damage at the time of division by dicing or the like even for a thinned semiconductor substrate.

FIG. 1A is a cross-sectional view schematically showing a state in a process to be described for describing a method for manufacturing a semiconductor device in an embodiment of the present invention. FIG. 1B is a cross-sectional view schematically showing a state in a process to be described for describing a method for manufacturing a semiconductor device in an embodiment of the present invention. FIG. 1C is a cross-sectional view schematically showing a state in a process to be described for describing a method for manufacturing a semiconductor device in an embodiment of the present invention. FIG. 1D is a cross-sectional view schematically showing a state in a process to be described for describing a method for manufacturing a semiconductor device in an embodiment of the present invention. FIG. 1E is a cross-sectional view schematically showing a state in a process to be described for describing a method for manufacturing a semiconductor device in an embodiment of the present invention. FIG. 1F is a cross sectional view schematically showing a state in a process which is a target for explaining a method for manufacturing a semiconductor device in an embodiment of the present invention. FIG. 1G is a cross-sectional view schematically showing a state in a process to be described for describing a method for manufacturing a semiconductor device in an embodiment of the present invention. FIG. 1H is a cross-sectional view schematically showing a state in a process to be described for describing a method for manufacturing a semiconductor device in an embodiment of the present invention. FIG. 2A is a cross-sectional view schematically showing a state in each step for explaining chip division by dicing. FIG. 2B is a cross-sectional view schematically showing a state in each step for explaining chip division by dicing. FIG. 2C is a cross-sectional view schematically showing a state in each step for explaining chip division by dicing. FIG. 2D is a cross-sectional view schematically showing a state in each step for explaining chip division by dicing.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1A to 1H are cross-sectional views schematically showing states in a process to be described for a method for manufacturing a semiconductor device in an embodiment of the present invention.

  In this method of manufacturing a semiconductor device, first, as shown in FIG. 1A, a plurality of element regions 102 composed of wiring, a plurality of elements, and the like are formed on the main surface of a substrate 101 made of a semiconductor (for example, InP). The element region 102 is formed in a region that becomes one chip. Here, in each element region 102, for example, an MMIC composed of a plurality of elements is formed. In each element region 102, only high-frequency wiring may be formed.

  Next, as shown in FIG. 1B, an adhesive layer 103 is formed on the main surface of the substrate 101 where the element region 102 is formed. For example, an adhesive may be applied to form the adhesive layer 103 by a coating method such as spin coating or spray coating. Here, a coating method that can suppress in-plane uniformity to 10% or less may be used.

  The thickness of the adhesive layer 103 may be at least the maximum unevenness difference on the formation surface of the element region 102. For example, when there is a maximum height difference of 5 μm in a circuit integrated mesa structure or multilayer wiring structure formed in the element region 102, the adhesive layer 103 having a thickness of at least about 5 μm may be formed. In order to reduce the stress applied to the substrate 101 from the adhesive layer 103, it is better to make the adhesive layer 103 thinner. However, considering the ease of peeling of the adhesive layer 103 in a later process, the maximum height difference is 3 to 10 times ( In this example, it is desirable to form in the order of 15 μm to 50 μm.

  Next, as illustrated in FIG. 1B, a support substrate 104 is attached to the adhesive layer 103. As a result, the support substrate 104 is attached to the substrate 101 via the adhesive layer 103. For example, it may be attached by vacuum pressure bonding. Here, a glass substrate which transmits ultraviolet light, laser light, or the like may be used for the support substrate 104. Moreover, if the board | substrate thickness is about 300-1000 micrometers, both the board | substrate support intensity | strength and peelability will be favorable. In addition, if the diameter of the support substrate 104 is about 0.5 to 3 mm larger than the substrate 101, wraparound to the surface of the adhesive constituting the adhesive layer 103 at the time of bonding can be suppressed, and good peeling is possible. It becomes.

  Next, the bonding of the support substrate 104 is performed in, for example, a predetermined sealed container, and the pressure (vacuum degree) in the container is about 5-50 Pa, and the applied pressure at the time of bonding is about 10-1000 kPa. It is possible to support the substrate with high parallelism without voids in the adhesive layer 103. Thus, even when the substrate 101 is thinned to 50 μm or less, there is no uneven grinding within the plane of the substrate 101 and no peeling from the adhesive layer 103, and the substrate 101 can be thinned satisfactorily.

  After the above steps, the adhesive layer 103 is cured. If the adhesive layer 103 is made of, for example, a UV curable adhesive, it can be attached without thermal stress. Alternatively, the adhesive layer 103 may be formed of a thermosetting adhesive as long as the combination is sufficiently small with respect to the substrate 101 to which the thermal stress is bonded. With each configuration described above, substrate support that can withstand loads such as back surface grinding and dicing of the substrate 101 in a later process can be realized. Further, as will be described later, when the chip is separated from the adhesive layer 103, it may be configured to be peelable by, for example, laser light irradiation.

  Next, as shown in FIG. 1C, the substrate 101 is thinned from the back surface side (third step). For example, by polishing the back surface, the substrate 101 is thinned to a thickness of about 5 to 50 μm. For thinning, a well-known mechanical grinding method or chemical mechanical polishing such as CMP (Chemical Mechanical Polishing) may be used. However, any thinning may be used as long as the adhesion of the support substrate 104 by the adhesive layer 103 is ensured. A stratification method may be used. After thinning in this manner, as is well known, for example, a substrate back surface via is formed on the substrate 101 and a back surface wiring pattern is formed on the back surface of the substrate 101. .

  Next, as shown in FIG. 1D, the substrate 101 is diced from the back surface of the thinned substrate 101 to be divided into a plurality of chips 105 (fourth step). For example, the rotating dicing blade 151 is relatively moved along a cutting line (not shown), so that the back surface of the substrate 101 is cut and divided into a plurality of chips 105. Here, in the groove 121 in the region of the cutting line formed by dicing, an interlayer film for the multilayer wiring of the integrated circuit and a ground back metal are arranged so that only the substrate 101 is exposed on both the front and back surfaces. It is desirable to be in a state.

  The amount of cut by the dicing blade 151 is set to a value about 5-20 μm larger than the thickness of the substrate 101. As a result, the chip 105 is not cracked or chipped, and the chip can be formed with the substrate 101 supported by the support substrate 104. There is a possibility that the dicing blade 151 does not penetrate the substrate 101 under the condition where the cutting amount is smaller than that described above. On the other hand, it is not desirable for the dicing blade 151 to cause chipping and cracking by entraining the adhesive of the adhesive layer 103 under conditions that are greater than the above-described cutting amount. It should be noted that other cutting / dividing methods such as stealth dicing and etching dicing may be used as long as there is no chipping or cracking of the chip 105 and a good end face of the chip 105 can be obtained.

  Here, in the above-described embodiment, at the stage where the substrate 101 is diced to form the plurality of chips 105, the thinned substrate 101 is supported by the support substrate 104 and is proportional to the area. Since the internal stress that becomes large is relieved, it is extremely advantageous for thinning the substrate 101 from the viewpoint of handling in the subsequent process.

  Next, as shown in FIG. 1E, an adhesive tape in which the back surfaces of a plurality of chips 105 divided on a support substrate 104 with an adhesive layer 103 attached thereto are stuck to a dicing frame. Affixed to 106 (fifth step).

  Next, the support substrate 104 is released by reducing the adhesive force (adhesiveness) of the adhesive layer 103 and separating from the plurality of chips 105 (substrate 101) (sixth step). For example, the adhesiveness of the adhesive layer 103 may be lowered to a bending strength of the substrate 101 or less. For example, in the case where the adhesive layer 103 is composed of a layer that can be peeled off by laser, the adhesive layer 103 is reduced in adhesiveness by transmitting the transparent support substrate 104 and irradiating the adhesive layer 103 with an infrared laser. The chip 105 can be separated. In the case where the adhesive layer 103 having thermoplasticity is used, the adhesive layer 103 may be softened by heating to reduce the tackiness and be separated from the chip 105. In this case, the support substrate 104 does not need to have translucency.

  As described above, as shown in FIG. 1F, the plurality of chips 105 are in a state where the element region 102 on the front surface is exposed and the back surface is bonded to the adhesive tape 106 and supported.

  Next, the chip 105 is released (separated) from the adhesive tape 106. At this time, it is important that the adhesive property of the adhesive tape 106 is lower than the bending strength of the substrate 101. For example, the adhesiveness of the adhesive tape 106 to be used may be lower than the bending strength of the substrate 101 as long as the support substrate 104 can be released with the chip 105 attached to the adhesive tape 106.

  Here, the adhesiveness of the adhesive tape 106 will be described. First, breakage at the time of forming the chip 105 due to the vulnerability of the substrate 101 will be described. For example, the substrate 101 made of InP is extremely mechanically fragile compared to other semiconductor substrates due to material properties. The mechanical strength is quantified as the bending strength by a three-point bending test or a four-point bending test (JIS R1601), but in the case of an InP substrate having a thickness of 100 μm, it is smaller than 10 kPa, although it depends on the plane orientation. There is only strength. Further, the substrate 101 on which the substrate through-via is formed is in a more fragile state.

  In such a fragile substrate 101, first, when a stress higher than the bending strength of the substrate 101 is generated at the stage of forming the plurality of chips 105 by dicing, the formed chip 105 is chipped or cracked. However, according to the above-described embodiment, since the dicing is performed while being supported by the support substrate 104, the above-described problem can be prevented.

  Similarly, when the support substrate 104 is released, as described above, the chip 105 is damaged by reducing the adhesiveness of the adhesive layer 103 to be equal to or lower than the bending strength of the substrate 101. I can prevent it. At this stage, the chip 105 is affixed to the adhesive tape 106, so that the chip 105 can be prevented from being damaged.

  Next, the same applies to the step of releasing the chip 105 from the adhesive tape 106. If the adhesive tape 106 has high adhesiveness at the stage of releasing the chip 105, the chip 105 is likely to be damaged when the chip 105 is separated. In particular, a general dicing tape is considered to have high adhesiveness because it is important that the chip is not released during dicing.

The adhesiveness of a dicing tape or the like is expressed as a probe tack. The probe tack is defined as S / F when the force when a probe having a certain area S [m ² ] is brought into contact with a substrate supporting adhesive tape such as a dicing tape and peeled in the vertical direction is F [N]. This is a value indicated by [Pa]. A dicing tape used for general purposes has a probe tack of about 100 kPa, which is much higher than the bending strength of the InP substrate. When such a dicing tape is used, breakage such as chipping and cracking occurs when the chip is released.

  On the other hand, for example, in a state where the support substrate 104 (adhesive layer 103) can be released in a state where the chip 105 is attached to the adhesive tape 106, the adhesive pressure-sensitive adhesive tape 106 having a lower bending strength than the substrate 101 is available. May be used. For example, an adhesive tape 106 having a probe tack smaller than ½ of the bending strength of the substrate portion made of InP of the chip 105 may be used. Specifically, if the bending strength of the substrate portion made of InP of the chip 105 with a chip size of 100 μm is 10 kPa, the probe tack of the low adhesive tape 106 may be 5 kPa or less.

  With the adhesive tape 106 having such adhesiveness, for example, when tweezers are used and the chip 105 is separated from the adhesive tape 106 and handled, damage can be suppressed. Further, when the support tape 104 is released after the adhesive tape 106 is applied to each divided chip 105, the state where the chip 105 is applied to the adhesive tape 106 can be maintained.

  Further, in the step of separating the chip 105 from the adhesive tape 106 after releasing the support substrate 104, the adhesiveness of the adhesive tape 106 is changed from the bending strength of the substrate 101 by irradiation with ultraviolet rays 161 as shown in FIG. 1G. Then, the chip 105 may be released after that. As described above, the adhesive tape 106 having a probe tack of 1/2 or less of the bending strength of the substrate 101 may be used by the irradiation of the ultraviolet rays 161. In this case, the adhesive tape 106 may be a probe tack exceeding the bending strength of the substrate 101 before the irradiation with the ultraviolet rays 161, and the chip 105 can be stably supported, and unnecessary peeling of the chip 105 due to impact or the like. In addition, changes over time can be suppressed.

  In addition, in the step of separating the chip 105 from the adhesive tape 106 after the support substrate 104 is released, the adhesive tape 106 is expanded to expand the adhesive property of the adhesive tape 106 as shown in FIG. 1H. The mold 105 may be released from the folding strength. The adhesive tape 106 is expanded in the plane direction of the adhesive tape 106. At this time, the adhesive tape 106 is expanded with a force equal to or less than the bending strength of the substrate 101. In this way, the probe tack of the adhesive tape 106 may be set to ½ or less of the bending strength of the substrate 101. In other words, the adhesive tape 106 whose probe tack becomes 1/2 or less of the bending strength of the substrate 101 due to expansion may be used.

  Also in this case, before expansion, the adhesive tape 106 may be a probe tack exceeding the bending strength of the substrate 101, and can stably support the chip 105. It is possible to suppress changes with time. Further, since no ultraviolet irradiation is performed, adverse effects on the chip 105 due to the ultraviolet irradiation can be suppressed.

  As described above, in the present invention, the element region forming surface of the main surface of the substrate such as InP is attached to the support substrate with the adhesive layer, and in this state, dicing is performed from the back surface of the substrate. In addition, after dicing, the support substrate is released after the back surfaces of a plurality of chips divided in a state of being attached to the support substrate via the adhesive layer are attached to the adhesive tape, and then the adhesive substrate is released. When the chip was released from the tape, the pressure-sensitive adhesive tape had a lower adhesive strength than that of the substrate. As a result, according to the present invention, even when dicing after thinning the substrate, it is possible to suppress damage or the like when dividing by dicing or when separating divided chips individually.

  The present invention is not limited to the embodiment described above, and many modifications and combinations can be implemented by those having ordinary knowledge in the art within the technical idea of the present invention. It is obvious. For example, in the above description, a substrate made of InP for high frequency, which is particularly mechanically fragile, has been described as an example. By performing the dicing method by supporting the substrate, the same effect can be obtained, which can greatly contribute to the stable operation of the MMIC.

  DESCRIPTION OF SYMBOLS 101 ... Board | substrate, 102 ... Element area | region, 103 ... Adhesive layer, 104 ... Support substrate, 105 ... Chip | tip, 106 ... Adhesive tape, 121 ... Groove, 151 ... Dicing blade, 161 ... Ultraviolet rays.

Claims (5)

A first step of forming a wiring on a main surface of a substrate made of a semiconductor;
A second step of attaching a support substrate to the main surface of the substrate on which the wiring is formed via an adhesive layer;
A third step of thinning the substrate from the back side;
A fourth step in which the substrate is diced from the back surface of the thinned substrate and divided into a plurality of chips;
A fifth step of affixing back surfaces of a plurality of chips divided in a state of being affixed on the support substrate via the adhesive layer to an adhesive tape;
A sixth step of releasing the support substrate by separating the adhesive layer from the plurality of chips;
And a seventh step of releasing the chip from the adhesive tape.
In the seventh step, the adhesive property of the adhesive tape is lower than the bending strength of the substrate. In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device according to claim 1, wherein the adhesive property of the adhesive tape is lower than a bending strength of the substrate in a range where the support substrate can be released in a state where the chip is attached to the adhesive tape. In the manufacturing method of the semiconductor device according to claim 1,
In the seventh step, the chip is released by lowering the adhesive strength of the adhesive tape below the bending strength of the substrate by irradiation with ultraviolet rays. In the manufacturing method of the semiconductor device according to claim 1,
In the seventh step, the chip is released by expanding the pressure-sensitive adhesive tape to lower the adhesive strength of the pressure-sensitive adhesive tape below the bending strength of the substrate. In the manufacturing method of the semiconductor device given in any 1 paragraph of Claims 1-4,
In the first step, an element is formed on the main surface of the substrate in addition to the wiring.

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