CN102693941A - Wafer cutting process - Google Patents

Abstract

A wafer dicing process is provided, wherein a wafer is provided. The wafer has a front surface and a back surface. Then, a grinding patch is attached to the front surface of the wafer, and the back surface of the wafer is precut to form a plurality of cutting channels on the back surface of the wafer. Then, the back side of the wafer is polished to reduce the thickness of the wafer and the depth of the scribe line. The abrasive patch is then removed. And then, attaching a cutting patch to the back surface of the wafer, and cutting the front surface of the wafer to form a plurality of chips separated from each other.

Description

Wafer Dicing Process

technical field

The present invention relates to a semiconductor manufacturing process, and more particularly to a wafer dicing process.

Background technique

With the rapid development of technology, integrated circuits (IC) components have been widely used in our daily life. Generally speaking, the production of integrated circuits is mainly divided into three stages: semiconductor wafer (wafer) manufacturing, integrated circuit fabrication and integrated circuit packaging.

In addition, after the integrated circuits are fabricated on the semiconductor wafer, the semiconductor wafer is diced to form a plurality of chips. Generally speaking, the above-mentioned dicing process usually attaches a grinding tape to the front of the wafer and grinds the back of the wafer to reduce the thickness of the wafer. Then, remove the grinding pad. Next, a first saw tape is pasted on the backside of the wafer, and the front side of the wafer is cut to form dicing lines on the front side of the wafer. Then, the first cut patch is removed. Afterwards, a second dicing patch is pasted on the front side of the wafer, and the back side of the wafer is cut to form a plurality of chips.

However, in the above-mentioned dicing process, chipping often occurs after dicing the backside of the wafer, that is, after dicing the backside of the wafer to form a plurality of chips, the chips will collide with each other or cause chip damage due to cutting stress. The backside of the chip is damaged, thus affecting the quality of the formed chip.

Contents of the invention

In view of this, the object of the present invention is to provide a wafer cutting process, which can solve the problem of wafer damage due to back avalanche.

The present invention proposes a wafer dicing process, which firstly provides wafers. A wafer has a front side and a back side. Then, a grinding patch is attached to the front side of the wafer, and the back side of the wafer is pre-cut to form a plurality of dicing lines on the back side of the wafer. Next, the backside of the wafer is ground to reduce the thickness of the wafer and the depth of the dicing lines. Then, remove the grinding patch. Afterwards, a first dicing sticker is pasted on the back of the wafer, and the front of the wafer is cut to form a plurality of chips separated from each other.

According to the wafer dicing process described in the embodiment of the present invention, the above-mentioned wafer has, for example, a plurality of bumps, and these bump arrays are arranged on the front side of the wafer.

According to the wafer dicing process described in the embodiment of the present invention, the above method of pre-cutting the back of the wafer is, for example, first placing the wafer with the grinding patch on the second dicing patch, wherein the grinding patch and Second cut patch contacts. Afterwards, dicing lines are formed on the backside of the wafer.

According to the wafer dicing process described in the embodiments of the present invention, after the backside of the wafer is pre-cut, the second dicing patch can also be removed.

According to the wafer dicing process described in the embodiment of the present invention, the method of pre-cutting the backside of the wafer is, for example, laser cutting, mechanical cutting or etching.

According to the wafer dicing process described in the embodiment of the present invention, the above-mentioned grinding patch is removed after the wafer is ground, for example.

In the present invention, after the backside of the wafer is pre-cut, the backside of the wafer is ground to remove the damage caused by the backside chipping of the wafer, so that chips with good quality can be formed.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

1A to 1E are schematic cross-sectional views of a wafer dicing process according to an embodiment of the present invention.

[Description of main component symbols]

100: Wafer

100a: Front

100b: back

102: Bump

104: Grinding patch

106, 112: cutting patch

108: Cutting Road

110: area

114: chip

Detailed ways

1A to 1E are schematic cross-sectional views of a wafer dicing process according to an embodiment of the present invention. First, referring to FIG. 1A , a wafer 100 is provided. Wafer 100 has a front side 100a and a back side 100b. The front surface 100a is an active surface with a plurality of protrusions 102 thereon. The bumps 102 are, for example, silver bumps, copper-gold bumps or gold bumps. The bumps 102 are, for example, arranged in an array on the front surface 100 a of the wafer 100 . Then, a grinding patch 104 is pasted on the front surface 100 a of the wafer 100 .

Referring to FIG. 1B , the wafer 100 attached with the grinding patch 104 is placed on the dicing patch 106 , so that the grinding patch 104 is in contact with the dicing patch 106 . After that, a pre-dicing step is performed to cut the backside 100 b of the wafer 100 to form a plurality of dicing lines 108 on the backside 100 b of the wafer 100 . The method of dicing the backside 100 b of the wafer 100 is, for example, laser dicing, mechanical dicing (eg using a dicing knife) or etching. It should be noted that in this step, the wafer 100 is not diced into a plurality of separate chips, that is, the dicing line 108 does not penetrate the wafer 100 .

In addition, after the dicing line 108 is formed, the backside 100 b of the wafer 100 may be damaged at the region 110 due to the cutting stress, which is known as back chipping.

Next, referring to FIG. 1C , the cutting patch 106 is removed. Afterwards, the backside 100 b of the wafer 100 is ground to reduce the thickness of the wafer 100 and the depth of the dicing lines 108 . In particular, after grinding the backside 100b of the wafer 100, the damage caused by the back avalanche at the region 110 has been removed together, thus solving the problem of the backside damage of the chips formed in the prior art .

Then, referring to FIG. 1D , the grinding patch 104 is removed. Then, the dicing sticker 112 is pasted on the back surface 100 b of the wafer 100 .

After that, a dicing step is performed, corresponding to the dicing lines 108 on the backside 100b of the wafer 100 , dicing the front side 100 a of the wafer 100 to form a plurality of chips 114 separated from each other. In particular, when dicing the front side 100 a of the wafer 100 , if a dicing knife is used for dicing, the width of the dicing knife used is greater than the width of the dicing knife used when dicing the back side 100 b of the wafer 100 .

To sum up, in the wafer dicing process of the present invention, the backside of the wafer is pre-cut first, and then the front side of the wafer is diced to form a plurality of chips, and the backside of the wafer is ground after pre-cutting. In this way, the damage caused by back chipping on the backside of the wafer can be removed during the grinding process, thus forming chips with good quality.

Although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the claims.

Claims (6)

1. A wafer cutting process, comprising: providing a wafer having a front side and a back side; attaching a grinding patch to the front side of the wafer, and pre-dicing the back side of the wafer to form a plurality of dicing lines on the back side of the wafer; grinding the backside of the wafer to reduce the thickness of the wafer and the depth of the scribe lines; remove the abrasive patch; and Attaching a first dicing sticker to the back side of the wafer, and cutting the front side of the wafer to form a plurality of chips separated from each other. 2. The wafer dicing process according to claim 1, wherein the wafer has a plurality of bumps, and the array of bumps is arranged on the front side of the wafer. 3. The wafer cutting process according to claim 1, wherein the method for pre-cutting the back side of the wafer comprises: placing the wafer with the abrasive patch attached on a second dicing patch, wherein the abrasive patch is in contact with the second dicing patch; and The dicing lines are formed on the backside of the wafer. 4. The wafer dicing process as claimed in claim 3, wherein the method for pre-cutting the back side of the wafer further comprises: After predicing the backside of the wafer, the second dicing patch is removed. 5. The wafer dicing process as claimed in claim 1, wherein the method for pre-cutting the backside of the wafer comprises performing laser cutting, mechanical cutting or etching. 6. The wafer dicing process as claimed in claim 1, wherein the grinding patch is removed after the wafer is ground.

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