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JP2014143265A - Semiconductor device - Google Patents

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JP2014143265A
JP2014143265A JP2013009981A JP2013009981A JP2014143265A JP 2014143265 A JP2014143265 A JP 2014143265A JP 2013009981 A JP2013009981 A JP 2013009981A JP 2013009981 A JP2013009981 A JP 2013009981A JP 2014143265 A JP2014143265 A JP 2014143265A
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substrate
semiconductor device
semiconductor chip
multilayer
multilayer substrate
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Inventor
Hiroshi Yamamoto
浩史 山本
Hironori Hiraoka
寛規 平岡
Hiroko Mori
寛子 森
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Sansha Electric Manufacturing Co Ltd
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Sansha Electric Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which supports low inductance and low heat resistance at the same time at low cost in an insulated semiconductor device which mounts a semiconductor chip on a substrate principal surface and in which insulation between the semiconductor chip and a substrate rear face side is ensured.SOLUTION: The present embodiment relates to an insulated semiconductor device which mounts a semiconductor chip on a substrate principal surface and in which insulation between the semiconductor chip and a substrate rear face side is ensured. A semiconductor device 1 comprises: a multilayer substrate 3 as a substrate, which has a penetration part 36 formed to pierce a principal surface and a rear face; a ceramic substrate 4 attached to the rear face of the multilayer substrate 3 so as to face a projection region 10 obtained by projecting the penetration part 36 to the rear face of the multilayer substrate 3; and a semiconductor chip 5 attached to the principal surface of the ceramic substrate 4, which is located in the projection region 10.

Description

この発明は、低インダクタンスおよび低熱抵抗を両立する絶縁型半導体装置に関する。   The present invention relates to an insulating semiconductor device having both low inductance and low thermal resistance.

近年ＩＧＢＴ、スーパージャンクション型のＭＯＳＦＥＴなどを搭載する半導体装置では、半導体チップの面積あたりの許容電流が大きくなっている。大電流が流れる経路には、物理的なループを持つとこの部分がインダクタンス成分として機能することがある。そうすると、スイッチング電源に使用される半導体装置では、短い時間で電流が流れたり、流れなかったりすることで、その電流が上記インダクタンス成分に起因して電圧に変化する。このような電圧が発生するとノイズとして周辺に悪影響を及ぼす虞がある。   In recent years, in a semiconductor device on which an IGBT, a super junction type MOSFET, or the like is mounted, an allowable current per area of a semiconductor chip has increased. If there is a physical loop in the path through which a large current flows, this part may function as an inductance component. Then, in the semiconductor device used for the switching power supply, current flows or does not flow in a short time, so that the current changes to a voltage due to the inductance component. If such a voltage is generated, there is a risk of adversely affecting the surroundings as noise.

低インダクタンスを実現する対策には、電流の経路に物理的なループを極力小さくすることが有効である。ループを小さくする方法としては、樹脂の多層基板の使用が好適である。   In order to realize low inductance, it is effective to make the physical loop as small as possible in the current path. As a method of reducing the loop, it is preferable to use a resin multilayer substrate.

半導体装置は、基板の表面に現れる導体パターンや搭載される半導体チップを埃や水分から保護するために、モールド樹脂によって基板主面側がパッケージングされた形で製品化される。大電流が流れる仕様の半導体装置では、通電時に半導体チップで発生する熱を効率良く放熱させる必要がある。しかし、多層基板は高熱抵抗（低熱伝導率）の樹脂で形成されているため、それ自体に放熱効果は期待出来ない。   2. Description of the Related Art A semiconductor device is commercialized in a form in which a main surface side of a substrate is packaged with a mold resin in order to protect a conductor pattern appearing on the surface of the substrate and a mounted semiconductor chip from dust and moisture. In a semiconductor device having a specification in which a large current flows, it is necessary to efficiently dissipate heat generated in the semiconductor chip when energized. However, since the multilayer substrate is made of a resin having a high thermal resistance (low thermal conductivity), the heat dissipation effect cannot be expected in itself.

そこで半導体チップの発熱対策のために、樹脂（樹脂にガラスなどの副成分が混合された複合体も含む。）の多層基板の裏面に導体層を形成し、この裏面側導体層を、放熱板を兼ねる熱伝導率の極めて高い金属材料（銅など。）で形成されたベース板に取付けるようにしている（例えば、特許文献１参照。）。   Therefore, as a countermeasure against heat generation of the semiconductor chip, a conductor layer is formed on the back surface of the multilayer substrate of resin (including a composite in which a subcomponent such as glass is mixed with the resin), and the back surface side conductor layer is formed on the heat sink. It is made to attach to the base board formed with the metal material (copper etc.) with extremely high thermal conductivity which serves as (for example, refer patent document 1).

また、樹脂基板に替えて低熱抵抗（高熱伝導率）のセラミックス基板を使用することも提案されている。例えば、特許文献２では、セラミックス（厳密には、セラミックスとガラスの複合体）の多層基板を使用し、この多層基板をベース板に取付けることが記載されている。これによれば、より効率良く半導体チップから生ずる熱を放熱することが出来る。   It has also been proposed to use a ceramic substrate having a low thermal resistance (high thermal conductivity) instead of the resin substrate. For example, Patent Document 2 describes using a multilayer substrate of ceramics (strictly speaking, a composite of ceramics and glass) and attaching the multilayer substrate to a base plate. According to this, the heat generated from the semiconductor chip can be radiated more efficiently.

特開２００２−２６１４５４号公報JP 2002-261454 A 特開平６−１０４３５０号公報JP-A-6-104350

絶縁型と呼ばれる半導体装置では、半導体チップと多層基板の裏面側との間の絶縁が完全に確保されていることも重要な要素である。   In a semiconductor device called an insulation type, it is also an important factor that insulation between the semiconductor chip and the back surface side of the multilayer substrate is completely ensured.

この点、特許文献１の半導体装置では、ビアポストと呼ばれる、多層基板を上下に貫通する導体の柱の上に半導体チップを搭載し、ビアポストを介して半導体チップとベース板とが導通することになる。このため、半導体チップとベース板との間の絶縁が十分に図れない問題がある。   In this regard, in the semiconductor device of Patent Document 1, a semiconductor chip is mounted on a pillar of a conductor that penetrates a multilayer substrate up and down, which is called a via post, and the semiconductor chip and the base plate are electrically connected via the via post. . For this reason, there is a problem that insulation between the semiconductor chip and the base plate cannot be sufficiently achieved.

また、特許文献２のようにセラミックス基板を使用する場合は、高価なセラミックス基板の使用量が多くなり、コストが高くなる問題がある。   Moreover, when using a ceramic substrate like patent document 2, there exists a problem that the usage-amount of an expensive ceramic substrate increases and cost becomes high.

この発明は上記課題に鑑みてなされたものであり、基板主面に半導体チップが搭載され、半導体チップと基板裏面側との間で絶縁が確保される絶縁型の半導体装置において、低インダクタンスおよび低熱抵抗を両立する半導体装置を低コストに提供することを目的とする。   The present invention has been made in view of the above problems, and in an insulated semiconductor device in which a semiconductor chip is mounted on a main surface of a substrate and insulation is ensured between the semiconductor chip and the back side of the substrate, low inductance and low heat An object of the present invention is to provide a semiconductor device having both resistance at low cost.

この発明は、基板主面に半導体チップが搭載され、半導体チップと基板裏面側との間で絶縁が確保される絶縁型の半導体装置に関する。このような装置において、この発明の半導体装置は、基板が多層基板であり、多層基板は主面と裏面とを貫通するように形成される貫通部を有し、多層基板の裏面に、貫通部を多層基板の裏面に投影した投影領域に臨ませてセラミックス基板が取付けられ、投影領域に位置するセラミックス基板の主面に半導体チップが取付けられたことを特徴とする。   The present invention relates to an insulating semiconductor device in which a semiconductor chip is mounted on a main surface of a substrate and insulation is ensured between the semiconductor chip and the back side of the substrate. In such a device, in the semiconductor device of the present invention, the substrate is a multilayer substrate, the multilayer substrate has a through portion formed so as to penetrate the main surface and the back surface, and the through portion is formed on the back surface of the multilayer substrate. The ceramic substrate is attached so as to face the projection area projected on the back surface of the multilayer substrate, and the semiconductor chip is attached to the main surface of the ceramic substrate located in the projection area.

配線パターンを有するメイン基板である多層樹脂基板に、セラミックス基板を介して半導体チップが搭載される。セラミックス基板とは、セラミックスベース板の両面に金属薄膜層を有する基板である。例えば、ＤＢＣ（Direct Bonded Copper）（登録商標）基板やＡＭＣ（ActiveMetal Brazed Copper）が挙げられる。   A semiconductor chip is mounted on a multilayer resin substrate, which is a main substrate having a wiring pattern, via a ceramic substrate. A ceramic substrate is a substrate having metal thin film layers on both sides of a ceramic base plate. Examples thereof include a DBC (Direct Bonded Copper) (registered trademark) substrate and an AMC (Active Metal Brazed Copper).

多層基板主面に搭載されるべき半導体チップは、セラミックス基板の主面に取付けられる。多層基板では、インダクタンスの発生要因となる電流の経路のループが層間距離に相当する長さまで短縮される。このため、装置の小型化に加えて低インダクタンスが実現される。   A semiconductor chip to be mounted on the main surface of the multilayer substrate is attached to the main surface of the ceramic substrate. In the multilayer substrate, the loop of the current path that causes the inductance is shortened to a length corresponding to the interlayer distance. For this reason, in addition to downsizing of the apparatus, low inductance is realized.

また、半導体チップと多層基板の裏面側との間は、セラミックス基板のセラミックスベース板により絶縁が十分に図られている。そのため、セラミックス基板の面積は半導体チップよりも一回り大きい程度で十分なので、高価なセラミックス基板の使用量を減らせるため低コストである。多層基板には、安価な多層樹脂基板が好適に用いられる。   Further, the semiconductor chip and the back surface side of the multilayer substrate are sufficiently insulated by the ceramic base plate of the ceramic substrate. For this reason, it is sufficient that the area of the ceramic substrate is one size larger than that of the semiconductor chip, so that the amount of use of the expensive ceramic substrate can be reduced and the cost is low. An inexpensive multilayer resin substrate is suitably used for the multilayer substrate.

貫通部は、多層基板に開口もしくは切り欠きとして形成されるものが挙げられる。多層基板は２枚以上の基板を並列に配置したものであっても良い。貫通部のその他の例として、隣接する２枚の多層基板間の間隙として形成されるものであっても構わない。   Examples of the through portion include those formed as openings or cutouts in the multilayer substrate. The multilayer substrate may be one in which two or more substrates are arranged in parallel. As another example of the penetrating portion, it may be formed as a gap between two adjacent multilayer substrates.

セラミックスは、樹脂に比べて低熱抵抗である。つまり、半導体チップからの熱は、セラミックス基板に伝熱され、多層基板の裏面側へ伝熱して効率良く放熱することが出来る。放熱効率は、このセラミックス基板の裏面に放熱板を取付けることにより、さらに向上する。   Ceramics have a lower thermal resistance than resin. That is, the heat from the semiconductor chip is transferred to the ceramic substrate, and is transferred to the back surface side of the multilayer substrate to be efficiently radiated. The heat dissipation efficiency is further improved by attaching a heat dissipation plate to the back surface of the ceramic substrate.

この発明によれば、基板主面に半導体チップが搭載され、半導体チップと基板裏面側との間で絶縁が確保される絶縁型の半導体装置において、低インダクタンスおよび低熱抵抗を両立する半導体装置を低コストに提供することが可能となる。   According to the present invention, in an insulating semiconductor device in which a semiconductor chip is mounted on the main surface of the substrate and insulation is ensured between the semiconductor chip and the back surface side of the substrate, a semiconductor device that achieves both low inductance and low thermal resistance is reduced. It becomes possible to provide the cost.

この発明の一実施形態に係る半導体装置を示す断面図である。1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention.

この発明の半導体装置は、半導体チップと基板裏面側との間で絶縁が確保される絶縁型と呼ばれるタイプの半導体装置に関する。具体的構成を以下に説明する。   The semiconductor device of the present invention relates to a semiconductor device of a type called an insulation type in which insulation is ensured between a semiconductor chip and a back surface side of a substrate. A specific configuration will be described below.

この発明の実施形態に係る半導体装置を図１を参照しながら説明する。本実施形態に係る半導体装置１は、放熱板２、多層基板３、セラミックス基板４、および半導体チップ５およびモールド樹脂６を備える。   A semiconductor device according to an embodiment of the present invention will be described with reference to FIG. A semiconductor device 1 according to the present embodiment includes a heat radiating plate 2, a multilayer substrate 3, a ceramic substrate 4, a semiconductor chip 5, and a mold resin 6.

放熱板２は、熱伝導率の高い材料で形成された板状部材であり、その材料は金属が用いられ、特に銅が好適に用いられる。放熱板２は半導体装置１のベース板を兼ねており、半導体装置１に機械的強度を持たせるためにある程度の厚みを有する。放熱板２は、後述するセラミックス基板４の裏面の導体層４３に取付けられる。   The heat radiating plate 2 is a plate-like member formed of a material having high thermal conductivity, and a metal is used as the material, and copper is particularly preferably used. The heat radiating plate 2 also serves as a base plate of the semiconductor device 1 and has a certain thickness to give the semiconductor device 1 mechanical strength. The heat sink 2 is attached to a conductor layer 43 on the back surface of the ceramic substrate 4 described later.

多層基板３の材質は問わないが、安価な樹脂を使用した多層樹脂基板を好適に用いることが出来る。多層基板３は、配線パターンが形成されたり、或いは配線パターンを有しないベタの導体層を複数有する基板である。この発明で定義される多層基板３の最もシンプルな構造は２層の樹脂基板である。   The material of the multilayer substrate 3 is not limited, but a multilayer resin substrate using an inexpensive resin can be suitably used. The multilayer substrate 3 is a substrate having a plurality of solid conductor layers on which a wiring pattern is formed or does not have a wiring pattern. The simplest structure of the multilayer substrate 3 defined in the present invention is a two-layer resin substrate.

本実施形態では、図１に示すように、多層基板３は、主面（同図では上面。）および裏面（同図では下面。）にそれぞれ導体層３１，３３を有する２層樹脂基板を例示している。さらに本実施形態では、主面の導体層３１は所定の配線パターンが形成されているが、裏面の導体層３３は特別な配線パターンを持たないベタの導体層として形成されている。主面の導体層３１は、アイランド３１Ｂを有する。   In the present embodiment, as shown in FIG. 1, the multilayer substrate 3 is an example of a two-layer resin substrate having conductor layers 31 and 33 on the main surface (upper surface in the figure) and the back surface (lower surface in the figure), respectively. doing. Furthermore, in the present embodiment, the conductor layer 31 on the main surface is formed with a predetermined wiring pattern, but the conductor layer 33 on the back surface is formed as a solid conductor layer having no special wiring pattern. The conductor layer 31 on the main surface has an island 31B.

多層基板３は、主面と裏面とを貫通するように形成される貫通部３６を有する。貫通部３６は、多層基板３に開口もしくは切り欠きとして形成されるものが挙げられる。多層基板３は２枚以上の基板を並列に配置したものであっても良い。貫通部３６のその他の例としては、隣接する２枚の多層基板３間の間隙として形成されるものであっても構わない。貫通部３６の平面サイズは、半導体チップ５をその内側に配置できるように、半導体チップ５の実装面積よりも大きなサイズに設定される。   The multilayer substrate 3 has a through portion 36 formed so as to penetrate the main surface and the back surface. Examples of the through portion 36 include those formed as openings or cutouts in the multilayer substrate 3. The multilayer substrate 3 may be one in which two or more substrates are arranged in parallel. As another example of the penetrating portion 36, it may be formed as a gap between two adjacent multilayer substrates 3. The planar size of the penetrating portion 36 is set to be larger than the mounting area of the semiconductor chip 5 so that the semiconductor chip 5 can be disposed inside thereof.

また、多層基板３には、貫通部３６から離れた箇所に導体の柱であるビアポスト３５が貫通している。ビアポスト３５は、主面側で導体層３１のアイランド３１Ｂに連結されるともに、裏面側で導体層３３に連結されている。ビアポスト３５は、一本の極太のビアポストで構成されていても良いし、多数本の細いビアポストの集合体で構成されていても良い。なお、本例ではビアポスト３５により表面と裏面の配線パターンを接続しているが、半導体チップ５のような発熱部品が搭載されていない部分は単に配線パターンが導通できれば良い。そのため、必ずしもビアポスト３５が必要なわけではなく、電流が小さい場合は電流密度に併せて、孔の表面にめっきが施されたスルーホール３５’としてもよく、スルーホール３５’にディスクリート部品等を挿入したり、スルーホール３５’に半田を充填するなど、通常の樹脂基板として使用すればよい。   In addition, a via post 35 that is a pillar of a conductor penetrates through the multilayer substrate 3 at a location away from the penetrating portion 36. The via post 35 is connected to the island 31B of the conductor layer 31 on the main surface side and is connected to the conductor layer 33 on the back surface side. The via post 35 may be composed of a single very thick via post, or may be composed of an aggregate of a large number of thin via posts. In this example, the wiring patterns on the front surface and the back surface are connected by the via posts 35. However, it is only necessary that the wiring pattern can be electrically connected to the portion where the heat generating component such as the semiconductor chip 5 is not mounted. For this reason, the via post 35 is not necessarily required. When the current is small, the through hole 35 ′ in which the surface of the hole is plated may be used in accordance with the current density, and a discrete part or the like is inserted into the through hole 35 ′. For example, it may be used as a normal resin substrate such as filling the through hole 35 'with solder.

セラミックス基板４は、セラミックスベース板４１の両面に金属薄膜層からなる導体層４２，４３を有する基板である。例えば、ＤＢＣ（Direct Bonded Copper）（登録商標）基板やＡＭＣ（ActiveMetal Brazed Copper）が挙げられる。本実施形態では、導体層４２，４３はともに配線パターンを持たないベタの導体層として形成されているが、この限りではない。   The ceramic substrate 4 is a substrate having conductor layers 42 and 43 made of metal thin film layers on both surfaces of a ceramic base plate 41. Examples thereof include a DBC (Direct Bonded Copper) (registered trademark) substrate and an AMC (Active Metal Brazed Copper). In the present embodiment, the conductor layers 42 and 43 are both formed as solid conductor layers having no wiring pattern, but this is not restrictive.

半導体チップ５は、導電性接合剤８を用いてセラミックス基板４の主面の導体層４２に取付けられる。セラミックス基板４は、導電性接合剤８を用いてセラミックス基板４の裏面の導体層４３に取付けられる。導電性接合剤８は熱伝導性にも優れる。   The semiconductor chip 5 is attached to the conductor layer 42 on the main surface of the ceramic substrate 4 using the conductive bonding agent 8. The ceramic substrate 4 is attached to the conductor layer 43 on the back surface of the ceramic substrate 4 using the conductive bonding agent 8. The conductive bonding agent 8 is also excellent in thermal conductivity.

このとき、セラミックス基板４は貫通部３６を多層基板３の裏面に投影した投影領域１０に臨ませて取付けられる。「臨ませて」とは、必ずしも図示の如くセラミックス基板４が投影領域１０を跨いで設置される必要はなく、半導体チップ５を安定して取付けられる程度の平面サイズでセラミックス基板４が部分的に投影領域１０の内側に位置していれば十分であることを意味している。   At this time, the ceramic substrate 4 is attached with the penetrating portion 36 facing the projection region 10 projected onto the back surface of the multilayer substrate 3. “Be faced” does not necessarily mean that the ceramic substrate 4 is placed across the projection region 10 as shown in the figure, and the ceramic substrate 4 is partially formed in a plane size that allows the semiconductor chip 5 to be stably attached. It means that it is sufficient if it is located inside the projection region 10.

セラミックス基板４はいわば半導体チップ５の台座であり、半導体チップ５と多層基板３の裏面側との絶縁をこのセラミックス基板４によって確保している。   The ceramic substrate 4 is a pedestal of the semiconductor chip 5, and insulation between the semiconductor chip 5 and the back surface side of the multilayer substrate 3 is ensured by the ceramic substrate 4.

半導体チップ５は、多層基板３の配線パターンとワイヤボンディングを介して接続される。半導体チップ５として例えばバイポーラ型のチップが用いられる場合、図示の如く１本のワイヤ７で多層基板３の主面の配線パターンと接続される。また、半導体チップ５の被実装面の電極はセラミックス基板４の主面の導体層４２および導電性接合剤８を介して多層基板３の裏面の導体層３３に接続される。本実施形態では、図示の如く、多層基板３の裏面の導体層３３はビアポスト３５を介して主面の導体層３１のアイランド３１Ｂに接続されている。結局、半導体チップ５は１本のワイヤ７と、セラミックス基板４、導体層３３およびビアポスト３５を用いて多層基板３の主面の配線パターンに接続されることになる。   The semiconductor chip 5 is connected to the wiring pattern of the multilayer substrate 3 through wire bonding. When a bipolar chip, for example, is used as the semiconductor chip 5, it is connected to the wiring pattern on the main surface of the multilayer substrate 3 with a single wire 7 as shown. The electrodes on the mounting surface of the semiconductor chip 5 are connected to the conductor layer 33 on the back surface of the multilayer substrate 3 through the conductor layer 42 on the main surface of the ceramic substrate 4 and the conductive bonding agent 8. In the present embodiment, as shown in the drawing, the conductor layer 33 on the back surface of the multilayer substrate 3 is connected to the island 31 </ b> B of the conductor layer 31 on the main surface via a via post 35. Eventually, the semiconductor chip 5 is connected to the wiring pattern on the main surface of the multilayer substrate 3 using one wire 7, the ceramic substrate 4, the conductor layer 33, and the via post 35.

多層基板３の主面側は、半導体チップ５を埃や水分から保護するために、モールド樹脂６で被覆される。さらに、セラミックス基板４が配置された、放熱板２と多層基板３との間の隙間にもモールド樹脂６が封入されている。高価なセラミックスの使用量を減らすために、セラミックス基板４は多層基板３に比べてサイズが小さいものを採用しているので、モールド樹脂６によってその隙間を埋めて製品の外形を整えている。このようにモールド樹脂６により、半導体装置１はパッケージングされる。   The main surface side of the multilayer substrate 3 is covered with a mold resin 6 in order to protect the semiconductor chip 5 from dust and moisture. Further, a mold resin 6 is also sealed in a gap between the heat sink 2 and the multilayer substrate 3 where the ceramic substrate 4 is disposed. In order to reduce the amount of expensive ceramics used, the ceramic substrate 4 is smaller in size than the multi-layer substrate 3, and the outer shape of the product is adjusted by filling the gap with the mold resin 6. Thus, the semiconductor device 1 is packaged by the mold resin 6.

以上説明したように、この発明に係る半導体装置１では、多層基板３主面に搭載されるべき半導体チップ５は、セラミックス基板４の主面に取付けられる。多層基板３では、インダクタンスの発生要因となる電流の経路のループが層間距離に相当する長さまで短縮される。このため、装置の小型化に加えて低インダクタンスが実現される。   As described above, in the semiconductor device 1 according to the present invention, the semiconductor chip 5 to be mounted on the main surface of the multilayer substrate 3 is attached to the main surface of the ceramic substrate 4. In the multilayer substrate 3, the loop of the current path that causes the inductance is shortened to a length corresponding to the interlayer distance. For this reason, in addition to downsizing of the apparatus, low inductance is realized.

また、半導体チップ５と多層基板３の裏面側との間は、セラミックス基板４のセラミックスベース板４１により絶縁が十分に図られている。高価なセラミックス基板４の使用量を減らせるため低コストである。   The semiconductor chip 5 and the back surface side of the multilayer substrate 3 are sufficiently insulated by the ceramic base plate 41 of the ceramic substrate 4. Since the amount of use of the expensive ceramic substrate 4 can be reduced, the cost is low.

セラミックスは、樹脂に比べて低熱抵抗である。つまり、半導体チップ５からの熱は、セラミックス基板４に伝熱され、多層基板３の裏面側へ伝熱して効率良く放熱することが出来る。   Ceramics have a lower thermal resistance than resin. That is, the heat from the semiconductor chip 5 is transferred to the ceramic substrate 4 and transferred to the back side of the multilayer substrate 3 so that it can be efficiently dissipated.

したがって、この発明によれば、基板主面に半導体チップが搭載され、半導体チップと基板裏面側との間で絶縁が確保される絶縁型の半導体装置において、低インダクタンスおよび低熱抵抗を両立する半導体装置を低コストに提供することが可能となる。   Therefore, according to the present invention, a semiconductor device in which a semiconductor chip is mounted on the main surface of the substrate and insulation is ensured between the semiconductor chip and the back surface side of the substrate is a semiconductor device that achieves both low inductance and low thermal resistance. Can be provided at low cost.

上述の実施形態の説明は、すべての点で例示であって、制限的なものではないと考えられるべきである。この発明の範囲は、上述の実施形態ではなく、特許請求の範囲によって示される。さらに、この発明の範囲には、特許請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。   The above description of the embodiment is to be considered in all respects as illustrative and not restrictive. The scope of the present invention is shown not by the above-described embodiments but by the claims. Furthermore, the scope of the present invention is intended to include all modifications within the meaning and scope equivalent to the claims.

１…半導体装置
２…放熱板
３…多層基板
４…セラミックス基板
５…半導体チップ
６…モールド樹脂
７…ワイヤ
８…導電性接合剤
１０…投影領域
３１，３３…導体層
３１Ｂ…アイランド
３５…ビアポスト
３６…貫通部
４１…セラミックスベース板
４２，４３…導体層 DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 2 ... Heat sink 3 ... Multilayer substrate 4 ... Ceramic substrate 5 ... Semiconductor chip 6 ... Mold resin 7 ... Wire 8 ... Conductive bonding agent 10 ... Projection area | region 31, 33 ... Conductive layer 31B ... Island 35 ... Via post 36 ... penetrating part 41 ... ceramics base plates 42,43 ... conductor layer

Claims (6)

基板主面に半導体チップが搭載され、前記半導体チップと前記基板裏面側との間で絶縁が確保される絶縁型の半導体装置において、
前記基板が多層基板であり、前記多層基板は主面と裏面とを貫通するように形成される貫通部を有し、前記多層基板の裏面に、前記貫通部を前記多層基板の裏面に投影した投影領域に臨ませてセラミックス基板が取付けられ、前記投影領域に位置する前記セラミックス基板の主面に前記半導体チップが取付けられたことを特徴とする、半導体装置。 In an insulating semiconductor device in which a semiconductor chip is mounted on the main surface of the substrate and insulation is ensured between the semiconductor chip and the back side of the substrate.
The substrate is a multilayer substrate, the multilayer substrate has a through portion formed so as to penetrate the main surface and the back surface, and the through portion is projected on the back surface of the multilayer substrate on the back surface of the multilayer substrate. A semiconductor device, wherein a ceramic substrate is attached facing a projection area, and the semiconductor chip is attached to a main surface of the ceramic substrate located in the projection area. 前記多層基板が多層樹脂基板である、請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the multilayer substrate is a multilayer resin substrate. 前記貫通部が前記多層基板に開口若しくは切り欠きとして形成される、請求項１または２に記載の半導体装置。   The semiconductor device according to claim 1, wherein the penetrating portion is formed as an opening or a notch in the multilayer substrate. 前記多層基板が複数の前記多層基板で構成され、前記貫通部が隣接する２枚の前記多層基板間の間隙として形成される、請求項１または２に記載の半導体装置。   3. The semiconductor device according to claim 1, wherein the multilayer substrate includes a plurality of the multilayer substrates, and the through portion is formed as a gap between two adjacent multilayer substrates. 前記セラミックス基板の裏面に放熱板が取付けられた、請求項１〜４のいずれかに記載の半導体装置。   The semiconductor device in any one of Claims 1-4 with which the heat sink was attached to the back surface of the said ceramic substrate. 前記放熱板は金属ベース板である、請求項５に記載の半導体装置。   The semiconductor device according to claim 5, wherein the heat radiating plate is a metal base plate.
JP2013009981A 2013-01-23 2013-01-23 Semiconductor device Pending JP2014143265A (en)

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08222670A (en) * 1995-02-15 1996-08-30 Tokuyama Corp Package for mounting semiconductor devices

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08222670A (en) * 1995-02-15 1996-08-30 Tokuyama Corp Package for mounting semiconductor devices

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