JP2014120920A - Station side device and received signal processing method - Google Patents

Abstract

Synchronization pull-in time is shortened without increasing jitter.
A no-signal period signal generation circuit generates a no-signal period signal NPS indicating a no-signal period NP included in a first received signal Rx1 based on a signal interruption period of an optical signal, and performs no-signal period interpolation. The circuit 13 interpolates a period of the first reception signal Rx1 in which the no-signal period signal NPS indicates a no-signal period with an interpolation signal NPI generated from the transmission signal Tx input to the transceiver 11. The CDR circuit 14 reproduces the reception clock signal RCLK synchronized with the interpolated reception signal RxI, and outputs the second reception signal Rx2 obtained by retiming the interpolated reception signal RxI based on the reception clock signal RCLK. .
[Selection] Figure 1

Description

  The present invention relates to PON technology, and in particular, an upstream burst signal transmitted in a time division manner from a plurality of home side devices is received by a station side device, and a reception signal obtained from these upstream burst signals is reproduced from the disturbing signal. The present invention relates to a received signal processing technique for retiming and outputting with a received clock signal.

FIG. 7 is a block diagram showing a general PON system and a station side device. FIG. 8 is a timing chart showing an upstream burst signal in a general PON system.
In a PON (Passive Optical Network) system in which optical communication is performed via an optical branching unit 70 between a station side device (OLT: Optical Line Terminal) 50 and a plurality of home side devices (ONU: Optical Network Unit) 60, In order to transmit an upstream burst signal from each home-side device 61 to 6n (n is an integer of 2 or more) to the station-side device 50, burst periods BP1 to BPn are set as different communication time zones for each home-side device 60. A time-sharing method assigned by the device 50 in a time-sharing manner is employed (for example, see Non-Patent Document 1).

Each of the home side devices 61 to 6n can transmit the upstream burst signals UB1 to UBn only in the burst periods BP1 to BPn assigned to the home side devices 61 to 6n by the station side device 50. At this time, a no-signal period NP is provided between adjacent burst periods BP1 to BPn.
In addition, when one station-side device 50 performs optical communication with each of the home-side devices 61 to 6n at different bit rates, the upstream burst signals UB1 to UBn of the burst periods BP1 to BPn are different for each home-side device 60. Generated based on bit rate. For this reason, when processing the received signals obtained from the upstream burst signals UB1 to UBn, the station side device 50 needs to regenerate the clock signals synchronized with the received signals.

In the station side device 50, the upstream burst signals UB1 to UBn from the respective home side devices 61 to 6n are received by the transceiver 51, converted from optical signals to electric signals, and then amplified, and received as a received signal Rx1 by CDR (Clock Data Recovery) circuit 54.
The CDR circuit 54 regenerates the reception clock signal RCLK synchronized with the reception signal Rx1 from the input reception signal Rx1, re-times the reception signal Rx1 based on the reception clock signal RCLK, and obtains the received signal Rx2 The reception clock signal RCLK is output to the transmission / reception processing circuit 55.
The transmission / reception processing circuit 55 performs various signal processing on the reception signal Rx2 based on the reception signal Rx2 from the CDR circuit 54 and the reception clock signal RCLK. The transmission signal Tx transmitted from the transmission / reception processing circuit 55 is converted from an electrical signal to an optical signal by the transceiver 51 and then transmitted to each of the home side devices 61 to 6n via the optical branching unit 70.

  When the station side device 50 reproduces the reception clock signal RCLK synchronized with the reception signal Rx1 and performs retiming, it is preferable that the CDR circuit 54 has a burst correspondence function having a short synchronization pull-in time. A code pattern (synchronization pattern) for synchronization acquisition is occupied from the beginning of each burst period to the synchronization acquisition time. For this reason, by shortening the synchronization pull-in time, the proportion of synchronization patterns that cannot be used for data transfer can be shortened, and the efficiency of communication can be improved.

Shibata Zanmichi, Nakanishi Mamoru, Kitamura Mamoru, "Large-scale circuit design technology for communication systems", NTT Technical Journal 2011.1.1, pp.14 Hiroaki Katsurai, Hideki Kamitsuna, Hiroshi Koizumi, Jun Terada, Yusuke Ohtomo, and Tsugumichi Shibata, "AN INJECTION-CONTROLLED 10-GB / S BURST-MODE CDR CIRCUIT FOR A 1G / 10G PON SYSTEM", ITC-CSCC 2010, pp. 478-481 http://pdfserv.maximintegrated.com/en/an/A5203J.pdf, "Evaluation of optical receiver performance", Maxim Integrated

  However, in such a conventional technique, when a burst-corresponding CDR circuit is used as the CDR circuit 54 that performs retiming by reproducing the reception clock signal RCLK synchronized with the reception signal Rx1 in the station side device 50, the synchronization pull-in time However, there is a problem that the synchronization timing is slightly shifted, that is, jitter is increased.

In general, in the station side device, AC coupling is used for passing the upstream burst signal between circuits, and therefore the average direct current voltage of the upstream burst signal varies greatly in the no-signal period, and therefore, a certain amount of time from the start of the burst period. As a result, it is impossible to accurately receive the upstream burst signal, which affects the synchronization pull-in time.
According to the prior art, by reducing the time constant of AC coupling and shortening the time from the start of the burst period until it can be used to accurately receive the upstream burst signal, the synchronization pull-in time can be shortened. Yes.

  However, when the synchronization pull-in time is shortened by reducing the AC coupling time constant, the attenuation of the upstream burst signal in the AC coupling increases. For this reason, the jitter of the upstream burst signal increases due to the influence of amplitude noise, waveform distortion, etc. (see, for example, FIG. 7 in Non-Patent Document 2), and reception sensitivity degradation (see, for example, FIG. 9 in Non-Patent Document 3). ) And bit slip.

  An object of the present invention is to solve such a problem, and an object of the present invention is to provide a received signal processing technique capable of reducing the synchronization pull-in time without increasing jitter.

  In order to achieve such an object, a station-side device according to the present invention is a station-side device used in a PON system that performs optical communication between an office-side device and a plurality of home-side devices via an optical branching unit. An optical signal received from the home device is converted into a first received signal that is an electrical signal and output, and a transmission signal that is an electrical signal is input and converted into an optical signal to be converted into an optical signal. A non-signal period signal generation circuit for generating a no-signal period signal indicating a no-signal period in which the first reception signal is no signal in response to a signal disconnection of the optical signal, and the transmission signal No signal for generating an interpolation signal having the same clock frequency as the transmission signal and generating an interpolated reception signal obtained by interpolating the no signal period indicated by the no signal period signal of the first reception signal with the interpolation signal A period interpolation circuit; Reproduces the received clock signal synchronized with Masumi received signal, and a CDR circuit for outputting a second received signal retiming the interpolated received signal based on the received clock signal.

  Further, in the configuration example of the station side device, the no signal period interpolation circuit generates the interpolation signal by inverting the sign of the transmission signal as a circuit for generating the interpolation signal, and outputs the interpolation signal. Or a toggle flip-flop circuit that changes and outputs the sign of the interpolation signal each time the sign of the transmission signal or the transmission clock signal of the transmission signal changes in any one direction.

  Further, in the configuration example of the station side device, the no-signal period signal generation circuit is assigned in advance to the bit rate of the first reception signal and the burst period of the first reception signal. When the bit rates do not match, the no-signal period signal indicating the no-signal period is output.

  In addition, one configuration example of the station side device reproduces an intermediate clock signal synchronized with the interpolated reception signal, and outputs an intermediate CDR signal in which the interpolated reception signal is retimed based on the intermediate clock signal. The CDR circuit has a longer synchronization pull-in time than the intermediate CDR circuit, reproduces the second clock signal synchronized with the intermediate received signal, and generates the intermediate clock based on the second clock signal. The second received signal is output by retiming the received signal.

  The received signal processing method according to the present invention is a received signal processing method for a station-side device used in a PON system that performs optical communication via an optical branching device between a station-side device and a plurality of home-side devices. The optical signal received from the home side device is converted into a first reception signal that is an electrical signal and output, and a transmission signal that is an electrical signal is input and converted into an optical signal and transmitted to the home side device. An optical signal transmitting / receiving step, a no-signal period signal generating step for generating a no-signal period signal indicating a no-signal period in which the first received signal becomes no signal in response to a signal interruption of the optical signal, and the transmission signal To generate an interpolation signal having the same clock frequency as the transmission signal, and generate an interpolated reception signal obtained by interpolating the no-signal period indicated by the no-signal period signal of the first reception signal with the interpolation signal. Signal period interpolation And step, the regenerated reception clock signal synchronized with the interpolated received signal, and a CDR step of outputting a second received signal retiming the interpolated received signal based on the received clock signal.

According to the present invention, an interpolated signal having the same frequency as the upstream burst signal in the burst period is input to the CDR circuit in the no-signal period immediately before the burst period. For this reason, among the synchronization pull-in processing in the CDR circuit, the frequency synchronization processing can be greatly reduced, and the time until the subsequent phase synchronization processing is started can be shortened.
Therefore, since the attenuation of the upstream burst signal by AC coupling does not increase as in the case where the synchronization pull-in time is shortened by reducing the time constant of AC coupling used for delivery of the upstream burst signal, without increasing the jitter, Furthermore, the synchronization pull-in time can be shortened while suppressing the deterioration of reception sensitivity and the occurrence of bit slip.

It is a block diagram which shows the structure of the station side apparatus concerning 1st Embodiment. It is a timing chart which shows the clock reproduction | regeneration operation | movement of the station side apparatus concerning 1st Embodiment. It is a block diagram which shows the structure of the station side apparatus concerning 2nd Embodiment. It is a block diagram which shows the structure of the station side apparatus concerning 3rd Embodiment. It is a block diagram which shows the structure of the station side apparatus concerning 4th Embodiment. It is a block diagram which shows the structure of the station side apparatus concerning 5th Embodiment. It is a block diagram which shows a general PON system and a station side apparatus. It is a timing chart which shows the upstream burst signal in a general PON system.

Next, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
First, with reference to FIG. 1, the station side apparatus 10 concerning the 1st Embodiment of this invention is demonstrated. FIG. 1 is a block diagram illustrating a configuration of a station-side apparatus according to the first embodiment.

  The station side device 10 (OLT: Optical Line Terminal) performs optical communication with a plurality of home side devices (ONU: Optical Network Unit: not shown) via an optical branching device (not shown). An optical communication device used in a PON (Passive Optical Network) system, which obtains a reception signal from each upstream burst signal transmitted in time division from these home-side devices and reproduces a clock signal synchronized with the reception signal. In addition, this clock signal has a function of retiming and outputting the received signal.

  The station-side device 10 includes a transceiver 11, a no-signal period signal generation circuit 12, a no-signal period interpolation circuit 13, a CDR circuit 14, and a transmission / reception processing circuit 15 as main circuit units.

  The transceiver 11 converts the optical signal (upstream burst signal) received from the home-side device into an electrical signal, amplifies it, and outputs it as a received signal Rx1 (first received signal) that is an electrical signal whose amplitude has been regenerated. The transmission signal that is an electrical signal is input from the transmission / reception processing circuit 15 and converted into an optical signal (downstream burst signal) and transmitted to the home device.

  The no-signal period signal generation circuit 12 receives the reception signal Rx1 from the transceiver 11, detects the optical signal interruption of the received optical signal based on the amplitude level of the reception signal Rx1, and in the optical signal interruption period It has a function of generating a non-signal period signal NPS indicating a certain non-signal period NP.

  Based on the transmission signal Tx output from the transmission / reception processing circuit 15 to the transceiver 11, the no-signal period interpolation circuit 13 generates an interpolation signal NPI having the same clock frequency as the transmission signal Tx, and receives the reception signal Rx 1 from the transceiver 11. Has a function of generating an interpolated reception signal RxI obtained by interpolating the no-signal period NP included in the signal with the interpolation signal NPI.

  In a general PON system, the transmission signal Tx is always transmitted in common from the station side device 10 to a plurality of home side devices, and each home side device has its own self contained in the received transmission signal Tx. The transmission signal Tx addressed to itself is identified based on the LLID (Logical Link. ID). At this time, the transmission signal Tx is switched from the start time of the no-signal period to the bit rate assigned to the next burst period in synchronization with the end timing of the burst period. In the present invention, the interpolation signal NPI is generated by paying attention to such a transmission signal Tx.

The no-signal period interpolation circuit 13 is provided with a sign inverter 13A and a signal selector 13B as main circuit portions.
The sign inverter 13A has a function of generating an interpolation signal NPI having the same clock frequency as that of the transmission signal Tx by inverting the phase of the transmission signal Tx.
The signal selector 13B selects the interpolation signal NPI as the interpolated reception signal RxI when the no-signal period signal NPS indicates the no-signal period NP among the reception signal Rx1 and the interpolation signal NPI from the sign inverter 13A. When the non-signal period signal NPS indicates a period other than the no-signal period NP, the reception signal Rx1 is selectively output as the interpolated reception signal RxI.

  The CDR circuit 14 receives the interpolated reception signal RxI from the signal selector 13B and performs a synchronous pull-in operation to reproduce the reception clock signal RCLK synchronized with the interpolated reception signal RxI. The interpolated reception signal RxI is retimed using the clock signal RCLK to generate the reception signal Rx2, and the reception signal Rx2 and the reception clock signal RCLK are output.

  Based on the reception signal Rx2 and the reception clock signal RCLK from the CDR circuit 14, the transmission / reception processing circuit 15 performs various signal processing on the reception signal Rx2, and based on the bit rate previously assigned to each burst period, It has a function of generating a transmission signal Tx having the same clock frequency as the reception clock signal RCLK and outputting it to the transceiver 11 and the signal selector 13B of the no-signal period interpolation circuit 13.

[Operation of First Embodiment]
Next, with reference to FIG. 2, the operation | movement of the station side apparatus 10 concerning this Embodiment is demonstrated. FIG. 2 is a timing chart showing the clock recovery operation of the station side apparatus according to the first embodiment. Here, a case where the burst period BP1 is shifted to the burst period PB2 through the no-signal period NP will be described as an example.

The transceiver 11 converts an optical signal (upstream burst signal) received from the home device into an electrical signal, amplifies it, and outputs it as a received signal Rx1 that is an electrical signal whose amplitude has been recovered.
In FIG. 2, the received signal Rx1 has a considerable jitter, and is represented by a wide line width as a variation in rising and falling timing.
The reception signal Rx1 has an amplitude in the burst periods BP1 and BP2, and has no amplitude in the no-signal period NP.

The no-signal period signal generation circuit 12 receives the reception signal Rx1 from the transceiver 11, detects an optical signal interruption based on the amplitude level of the reception signal Rx1, and generates a no-signal period NP that is the optical signal interruption period. The no-signal period signal NPS shown is generated.
The no-signal period signal NPS has a value of “1” (no signal period NP) during the optical signal interruption period of the optical signal transmitted from the home-side apparatus, and the value during a period other than the optical signal interruption (during optical reception). This signal is “0” (reception period).

The sign inverter 13A inverts the phase of the transmission signal Tx to generate an interpolation signal NPI having the same clock frequency as that of the transmission signal Tx. As described above, the station-side device 10 transmits the transmission signal Tx having the same frequency as the reception signal Rx1. Therefore, the interpolation signal NPI has the same clock frequency not only for the transmission signal Tx but also for the reception signal Rx1.
The interpolation signal NPI is a signal obtained by inverting the sign of the transmission signal Tx. When the value of the transmission signal Tx is “1”, the interpolation signal NPI is “0”, and when the value of the transmission signal Tx is “0”, the interpolation signal The NPI is “1”.

The signal selector 13B selects and outputs the interpolation signal NPI as the interpolated reception signal RxI when the no-signal period signal NPS indicates the no-signal period NP among the reception signal Rx1 and the interpolation signal NPI. When NPS indicates a period other than the no-signal period NP, the reception signal Rx1 is selectively output as the interpolated reception signal RxI.
Therefore, the interpolated received signal RxI coincides with the interpolation signal NPI in the period in which the value of the no-signal period signal NPS is “1” (no-signal period NP), and the period in which the value of the no-signal period signal NPS is “0” ( It coincides with the reception signal Rx1 in the reception period).

The CDR circuit 14 receives the interpolated reception signal RxI from the signal selector 13B and performs a synchronous pull-in operation to reproduce the reception clock signal RCLK synchronized with the interpolated reception signal RxI.
The reception clock signal RCLK is a clock signal regenerated from the interpolated reception signal RxI. Since the phase of the interpolated reception signal RxI changes greatly at the boundaries of the burst period BP1, the no-signal period NP, and the burst period BP2, the reception clock signal RCLK in the synchronization pull-in period immediately after the boundary is timed from the boundary of each period. As time elapses, the phase gradually changes from a phase suitable for the signal before the boundary to a phase suitable for the signal after the boundary.

  In FIG. 2, a period indicated by hatching in the received clock signal RCLK represents a difference between the signal phase before the boundary and the signal phase after the boundary. In addition, since the signals in each of the burst periods BP1 and BP2 have considerable jitter, the reception clock signal RCLK also has jitter, and the line width is widened as variations in rising and falling timings. It is expressed by.

The CDR circuit 14 generates a reception signal Rx2 by retiming the interpolated reception signal RxI using the reception clock signal RCLK, and outputs the reception signal Rx2 and the reception clock signal RCLK.
The reception signal Rx2 is a signal obtained by retiming the interpolated reception signal RxI using the reception clock signal RCLK.

  In FIG. 2, during the synchronous pull-in period of the reception clock signal RCLK indicated by hatching, it cannot be normally retimed and includes many errors. Further, in each of the burst periods BP1 and BP2, since the reception clock signal RCLK used for retiming has jitter, the reception signal Rx2 also has the same jitter, so the reception clock signal RCLK also has jitter. The variation in the rise and fall timing is expressed by the width of the line.

[Effect of the first embodiment]
As described above, in the present embodiment, the no-signal period signal generation circuit 12 generates the no-signal period signal NPS indicating the no-signal period NP in which the first reception signal Rx1 becomes no signal in response to the signal interruption of the optical signal. The no-signal period interpolation circuit 13 generates an interpolation signal NPI having the same clock frequency as the transmission signal Tx from the transmission signal Tx, and the no-signal period NP indicated by the no-signal period signal NPS in the reception signal Rx1 The interpolated reception signal RxI interpolated with the interpolation signal NPI is generated, and the CDR circuit 14 reproduces the reception clock signal RCLK synchronized with the interpolated reception signal RxI, and regenerates the interpolated reception signal RxI based on the reception clock signal RCLK. The timed reception signal Rx2 is output.

As a result, the CDR circuit 14 receives the interpolation signal NPI having the same clock frequency as that of the upstream burst signal in the burst period BP2 in the no-signal period BP immediately before the burst period BP2. For this reason, among the synchronization pull-in processing in the CDR circuit 14, the frequency synchronization processing can be significantly reduced, and the time until the subsequent phase synchronization processing is started can be shortened.
Therefore, according to this embodiment, the attenuation of the upstream burst signal due to AC coupling does not increase as in the case where the time constant of AC coupling used for delivery of the upstream burst signal is reduced to shorten the synchronization pull-in time. Thus, the synchronization pull-in time can be shortened without increasing the jitter and further suppressing the deterioration of the reception sensitivity and the occurrence of the bit slip.

As a result, the proportion of the synchronization pattern that cannot be used for data transfer in the upstream burst signal can be shortened, and the communication efficiency can be improved.
At this time, if a certain degree of communication efficiency is obtained, the AC coupling time constant can be increased by the amount corresponding to the shortening of the synchronization pull-in time. Thereby, it is possible to suppress the jitter of the upstream burst signal while maintaining the synchronization pull-in time.

  Further, according to the present embodiment, the interpolation signal NPI can be generated with a very simple circuit configuration of the sign inverter 13A using the transmission signal Tx, and the circuit scale and power consumption are hardly increased. At this time, the transmission signal Tx can be used as it is as the interpolation signal NPI. However, in the circuit block subsequent to the station side device 10, the interpolation signal NPI composed of the transmission signal Tx having the same code string format as the reception signal Rx1. Entering may cause malfunction. In the present embodiment, since the interpolation signal NPI is generated by inverting the sign of the transmission signal Tx by the sign inverter 13A, it is possible to avoid the occurrence of malfunction.

  When an interpolation signal NPI having a transmission signal Tx having the same code string format as the reception signal Rx1 is input to the transmission / reception processing circuit 15, the interpolation signal NPI is included in the interpolation signal NPI by processing the interpolation signal NPI as the reception signal Rx1. The received transmission frame is received as a reception frame. Since this transmission frame has a destination address that is not expected to be received, it is normally discarded. When the problem is that the original received frame included in the upstream burst signal is discarded, there is a possibility that the problem may be overlooked due to the generation of the discarded transmission frame.

  Further, when the interpolation signal NPI composed of the transmission signal Tx having the same code string format as the reception signal Rx1 is input to the circuit that performs code synchronization by detecting the code-code boundary from the bit string based on the code string format, Code synchronization synchronized with the interpolation signal NPI is performed. However, even if an upstream burst signal is input during code synchronization with the interpolated signal NPI, there is a protection period for preventing the code synchronization from being lost due to the occurrence of an error during transmission until it is determined that the code synchronization is lost. Code synchronization for the upstream burst signal is not established until the period ends. For this reason, there is a possibility that a problem arises because the code synchronization for the upstream burst signal is delayed by the protection time.

  In IEEE802.3av (10G-EPON), the burst delimiter pattern is detected to detect the subsequent signal, but the burst delimiter pattern in the transmission signal Tx is, for example, 2-64. Since it occurs only with a very small probability, the transmission signal Tx can be used as it is as the interpolation signal NPI. In such a case, the configuration may be such that the sign inverter 13A is excluded from the present embodiment. In other words, the no-signal period interpolation circuit 13 includes a signal selector 13B, and the interpolated received signal RxI is equal to the transmission signal Tx in the period (the no-signal period NP) in which the value of the no-signal period signal NPS is “1”. Then, the value of the non-signal period signal NPS coincides with the reception signal Rx1 in the period (reception period) where the value is “0”.

  Further, according to the present embodiment, since the clock frequency of the interpolation signal NPI and the clock frequency of the upstream burst signal are the same frequency, the CDR circuit 14 can perform the upstream burst signal in the burst period in a state of frequency synchronization. Will start receiving. As a result, the CDR circuit 14 only needs to align the phase of the reception clock signal RCLK generated for the upstream burst signal, and the synchronization pull-in time can be shortened.

Therefore, even if a signal synchronized with a clock source different from the upstream burst signal is input to the CDR circuit 14 in the no-signal period NP, there is little effect of shortening the synchronization pull-in time. (Burst signal) Since the downstream signal is input to the CDR in the no-signal period NP by utilizing the fact that the clock frequency of the Tx and the upstream burst signal are the same frequency, the effect of shortening the synchronization pull-in time is obtained. be able to.
In particular, the home device of the PON system generates an uplink signal in synchronization with the clock signal of the downlink signal and sends it to the station device 10, so the clock signal of the uplink signal and the clock signal of the downlink signal are: If the frequency division ratio is 1, the same frequency is obtained.

  Further, in the case of a configuration in which a dummy signal synchronized with the reception clock signal RCLK generated by the CDR circuit 14 is generated and input to the CDR circuit 14 during the no-signal period NP, the CDR circuit 14 outputs the upstream burst signal as the no-signal period NP. There is no problem as long as the clock frequency extracted from is long enough to hold the clock frequency. However, as a compensation for shortening the synchronization pull-in time, the jitter of the reception clock signal RCLK to be generated becomes large. Therefore, the jitter accumulates in the no-signal period NP, and the clock frequency shifts as the no-signal period NP becomes longer. There arises a problem that the synchronization pull-in time increases.

At this time, the phase of the clock signal needs to be aligned with the upstream burst signal when the dummy signal is switched to the upstream burst signal. Therefore, in order to reduce the phase alignment time, the CDR circuit for continuous signals is used. However, a CDR circuit having a characteristic that the synchronization pull-in time is short is required.
On the other hand, in the present embodiment, a downstream signal having the same clock frequency as that of the upstream burst signal is used as an input to the CDR circuit 14 in the no-signal period. The clock frequency does not differ from the clock signal of the upstream burst signal.

The exclusive OR of the dummy signal and the upstream burst signal described above is taken by the EXOR circuit, and further, the exclusive logical sum of the dummy signal and the dummy signal is taken again by the EXOR circuit before the reception processing is performed. A configuration is also conceivable in which a malfunction due to a dummy signal is suppressed by removing the dummy signal before reception processing.
Similarly to this configuration, when the EXOR circuit is applied to the present embodiment, the EXOR circuit takes an exclusive OR of the downlink burst signal and the uplink burst signal, passes the CDR to the signal, and again outputs the downlink signal at the EXOR circuit. Is taken back to the upstream burst signal.

  However, if the phases and clock frequencies of the upstream burst signal and downstream burst signal do not match, the output of the CDR circuit 14 that outputs data after retiming is returned to the upstream signal even if exclusive OR with the downstream signal is taken. It is not possible. In the configuration in which only the clock signal is extracted by the PLL instead of the CDR circuit 14, the clock signal can be reproduced by inputting the exclusive OR of the downstream signal and the upstream signal to the PLL by the EXOR circuit. If the clock frequency of the upstream signal and downstream signal do not match, the PLL will output a clock frequency that is intermediate between the upstream signal and downstream signal, and thus will not operate correctly.

  Therefore, the above configuration cannot be applied to this embodiment as it is. In this embodiment, a downlink burst signal is selected in the no-signal period NP, and an uplink burst signal is selected in a period other than the no-signal period NP. It is necessary that the downstream burst signal and upstream burst signal masked (fixed to 0) other than the no-signal period PN are input to the EXOR circuit and this output is input to the CDR circuit 14 so as to be a circuit that performs this operation. is there.

[Second Embodiment]
Next, with reference to FIG. 3, the station side apparatus 10 concerning the 2nd Embodiment of this invention is demonstrated. FIG. 3 is a block diagram illustrating a configuration of a station-side apparatus according to the second embodiment.

  In the PON system, the transmission timing (burst period) and transmission data amount (bandwidth) of the uplink burst signal transmitted from each home side device are determined by the station side device 10 and assigned to each home side device by the GATE frame. Here, there are a plurality of bit rates of the upstream burst signal transmitted from the home side device to the station side device 10, and it is determined in advance which bit rate is used according to the home side device.

  For this reason, the station side device 10 receives an optical signal in which the bit rate of a certain burst period is different from the bit rate of another burst period, and retimates the received signal Rx1 in accordance with each bit rate. . Therefore, for example, even when a signal cannot be transmitted at a regular bit rate at a regular transmission timing due to a failure of the home device, the bit rates do not match.

In the present embodiment, the transmission / reception processing circuit 15 preliminarily sends to the home device at the transmission source in synchronization with the reception timing of each reception signal Rx1, based on the value of the internal timer for the PON system used for the control of the PON system. It has a function of outputting a rate selection signal RSEL indicating the assigned bit rate.
The no-signal period signal generation circuit 12 receives the reception signal Rx1 and the rate selection signal RSEL, and in addition to the period indicating the optical signal interruption, the bit rate and rate of the reception signal Rx1 that the CDR circuit 14 should retime. When the bit rate indicated by the selection signal RSEL does not match, it has a function of outputting the no-signal period signal NPS. Note that the bit rate of the reception signal Rx1 may be extracted from the reception signal Rx1, or may be received from another circuit such as the CDR circuit 14.

The no-signal period interpolation circuit 13 has a toggle flip-flop circuit 13C instead of the sign inverter 13A. The toggle flip-flop circuit 13C receives the transmission signal Tx, and triggered by either a change from “0” to “1” or a change from “1” to “0” of the sign of the transmission signal Tx. It has a function of generating and outputting an interpolation signal NPI by inverting the sign of the signal being output.
Other configurations according to the present embodiment are the same as those of the first embodiment, and a description thereof is omitted here.

  The difference from the first embodiment is that when the bit rate of the reception signal Rx1 and the bit rate indicated by the rate selection signal RSEL do not match, the no-signal period interpolation circuit 13 does not detect the The same operation as in the period NP is performed.

That is, the no-signal period interpolation circuit 13 inputs the reception signal Rx1 to the CDR circuit 14 during a period in which the reception signal Rx1 is received at a bit rate different from the bit rate handled by the CDR circuit 14 indicated by the rate selection signal RSEL. Instead, the interpolation signal NPI is input instead.
As a result, the interpolation signal NPI having the same frequency as that of the transmission signal Tx is input to the CDR circuit 14 during a period in which the reception signal Rx1 having a bit rate different from the bit rate indicated by the rate selection signal RSEL is received.

  For this reason, the CDR circuit 14 starts to receive the upstream burst signal in the burst period in a state where the frequency synchronization is established, as in the case of shifting from the optical signal interruption period to the burst period. Therefore, it is possible to prevent the frequency of the reception clock signal RCLK being reproduced from greatly deviating from the original clock frequency of the reception signal Rx1.

On the other hand, in the conventional configuration shown in FIG. 7 described above, during the period in which signals of different bit rates are input, the synchronization pull-in fails or the clock frequency is different from the original clock frequency. The difference from the original frequency of the clock signal becomes large. For this reason, the frequency is greatly deviated at the time when reception of the signal of the bit rate to be reproduced is started.
Accordingly, the synchronization pull-in time is shorter in the configuration according to the present embodiment than in the conventional configuration.

[Effect of the second embodiment]
As described above, in the present embodiment, the no-signal period signal generation circuit 12 is assigned in advance to the bit rate of the reception signal Rx1 transmitted from the home-side apparatus and the burst period BP in which the reception signal Rx1 is transmitted. When the two bit rates do not match, a no-signal period signal NPS indicating the no-signal period NP is output.

For this reason, even when shifting from a state in which both bit rates do not match to a state in which they match, the CDR circuit 14 in the burst period is in a state of frequency synchronization, as in the case of shifting from the optical signal interruption period to the burst period. The reception of the upstream burst signal is started. Therefore, it is possible to prevent the frequency of the reception clock signal RCLK being reproduced from greatly deviating from the original clock frequency of the reception signal Rx1.
Therefore, even when shifting from a state where both bit rates do not match to a state where they match, it is possible to shorten the synchronization pull-in time without increasing jitter and further suppressing deterioration of reception sensitivity and occurrence of bit slip. it can.

  Further, according to the present embodiment, the interpolation signal NPI can be generated with a very simple circuit configuration called the toggle flip-flop circuit 13C using the transmission signal Tx, and the circuit scale and power consumption are hardly increased. At this time, as in the case of using a signal obtained by inverting the sign of the transmission signal Tx, the interpolated signal NPI having a code string format different from the received signal Rx1 in the circuit block subsequent to the station side device 10 is A malfunction in a subsequent circuit block can be prevented.

  In the present embodiment, the no-signal period signal generation circuit 12 generates the rate selection signal RSEL generated based on the received signal Rx1 and the value of the internal timer for the PON system (the bit rate allocation content for each burst period). From the above, the no-signal period signal NPS is generated, but a configuration in which the no-signal period signal NPS is generated based only on the value of the internal timer for the PON system is also possible.

  The no-signal period signal NPS may be the same as a general LOS signal used in a normal optical communication device. However, the delay from the start of reception until the no-signal period signal NPS is deasserted, that is, the delay until the value of the no-signal period signal NPS changes from “1: optical signal interruption” to “0: optical reception in progress” This is a delay in switching from the interpolation signal NPI to the upstream burst signal. For this reason, the synchronization pull-in time is increased by this delay. Therefore, in this embodiment, the smaller the delay from the start of reception until the no-signal period signal generation circuit 12 deasserts the no-signal period signal NPS, the greater the effect of reducing the synchronization pull-in time.

In the present embodiment, since the interpolation signal NPI is generated by the toggle flip-flop circuit 13C using the transmission signal Tx, the following effects can be obtained.
In the circuit that performs code synchronization with respect to the 8B / 10B code, the comma pattern “1000001” or “0111110” is detected from the bit string, and code synchronization is performed based on this detection position. In addition, even if a comma pattern is detected at a position different from the current code synchronization, this circuit does not immediately reset the code synchronization, but resets the code synchronization when the comma pattern is detected multiple times. Process.

  Therefore, even if a signal obtained by bit-inversion of the transmission signal Tx is used as the interpolation signal NPI, a comma pattern is included in the interpolation signal NPI. Therefore, the interpolation signal NPI is converted from the transmission signal Tx using a toggle flip-flop circuit cascaded in three stages. The structure which produces | generates is required. When the interpolation signal NPI is generated using a toggle flip-flop circuit cascaded in three stages, no comma pattern is generated because at least eight “0” s or “1” s continue.

[Third Embodiment]
Next, with reference to FIG. 4, the station side apparatus 10 concerning the 3rd Embodiment of this invention is demonstrated. FIG. 4 is a block diagram illustrating a configuration of a station-side apparatus according to the third embodiment.

  In the present embodiment, the intermediate CDR circuit 14M receives the interpolated reception signal RxI, reproduces the intermediate clock signal MCLK synchronized with the interpolated reception signal RxI, and uses the intermediate clock signal MCLK to interpolate the reception signal after interpolation. It has a function of generating and outputting an intermediate received signal RxM by retiming RxI.

  The CDR circuit 14 has a longer synchronization pull-in time than the intermediate CDR circuit 14M, receives the intermediate reception signal RxM, reproduces the reception clock signal RCLK synchronized with the intermediate reception signal RxM, and uses the reception clock signal RCLK. The intermediate reception signal RxM has a function of generating a reception signal Rx2 by retiming and outputting the reception signal Rx2 and the reception clock signal RCLK.

  The difference from the first embodiment is that an intermediate CDR circuit 14M is provided in the preceding stage of the CDR circuit 14 of FIG. At this time, the CDR circuit 14 is set to have a longer synchronization pull-in time than the intermediate CDR circuit 14M, so that the effect of reducing jitter is high. As a result, the jitter of the received signal Rx2 is greatly reduced in the CDR circuit 14, so that a problem due to jitter in the transmission / reception processing circuit 15 can be prevented.

[Effect of the third embodiment]
As described above, this embodiment reproduces the intermediate clock signal MCLK synchronized with the interpolated reception signal RxI, and outputs an intermediate reception signal RxM obtained by retiming the interpolated reception signal RxI based on the intermediate clock signal MCLK. The CDR circuit 14M is further provided. The CDR circuit 14 has a longer synchronization pull-in time than the intermediate CDR circuit 14M, reproduces the reception clock signal RCLK synchronized with the intermediate reception signal RxM, and receives the intermediate reception signal based on the reception clock signal RCLK. The reception signal Rx2 is output by retiming RxM.

  Therefore, in the intermediate CDR circuit 14M, the synchronization acquisition is performed with a short synchronization acquisition time, and the jitter is effectively reduced in the CDR circuit 14 having a longer synchronization acquisition time than the intermediate CDR circuit 14M. As a result, the jitter of the reception signal Rx2 can be significantly reduced without increasing the synchronization pull-in time, and problems due to jitter in the transmission / reception processing circuit 15 can be prevented.

  Further, although the intermediate CDR circuit 14M has a short synchronization pull-in time, the effect of reducing the jitter of the intermediate clock signal MCLK output from the intermediate CDR circuit 14M is small. Therefore, if the input level of the optical signal is reduced, the jitter of the received signal Rx1 increases. In the intermediate CDR circuit 14M, a bit slip may occur. However, the correct reception clock signal RCLK can be reproduced by performing retiming again with the reception clock signal RCLK with small jitter by the CDR circuit 14. This is because the jitter of the intermediate clock signal MCLK reproduced by the upstream intermediate CDR circuit 14M can be filtered by the downstream CDR circuit 14. With retiming, it is difficult to restore the lost bits correctly, but since the erroneous code can be corrected by the code error correction function in the transmission / reception processing circuit 15 at the subsequent stage, it is not a serious problem.

  The CDR circuit 14 has a characteristic that the synchronization pull-in time is long, but the intermediate reception signal RxM output from the intermediate CDR circuit 14M is a continuous signal that does not need to be synchronized every burst period BP. That is, the interpolation signal NPI is inserted in the no-signal period NP between the burst period BP and the burst period BP, and the steep generated at the boundary between the burst period BP and the no-signal period BP by the intermediate CDR circuit 14M. Since the intermediate reception signal RxM whose phase change has been relaxed is input to the CDR circuit 14, no loss of synchronization occurs in the CDR circuit 14.

  Therefore, it is not necessary to extend the length of the synchronization pattern for the upstream burst signal in accordance with the characteristics of the CDR circuit 14, and the synchronization pattern length can be adjusted to the short synchronization pull-in time based on the characteristics of the intermediate CDR circuit 14M. Therefore, the proportion of synchronization patterns that cannot be used for data transfer can be shortened, and communication efficiency can be improved.

  On the other hand, in the conventional configuration shown in FIG. 7, since it is necessary to perform synchronization pull-in every time the burst period BP starts, in order not to reduce communication efficiency, the CDR circuit 54 has a short synchronization pull-in time, but reduces jitter. It is necessary to make the characteristics low in effect. For this reason, in the transmission / reception processing circuit 55 in the subsequent stage, a problem may occur due to the jitter of the reception clock signal RCLK and the reception signal Rx2 output from the CDR circuit 54.

  Further, in the conventional configuration of FIG. 7, when the input level of the optical signal is reduced, the jitter of the received signal Rx1 increases, and there is a possibility that bit slip occurs in the CDR circuit. When a bit slip occurs, the error cannot be corrected even by the code error correction function in the transmission / reception processing circuit 55 in the subsequent stage, causing a problem that a large amount of received data is lost, and the reception sensitivity is deteriorated.

  In this embodiment, a PLL circuit for reducing the jitter of the intermediate clock signal MCLK generated by the intermediate CDR circuit 14M may be used instead of the CDR circuit 14. Specifically, the intermediate CDR circuit 14M outputs an intermediate clock signal MCLK synchronized with the intermediate reception signal RxM together with the intermediate reception signal RxM, inputs the intermediate clock signal MCLK to the PLL circuit, and the PLL circuit outputs the intermediate clock signal. What is necessary is just to make it output as the receiving clock signal RCLK which reduced the jitter contained in MCLK.

[Fourth Embodiment]
Next, with reference to FIG. 5, the station side apparatus 10 concerning the 4th Embodiment of this invention is demonstrated. FIG. 5 is a block diagram illustrating a configuration of a station-side device according to the fourth embodiment.
In each of the embodiments described above, the interpolation signal NPI is generated using the transmission signal Tx. However, the interpolation signal NPI is changed using the transmission clock signal TCLK synchronized with the transmission signal Tx instead of the transmission signal Tx. It is also possible to generate.

In FIG. 5, the transmission clock signal TCLK output from the transmission / reception processing circuit 15 is input to the toggle flip-flop circuit 13 </ b> C of the no-signal period interpolation circuit 13 instead of the transmission signal Tx, using FIG. 3 as an example. Yes.
The toggle flip-flop circuit 13C receives the transmission clock signal TCLK and is triggered by either a change from “0” to “1” or a change from “1” to “0” of the transmission clock signal TCLK. Furthermore, it has a function of generating and outputting an interpolation signal NPI by inverting the sign of the signal being output.

[Effect of the fourth embodiment]
Thus, in this embodiment, the interpolation signal NPI is generated using the transmission clock signal TCLK synchronized with the transmission signal Tx.
In the circuit block subsequent to the station-side device 10, there is a possibility of malfunction by inputting the interpolation signal NPI that is the transmission signal Tx having the same code string format as the reception signal Rx1. For this reason, when the interpolation signal NPI is generated based on the transmission signal Tx, the interpolation signal NPI that has been processed so as not to cause a malfunction in the transmission signal Tx is used.

In the third embodiment described above, the case where the interpolation signal NPI is generated by using the toggle flip-flop circuit 13C cascade-connected in three stages to the transmission signal Tx encoded by 8B / 10B has been described as an example.
In this embodiment, a simple signal pattern in which “0” / “1” obtained by inputting the transmission clock signal TCLK to one toggle flip-flop circuit is switched every clock cycle is used as the interpolation signal NPI. If this pattern is not a pattern that causes a malfunction, it can be realized by an extremely simple circuit of one toggle flip-flop circuit, so that the circuit scale can be reduced.

[Fifth Embodiment]
Next, with reference to FIG. 6, the station side apparatus 20 concerning the 5th Embodiment of this invention is demonstrated. FIG. 6 is a block diagram illustrating a configuration of a station-side device according to the fifth embodiment.
In the above embodiment, the configuration in which the CDR circuit 14 is switched at the bit rate of the reception signal Rx1 has been described as an example. In the present embodiment, a station side device 20 in which station side modules are arranged in parallel for different bit rates will be described.

In this station side device 20, two station side modules 10A and 10B are arranged in parallel corresponding to the bit rate of 1 Gbit / s for GE-PON and the bit rate of 10 Gbit / s for 10G-EPON. The received signal Rx1 obtained by converting the optical signal received from the home device by the transceiver 11 into an electric signal is distributed to the station side modules 10A and 10B.
At this time, since the received signal Rx1 is equally distributed to these station side modules 10A and 10B, each station side module 10A and 10B receives itself depending on the communication timing assigned to each home device. A reception signal Rx1 having a bit rate different from the bit rate to be processed is received.

In the present embodiment, as the station side modules 10A and 10B, each module uses the circuit configuration excluding the transceiver 11 from the station side apparatus 10 according to the second or fourth embodiment described above, and each module performs reception processing. For the reception signal Rx1 having a bit rate other than the bit rate to be used, the interpolation signal NPI is output to the CDR circuit 14 during the reception period.
Specifically, in the station side modules 10A and 10B, the no-signal period signal generation circuit 12 compares the bit rate detected from the received signal Rx1 with the bit rate indicated by the rate selection signal RSEL, and the bit rates do not match. In this case, the no-signal period signal NPS is output in the same manner as the optical signal interruption period.

Accordingly, the no-signal period signal generation circuit 12 of the station side module 10A corresponding to the bit rate of 1 Gbit / s is the same as the optical signal interruption period when the bit rate of the reception signal Rx1 is 10 Gbit / s instead of 1 Gbit / s. In addition, a no-signal period signal NPS is output.
As a result, in the station side module 10A, a 1 Gbit / s interpolation signal NPI having the same frequency as the transmission signal Tx is output to the CDR circuit 14 from the no-signal period interpolation circuit 13 instead of the 10 Gbit / s reception signal Rx1. Is done. Therefore, the CDR circuit 14 can start reception of the upstream burst signal in the burst period in a state where the frequency is synchronized, and the frequency of the reception clock signal RCLK being reproduced is the original clock of the reception signal Rx1. It can be prevented from greatly deviating from the frequency.

Further, the no-signal period signal generation circuit 12 of the station side module 10B corresponding to the 10 Gbit / s bit rate is the same as the optical signal interruption period when the bit rate of the reception signal Rx1 is 1 Gbit / s instead of 10 Gbit / s. In addition, a no-signal period signal NPS is output.
As a result, a 10 Gbit / s interpolation signal NPI having the same frequency as the transmission signal Tx is output to the CDR circuit 14 from the no signal period interpolation circuit 13 of the station side module 10A, instead of the 1 Gbit / s reception signal Rx1. . Therefore, the CDR circuit 14 can start reception of the upstream burst signal in the burst period in a state where the frequency is synchronized, and the frequency of the reception clock signal RCLK being reproduced is the original clock of the reception signal Rx1. It can be prevented from greatly deviating from the frequency.

  Therefore, station-side modules 10A and 10B are provided in parallel for each different bit rate, and these station-side modules 10A and 10B receive signal Rx1 having a bit rate different from the bit rate that they should receive depending on the burst period. The CDR circuit 14 can start receiving the upstream burst signal in a state where the frequency synchronization is established. As a result, the synchronization pull-in time can be shortened without increasing the jitter and further suppressing the deterioration of reception sensitivity and the occurrence of bit slip.

[Extended embodiment]
The present invention has been described above with reference to the embodiments, but the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention. In addition, each embodiment can be implemented in any combination within a consistent range.

In the first and second embodiments, the case where the sign inverter 13A is used when generating the interpolation signal NPI from the transmission signal Tx has been described as an example. However, the present invention is not limited to this. The interpolation signal NPI may be generated by using the toggle flip-flop circuit 13C of the fourth and fifth embodiments.
On the contrary, in the second, fourth, and fifth embodiments, a sign inverter 13A may be used instead of the toggle flip-flop circuit 13C. At this time, there may be a case where the code synchronization is temporarily lost as described above, but the synchronization pull-in time can be greatly shortened as described above.

  DESCRIPTION OF SYMBOLS 10,20 ... Station side apparatus, 10A, 10B ... Station side module, 11 ... Transceiver, 12 ... No signal period signal generation circuit, 13 ... No signal period interpolator, 13A ... Sign inverter, 13B ... Signal selector, 13C ... Toggle flip-flop, 14 ... CDR circuit, 14M ... Intermediate CDR circuit, 15 ... Transmission / reception processing circuit, Rx1 ... Reception signal (first reception signal), NPS ... Non-signal period signal, NPI ... Interpolation signal, RxI ... Interpolated Reception signal, RxM: intermediate reception signal, MCLK: intermediate clock signal, Rx2: reception signal (second reception signal), RCLK: reception clock signal, Tx: transmission signal, TCLK: transmission clock signal, RSEL: rate selection signal.

Claims (5)

A station-side device used in a PON system that performs optical communication via an optical branching device between a station-side device and a plurality of home-side devices,
A transceiver that converts an optical signal received from the home-side device into a first received signal that is an electrical signal and outputs the first received signal, converts a transmission signal that is an electrical signal into an optical signal, and transmits the optical signal to the home-side device When,
A no-signal period signal generation circuit that generates a no-signal period signal indicating a no-signal period in which the first reception signal is no signal in response to a signal interruption of the optical signal;
An interpolation signal having the same clock frequency as the transmission signal is generated from the transmission signal, and an interpolated reception signal obtained by interpolating the no-signal period indicated by the no-signal period signal among the first reception signals by the interpolation signal A no-signal period interpolator to generate,
And a CDR circuit that reproduces a reception clock signal synchronized with the interpolated reception signal and outputs a second reception signal obtained by retiming the interpolated reception signal based on the reception clock signal. apparatus. In the station side apparatus of Claim 1,
The no-signal period interpolation circuit is a circuit that generates the interpolation signal, a code inverter that generates and outputs the interpolation signal by inverting the sign of the transmission signal, or the transmission signal or the transmission signal. A station-side apparatus comprising a toggle flip-flop circuit that changes and outputs the sign of the interpolation signal every time the sign of the transmission clock signal changes in any one direction. In the station side apparatus of Claim 1 or Claim 2,
The no-signal period signal generation circuit compares the bit rate of the first received signal with a bit rate previously assigned to the burst period of the first received signal, and the bit rates do not match A station-side apparatus that outputs the no-signal period signal indicating the no-signal period. In the station side apparatus as described in any one of Claims 1-3,
An intermediate CDR circuit for reproducing an intermediate clock signal synchronized with the interpolated reception signal and outputting an intermediate reception signal obtained by retiming the interpolated reception signal based on the intermediate clock signal;
The CDR circuit has a longer synchronization pull-in time than the intermediate CDR circuit, regenerates the second clock signal synchronized with the intermediate received signal, and retimes the intermediate received signal based on the second clock signal. By doing so, the second received signal is output. A received signal processing method for a station-side device used in a PON system that performs optical communication via an optical branching device between a station-side device and a plurality of home-side devices,
Light that is converted from an optical signal received from the home-side device into a first received signal that is an electrical signal and then output, and a transmission signal that is an electrical signal is input and converted into an optical signal that is transmitted to the home-side device A signal transmission and reception step;
A no-signal period signal generating step for generating a no-signal period signal indicating a no-signal period in which the first received signal becomes no signal in response to the signal interruption of the optical signal;
An interpolation signal having the same clock frequency as the transmission signal is generated from the transmission signal, and an interpolated reception signal obtained by interpolating the no-signal period indicated by the no-signal period signal among the first reception signals by the interpolation signal A no-signal period interpolation step to generate;
A CDR step of reproducing a reception clock signal synchronized with the interpolated reception signal and outputting a second reception signal obtained by retiming the interpolated reception signal based on the reception clock signal. Processing method.

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