JP2014103210A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device which can form a through electrode on a thick semiconductor substrate for MEMS application with high throughput, and to provide a semiconductor device obtained thereby.SOLUTION: In an embodiment, a method for manufacturing a semiconductor device comprises: a first through hole formation process S1; a second through hole formation process S2; and a plating process S3. The first through hole formation process S1 is a process for forming a first through hole piercing a first semiconductor substrate such that a diameter gradually decreases from an outside surface toward an inside surface of the first semiconductor substrate. The second through hole formation process S2 is a process of forming a second through hole piercing an insulation layer and a second semiconductor substrate, after the first through hole formation process S1, such that a diameter gradually increases from a bottom of the first through hole toward an outside surface of the second semiconductor substrate. The plating process S3 is a process for forming a through electrode by performing metal plating on the first through hole and the second through hole.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device in which a through electrode is formed on a semiconductor substrate having a thick SOI (Silicon on Insulator) structure that is often used in MEMS applications and the like, and a manufacturing method thereof. .

Conventionally, a semiconductor device has been formed on the front surface or the back surface of a semiconductor substrate and wired by wire bonding. In recent years, semiconductor devices such as semiconductor memories have a structure that is three-dimensionally mounted as the size and capacity increase.
Here, when a semiconductor device is mounted three-dimensionally, as a result of an increase in wiring length in the thickness direction, signal delay due to wiring has become prominent, and speeding up of operation speed and signal transmission is required. Yes.

Therefore, in order to shorten the wiring length and avoid signal delay, a semiconductor device mounting structure called flip-chip mounting in which the electrodes of the semiconductor device are directly connected to the mounting substrate has been used. .
However, even in the flip-chip mounting method, the semiconductor devices are once electrically connected via the mounting substrate, so that the length of the wiring is increased to some extent.

Therefore, in order to further shorten the wiring length and avoid signal delay, a through hole is formed in the semiconductor device, a through electrode is formed by metal plating on the through hole, and the semiconductor device is laminated in three dimensions. The technique to do is disclosed (for example, refer patent document 1).
In forming such a through electrode, a vertical shape or a tapered shape (see, for example, Patent Document 2) is often applied as a cross-sectional shape of the through hole.

JP 05-63137 A JP 2001-44197 A

  However, in the case of forming a vertical through electrode, a stable insulating layer or seed for securing an insulating state with respect to an electrode on an SOI substrate or a thick semiconductor substrate often used in MEMS applications. Formation of the layer is difficult. In the case of forming a vertical through electrode, if the vertical shape has a high aspect ratio during metal plating, voidless filling is difficult and there is room for improvement.

  Also, in the case of forming a tapered through electrode, as in the case of forming a vertical through electrode, the conditions for etching a thick film wafer into a tapered shape are those with a very low selectivity. Therefore, in general mask materials (resist, oxide film, metal, etc.), it is very difficult to etch a high aspect ratio taper shape, and there is room for improvement.

  As a measure against the above selection ratio, it is conceivable to increase the thickness of the resist. However, increasing the thickness of the resist increases the internal stress, which increases the possibility of causing a problem that the resist itself cracks. . Therefore, to suppress cracking of the resist, it is conceivable to increase the pre-baking temperature. However, if the pre-baking temperature is too high, patterning is difficult in the next exposure and development processes. There is a risk of inviting.

Furthermore, in the technique disclosed in Patent Document 2, the cross-sectional area of the through electrode formed on the thin-film semiconductor substrate changes in the thickness direction (preferably, it has a small cross-sectional area partway in the thickness direction). It is characterized by forming as follows. However, since the technique disclosed in Patent Document 2 forms through holes from the front and back surfaces of the thin-film semiconductor substrate, there is a possibility that work efficiency may be reduced.
Accordingly, the present invention has been made paying attention to the above-mentioned problems, and the object thereof is to form a through-hole electrode that enables metal voidless filling of a thick semiconductor substrate for MEMS use with high throughput. Another object of the present invention is to provide a method for manufacturing a semiconductor device and a semiconductor device obtained thereby.

In order to solve the above-mentioned problem, the present inventor has made extensive studies, and as a result, a through hole is formed with a forward taper from one surface of a semiconductor substrate, and a through hole is formed with a reverse taper from the bottom of the through hole. It has been found that it is possible to form a through-hole which can be easily filled with a voidless material and formed with an insulating layer and can be formed easily.
This invention is based on the said knowledge by this inventor, and the manufacturing method of the semiconductor device of the aspect with this invention for solving the said subject is a 1st semiconductor substrate and a 2nd semiconductor substrate. A method of manufacturing a semiconductor device, wherein a through electrode is formed in a semiconductor substrate laminated via
A first through-hole forming step of forming a first through-hole penetrating the first semiconductor substrate so that the diameter decreases from the outer surface of the first semiconductor substrate toward the inner surface;
After the first through-hole forming step, a second through-hole penetrating the insulating layer and the second semiconductor substrate so that the diameter increases from the bottom of the first through-hole toward the outer surface of the second semiconductor substrate. A second through-hole forming step of forming
A plating step of performing metal plating on the first through hole and the second through hole to form a through electrode.

  According to another aspect of the present invention, there is provided a semiconductor device manufacturing method including the above-described steps, whereby a through-electrode having a drum-shaped (hourglass-shaped) cross-sectional shape with respect to a thick-film SOI wafer for MEMS applications. Can be manufactured with high throughput. This is because the technique disclosed in Patent Document 2 described above is a process of forming a through hole by similarly performing taper processing for reducing the diameter from both sides of a semiconductor substrate, and filling the metal with one of the processes. This is because a drum-shaped through hole is formed in the direction and filled with metal.

  In particular, since the cross-sectional shape of the through hole is a drum shape, stable film formation with good uniformity can be performed by, for example, a sputtering apparatus or the like in the insulating layer forming step of forming the insulating layer after the through hole is formed. Further, in the metal plating step after the formation of the through hole, a bottom is formed at a location where the intermediate cross-sectional area is small, and the plating proceeds upward and downward from there, so that high-speed filling and voidless filling are possible.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, wherein a through electrode is formed on a semiconductor substrate in which a first semiconductor substrate and a second semiconductor substrate are stacked via an insulating layer. A first through hole forming step of forming a first through hole penetrating the first semiconductor substrate and the insulating layer so that the diameter decreases from the outer surface of the first semiconductor substrate toward the inner surface; After the first through-hole forming step, a second through-hole that penetrates the second semiconductor substrate is formed so that the diameter increases from the bottom of the first through-hole toward the outer surface of the second semiconductor substrate. 2 through-hole formation process, and the plating process which metal-plates to the said 1st through-hole and the said 2nd through-hole, and forms a through-electrode.

Here, the film forming process for forming the metal film or the oxide film on the outer surface of the second semiconductor substrate may be performed between the first through hole forming process and the second through hole forming process.
The semiconductor device according to an aspect of the present invention is a semiconductor device in which a through electrode is formed on a semiconductor substrate in which a first semiconductor substrate and a second semiconductor substrate are stacked with an insulating layer interposed therebetween. The intermediate part is composed of a narrow through hole and a metal plating layer applied to the through hole.

  Thus, since the cross-sectional shape of the through hole is a drum shape in which the intermediate portion is formed narrow, in the insulating layer forming step of forming the insulating layer after forming the through hole, the uniformity is good by, for example, a sputtering apparatus or the like. Stable film formation is possible. Further, in the metal plating step after the formation of the through hole, a bottom is formed at a location where the intermediate cross-sectional area is small, and the plating proceeds upward and downward from there, so that high-speed filling and voidless filling are possible.

  Here, the first through hole formed in the first semiconductor substrate from the outer surface side so that the diameter decreases from the outer surface of the first semiconductor substrate toward the inner surface, The second through hole is formed from the inner side surface of the second semiconductor substrate so as to increase in diameter as it goes from the inner side surface to the outer side surface of the second semiconductor substrate. It is preferable.

  As described above, according to a semiconductor device and a manufacturing method thereof according to an aspect of the present invention, it is possible to form a through electrode that enables metal voidless filling of a thick semiconductor substrate for MEMS use with high throughput. A method for manufacturing a semiconductor device and a semiconductor device obtained thereby can be provided.

It is sectional drawing which shows the structure of the semiconductor device of an aspect with this invention. It is a flowchart which shows the flow of the manufacturing method of the semiconductor device of a certain aspect of this invention. (A)-(e) is sectional drawing which shows the flow of the manufacturing method of the semiconductor device of a certain aspect of this invention. (A)-(e) is sectional drawing which shows the flow of the manufacturing method of the semiconductor device of a certain aspect of this invention. (A)-(e) is sectional drawing which shows the flow of the manufacturing method of the semiconductor device of a certain aspect of this invention. It is the schematic which shows the structure of the etching apparatus used for the manufacturing method of the semiconductor device of an aspect with this invention. It is sectional drawing which shows the laminated structure of the semiconductor device of an aspect with this invention. It is sectional drawing which shows the structure of the semiconductor device of the other aspect of this invention. It is sectional drawing which shows the structure of the semiconductor device of the other aspect of this invention.

Hereinafter, a semiconductor device and a manufacturing method thereof according to an aspect of the present invention will be described with reference to the drawings.
(Semiconductor device)
FIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor device according to an aspect of the present invention.
As shown in FIG. 1, in the semiconductor device 1 of this embodiment, a through electrode 20 is formed in a semiconductor substrate 10 in which a first semiconductor substrate 11 and a second semiconductor substrate 12 are stacked with an insulating layer 13 interposed therebetween. That is, the semiconductor substrate 10 has a structure in which a through hole is formed in a thick SOI (Silicon On Insulator) wafer for MEMS. In addition, as a material of the 1st semiconductor substrate 11 and the 2nd semiconductor substrate 12, a silicon | silicone is mentioned, for example, A silicon oxide is mentioned as a material of the insulating layer 13, for example.

<Penetration electrode>
The through electrode 20 has a through hole 21 having a drum-shaped (hourglass-shaped) cross-sectional shape with a narrow middle portion along the thickness direction of the semiconductor substrate 10, and plating the through hole 21. A metal plating layer 26 filled with metal. The through electrode 20 is preferably provided by laminating an insulating layer 24 and a seed layer 25 between the through hole 21 and the metal plating layer 26 as necessary.

[Through hole]
The through hole 21 is a through hole penetrating in the thickness direction with respect to the semiconductor substrate 10 (the first semiconductor substrate 11, the second semiconductor substrate 12, and the insulating layer 13). The through hole 20 is preferably composed of a first through hole 22 and a second through hole 23.
The diameter of the first through hole 22 increases from the outer surface 11a (the front surface 10a of the semiconductor substrate 10) of the first semiconductor substrate 11 toward the inner surface (the interface of the first semiconductor substrate 11 with respect to the insulating layer 13) 11b. The through holes are formed in the first semiconductor substrate 11 from the outer surface 11a side so as to be smaller. Here, the inner side surface 11 b is an interface of the first semiconductor substrate 11 with respect to the insulating layer 13.

  The second through hole 23 communicates with the first through hole 22 on the inner side surface 11b, and the diameter of the second semiconductor substrate 12 increases so as to increase from the inner side surface 12a of the second semiconductor substrate 12 toward the outer side surface 12b. The through hole is formed so as to penetrate from the inner side surface 12 a to the outer side surface 12 b of the second semiconductor substrate 12 (the back surface 10 b of the semiconductor substrate 10). Here, the inner side surface 12 a is an interface of the second semiconductor substrate 12 with respect to the insulating layer 13.

  Each of the first through hole 22 and the second through hole 23 may have a shape in which each cross-sectional shape is reduced or expanded in a straight line shape (see FIG. 1) in the thickness direction. You may make the shape diameter-reduced or expanded in the shape of a curve. In the description of the present embodiment, the shape of the through hole 20 reduced in the thickness direction of the semiconductor substrate 10 along the direction in which the through hole 20 is formed is referred to as a “forward taper shape”, and the diameter of the through hole is increased. The shape of the hole 20 is referred to as “reverse taper shape”. That is, the first through hole 22 in the present embodiment is formed in a forward taper shape with the front surface 10 a of the semiconductor substrate 10 as a reference, and the second through hole 23 is inversely tapered toward the back surface 10 b of the semiconductor substrate 10. It is formed in a shape (see FIG. 1).

(Method for manufacturing semiconductor device)
FIG. 2 is a flowchart showing a flow of a manufacturing method of a semiconductor device according to an aspect of the present invention. 3 to 5 are cross-sectional views showing a flow of a method for manufacturing a semiconductor device according to an aspect of the present invention.
As shown in FIG. 2, the manufacturing method for manufacturing the semiconductor device having the above-described configuration includes the “first through hole forming step (S1)”, the “second through hole forming step (S2)”, and the “plating step”. (S3) ". If necessary, a film forming step may be included between the first through hole forming step (S1) and the second through hole forming step (S2).

<First through hole forming step>
The first through-hole forming step S1 is a step of forming the first through-hole 22 that is a forward-tapered bottomed hole from the outer surface 11a of the first semiconductor substrate 11 constituting the semiconductor substrate 1 by a photolithography technique. . The processing of the first through hole 22 does not reach the insulating layer 13, but is stopped-etched on the inner side surface 11 b (interface with the insulating layer 13) of the first semiconductor substrate 11. Hereinafter, specific process contents will be described.

First, a first resist film 14 that is a mask material is applied to a semiconductor substrate 10 shown in FIG. 3A in which a first semiconductor substrate 11 and a second semiconductor substrate 12 are laminated via an insulating layer 13 ( (Refer FIG.3 (b)). The first resist film 14 may be a two-layer mask of a resist material and an oxide film when the resist material alone or the resist material alone is insufficient in the selection ratio.
Next, as shown in FIG. 3C, the first resist film 14 is patterned into a desired shape by exposure, development, and baking (in the case of a two-layer mask, oxide film etching is performed after baking).

  Next, as shown in FIG. 3D, a tapered first through hole 22 is formed by dry etching. The first through hole 22 has a forward taper shape in which the diameter decreases from the outer surface 11a (the front surface 10a of the semiconductor substrate 10) of the first semiconductor substrate 11 toward the inner surface 11b. Although the first through hole 22 is described as being a tapered bottomed hole, the bottom of the first through hole 22 that penetrates the first semiconductor substrate 11 is exposed to close the opening 11c of the inner side surface 11b. This is the insulating layer 13. Thereafter, as shown in FIG. 3E, the first resist film 14 is removed by, for example, a plasma ashing apparatus.

[Configuration of etching apparatus]
The dry etching method in this step is performed using a dry etching apparatus 100 shown in FIG. The dry etching apparatus 100 includes a reaction chamber 101 that accommodates a semiconductor substrate 10 to be etched in an interior 101A, a reaction gas introduction unit 110, a semiconductor substrate support unit 120, an exhaust unit 130, and a plasma generation unit 140. .

[Reactive gas introduction part]
The reactive gas introduction unit 110 includes a gas introduction pipe 111, a plurality of gas pipes 112 (112a, 112b, 112c), a plurality of mass flow controllers 113 (113a, 113b, 113c), and a plurality of gas inflow ends 114 (114a, 114b, 114c) and a plurality of gas sources (not shown) connected to each other.
The reaction chamber 101 is provided with a gas introduction pipe 111 for introducing gas from the outside into the interior 101 </ b> A of the reaction chamber 101. A gas discharge end 111 a of the gas introduction pipe 111 is opened in the reaction chamber 101. A plurality of gas pipes 112 a to 112 c are connected in parallel to the gas inflow side of the gas introduction pipe 111. In addition, mass flow controllers 113a to 113c are connected in series in the middle of each of the plurality of gas pipes 112a to 112c. The flow rate to the internal 101A can be adjusted.

Here, in the present embodiment, examples of the gas supplied from the gas sources respectively connected to the plurality of gas pipes 112a to 112c include SF ₆ , C ₄ F ₈ , and O _2. At 111, these gases are mixed. Note that the taper angle is controlled by the gas flow rate of C ₄ F ₈ controlled by the mass flow controller 113 provided in each gas pipe 112, and the roughness of the side wall of the through hole 21 is controlled by the O ₂ gas flow rate.

[Semiconductor substrate support part]
The semiconductor substrate support unit 120 includes a stage 121, a lower electrode 122, and a gas pipe 123. Specifically, a stage 121 on which the semiconductor substrate 10 is placed and a lower electrode 122 made of a conductive material that supports the stage 121 are disposed at the bottom of the interior 101A of the reaction chamber 101.
The lower electrode 122 is provided with a gas pipe 123 through which helium (He) gas is introduced into the stage 121. The gas pipe 123 introduces helium (He) gas into the semiconductor substrate 10 on the stage 121, and the semiconductor substrate 10 is cooled.

A mass flow controller 124 is connected in the middle of the gas pipe 123 so that the flow rate of the cooling gas (helium (He) gas) supplied from a gas source (not shown) to the stage 121 can be adjusted.
Further, a high frequency power source 125 for bias is connected to the lower electrode 122 via a matching box 126. Further, a DC power source 127 for fixing the semiconductor substrate 10 placed on the stage 121 to the stage 121 by electrostatic adsorption is connected to the lower electrode 122.

[Exhaust section]
The exhaust unit 130 includes a conductance valve 131, a turbo pump 132, and a rough pump 133. Specifically, a conductance valve 131, a turbo pump 132, and a rough pump 133 are connected in series to the reaction chamber 101, and the inside 101A of the reaction chamber 101 is exhausted by these, and the pressure of the inside 101A of the reaction chamber 101 is exhausted. Can be adjusted.

[Plasma generator]
The plasma generator 140 includes an insulator 141, an antenna 142, a matching box 144, and a plasma generating high frequency power source 145.
The insulator 141 has a plate shape and is airtightly provided on the ceiling portion of the reaction chamber 101 facing the stage 121. The insulator 141 is made of a material that transmits microwaves (for example, aluminum nitride).
The antenna 142 has a disk shape and is provided on the insulator 141 to function as an upper electrode that is electrically insulated from the interior 101 </ b> A of the reaction chamber 101.

The antenna 142 is connected via a matching box 144 to a plasma generating high frequency power supply 145 that generates high frequency power to be supplied to the antenna 142. The antenna 142 may be formed as a coil wound in a flat spiral shape.
The dry etching apparatus 100 having such a configuration is arranged to face the antenna 142 and the antenna 142 by supplying power to the antenna 142 from the high frequency power source 145 for plasma generation via the matching box 144. Plasma can be generated by exciting gas with the lower electrode 122.

[Etching method]
In the etching method of this embodiment, first, the semiconductor substrate 10 is carried into the decompressed reaction chamber 101 of the dry etching apparatus 100 having the above-described configuration, and the semiconductor substrate 10 is placed on the stage 121.
Next, the exhaust amount is adjusted so that the pressure in the reaction chamber 101 becomes 5 Pa, an etching gas is introduced into the reaction chamber 101, and a high frequency power of about 50 W is applied to the lower electrode 122, thereby providing the first semiconductor substrate. 11, a first through hole 22 having a forward taper shape is formed.

At this time, as an etching gas introduced into the inside 101A of the reaction chamber 101, for example, SF _{6 is} supplied from a gas supply source (not shown) to the inside 101A of the reaction chamber 101 through the gas pipes 112a to 112c and the gas introduction pipe 111. , C ₄ F ₈ , and a gas containing O ₂ are introduced. Here, the ratio of the gas flow rate of C ₄ F ₈ to the total gas flow rate of SF ₆ , C ₄ F ₈ , and O ₂ is set to 35% to 40% by the mass flow controllers 113a to 113c, so that the forward tapered shape is obtained. The first through hole 22 can be formed. Further, the mass flow controllers 113a to 113c set the ratio of the gas flow rate of O ₂ to the total gas flow rate of SF ₆ , C ₄ F ₈ , and O ₂ to 15% to 20%, so that the side wall of the first through hole 22 The roughness of 22a (see FIG. 4B) can be controlled.

Subsequently, a reverse through-hole-shaped second through hole 23 is formed in the insulating layer 13 and the second semiconductor substrate 12. In the formation of the second through hole 23, the mass flow controller 113 a to 113 _c, the SF _6, C 4 _{F 8,} carried out with the protective film forming process by machining process and _C 4 _{F 8} by SF ₆ plasma alternately, The second through hole 23 having a reverse taper shape can be formed by using a Bosch process that processes in the depth direction while protecting the side wall. At this time, the reverse taper angle can be controlled by lowering the bias power applied to the lower electrode and extending the application time.

<Film formation process>
Here, as described above, the “film formation step” may be performed after the first through-hole forming step S1 and before the second through-hole forming step S2.
This “film formation step” is a step of forming a penetration preventing film 15 made of a metal film or an oxide film on the outer surface 12 b of the second semiconductor substrate 12 as shown in FIG. In the “film formation step”, an oxide film may be formed on the outer surface 11 a of the first semiconductor substrate 11 and the outer surface 12 b of the second semiconductor substrate 12 by a thermal oxidation method. Examples of the metal used for the penetration preventing film 15 include Al, Ti, Ni, and the like. By performing this “film formation step” between the first through-hole forming step S1 and the second through-hole forming step S2, when the second semiconductor substrate 12 is penetrated in the second through-hole forming step to be described later This prevents the problem that He for leaking the semiconductor substrate 10 leaks, the temperature of the semiconductor substrate 10 rises, and the second resist film 16 disappears.

<Second through-hole forming step>
In the second through-hole forming step S2, an inversely tapered shape is formed from the opening 11c of the first semiconductor substrate 11 in which the first through-hole 22 penetrating in the thickness direction by the first through-hole forming step S1 is formed by a photolithography technique. This is a step of forming the second through hole 23 which is a bottomless hole. Hereinafter, specific process contents will be described.
First, as shown in FIG. 4B, a second resist film 16 that is a mask material is applied to the outer side surface 11 a and the first through hole 22 of the first semiconductor substrate 11. Here, since the outer surface 11a of the first semiconductor substrate 11 and the first through hole 22 are not flat, the second resist film 16 uses a spray resist that can be applied to a stepped portion. Further, when a resist mask is used as the second resist film 16, the second resist film 16 on the side wall portion 22 a of the first through hole 22 is thin, and particularly when the first semiconductor substrate 11 is thick, the resist Since there is a possibility that the side wall 22a cannot be protected only by the mask, an oxide film is formed on the base by a thermal oxidation method or a CVD method. In addition, when the film formation process is adopted and an oxide film (penetration prevention film 15) is formed on the outer surface 11a of the first semiconductor substrate 11 and the outer surface 12b of the second semiconductor substrate 12, this base is provided. It does not have to be.

Next, the patterning portion 17a of the second resist film 16 at the bottom of the first through hole 22 is patterned by exposure, development, and post-baking, and the insulating layer 13 exposed by patterning the second resist 17 is exposed. The exposed portion is etched by the dry etching apparatus 100 (see FIG. 6) (see FIG. 4C). In this etching, the insulating layer 13 is processed with a mixed gas of CF ₄ , CHF ₃ , and O ₂ . Note that the exposed portion of the insulating layer 13 may be removed in advance by a wet etching method or a dry etching method after the step shown in FIG.

Next, by etching the insulating layer 13, the second through hole 23 having a reverse taper shape is formed in the second through hole 23 by a dry etching method (Bosch process) from a portion where the inner surface 12 a of the second semiconductor substrate 12 is exposed. It is formed on the semiconductor substrate 12 (see FIG. 4D). Specifically, the reverse through-hole shaped second through hole 23 can be formed by lowering the application voltage of the bias voltage applied to the semiconductor substrate 10 via the lower electrode 122 and extending the application time. Here, as described above, the Bosch process is performed by repeating the sidewall protection cycle using Teflon (registered trademark) plasma using C ₄ F _{8 and the} like and the etching processing cycle using halogen plasma using SF ₆ or the like. This is a method of deep drilling. Thereafter, as shown in FIG. 4E, for example, the second resist film 16 is removed by a plasma ashing apparatus, and then, the outer surface 12b of the second semiconductor substrate 12 (the back surface of the semiconductor substrate 10) by a wet etching method. The penetration preventing film 15 formed in 10b) is removed. In this way, the first through hole 22 having a forward taper shape and the second through hole 23 having a reverse taper shape communicate with each other, and the semiconductor substrate 10 is formed as a through hole 21 having a narrow middle portion. Formed.

<Plating process>
The plating step S3 is a step of forming the through electrode 20 by performing metal plating on the first through hole 22 and the second through hole 23.
First, an oxide film is formed on the front surface 10a, the back surface 10b, and the inner wall surface of the through hole 21 of the semiconductor substrate 10 as an insulating layer 24 with a metal wiring (not shown) by a thermal oxidation method, a CVD method, or the like. (FIG. 5 (a)).
Next, the seed layer 25 is formed on the insulating layer 14 by electrolytic plating, electroless plating, sputtering, or the like (FIG. 5B).

Next, metal plating is performed in the through hole 21 by electrolytic plating. Here, the plated metal is first embedded in the narrowest portion 20A (see FIG. 5B) of the intermediate portion of the through hole 21 to form the plated metal initial filling portion 26A (FIG. 5C). ).
In this plating step, as shown in FIG. 5D, the metal plating layer 26 not only fills the through hole 21 with the plated metal initial filling portion 26A (see FIG. 5C) as a base point, but also the semiconductor substrate 10 It is formed so as to cover. In this step, since the filling of the plating metal proceeds in a bottom-up direction in the direction of the front surface 10a and the back surface 10b of the semiconductor substrate 10, high-speed metal filling is possible with a voidless.

  Next, the insulating layer 24, the seed layer 25, and the plating metal are applied to the front surface 10a of the semiconductor substrate 10 (the outer surface 11a of the first semiconductor substrate 11) by the CMP method, the electropolishing method, the wet etching method, and the like. Processing is performed until the back surface 10b of the semiconductor substrate 10 (the outer surface 12b of the second semiconductor substrate 12) is exposed, and the drum-shaped through electrode 20 is formed (FIG. 5E). In this way, the semiconductor device 1 according to the present embodiment in which the drum-shaped through hole 21 is filled with the metal plating layer 26 is manufactured.

Here, as an example of a form in which the semiconductor device 1 of the present embodiment is mounted on a wiring board, as shown in FIG. Are stacked so that the through electrodes 20 are connected to each other via bumps (protruding terminals) 202, and are connected to the electrodes 201 on the wiring substrate 200.
As described above, according to an embodiment of the semiconductor device manufacturing method of the present invention, the through electrode 20 having a drum-shaped cross-sectional shape is formed on the semiconductor substrate 10 which is a thick film SOI wafer for MEMS use. It is possible to manufacture the semiconductor device 1 having high throughput. This is because the drum-shaped through hole 21 is formed in one direction from the front surface 10a to the back surface 10b of the semiconductor substrate 10, and the through electrode 20 is formed by filling with metal.

  According to an embodiment of the semiconductor device of the present invention, since the cross-sectional shape of the through hole 21 is a drum shape, in the insulating layer forming step for forming the insulating layer after the through hole 21 is formed, for example, a sputtering apparatus Thus, stable film formation with good uniformity can be achieved. Further, in the metal plating step S3 after the through hole 21 is formed, the bottom is formed in the portion 20A having a small intermediate cross-sectional area, and the plating proceeds vertically from there, so that high-speed filling and voidless filling are possible.

(Other embodiments)
Hereinafter, a semiconductor device according to another embodiment of the present invention and a manufacturing method thereof will be described.
In one embodiment of the semiconductor device described above, in the “first through-hole forming step S1”, the first semiconductor substrate 11 is etched in a forward tapered shape up to the point where the insulating layer 3 is reached, and the “second through-hole forming step S2” is performed. The insulating layer 3 and the second semiconductor substrate 12 were etched in a reverse taper shape.

  On the other hand, as shown in FIG. 8, in the semiconductor device according to another aspect of the present invention and the manufacturing method thereof, the “first through hole forming step S1” includes not only the first semiconductor substrate 11 but also the insulating layer. 13 may also be etched in a forward tapered shape, and stop etching may be performed at the inner side surface 12a (interface with the insulating layer 3) of the second semiconductor substrate 12, or may be stopped within the second semiconductor substrate 12 beyond the insulating layer 13. Etching may be performed. Thereafter, only the second semiconductor substrate 12 is etched in a reverse taper shape in the “second through-hole forming step S2” in the same manner as in the above-described embodiment.

In the embodiment of the semiconductor device described above, the cross-sectional structure of the through-hole 21 is such that the first through-hole 22 is etched in a forward taper shape and the second through-hole 23 is reverse-tapered as shown in FIG. It is etched into a shape. On the other hand, as a semiconductor device according to another aspect of the present invention and a manufacturing method thereof, as shown in FIG. 9, the shape of the first through hole 22 may be a shape whose diameter is not changed in the thickness direction. In addition, the structure of the 1st through-hole 22 of this embodiment is the 1st through-hole 22 made into the shape where the 1st semiconductor substrate 11 in the semiconductor substrate (SOI substrate) 10 is thin enough and does not change a diameter in the thickness direction. It is assumed that the insulating layer (insulating layer with metal wiring) 24 and the seed layer 25 can be formed on the inner peripheral surface.
As mentioned above, although embodiment of this invention has been described, this invention is not limited to this, A various change and improvement can be performed.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 10 Semiconductor substrate 11 1st semiconductor substrate 11a Outer side surface 11b Inner side surface 12 2nd semiconductor substrate 12a Inner side surface 12b Outer side surface 13 Insulating layer 15 Penetration prevention film 20 Through-electrode 21 Through-hole 22 1st through-hole 23 2nd through-hole Hole

Claims (5)

A method of manufacturing a semiconductor device, wherein a through electrode is formed in a semiconductor substrate in which a first semiconductor substrate and a second semiconductor substrate are laminated via an insulating layer,
A first through hole forming step of forming a first through hole penetrating the first semiconductor substrate so that the diameter decreases from the outer surface of the first semiconductor substrate toward the inner surface;
After the first through-hole forming step, the second through-hole penetrating the insulating layer and the second semiconductor substrate so that the diameter increases from the bottom of the first through-hole toward the outer surface of the second semiconductor substrate. A second through-hole forming step of forming
And a plating step of forming a through electrode by performing metal plating on the first through hole and the second through hole. A method of manufacturing a semiconductor device, wherein a through electrode is formed in a semiconductor substrate in which a first semiconductor substrate and a second semiconductor substrate are laminated via an insulating layer,
A first through hole forming step of forming a first through hole penetrating the first semiconductor substrate and the insulating layer so that the diameter decreases from the outer surface of the first semiconductor substrate toward the inner surface;
After the first through hole forming step, a second through hole penetrating the second semiconductor substrate is formed so that the diameter increases from the bottom of the first through hole toward the outer surface of the second semiconductor substrate. 2 through-hole forming step;
And a plating step of forming a through electrode by performing metal plating on the first through hole and the second through hole.   The film forming step of forming a metal film or an oxide film on the outer surface of the second semiconductor substrate is performed between the first through hole forming step and the second through hole forming step. 3. A method for manufacturing a semiconductor device according to 2. A semiconductor device in which a through electrode is formed in a semiconductor substrate in which a first semiconductor substrate and a second semiconductor substrate are stacked via an insulating layer,
The through electrode is
A through hole having a narrow intermediate portion;
A semiconductor device comprising: a metal plating layer applied to the through hole. The semiconductor device according to claim 4,
The through hole is
A first through hole formed in the first semiconductor substrate from the outer surface side so that the diameter decreases from the outer surface of the first semiconductor substrate toward the inner surface;
A second through hole formed from the inner surface side of the second semiconductor substrate so as to increase in diameter as it goes from the inner surface to the outer surface of the second semiconductor substrate.
A semiconductor device comprising:

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