JP2014026997A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a structure body that reduces the load capacity between wiring of a wiring substrate and a semiconductor chip.SOLUTION: A semiconductor device 1a comprises: a wiring substrate 20a; and a chip laminate 30 mounted on the wiring substrate 20a. The wiring substrate 20a has a base material 21, wiring 24 having a predetermined thickness formed on a surface of the base material 21, and a conductive portion 40 formed on the wiring 24. The chip laminate 30 has a plurality of semiconductor chips 10a, 10b, and 10c that are stacked one another, and a bump electrode 17a formed on the first semiconductor chip 10a facing the wiring substrate 20a of the plurality of semiconductor chips 10a, 10b, and 10c. The bump electrode 17a is electrically connected to the conductor portion 40.

Description

  The present invention relates to a semiconductor device including a semiconductor chip mounted on a wiring board.

  2. Description of the Related Art In recent years, with the downsizing and higher functionality of electronic devices, chip-on-chip (CoC) type semiconductor devices in which a plurality of semiconductor chips are stacked on each other have been developed. Patent Document 1 discloses a method for manufacturing a CoC type semiconductor device. The manufacturing method includes a step of stacking a plurality of semiconductor chips to form a chip stack, a step of filling an underfill between chips constituting the chip stack, and mounting the chip stack on a wiring board. Steps.

JP 2010-251347 A

  In the CoC type semiconductor device as described above, the distance between the uppermost semiconductor chip of the chip stack, that is, the surface of the interface (IF) chip, and the electrode (surface wiring) of the wiring board is shortened. As a result, there is a problem that the load capacitance (parasitic capacitance or stray capacitance) between the IF chip and the wiring board increases.

  In the CoC type semiconductor device described in Patent Document 1, the chip stack is connected to a wiring board via wire bumps. However, even in this case, there is a limit in securing a sufficient distance between the electrode of the wiring board and the surface of the IF chip.

  Therefore, a semiconductor device that can reduce the load capacity between the semiconductor chip and the wiring board is desired.

  A semiconductor device according to an embodiment includes a wiring board and a chip stacked body mounted on the wiring board. The wiring board includes a base material, a wiring having a predetermined thickness formed on the surface of the base material, and a conductive portion formed on the wiring. The chip stack includes a plurality of semiconductor chips stacked on each other and a bump electrode formed on a first semiconductor chip facing the wiring substrate among the plurality of semiconductor chips. The bump electrode is electrically connected to the conductive portion.

  A semiconductor device according to another embodiment is mounted on a wiring board having a base material, a wiring having a predetermined thickness formed on the surface of the base material, and a conductive portion formed on the wiring, and the wiring board A first semiconductor chip; and a bump electrode formed on the first semiconductor chip and electrically connected to the conductive portion.

  In the semiconductor device described above, a sufficient distance between the wiring of the wiring board and the first semiconductor chip can be secured by the conductive portion. As a result, the load capacity between the wiring of the wiring board and the first semiconductor chip can be reduced.

  According to the present invention, the load capacity between the wiring of the wiring board and the first semiconductor chip can be reduced.

1 is a schematic cross-sectional view of a CoC type semiconductor device according to a first embodiment of the present invention. (A)-(d) is a schematic process drawing which shows an example of the method of manufacturing the chip laminated body on which the semiconductor chip was laminated | stacked mutually. (A)-(e) is a schematic process drawing which shows an example of the method of mounting a chip laminated body on a wiring board. It is a schematic sectional drawing of the CoC type semiconductor device in the 2nd example of the present invention. It is a schematic sectional drawing of the CoC type semiconductor device in the 3rd example of the present invention.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a schematic cross-sectional view of a CoC type semiconductor device according to the first embodiment of the present invention. The semiconductor device 1a includes a wiring board 20a and a chip stack 30 mounted on the wiring board 20a. The chip stack 30 includes a plurality of semiconductor chips 10a, 10b, and 10c stacked on each other.

  Of the plurality of semiconductor chips 10a, 10b, 10c constituting the chip stacked body 30, the first semiconductor chip 10a (hereinafter sometimes referred to as the uppermost semiconductor chip) facing the wiring substrate 20a is wired. A bump electrode 17a connected to the substrate 20a is provided.

  The wiring substrate 20 a includes an insulating base material 21 and wiring patterns 24 and 25 having a predetermined thickness formed on the insulating base material 21. The wiring patterns 24 and 25 may be formed on both surfaces of the insulating base material 21. The wiring patterns 24 and 25 can be formed from a conductor such as Cu, for example. The insulating base material 21 may be a glass epoxy base material, for example. Insulating films 22 and 23 may be formed on both surfaces of the insulating base material 21, respectively. The insulating films 22 and 23 can be formed from, for example, a solder resist.

  A columnar conductive portion 40 is formed on the first wiring pattern 24 formed on the surface of the insulating base 21 facing the chip stack 30. That is, it can be said that the conductive portion 40 is a thick portion of the first wiring pattern 24. The conductive portion 40 is provided corresponding to the bump electrode 17 a formed on the first semiconductor chip 10 a of the chip stack 30. The conductive portion 40 may be formed of the same material as that of the wiring pattern 24, but may be formed of a material different from that of the wiring pattern 24.

  The insulating film 22 preferably covers the first wiring pattern 24 of the wiring board 20 a and surrounds the side surface of the conductive portion 40. The conductive portion 40 is stably placed by the insulating film 22 surrounding the side surface of the conductive portion 40. At this time, the top surface of the conductive portion 40 is exposed from the insulating film 22, and the wire bump 36 is provided on the top surface of the conductive portion 40. A plating layer such as Ni / Au may be formed on the top of the conductive portion 40. It is preferable that the top surface of the conductive portion 40 forms a plane that is substantially the same as the surface of the insulating film 22.

  A part of the second wiring pattern 25 formed on the surface of the insulating base material 21 facing away from the chip stack 30 is exposed from the opening of the insulating film 23, and the second wiring pattern 25 exposed portions constitute a land 27. The land 27 is provided with an external terminal 35. The external terminal 35 may be a metal ball such as a solder ball.

  The semiconductor chips 10a, 10b, and 10c constituting the chip stack 30 may be a memory chip having a memory circuit, an interface chip, or the like. In the present embodiment, the first semiconductor chip 10a is an interface chip, and the second semiconductor chip 10b and the third semiconductor chip 10c are memory chips. Here, the third semiconductor chip 10c means a semiconductor chip located farthest from the wiring board 20a.

  An underfill material 32 may be filled in the gaps between the semiconductor chips 10a, 10b, and 10c constituting the chip stacked body 30. Further, a sealing resin 34 may be formed around the chip laminated body filled with the underfill material 32.

  The semiconductor chips 10a, 10b, and 10c have a semiconductor substrate 13 and a circuit 14 formed on the semiconductor substrate. The circuit 14 is a predetermined circuit corresponding to the function and use of the chip. When the semiconductor chip is a memory chip, the circuit 14 is a memory circuit, and when the semiconductor chip is an interface chip, the circuit 14 is an interface circuit. In this embodiment, a circuit 14 is formed on one surface of the semiconductor substrate 13 facing the wiring substrate side.

  The first semiconductor chip 10a and the first semiconductor chip 10b include first bump electrodes 17a and 17b formed on the first surface, through wirings 19a and 19b, and a first electrode opposite to the first surface. The second bump electrodes 18a and 18b formed on the second surface may be provided. The through wirings 19a and 19b electrically connect the first bump electrodes 17a and 17b and the second bump electrodes 18a and 18b.

  The second bump electrode 18a of the first semiconductor chip 10a is connected to the first bump electrode 17b of the second semiconductor chip 10b. The first bump electrode 17c of the third semiconductor chip 10a is connected to the second bump electrode 18b of the second semiconductor chip 10b. The second semiconductor chips 10b adjacent to each other are connected to each other by bump electrodes 17b and 18b.

  The third semiconductor chip 10c does not have to have a through wiring. Further, the third semiconductor chip 10c does not have to have a bump electrode on the surface facing the side opposite to the wiring substrate 20a. Furthermore, the third semiconductor chip 10c is preferably thicker than the semiconductor chip. Thereby, the intensity | strength of the part far from the wiring board 20a of the chip laminated body 30 can be increased.

  Dummy bumps 42 that do not contribute to electrical connection may be formed in the peripheral positions of the second and third semiconductor chips 10b and 10c. By connecting the dummy bumps 42 of the semiconductor chips 10b and 10c adjacent to each other, the bonding of the semiconductor chips 10b and 10c can be reinforced.

  The first bump electrode 17a of the first semiconductor chip 10a may be bonded to the conductive portion 40 of the wiring board 20a via a wire bump 36 made of Au or the like. As a result, the surface of the first semiconductor chip 10a on which the circuit 14 is formed is directed to the wiring board 20a.

  In the present embodiment, the conductive portion 40 on the wiring pattern 24 is connected to the bump electrode 17 a of the first semiconductor chip 10 a of the chip stack 30 via the wire bump 36. That is, the conductive portion 40 and the wire bump 36 define the distance between the first semiconductor chip 10a and the wiring 24 of the wiring board 20a.

  In the example shown in FIG. 1, the conductive portion 40 is connected to the bump electrode 17a of the first semiconductor chip 10a via the wire bump 36. However, if possible, the conductive portion 40 is connected to the bump of the first semiconductor chip 10a. It may be directly connected to the electrode 17a. In this case, the conductive portion 40 defines the distance between the first semiconductor chip 10a and the wiring 24 of the wiring board 20a.

  The conductive portion 40 can secure a sufficient distance between the wiring 24 of the wiring board 20a and the first semiconductor chip 10a. As a result, the load capacitance (parasitic capacitance or stray capacitance) between the wiring 24 of the wiring board 20a and the first semiconductor chip 10a can be reduced.

  Further, since the insulating film 22 surrounds the side surface of the conductive portion 40, the conductive portion is stably held. The conductive portion 40 may be formed integrally with the wiring pattern 24 as a part of the wiring pattern 24.

  The thickness of the thick film portion 40 is appropriately selected according to the distance to be secured between the chip stack 30 and the wiring board 20a. Since the parasitic capacitance or stray capacitance can be reduced by the conductive portion 40, there is no need to form a plurality of wire bumps between the chip stack 30 and the wiring board 20a. As a result, the wire bumps 36 can be prevented from falling due to a load when the chip stack 30 is flip-chip mounted on the wiring board 20a. As a result, the chip stack 30 and the wiring board 20a can be stably bonded.

  A non-conductive paste (NCP) 37 may be provided between the chip stack 30 and the wiring board 20a. A sealing resin 34 made of a thermosetting resin such as an epoxy resin is provided on the surface of the wiring board 20 a, and the chip stack 30 is covered with the sealing resin 34.

  The wiring pattern 24 is preferably covered with the insulating film 22 except for the conductive portion 40. Thereby, the metal part exposed from the insulating film 22, for example, the area | region of a gold plating layer can be reduced. Thereby, the adhesiveness of NCP37 and the wiring board 20a can be improved.

  FIG. 2A to FIG. 2D are schematic cross-sectional views illustrating an example of a method for manufacturing a chip stacked body in which semiconductor chips are stacked on each other.

  First, the third semiconductor chip 10c is placed on the suction stage 114 (see FIG. 2A). The surface (circuit formation surface) on which the circuit 14 of the third semiconductor chip 10c is formed faces upward. Bump electrodes 17c are provided on the circuit formation surface of the third semiconductor chip 10c. The third semiconductor chip 10c is held and fixed by suction through the suction hole 116 by a vacuum device (not shown).

  Next, the second semiconductor chip 10b is mounted on the third semiconductor chip 10c. By vacuum suction from the suction hole 112 of the bonding tool 110, the second-stage semiconductor chip 10b is held by the bonding tool 110. Then, as shown in FIG. 2B, the second-stage semiconductor chip 10b is stacked on the first-stage semiconductor chip 10c. At this time, the second-stage semiconductor chip 10b is stacked using the bonding tool 110 while applying a load to the second-stage semiconductor chip 10b at a high temperature of about 300 ° C., for example. At this time, the bump electrode 17c on one surface of the first-stage memory chip 10c and the corresponding bump electrode 18b of the second-stage semiconductor chip 10b are electrically connected by thermocompression bonding. Similarly, the third and fourth semiconductor chips 10b are stacked on the second semiconductor chip 10b. Similarly, the fifth-stage semiconductor chip 10a is mounted on the fourth-stage semiconductor chip 10b (see FIG. 2B).

  On the uppermost first semiconductor chip 10a, bump electrodes 18a are arranged corresponding to the bump electrodes 17b of the second semiconductor chip 10b. In the first semiconductor chip 10a, the bump electrodes 17a formed on the surface directed to the wiring board side are arranged at a wide pitch of 200 μm or more in order to join the conductive portion 40 of the wiring board 20a.

  As shown in FIG. 2C, the chip stack 30 is placed on a coating sheet 121 that is pasted on the stage. The coating sheet 121 is preferably formed of a material having poor wettability with the underfill material 32, such as a fluorine sheet or a sheet to which a silicone adhesive is applied.

  The underfill material 32 is supplied from the dispenser 130 to the chip stack 30 placed on the coating sheet 121 in the vicinity of the end of the chip stack 30. The underfill material 32 is filled in the gaps between the semiconductor chips 10a, 10b, and 10c by capillary action. The chip stack 30 is covered with the underfill material 32, but the surface on which the bump electrodes 17 a of the first semiconductor device 10 a are formed is exposed from the underfill material 32.

  After the filling of the underfill material 32 is completed, the underfill material 32 is cured by curing the chip laminated body 30 together with the coating sheet 121 at a predetermined temperature, for example, about 150 ° C. As a result, an underfill material 32 is formed on the chip stack 30 as shown in FIG. Here, the use of the coating sheet 121 prevents the underfill material 32 from adhering to the stage 23.

  FIG. 3A to FIG. 3E are schematic cross-sectional views showing an example of a method for mounting a chip stack on a wiring board. First, a wiring board 20 as shown in FIG. The wiring board 20 is a glass epoxy wiring board having a thickness of 0.14 mm, for example, and a plurality of product forming portions 20a are arranged in a matrix. Each product forming portion 20a is a portion that becomes a wiring substrate of each semiconductor device 1a. The wiring board 20 is provided with a dicing line 28 between the product forming portions 20a. Predetermined wiring patterns 24 and 25 are formed on both surfaces of each product forming portion 20a of the wiring board 20. The wiring patterns 24 and 25 are partially covered with insulating films 22 and 23.

  A conductive portion 40 penetrating the insulating film 22 is formed on the first wiring pattern 24, and the top surface of the conductive portion 40 is exposed from the insulating film 22. A portion of the second wiring pattern 25 of the product forming portion 20a exposed from the insulating film 23 forms a land 27. The conductive portion 40 and the land 30 corresponding to the conductive portion 40 are electrically connected to each other by wiring in the wiring board 20a.

  As shown in FIG. 3A, wire bumps 36 are formed on the conductive portions 40 of the respective product forming portions 20a. The wire bump 36 is made of, for example, Au or Cu, and a wire in which a ball is formed on the melted tip is ultrasonically thermocompression-bonded on the conductive portion 40 by a wire bonding apparatus (not shown), and then the rear end of the wire is drawn. It is formed by cutting.

  The wire bump 36 is formed in a convex shape on the conductive portion 40. Therefore, by mounting the chip stacked body 30 via the wire bumps 36, the bump electrodes 17a and the through wiring 19a of the semiconductor chip 10a of the chip stacked body 30 can be reduced in diameter.

  Next, as shown in FIG. 3A, an insulating adhesive member 37 such as NCP is applied to the product forming portion 20 a of the wiring board 20.

  Subsequently, as illustrated in FIG. 3B, the chip stack 30 is mounted on each product forming unit 20 a. The chip stacked body 30 can be mounted on the product forming portion 20a of the wiring board 20 by, for example, thermocompression bonding. Specifically, the bump electrodes 17a arranged on the uppermost first semiconductor chip 10a of the chip stack 30 are thermocompression bonded to the corresponding wire bumps 36 at a predetermined temperature, for example, about 300 ° C. At this time, the adhesive member 37 spreads and is filled between the chip stack 30 and the wiring board 20.

  Note that when the interface chip 10a having a relatively small chip size and the wiring substrate 20 are electrically connected, there is an advantage that poor connection between the wiring substrate 20 and the semiconductor chip 10a due to warpage of the semiconductor chip 10a is unlikely to occur. is there.

  Next, the wiring board 20 on which the chip stack 30 is mounted is transferred to a molding process (see FIG. 3C). In the molding process, the wiring substrate 20 is set in a molding die including an upper mold and a lower mold (not shown). A cavity that collectively covers a plurality of chip mounting portions in the wiring substrate 20 is formed in the upper mold of the molding die, and the chip stack 30 on the wiring substrate 20 is disposed in the cavity.

  Then, the sealing resin 34 heated and melted is injected into the cavity from the gate portion, and the mounting surface side of the chip stack 30 of the wiring substrate 20 is sealed with the sealing resin 34. In a state where the cavity on one surface side of the wiring substrate 20 is filled with the sealing resin 34, the sealing resin 34 is thermally cured by curing at a predetermined temperature, for example, about 180 ° C. As a result, the sealing resin 34 that collectively covers the plurality of product forming portions 20a of the wiring board 20 is formed. Thereafter, the sealing resin 34 is completely cured by baking at a predetermined temperature.

  After filling the underfill material 32 between the semiconductor chips of the chip stack 30, the formation of a sealing resin 34 that collectively covers the wiring substrate 20 prevents the occurrence of voids between the semiconductor chips during molding. it can.

  Next, a ball mounting process is performed (see FIG. 3D). A conductive metal ball, for example, a solder ball 35 is mounted on a land 27 formed on one surface of the wiring board 20. Thereby, an external terminal is formed.

  Next, a substrate dicing process is performed (see FIG. 3E). The wiring board 20 and the sealing resin 34 are cut along the dicing line 28 and separated into individual product forming portions 20a. This substrate dicing step is preferably performed in a state where the sealing resin side of the wiring substrate 20 is attached to the dicing tape. After cutting the wiring board 20, the separated semiconductor device 1a is picked up from the dicing tape. Thereby, the CoC type semiconductor device 1a shown in FIG. 1 is obtained.

  FIG. 4 is a sectional view showing a schematic configuration of the semiconductor device according to the second embodiment. Similar to the first embodiment, the semiconductor device 1b according to the second embodiment includes a wiring board 20b and a chip stack 30 mounted on the wiring board 20b. The same components as those in the semiconductor device 1a of the first embodiment are denoted by the same reference numerals. In the semiconductor device 1b in the second embodiment, the configuration of the wiring board 20b is different from that of the semiconductor device 1a in the first embodiment. In the following, the configuration different from the semiconductor device 1a of the first embodiment will be mainly described.

  The wiring substrate 20 b includes an insulating base material 21 and a wiring pattern 24 having a predetermined thickness formed on the surface of the insulating base material 21. A conductive portion 40 is formed on the wiring pattern 24. A solder layer 44, for example, a SnAg layer is further formed on the conductive portion 40. The wire bumps 36 are formed on the bump electrodes 17a of the first semiconductor device 10a of the chip stack 30.

  A first insulating film 22 a is formed around the conductive portion 40, and a second insulating film 22 b is formed around the solder layer 44. The second insulating film 22b is formed on the first insulating film 22a. Note that the second insulating film 22b may be formed of the same material as the first insulating film 22a. The second insulating film 22b may be formed integrally with the first insulating film 22a.

  When the chip stack 30 is mounted on the wiring board 20b, the wire bumps 36 formed on the bump electrodes 17a of the first semiconductor device 10a are joined to the conductive portion 40 via the solder layer 44. When the wire bump 36 is a gold bump made of gold, the bonding force between the gold bump 36 and the solder layer 44 is improved by the gold-solder bonding between the solder layer 44 and the gold bump. As a result, the reliability of bonding between the chip stack 30 and the wiring board 20b is improved.

  In the semiconductor device 1b in the second embodiment, the bump electrode 17a of the first semiconductor device 10a and the conductive portion 40 are connected via the solder layer 44 and the wire bump 36 formed on the conductive portion 40, The conductive portion 40, the wire bump 36, and the solder layer 44 define the distance between the first semiconductor chip 10a and the wiring 24 of the wiring board 20c. Therefore, similarly to the first embodiment, there is an advantage that the distance between the wiring 24 of the wiring board 20b and the first semiconductor chip 10a can be sufficiently secured by the conductive portion 40.

The conductive portion 40 and the solder layer 44 are preferably provided in the openings of the first and second insulating films 22a and 22b. in this case,
Since the wire bumps 36 on the bump electrodes 17a formed on the first semiconductor chip 10a of the chip stack 30 are disposed in the openings of the first and second insulating films 22a and 22b, the position of the chip stack 30 Deviation is suppressed.

  FIG. 5 is a sectional view showing a schematic configuration of the semiconductor device according to the third embodiment. Similar to the first embodiment, the semiconductor device 1c according to the third embodiment includes a wiring board 20c and a chip stack 30 mounted on the wiring board 20c. The same components as those in the semiconductor device 1a of the first embodiment are denoted by the same reference numerals. In the semiconductor device 1c according to the third embodiment, the configuration of the wiring board 20c is different from that of the semiconductor device 1a according to the first embodiment. In the following, the configuration different from the semiconductor device 1a of the first embodiment will be mainly described.

  The wiring substrate 20 c includes an insulating base material 21 and a wiring pattern 24 having a predetermined thickness formed on the surface of the insulating base material 21. A conductive portion 40 is formed on the wiring pattern 24. In the present embodiment, the conductive portion 40 has a tapered shape. Even in this case, there is an advantage that the distance between the wiring 24 of the wiring board 20c and the first semiconductor chip 10a can be sufficiently secured by the conductive portion 40.

  As mentioned above, although the invention made | formed by this inventor was demonstrated based on the Example, this invention is not limited to the said Example, It cannot be overemphasized that it can change variously in the range which does not deviate from the summary.

  For example, in the above embodiment, the case where the chip stack 30 having four memory chips and one interface chip is mounted on the wiring boards 20a, 20b, and 20c has been described. However, the type and number of semiconductor chips constituting the chip stack 30 are arbitrary and are appropriately selected according to the purpose and application. Also, the size of the semiconductor chip is arbitrary.

  Moreover, although the said Example demonstrated the case where the chip laminated body 30 was mounted in wiring board 20a, 20b, 20c, one semiconductor chip may be mounted in wiring board 20a, 20b, 20c.

1a, 1b, 1c Semiconductor device 10a First semiconductor chip 10b Second semiconductor chip 10c Third semiconductor chip 13 Semiconductor substrate 14 Circuits 17a, 17b, 17c First bump electrodes 18a, 18b Second bump electrodes 19a, 19b Through wiring 20a, 20b, 20c Wiring substrate 21 Insulating base material 22, 22a, 22b, 23 Insulating film 24, 25 Wiring pattern 27 Land 28 Dicing line 30 Chip laminated body 32 Underfill material 34 Sealing resin 36 Wire bump 37 Non-conductive Conductive paste 40 conductive portion 42 dummy bump 44 solder layer

Claims (10)

A wiring board having a base material, a wiring having a predetermined thickness formed on the surface of the base material, and a conductive portion formed on the wiring;
A chip stack mounted on the wiring board, formed on a plurality of semiconductor chips stacked on each other, and a first semiconductor chip facing the wiring board among the plurality of semiconductor chips, and the conductive portion And a chip laminated body having a bump electrode electrically connected to the semiconductor device. A wiring board having a base material, a wiring having a predetermined thickness formed on the surface of the base material, and a conductive portion formed on the wiring;
A first semiconductor chip mounted on the wiring board;
A semiconductor device comprising: a bump electrode formed on the first semiconductor chip and electrically connected to the conductive portion. The wiring board has an insulating film that covers the wiring and surrounds a side surface of the conductive portion;
The semiconductor device according to claim 1, wherein a top surface of the conductive portion is exposed from the insulating film.   The semiconductor device according to claim 3, wherein a top surface of the conductive portion forms a plane that is substantially the same as a surface of the insulating film.   5. The semiconductor device according to claim 3, wherein a non-conductive adhesive member that fills a space between the insulating film and the first semiconductor chip is provided.   5. The semiconductor device according to claim 1, wherein a predetermined circuit is formed on one surface of the first semiconductor chip facing the wiring substrate side. 6.   The bump electrode and the conductive part are directly connected, and the conductive part defines a distance between the first semiconductor chip and the wiring of the wiring board. 2. The semiconductor device according to claim 1.   The bump electrode and the conductive portion are connected via a conductive wire bump, and the conductive portion and the wire bump define a distance between the first semiconductor chip and the wiring of the wiring board. The semiconductor device according to any one of claims 1 to 6.   The bump electrode and the conductive portion are connected via a solder layer and a gold bump formed on the conductive portion, and the conductive portion, the solder layer, and the gold bump are connected to the first semiconductor chip. The semiconductor device according to claim 1, wherein a distance between the wiring board and the wiring is defined.   The semiconductor device according to claim 1, wherein the first semiconductor chip is an interface chip.

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