JP2013258351A - Wiring board and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technology capable of inhibiting falling of a bump during and after the manufacturing of a wiring board and increasing a height of the bump while maintaining the strength of the bump.SOLUTION: A wiring board 1 includes: an insulation substrate 2; wiring 3 formed on the insulation substrate 2; and a bump 4 formed on the wiring 3. The bump 4 has a multilevel structure where dimensions of the bump 4 in a formation portion thereof, which are measured in a width direction X and a length direction Y of the wiring 3, gradually increase from the top part to the bottom part of the bump 4.

Description

  The present invention relates to a wiring board having bumps on wiring of an insulating substrate and a method for manufacturing the same.

  As one form of the wiring board, there is one in which a wiring pattern is formed on a flexible insulating board. As this type of wiring board, for example, a tape for TAB (Tape Automated Bonding) (hereinafter referred to as “TAB tape”) is widely known. There are several types of TAB tapes depending on the purpose of use. As one of them, a TAB tape having a BOF (Bump On Film) structure is known (see, for example, Patent Document 1).

  In a TAB tape having a BOF structure, wiring is formed on a film-like insulating substrate, and bumps are formed on the wiring. When such a TAB tape is used for electrical connection with, for example, a semiconductor chip, it is necessary to form wirings and bumps on the insulating substrate in accordance with the positions of electrode pads formed on the semiconductor chip.

A conventional method for manufacturing a TAB tape having a BOF structure will be described below.
First, after preparing a copper-clad base material having a structure in which a copper foil is laminated on an insulating substrate, after covering the copper foil with a resist layer made of a photosensitive resist, by subjecting the resist layer to exposure and development, A resist pattern is formed in accordance with a desired wiring pattern. Next, the copper foil on the insulating substrate is etched using the resist pattern as a mask. Thereby, the copper foil on the insulating substrate is processed according to the shape of the resist pattern. Thereafter, the resist pattern used in the etching is removed from the insulating substrate.

  Next, after covering the wiring on the insulating substrate with a resist layer, the resist layer is exposed and developed to form a resist pattern having openings at positions where bumps are to be formed. At this time, a part of the wiring is exposed in the opening of the resist pattern. Next, bumps are formed by depositing a metal by plating (semi-additive method) on the wiring exposed in the opening. Next, the resist pattern used in the plating method is removed from the insulating substrate. Next, the surface of the wiring and bump on the insulating substrate is covered with a protective plating layer. Thereafter, if necessary, the main part (including part of the wiring) on the insulating substrate is covered with an insulating protective film.

JP 2006-216694 A

  The prior art described above has the following disadvantages when it is desired to increase the bump height. That is, the bump aspect is increased due to the bump miniaturization, so that the bump easily falls during and after the production of the wiring board, and the strength of the bump also decreases. For this reason, there is a limit to increasing the height of the bump.

  The main object of the present invention is to provide a technology capable of increasing the height of the bump while suppressing the collapse of the bump during and after the production of the wiring board and maintaining the strength of the bump. is there.

The first aspect of the present invention is:
An insulating substrate;
Wiring formed on the insulating substrate;
A bump formed on the wiring,
The bump is a wiring board characterized by having a multi-stage structure that gradually increases from the top to the bottom of the bump.

The second aspect of the present invention is:
The bump has a stepped dimension from the top to the bottom of the bump in at least one of the width direction and the length direction of the wiring at the bump formation site or in a direction oblique thereto. The wiring board according to the first aspect, wherein the wiring board has a multi-stage structure.

The third aspect of the present invention is:
The ratio of the height dimension of the bump to the dimension of the top of the bump in at least one of the width direction and the length direction of the wiring or in an oblique direction thereof is 1.2 or more. A wiring board according to the second aspect, characterized in that:

The fourth aspect of the present invention is:
As a manufacturing process of a wiring board comprising an insulating substrate, a wiring formed on the insulating substrate, and a bump formed on the wiring,
A bump forming step of forming the bump by etching a conductor layer formed on at least one surface of the insulating substrate;
A wiring forming step of forming the wiring by etching the conductor layer so as to leave the bump formed by the bump forming step;
Have
In the bump forming step, the bump is formed so as to have a multi-stage structure that gradually increases from the top to the bottom of the bump.

According to a fifth aspect of the present invention,
In the bump formation step, the size of the bump in at least one of the width direction and the length direction of the wiring at the bump formation site or in an oblique direction from the top to the bottom of the bump. The method for manufacturing a wiring board according to the fourth aspect, wherein the bumps are formed so as to have a multistage structure that increases stepwise.

The sixth aspect of the present invention is:
In the bump forming step, a resist pattern forming step of forming a resist pattern corresponding to the shape and size of the bump on the conductor layer and at a position where the bump is to be formed, and using the resist pattern as a mask, The wiring board manufacturing method according to the fourth or fifth aspect, wherein the multi-stage bump is obtained by repeating an etching step of half-etching the conductor layer a plurality of times.

The seventh aspect of the present invention is
In the bump forming step, at least one of the plurality of etching steps is performed by half-etching the conductor layer using an etching solution to which an etching inhibitor is added. It is a manufacturing method of the wiring board as described in an aspect.

  ADVANTAGE OF THE INVENTION According to this invention, the height of a bump can be made high, suppressing the fall of the bump during manufacture of a wiring board, or after manufacture, and maintaining the intensity | strength of a bump.

It is a schematic plan view which shows one structural example of the wiring board which concerns on embodiment of this invention. It is principal part sectional drawing of the wiring board shown in FIG. It is the P section enlarged view of FIG. It is process drawing (the 1) which shows an example of the manufacturing method of the wiring board which concerns on embodiment of this invention. It is process drawing (the 2) which shows an example of the manufacturing method of the wiring board which concerns on embodiment of this invention. It is process drawing (the 3) which shows an example of the manufacturing method of the wiring board which concerns on embodiment of this invention. It is a top view which shows the state of the insulated substrate of the step which formed the 1st resist pattern on the insulated substrate. It is a top view which shows the state of the insulated substrate of the step which formed the 2nd resist pattern on the insulated substrate. It is a top view which shows the state of the insulated substrate in the stage which formed the 3rd resist pattern on the insulated substrate. It is FIG. (1) explaining the modification etc. of this invention. It is FIG. (2) explaining the modification etc. of this invention. It is FIG. (3) explaining the modification etc. of this invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
In the embodiment of the present invention, description will be given in the following order.
1. Configuration of wiring board 2. Manufacturing method of wiring board 2-1. Bump formation process 2-1-1. First resist pattern forming step 2-1-2. First etching step 2-1-3. Second resist pattern forming step 2-1-4. Second etching step 2-2. Wiring formation process 2-2-1. Third resist pattern forming step 2-2-2. Third etching step 2-3. Post process 3. Effects according to the embodiment Modifications etc.

<1. Configuration of wiring board>
FIG. 1 is a schematic plan view showing a configuration example of a wiring board according to an embodiment of the present invention. 2A is a cross-sectional view taken along line x1-x1 in FIG. 1, and FIG. 2B is a cross-sectional view taken along line y1-y1 in FIG. In FIG. 1, for convenience of explanation, a direction parallel to one side of the wiring board 1 is referred to as an “X direction”, a direction perpendicular thereto is referred to as a “Y direction”, and a thickness direction of the wiring board 1 is referred to as a “Z direction”. " These three directions are orthogonal to each other.

The illustrated wiring board 1 includes an insulating substrate 2, wiring 3 formed on the insulating substrate 2, and bumps 4 formed on the wiring 3.
The wiring board 1 is configured based on an insulating board 2 having electrical insulation. The insulating substrate 2 is made of, for example, a flexible resin film and is formed in a rectangular shape as a whole. In this case, the wiring board 1 is a flexible wiring board. The wiring board 1 is a flexible wiring board having a BOF structure due to the presence of the bumps 4 on the wiring 3. The bump 4 described here is a portion that protrudes above the upper surface 3 a of the wiring 3 and does not include the wiring 3. For the insulating substrate 2, for example, a resin film having a thickness of 25 to 125 μm can be used.

The insulating substrate 2 can be preferably formed using a polyimide resin. However, in addition to this, for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyphenylene sulfide (PPS), polyamideimide (PAI), or aramid may be used as the main material of the insulating substrate 2. it can. In addition, as a constituent material of the insulating substrate 2, BT (bismaleimide triazine) resin, LCP (Liquid Crystal)
Plastic) or the like can also be used. The insulating substrate 2 is formed in a desired shape (rectangular in the illustrated example) in the manufacturing process of the wiring substrate 1 to be described later, for example, based on a base substrate having a long film (tape) shape. And it is separated into individual pieces by cutting into dimensions.
However, the wiring board 1 may be distributed as a single board product in a state before being separated into individual pieces, or may be distributed as a single board product in a state after being separated into individual pieces.

  A wiring 3 is formed on one surface (hereinafter also referred to as “main surface”) 2 a of the insulating substrate 2. The wiring 3 is configured using, for example, a conductive material such as copper. The wiring 3 is formed in accordance with a predetermined pattern shape. The position, shape, dimensions, and the like of the wiring 3 on the insulating substrate 2 can be arbitrarily set or changed according to an object (not shown) that is electrically connected to the wiring 3. Incidentally, in FIG. 1, a plurality of wirings 3 are formed in parallel in a linear pattern on the insulating substrate 2. For this reason, in the formation part of the bump 4, the width direction of the wiring 3 corresponds to the X direction, the length direction of the wiring 3 corresponds to the Y direction, and the thickness direction of the wiring 3 corresponds to the Z direction.

  Bumps 4 are formed on the wiring 3 of the insulating substrate 2. The bumps 4 are formed at predetermined positions on the insulating substrate 2. The bump 4 is formed so as to protrude in the Z direction from the upper surface 3 a of the wiring 3. The upper surface 41 a of the bump 4 is formed flat so as to be parallel to the main surface 2 a of the insulating substrate 2. The bumps 4 are formed in a circular shape in plan view. The bump 4 is formed integrally with the wiring 3 using the same material (copper in this embodiment) as the conductive material used for forming the wiring 3. That is, the wiring 3 and the bump 4 are integrally formed with no boundary (crystal grain boundary) where the crystal is discontinuous between them. The position, shape, dimensions, and the like of the bump 4 on the wiring 3 can be arbitrarily set or changed according to the position of the electrode of the object that is physically connected (joined) or contacted with the bump 4. .

Here, the dimension of each part in the wiring board 1 is demonstrated using FIG.
FIG. 3 is an enlarged view of a portion P in FIG. The symbol W in the figure indicates the width dimension of the wiring 3 in the base portion of the bump 4. In the figure, the symbol T indicates the thickness dimension of the wiring 3, and the symbol H indicates the height dimension of the bump 4.
As shown in the figure, the bumps 4 are formed in a multi-stage structure in which the dimensions (Lb1, Lb2) of the bumps 4 in the X direction in the bump 4 formation site increase stepwise from the top to the bottom of the bumps 4. . A multistage structure refers to a structure having two or more stages. The top of the bump 4 refers to the top of the bump 4 (the end far from the insulating substrate 2), and the bottom of the bump 4 refers to the bottom of the bump 4 in contact with the upper surface 3a of the wiring 3 (insulating substrate). 2). The details are described below.

  The bump 4 has a two-step upper and lower stepped structure having a first-step bump portion 41 and a second-step bump portion 42. The first bump portion 41 is arranged in the upper stage, and the second bump portion 42 is arranged in the lower stage. When the dimensions of the bump portions 41 and 42 are compared in the X direction, which is the width direction of the wiring 3, the size Lb1 of the first bump portion 41 is set smaller than the size Lb2 of the second bump portion 42. Yes. The dimension Lb1 is preferably set to a dimension range of 5 μm or more and 40 μm or less, and the difference between the dimension Lb2 and the dimension Lb1 is set to 10 μm on one side (20 μm on both sides), more preferably 5 μm on one side (10 μm on both sides). Has been. Further, the first bump portion 41 and the second bump portion 42 are arranged concentrically as shown in FIG. For this reason, with respect to the dimension of the bump 4 in the Y direction, the dimension Lb1 of the bump part 41 in the first stage is set smaller than the dimension Lb2 of the bump part 42 in the second stage. Further, the dimension Lb2 of the second bump portion 42 is set to be equal to or less than the width dimension W of the wiring 3. A specific manufacturing method for obtaining such a multistage bump 4 will be described in detail later.

As another element that defines the size of the bump 4, the aspect ratio of the bump 4 is preferably set to 1 or more, more preferably 1.5 or more. The aspect ratio of the bump 4 described here is defined as follows.
That is, the dimension Lb1 of the bump part 41 in the first stage is set as the dimension Lb1 of the top part of the bump 4. Further, the height dimension of the bump part 41 of the first stage described above is “H1”, the height dimension of the bump part 42 of the second stage is “H2”, and the sum of these is the height of the bump 4. Dimension H. In such a case, the aspect ratio of the bump 4 is defined by the ratio (H / Lb1) of the height dimension H of the bump 4 to the dimension Lb1 at the top of the bump 4. Although the maximum value of the aspect ratio of the bump 4 depends on the strength of the bump 4 and the manufacturing limit, it is preferable to set it to about 5 or less.

  In the present embodiment, since the bump 4 is formed in a circular shape (like a wedding cake) in plan view, the dimension Lb1 of the first bump part 41 and the dimension Lb2 of the second bump part 42 are as follows. These correspond to the diameters of the bump portions 41 and 42, respectively. Further, the upper surface 41a of the first-stage bump portion 41 and the upper surface 42a of the second-stage bump portion 42 are formed flat. In particular, the upper surface 41a of the first bump portion 41 has higher flatness than the upper surface 42a of the second bump portion 42. The reason will be described together with the manufacturing method of the wiring board 1 described later.

The bottom of the first bump portion 41 is in contact with the upper surface 42a of the second bump portion 42 over the entire circumference, and the bottom of the second bump portion 42 (bump 4) is the wiring 3 over the entire circumference. It is in contact with the upper surface 3a. That is, the upper surface 42a of the second bump portion 42 exists around the entire first bump portion 41, and the entire upper portion 42a of the second bump portion 42 (bump 4) is surrounded by the entire upper periphery 42a. The upper surface 3a of the wiring 3 exists over the circumference.
Although not shown, when the bump 4 is formed in a rectangular shape in plan view, the dimension Lb1 of the first bump part 41 and the dimension Lb2 of the second bump part 42 in FIG. This corresponds to the dimension of the portion in the X direction.

Further, the thickness dimension T of the wiring 3 and the height dimension H of the bump 4 are set as follows. That is, the dimension obtained by adding the thickness dimension T of the wiring 3 and the height dimension H of the bump 4 (thickness dimension of the copper foil 11 described later) is, for example, in the range of 15 to 100 μm, preferably in the range of 20 to 50 μm. Is set to Further, the thickness dimension T of the wiring 3 and the height dimension H of the bump 4 are set to a predetermined dimensional relationship.

<2. Manufacturing method of wiring board>
Then, an example of the manufacturing method of the wiring board which concerns on embodiment of this invention is demonstrated using FIGS. 4 to 6, the cross section at the position x1-x1 in FIG. 1 is shown on the left side, and the cross section at the position y1-y1 in FIG. 1 is shown on the right side.
Here, a series of manufacturing steps of the wiring board will be roughly classified into “bump forming step”, “wiring forming step”, and “post-process”. The “bump formation step” will be described separately as “first resist pattern formation step”, “first etching step”, “second resist pattern formation step”, and “second etching step”. The “wiring forming step” will be described separately as a “third resist pattern forming step” and a “third etching step”.

(2-1. Bump formation process)
The bump forming step is a step of forming a bump 4 by etching a conductor layer (described later) formed on at least one surface of the insulating substrate 2. This will be described in detail below.

(2-1-1. First resist pattern forming step)
First, as shown in FIG. 4A, a copper-clad base material is prepared by forming a copper foil 11 as a metal foil on at least one surface of an insulating substrate 2 by lamination or the like. The copper foil 11 has a thickness of 40 μm, for example, within the range of the thickness dimension described above. The thickness dimension of the copper foil 11 corresponds to the dimension obtained by adding the thickness dimension T of the wiring 3 and the height dimension H of the bump 4 shown in FIG. The accuracy of the thickness dimension of the copper foil 11 in the copper-clad substrate is, for example, ± 0.1 μm or less. The copper foil 11 is a component corresponding to a “conductor layer” formed on one side of the insulating substrate 2. The conductor layer may be formed of a metal foil other than copper, or may be formed of a layer other than the metal foil. However, in consideration of the flatness of the surface of the conductor layer formed on one side of the insulating substrate 2 and the accuracy of the thickness dimension of the conductor layer, a copper-clad base material having a copper foil as a metal foil on one side or both sides is used. desirable. At this stage, it is assumed that the insulating substrate 2 made of a copper-clad base material has a long film shape.

  Next, as shown in FIG. 4B, a first resist layer 12 is formed on one side of the insulating substrate 2 so as to cover the copper foil 11. The first resist layer 12 is formed by laminating, for example, a dry film resist having a thickness of 15 μm on one surface of the insulating substrate 2. The thickness of the dry film resist can be appropriately changed according to the composition of the etching solution used in the first etching step described later, the desired etching amount, and the like. There are two types of apparatuses (hereinafter referred to as “laminators”) for laminating dry film resists depending on the pressure atmosphere. One is a type that laminates in a normal pressure atmosphere, and the other is a type that laminates in a reduced pressure atmosphere (including a vacuum atmosphere) lower than the normal pressure. Among these, it is desirable to use the former laminator from the viewpoint of production efficiency and manufacturing cost, and it is desirable to use the latter laminator from the viewpoint of preventing air bubbles from being mixed. At the stage of FIG. 4B, since the surface of the copper foil 11 is flat, it is preferable to use the former laminator.

  Next, after exposing the 1st resist layer 12 using the photomask which adapts the shape and dimension of the bump part 41 of the 1st step | paragraph of the bump 4 mentioned above, the unnecessary part of the 1st resist layer 12 is developed by development. By removing, the first resist pattern 13 corresponding to the shape and size of the bump part 41 of the first stage of the bump 4 is formed on the copper foil 11 as shown in FIG. Since the first resist pattern 13 is a mask used for etching in a first etching process to be described later, it has etching resistance.

FIG. 7 is a plan view showing the state of the insulating substrate 2 at the stage where the first resist pattern 13 is formed on the insulating substrate 2. As shown in the figure, the first resist pattern 13 is formed at the planned formation position of the bump 4 shown in FIG.

(2-1-2. First Etching Step)
Next, as shown in FIG. 4D, the copper foil 11 is etched using the first resist pattern 13 as a mask. However, at this stage, “half etching” is applied in which etching is performed so as to leave a part of the copper foil 11 in the thickness direction of the insulating substrate 2. When half-etching is applied, the portion covered with the first resist pattern 13 is not etched, and the portion not covered with the first resist pattern 13 (exposed portion) is etched. However, the depth dimension by etching is set (adjusted) according to the height dimension H1 of the bump part 41 in the first stage. The surface state of the copper foil 11 after half-etching is a state in which only the portion covered with the first resist pattern 13 protrudes. This protruding portion becomes the first bump portion 41 of the bump 4.

  Next, as shown in FIG. 4E, the first resist pattern 13 is removed from the insulating substrate 2. The removal of the first resist pattern 13 is performed using, for example, a resist remover. As a result, a first bump portion 41 is formed in a protruding shape on the surface of the copper foil 11 by a predetermined number of bumps 4.

Here, the etching method of the copper foil 11 in the first etching step will be described in detail. In the first etching step, the copper foil 11 is half-etched by the method described below.
First, the copper foil 11 is etched by wet etching using an etchant. At that time, it is preferable to etch the copper foil 11 while suppressing isotropic etching using an etching solution to which an etching inhibitor (inhibitor) is added. Specifically, the copper foil 11 may be half-etched by spraying an etching solution to which an etching inhibitor is added onto the copper foil 11 on the insulating substrate 2 by employing, for example, a spray method. As an etchant, for example, a ferric chloride (FeCl ₃ ) solution, a cupric chloride (CuCl ₂ ) solution, or the like can be used. Moreover, as an etching inhibitor, compounds, such as amines, ethers, glycols, azoles, etc. can be used, for example.

  When an etching solution to which such an etching inhibitor is added is sprayed vertically onto the copper foil 11 by spraying or the like, the etching solution is directly sprayed on the surface of the copper foil 11 not covered with the first resist pattern 13. Further, since the etching solution is sprayed vertically toward the copper foil 11, the etching pressure of the etching solution is applied to the surface of the copper foil 11. On the other hand, the portion of the copper foil 11 covered with the first resist pattern 13 is shielded (protected) by the first resist pattern 13 against the spray of the etchant. For this reason, the etching solution is not directly sprayed on the portion of the copper foil 11 covered with the first resist pattern 13.

In such a case, the etching solution is sprayed with a striking force on the surface of the copper foil 11 that is not covered with the first resist pattern 13. For this reason, even when an etching solution to which an etching inhibitor is added is used, the etching of the surface of the copper foil 11 not covered with the first resist pattern 13 proceeds vertically. On the other hand, the jetting pressure (striking force) of the etching liquid hardly acts on the portion of the copper foil 11 covered with the first resist pattern 13. In addition, since an etching inhibitor is added to the etching solution, a poorly soluble compound is generated on the side walls of the bumps 4 in parallel with the progress of the etching in the vertical direction described above. Due to the generation of the hardly soluble compound, an etching protective film is formed on the side wall of the bump 4. For this reason, horizontal etching (side etching) hardly proceeds in the portion of the copper foil 11 covered with the first resist pattern 13. Therefore, the portion of the copper foil 11 covered with the first resist pattern 13 remains as the first bump portion 41 in a manner that faithfully reproduces the shape, dimensions, etc. of the first resist pattern 13. Therefore, the first bump portion 41 obtained after the etching is formed with a uniform dimension Lb1 from the upper part to the lower part.

(2-1-3. Second resist pattern forming step)
Next, as shown in FIG. 5A, the second resist layer 16 is formed on the insulating substrate 2 so as to cover the copper foil 11 and the first bump portion 41. The second resist layer 16 is formed, for example, by laminating a dry film resist on one side of the insulating substrate 2 so as to cover the copper foil 11 as described above. At this stage, the surface of the copper foil 11 is uneven due to the presence of the first bump portion 41. For this reason, it is desirable to use a dry film resist thicker than the dry film resist used in the first resist pattern forming step. For example, if the thickness of the dry film resist used in the first resist pattern forming step is 15 μm, it is desirable to use a thicker 25-30 μm dry film resist in the second resist pattern forming step. . However, the thickness of the dry film resist used in the second resist pattern forming step can be appropriately changed according to the composition of the etching solution used in the second etching step described later, the desired etching amount, and the like. Regarding the laminator to be used, it is preferable to use a laminator that is laminated in a reduced-pressure atmosphere that is effective in suppressing the mixing of air bubbles among the two types of laminators described above.

  Next, the second resist layer 16 is exposed using a photomask that matches the shape and dimensions of the second bump portion 42 of the bump 4, and then unnecessary portions of the second resist layer 16 are removed by development. As a result, as shown in FIG. 5B, the second resist pattern corresponding to the shape and dimensions of the second bump portion 42 is formed on the copper foil 11 at a position overlapping the first bump portion 41. 17 is formed. The alignment between the first-stage bump portion 41 and the second resist pattern 17 may be performed, for example, by providing an alignment mark on the insulating substrate 2 and using this alignment mark. Specifically, the position of the alignment mark is recognized by image processing or the like, and the photomask may be positioned with respect to the insulating substrate 2 based on the recognition result. Since the second resist pattern 17 is a mask used for etching in a second etching step to be described later, it has etching resistance.

  FIG. 8 is a plan view showing a state of the insulating substrate 2 at the stage where the second resist pattern 17 is formed on the insulating substrate 2. As shown in the drawing, the second resist pattern 17 is formed at the planned formation position of the bump 4 shown in FIG. Further, the second resist pattern 17 is formed so as to cover the entire surface of the first bump portion 41 formed on the surface of the copper foil 11.

(2-1-4. Second etching step)
Next, as shown in FIG. 5C, the copper foil 11 is etched using the second resist pattern 17 as a mask. Even at this stage, the above-described “half etching” is applied to leave a part of the copper foil 11. The depth dimension by etching is set in accordance with the height dimension H2 of the bump part 42 in the second stage. As a result, the second bump portion 42 is formed below the first bump portion 41. At this time, if the second resist pattern 17 is formed so as to cover the entire surface of the first-step bump portion 41, the bottom of the first-step bump portion 41 is completely removed when the copper foil 11 is etched. A structure in contact with the upper surface 42a of the bump part 42 at the second stage over the circumference is obtained.

As in the first etching step, the second etching step is preferably performed by spraying an etching solution added with an etching inhibitor vertically onto the copper foil 11 on the insulating substrate 2. 11 may be performed by half-etching. As a result, the second bump portion 42 obtained after etching is formed to have a uniform dimension Lb2 from the upper part to the lower part.

Next, as shown in FIG. 5D, the second resist pattern 17 is removed from the insulating substrate 2. The removal of the second resist pattern 17 is performed using, for example, a resist remover. As a result, the bump 4 having a multi-stage structure including the first-stage bump portion 41 and the second-stage bump portion 42 is formed on the insulating substrate 2.
In the following description, a bump structure that is not a multistage structure (stepped structure) is described as a “non-multistage structure” for comparison with the bump 4 having a multistage structure.

Here, the reason why the upper surface 41a of the first bump portion 41 is formed with higher flatness than the upper surface 42a of the second bump portion 42 will be described.
First, when the surface of the copper foil 11 laminated on the insulating substrate 2 is partially etched, the bottom surface of the actually etched recess is less flat than the surface of the original copper foil 11 due to the influence of etching. Become. Further, the upper surface 41 a of the first bump portion 41 is formed by a part of the surface of the copper foil 11, whereas the upper surface 42 a of the second bump portion 42 is formed by etching the copper foil 11. Is done. For this reason, the upper surface 41a of the bump part 41 of the first step has higher flatness than the upper surface 42a of the bump part 42 of the second step. However, when the copper foil 11 is half-etched using the etching solution to which the etching inhibitor is added, the flatness of the etched surface is compared with the case of using a normal etching solution to which no etching inhibitor is added. There is an advantage that becomes high.

(2-2. Wiring formation process)
The wiring forming step is a step of forming the wiring 3 by etching the copper foil 11 so as to leave the bumps 4 formed by the bump forming step. This will be described in detail below.

(2-2-1. Third resist pattern forming step)
Next, as shown in FIG. 6A, a third resist layer 18 is formed on the insulating substrate 2 so as to cover the copper foil 11 and the bumps 4. The third resist layer 18 is formed, for example, by laminating a dry film resist on one surface of the insulating substrate 2 so as to cover the copper foil 11 as described above. At this stage, the surface of the copper foil 11 is uneven due to the presence of the bumps 4. For this reason, it is desirable to use a dry film resist thicker than the dry film resist used in the first resist pattern forming step. For example, if the thickness of the dry film resist used in the first resist pattern forming step is 15 μm, it is desirable to use a thicker dry film resist of 20 to 30 μm in the third resist pattern forming step. . However, the thickness of the dry film resist used in the third resist pattern forming step can be appropriately changed according to the composition of the etching solution used in the third etching step described later, the desired etching amount, and the like. Regarding the laminator to be used, it is preferable to use a laminator that is laminated in a reduced-pressure atmosphere that is effective in suppressing the mixing of air bubbles among the two types of laminators described above.

  Next, after the third resist layer 18 is exposed using a photomask that conforms to the shape and dimensions of the pattern of the wiring 3 described above, unnecessary portions of the third resist layer 18 are removed by development, thereby removing the figure. As shown in FIG. 6B, a third resist pattern 19 corresponding to the shape and dimensions of the wiring 3 is formed on the copper foil 11 and at a position overlapping the bump 4. The alignment between the bump 4 and the third resist pattern 19 may be performed using an alignment mark or the like as described above. Since the third resist pattern 19 is a mask used for etching in a third etching process to be described later, it has etching resistance.

FIG. 9 is a plan view showing the state of the insulating substrate 2 at the stage where the third resist pattern 19 is formed on the insulating substrate 2. As shown in the figure, the third resist pattern 19 is formed at the planned formation position of the wiring 3 shown in FIG. Further, the third resist pattern 19 is formed so as to cover the entire surface of the bump 4 (first bump portion 41 and second bump portion 42) formed on the surface of the copper foil 11.

(2-2-2. Third etching step)
Next, as shown in FIG. 6C, the copper foil 11 is etched using the third resist pattern 19 as a mask. At this stage, in the thickness direction of the insulating substrate 2, “full etching” is applied in which etching is performed without leaving a portion of the copper foil 11 not covered with the third resist pattern 19. That is, except for the portion covered with the third resist pattern 19, the copper foil 11 remaining after the half etching in the second etching step is completely removed by full etching. Further, as shown in FIG. 3, the copper foil 11 is fully etched so that the width dimension W of the wiring 3 is equal to or larger than the dimension Lb2 of the bump part 42 in the second stage. At this time, if the third resist pattern 19 is formed so as to cover the entire surface of the bump 4, when the copper foil 11 is etched, the bottom of the second bump portion 42 (bump 4) Thus, a structure in contact with the upper surface 3a of the wiring 3 is obtained.

  In the third etching step, normal wet etching using an etchant to which no etching inhibitor is added may be applied. However, if it is desired to maintain the dimensions and shape of the wiring 3 with high accuracy, the copper foil 11 on the insulating substrate 2 can be applied to the copper substrate 11 on the insulating substrate 2 as necessary, similarly to the first etching process and the second etching process. Therefore, it is desirable to employ a method in which an etching solution to which an etching inhibitor is added is sprayed vertically.

  Next, as shown in FIG. 6D, the third resist pattern 19 is removed from the insulating substrate 2. The removal of the third resist pattern 19 is performed using, for example, a resist remover. As a result, the wiring 3 is formed on the insulating substrate 2 and the bumps 4 having a multistage structure are formed on the wiring 3.

(2-3. Post process)
Thereafter, although not shown, a protective plating layer is formed on the surfaces of the wiring 3 and the bumps 4. This plating layer is formed by, for example, gold plating.
Next, a resin protective film is formed on the insulating substrate 2 so as to cover the main part of the wiring 3 except for the bumps 4. This protective film may be formed as necessary.
Next, the insulating substrate 2 is separated into pieces by punching or the like. However, when the long film-shaped wiring board 1 before being separated into individual pieces is distributed as a product, it is not necessary to perform the individualization step.
The wiring board 1 according to the embodiment of the present invention is obtained by the above manufacturing process.

<3. Effect of Embodiment>
In the present embodiment, since the bumps 4 formed on the wiring 3 of the insulating substrate 2 have a multi-stage structure, the bumps are less likely to collapse during and after the production of the wiring board than the non-multi-stage bumps. Also, when bumps of the same height are formed on the wiring with multi-stage structure and non-multi-stage structure, the bump of multi-stage structure is better than the bump of multi-stage structure under the condition that the top dimension of the bump of each structure is the same. The strength is much higher than that. The main reason why such an action is obtained is that, in the case of the bump 4 having the above-described multi-stage structure, the first-stage bump portion 41 is supported from below by the second-stage bump portion 42 having a larger dimension. Because.
From the above, when a bump with a multi-stage structure is adopted, the bump height can be increased while suppressing the collapse of the bump during and after the production of the wiring board and maintaining the strength of the bump. it can.

  Further, if the bump aspect ratio is as high as 1.2 or more, and further 1.5 or more, the bump collapses very easily during the manufacturing process (etching process or the like) in the bump having a non-multistage structure. For this reason, when forming bumps having an aspect ratio of 1.2 or more, more preferably 1.5 or more, it is particularly effective to employ bumps 4 having a multistage structure.

  Further, as described in the above manufacturing process, if the bumps 4 and the wirings 3 having a multi-stage structure are formed by sequentially etching the copper foil 11 on the insulating substrate 2, the boundary where the crystals become discontinuous (crystal grains They can be formed integrally in the absence of a boundary. As a result, peeling or the like hardly occurs at the boundary portion between the first bump portion 41 and the second bump portion 42 or at the boundary portion between the second bump portion 42 and the wiring 3. Therefore, the effect of suppressing the collapse of the bump and the effect of increasing the strength of the bump are greater than when the bump is formed by plating. Further, the electrical characteristics (electric resistance value, etc.) of the wiring 3 and the bump 4 are also stable.

Moreover, in the manufacturing method of the wiring board 1 of this embodiment, the bump 4 having a multistage structure is formed by etching the copper foil 11 formed on the insulating substrate 2. According to this method, since the etching rate is faster than the growth rate of plating, the time required for bump formation is shorter than when a bump having a multi-stage structure is formed by plating. For this reason, productivity higher than a plating process is realizable. Further, since the height of the bump 4 formed on the wiring 3 is determined by the etching amount of the half etching, the height variation of the bump 4 is smaller than that of the bump formation by the plating process. The reason is that in the plating process, the current density distribution changes due to the influence of the wiring pattern arrangement (mainly density) and it is difficult to obtain bumps of uniform height.
From the above, the height variation of the bumps 4 can be reduced and the productivity can be improved as compared with bump formation by plating.

Furthermore, according to the manufacturing method of the wiring board 1 of this embodiment, the following effects can be obtained in addition to the above effects.
That is, in the first etching step, the first-stage bump portion 41 is formed by half-etching the copper foil 11 by spraying an etching solution added with an etching inhibitor perpendicularly to the copper foil 11. . Also in the second etching step, the second-stage bump portion 42 is formed by half-etching the copper foil 11 by spraying an etching solution added with an etching inhibitor perpendicularly to the copper foil 11. .
For this reason, there are the following merits (1) and (2).
(1) Immediately below the first resist pattern 13, the copper foil 11 is etched while suppressing isotropic etching, so that the side wall of the first bump portion 41 obtained after the etching is vertical. In addition, the shape, dimensions, and the like of the first resist pattern 13 are faithfully reproduced as the shapes, dimensions, and the like of the first-stage bump portion 41.
Similarly, since the copper foil 11 is etched immediately under the second resist pattern 17 while suppressing isotropic etching, the side wall of the second bump portion 42 obtained after the etching is vertical. In addition, the shape, dimensions, and the like of the second resist pattern 17 are faithfully reproduced as the shapes, dimensions, etc. of the second bump portion 42.
For this reason, the fine bumps 4 can be formed on the wiring 3 with high accuracy. Further, in a normal wet etching using an etching solution to which no etching inhibitor is added, the side walls of the bumps 4 are tapered outwardly by side etching. For this reason, it is necessary to set the line width of the wiring 3 that becomes the base portion of the bump 4 to be thick in advance in anticipation of a tapered shape by side etching. On the other hand, when the manufacturing method of the present embodiment is employed, the first bump portion 41 and the second bump portion 42 are formed vertically with uniform dimensions Lb1 and Lb2, respectively. The line width W of the wiring 3 that becomes the base portion of the line 4 can be set relatively narrow. For this reason, the pitch between the bumps 4 adjacent in the width direction X of the wiring 3 can be reduced. Therefore, the bump 4 can be miniaturized and the pitch can be reduced at the same time.
(2) In the first etching step, when the copper foil 11 is half-etched using the first resist pattern 13 as a mask, the surface of the copper foil 11 is the top of the bump 4 (the bump portion 41 of the first step). The upper surface 41a) will be formed. For this reason, the top of the bump 4 can be formed flat.

Such a merit is particularly effective when, for example, the wiring board 1 manufactured by the manufacturing method of the present embodiment is used as an inspection probe board.
The inspection probe substrate is used when, for example, inspecting the electrical characteristics of each semiconductor element formed in a matrix arrangement on a wafer. Each semiconductor element has a plurality of electrode pads. For this reason, when inspecting the electrical characteristics of the semiconductor element, it is necessary to bring the bumps of the inspection probe substrate into contact with the electrode pads of the semiconductor element. At this time, if there are variations in the bump height of the inspection probe substrate, the plurality of bumps formed on the inspection probe substrate can be simultaneously brought into contact with the plurality of electrode pads formed on the semiconductor element. Disappear. Further, when the size of the top of the bump is increased, there is a high possibility that the bump comes into contact with an electrode pad other than the electrode pad to be originally connected due to a relative positional shift between the semiconductor element and the inspection probe substrate.

  On the other hand, when the manufacturing method of this embodiment is applied, the height variation of the bumps 4 is reduced, so that the plurality of electrode pads formed on the semiconductor element are formed on the inspection probe substrate (wiring substrate 1). The plurality of bumps 4 can be brought into contact with each other at the same time. Moreover, since the tops of the bumps 4 are formed flat, the contact state between the electrode pads and the bumps 4 becomes stable. In addition, since the fine bumps 4 can be formed on the wiring 3 with high accuracy, the position of the bumps 4 from the electrode pads to be originally connected can be obtained even if there is a relative misalignment between the semiconductor element and the inspection probe substrate. Is difficult to come off. In particular, the top portion of the bump 4 that directly contacts the electrode pad can be formed very small by the bump portion 41 of the first stage, so that a larger margin can be secured as the relative positional deviation. It becomes possible. Further, since the bump 4 has excellent mechanical strength, even when the bump 4 of the inspection probe substrate is repeatedly brought into contact with each semiconductor element on the wafer, the bump 4 is a boundary portion with the wiring 3. There is no possibility that the bump 4 will be peeled off or the bump 4 itself will fall down. Furthermore, since the bumps 4 can be miniaturized and the pitch can be reduced at the same time, it is possible to flexibly cope with the miniaturization and narrowing of the electrode pads accompanying the downsizing of the semiconductor element.

In the method for manufacturing the wiring board 1 of the present embodiment, the second resist pattern 17 is formed in a state in which the entire surface of the first bump portion 41 is covered in the second resist pattern forming step. For this reason, in the second etching step performed thereafter, the copper foil 11 is half-etched by protecting the entire surface of the first-step bump portion 41 with the second resist pattern 17 and the second-step bump portion. 42 can be formed.
Thereby, the dimension, shape, etc. of the bump part 41 in the first stage are not broken by the half etching in the second etching process. Therefore, the size, shape, and the like of the first bump portion 41 obtained in the first etching process can be maintained with high accuracy as they are in the second etching process.

Similarly, in the third resist pattern forming step, the third resist pattern 19 is formed so as to cover the entire surface of the first bump portion 41 and the second bump portion 42. For this reason, in the subsequent third etching step, the copper foil 11 is fully etched while protecting the entire surface of the first bump portion 41 and the second bump portion 42 with the third resist pattern 19. Thus, the wiring 3 can be formed.
Thereby, the dimension, shape, etc. of the bump part 41 of the first step and the bump part 42 of the second step are not destroyed by the full etching in the third etching process. Therefore, each dimension, shape, and the like of the first-step bump portion 41 obtained in the first etching step and the second-step bump portion 42 obtained in the second etching step are changed in the third etching step. The high accuracy can be maintained as it is.

  Further, according to the present embodiment, it is possible to realize a high aspect of the bump 4. When the aspect ratio of the bumps 4 is increased, for example, when the wiring substrate 1 is used as the above-described inspection probe substrate, it is less likely to be affected by foreign matter. The reason is as follows. First, when the aspect ratio of the bump 4 is increased, the height (protrusion dimension) of the bump 4 is increased even when the bump 4 has the same dimension in plan view. For this reason, even if there is a foreign substance on the semiconductor element, the bump 4 can be brought into contact with the electrode pad of the semiconductor element so as to straddle the foreign substance if the protruding dimension of the bump 4 is larger than the dimension of the foreign substance. . For this reason, it becomes difficult to receive the influence of a foreign material. Therefore, it is suitable for use as an inspection probe substrate.

<4. Modified example>
The technical scope of the present invention is not limited to the above-described embodiments, and includes various modifications and improvements as long as the specific effects obtained by the constituent elements of the invention and combinations thereof can be derived.

  For example, the position of the bump 4 formed on the wiring 3 may be not the middle of the wiring 3 but the end of the wiring 3 or the vicinity thereof. In that case, at least one side surface of the lowermost bump portion may be formed flush with the end surface of the wiring 3 in the length direction Y. Further, regarding the dimensions of the bumps 4, the dimension of the lowermost bump part in the width direction X of the wiring 3 (the dimension Lb <b> 2 in FIG. 3) may be set to the same dimension as the width dimension W of the wiring 3.

  Moreover, the height dimensions (H1 and H2 shown in FIG. 3) of the bump portions at each stage of the bump 4 may be set not only to the same dimension but also to different dimensions. As a preferred form in that case, a form in which the height dimension of the uppermost bump part is set smaller than the height dimension of the lower bump part is conceivable. When such a form is employed, the height dimension of the entire bump can be secured large while the height dimension of the uppermost bump portion is kept small. For this reason, especially when used as a probe substrate for inspection, the height dimension of the bump portion that directly contacts the electrode pad of the semiconductor element can be kept small. For this reason, when bumps are repeatedly brought into contact with the electrode pads of the semiconductor element, the tops of the bumps are less likely to be damaged by an impact or the like at the time of contact. Therefore, an inspection probe substrate having excellent durability can be realized. Moreover, if the height dimension of the uppermost bump portion is reduced, the strength of that portion can be maintained even if the dimension Lb1 of the first bump portion 41 is reduced. In such a case, in the use of the inspection probe substrate, the dimension Lb1 of the first-stage bump portion 41 can be further reduced, so that a wide margin of relative displacement between the semiconductor element on the wafer and the inspection probe substrate is ensured. It becomes possible.

  Further, the shape of the bump 4 formed on the wiring 3 is not limited to a circle, but may be a polygon (preferably a rectangle), an ellipse, or the like. Moreover, it is good also as a thing different in planar view shape of the bump part of each step | level. As one of the preferable forms in that case, a form in which the uppermost bump part is formed in a circle or an ellipse and the lower bump part is formed in a rectangle is conceivable. When such a configuration is used, when used as a probe substrate for inspection, the outer peripheral shape of the uppermost bump portion that contacts the electrode pad of the semiconductor element is rounded, so that a minute chip or the like occurs. The effect of suppressing is obtained.

Further, even when the bump portions at each step are formed concentrically, the center position of the bump portion at each step is shifted in the X direction or the Y direction from the top to the bottom of the bump 4 (eccentric structure). May be.

  Further, as shown in FIGS. 2A and 2B, the bump 4 having a multi-stage structure is only a structure in which the cross-sectional shape of the bump 4 when viewed in the x1-x1 cross section and the y1-y1 cross section is the same. Instead, for example, the following structure may be used. That is, as shown in FIGS. 10A and 10B, the bump 4 has a multistage structure when viewed in the x1-x1 cross section and a non-multistage structure when viewed in the y1-y1 cross section. It may be. On the other hand, as shown in FIGS. 11A and 11B, the cross-sectional shape of the bump 4 is a non-multistage structure when viewed in the x1-x1 cross section and multistage when viewed in the y1-y1 cross section. It may be a structure. The bump 4 may have a multistage structure in which the size of the bump 4 in an oblique direction with respect to the X direction or the Y direction increases stepwise from the top to the bottom of the bump 4. That is, the bump 4 has a dimension of the bump 4 in at least one of the width direction X and the length direction Y of the wiring 3 at the formation site or in an oblique direction from the top to the bottom of the bump 4. What is necessary is just to become the multistage structure which becomes large in steps. However, in order to obtain a greater effect, it is preferable that the bumps 4 have a multistage structure in both the width direction X and the length direction Y of the wiring 3.

  In addition, when the bumps have a multi-stage structure, the bumps 4 are not limited to the two-stage bumps 4 described above. For example, as shown in FIG. 12, a bump 4 having a three-stage structure including three bump portions 41 to 43 may be used. It may be a multi-stage structure.

  When obtaining bumps 4 having two or more stages, a resist pattern corresponding to the shape and dimensions of bumps 4 on the copper foil 11 and at the positions where the bumps 4 are to be formed in the bump formation step described above. The bump 4 having a multi-stage structure may be obtained by repeating the process of forming the film and the process of half-etching the copper foil 11 using the resist pattern as a mask. The number of repetitions in this case may be set according to the desired number of bumps. That is, when the bump 4 having an n-stage structure (n is an integer of 2 or more) is formed, the number of repetitions of the above two steps may be set to n times. Preferably, at least one of the plurality of etching steps is performed by half-etching the copper foil 11 by spraying an etching solution added with an etching inhibitor vertically onto the copper foil 11. That's fine. In each resist pattern forming step, a resist pattern corresponding to the shape and size of the bump portion of each step of the bump 4 having a multi-step structure may be formed.

  Further, in the first resist pattern forming step, the second resist pattern forming step, and the third resist pattern forming step, a photoresist may be used instead of the dry film resist, and the resist type is also a positive type. Either a negative type or a negative type may be used.

  In addition, as a method for forming the bump 4 having a multi-stage structure on the wiring 3 of the insulating substrate 2, it is preferable to employ the bump forming method by the etching process as described above. The method may be adopted. That is, the wiring board according to the present invention is not realized only by a specific manufacturing method.

  The wiring board according to the present invention is not limited to the use of the inspection probe board. For example, when a semiconductor device having a COF (Chip On Film) structure is manufactured, the wiring board 1 using a resin film as a base material is used as a semiconductor. You may use for the use which mounts an element directly. In particular, when the wiring board 1 is used for mounting a driver IC (Integrated Circuit) for FPD (Flat Panel Display) represented by LCD (Liquid Crystal Display) and PDP (Plasma Display Panel) in the COF method, It is possible to flexibly cope with the miniaturization and narrowing of the electrode pads of the driver IC.

  Moreover, in the said embodiment, although the case where the insulating substrate 2 in which the copper foil 11 was formed in the single side | surface was used as an example of the manufacturing method of the wiring board 1, the insulation in which the copper foil 11 was formed in both surfaces is illustrated. The substrate 2 may be used. In that case, in the third resist pattern forming step described above, a third resist pattern is formed on both surfaces of the insulating substrate 2 in accordance with a desired wiring pattern, and then in the third etching step, the insulating substrate 2 is formed. The copper foils 11 on both sides may be etched (full etching) simultaneously. Thereby, wiring can be simultaneously formed on both surfaces of the insulating substrate 2.

  In addition, the method for manufacturing a wiring board according to the present invention can be applied to any method for manufacturing a flexible wiring board and a rigid wiring board depending on whether the insulating substrate 2 has flexibility.

DESCRIPTION OF SYMBOLS 1 Wiring board 2 Insulating board 3 Wiring 4 Bump 11 Copper foil 12 1st resist layer 13 1st resist pattern 16 2nd resist layer 17 2nd resist pattern 18 3rd resist layer 19 3rd resist pattern 41 First bump part 42 Second bump part

Claims (7)

An insulating substrate;
Wiring formed on the insulating substrate;
A bump formed on the wiring,
The wiring board is characterized in that the bump has a multi-stage structure that gradually increases from the top to the bottom of the bump. The bump has a stepped dimension from the top to the bottom of the bump in at least one of the width direction and the length direction of the wiring at the bump formation site or in a direction oblique thereto. The wiring board according to claim 1, wherein the wiring board has a multi-stage structure. The ratio of the height dimension of the bump to the dimension of the top of the bump in at least one of the width direction and the length direction of the wiring or in an oblique direction thereof is 1.2 or more. The wiring board according to claim 2. As a manufacturing process of a wiring board comprising an insulating substrate, a wiring formed on the insulating substrate, and a bump formed on the wiring,
A bump forming step of forming the bump by etching a conductor layer formed on at least one surface of the insulating substrate;
A wiring forming step of forming the wiring by etching the conductor layer so as to leave the bump formed by the bump forming step;
Have
In the bump forming step, the bump is formed so as to have a multi-stage structure that gradually increases from the top to the bottom of the bump. In the bump formation step, the size of the bump in at least one of the width direction and the length direction of the wiring at the bump formation site or in an oblique direction from the top to the bottom of the bump. The method for manufacturing a wiring board according to claim 4, wherein the bumps are formed so as to have a multistage structure that increases stepwise. In the bump forming step, a resist pattern forming step of forming a resist pattern corresponding to the shape and size of the bump on the conductor layer and at a position where the bump is to be formed, and using the resist pattern as a mask, The method for manufacturing a wiring board according to claim 4 or 5, wherein the multi-stage bump is obtained by repeating an etching step of half-etching the conductor layer a plurality of times. 7. The bump forming step is characterized in that at least one of the plurality of etching steps is performed by half-etching the conductor layer using an etching solution to which an etching inhibitor is added. The manufacturing method of the wiring board as described in 2 ..

Images