JP2013229075A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of flexibly responding to the lowering of a power supply voltage without providing a high breakdown voltage circuit element.SOLUTION: A semiconductor memory device 1 includes word lines WL and memory cells 10 connected to the word lines. One end of each of the word lines is connected with serially connected first and second switch elements TG1 and TG2. A potential fixing circuit 52 fixes a potential at a connection point between the first switch element TG1 and the second switch element TG2. A decoding circuit 30 is connected to the word lines WL via the first and second switch elements; and in response to a control input, outputs a first voltage according to a power supply voltage, from output terminals corresponding to the word lines WL. The other end of each of the word lines is connected with a third switch element TG3. A step-up circuit 40 is connected to the word lines WL via the third switch element TG3; and in response to the control input, outputs a second voltage that is higher than the first voltage, from output terminals corresponding to the word lines WL.

Description

  The present invention relates to a semiconductor memory device including semiconductor memory cells.

  As a nonvolatile semiconductor memory, for example, an EEPROM (Electrically Erasable Programmable ROM) capable of electrically writing and erasing data is known. In the EEPROM, a plurality of memory cells each having a control gate and a floating gate are arranged in a matrix. In general, a word line is provided for each row, and each word line is connected to each control gate of the memory cell. A bit line is provided for each column, and each bit line is connected to each drain of the memory cell. Furthermore, a source line is provided for each memory block, and each source line is connected to each source of a plurality of memory cells included in the corresponding memory block. By appropriately applying voltages to these word lines, bit lines, and source lines, at least one memory cell is selected, and data is written, read, and erased.

  In the EEPROM, for example, there are the following techniques for preventing circuit elements (transistors and the like) from being destroyed during a data rewrite operation on a memory cell.

  For example, in Patent Document 1, in a flash memory that rewrites data by applying a high voltage to a memory cell using a booster circuit, the discharge circuit is activated even when a reset signal is given during the rewrite operation. It is described that dynamic latch-up is suppressed and transistor breakdown is prevented by gradually shifting the high voltage output from the booster circuit to the reference potential.

  Further, in the cited document 2, in a level shifter circuit provided in a non-volatile semiconductor memory device, a first negative voltage level shifter configured by a normally withstand voltage transistor and shifting an input signal of level Vcc / Vss to level Vcc / Vnmin; The level Vcc / Vnmin from the first negative voltage level shifter is converted to the level Vnmin / Vss during the second negative voltage level shifter which is composed of a normal withstand voltage transistor and shifts the input signal of the level Vnmin / Vss to the level Vss / Vneg. And an inverter 8 for supplying to the second negative voltage level shifter, and Vnmin is an intermediate level between Vss and Vneg, and the maximum voltage difference applied to the transistor of the first negative voltage level shifter is less than the withstand voltage of the transistor. What is set to fit is listed.

JP 2004-362703 A JP 2000-174600 A

  In a semiconductor memory device such as an EEPROM, when erasing data stored in a memory cell, there is a method of applying a high voltage VPP having a voltage level higher than the power supply voltage VDD to the gate of the memory cell via a word line. As the high voltage VPP is applied to the word line, for example, a voltage (VPP−VDD) corresponding to the difference between the high voltage VPP and the power supply voltage VDD may be applied to the circuit elements connected to the word line. Accordingly, the circuit element connected to the word line is designed withstand voltage assuming that such a voltage (VPP-VDD) is applied.

  However, if an attempt is made to meet the demand for lowering the power supply voltage VDD while maintaining the high power supply VPP, the value of VPP-VDD becomes higher than before. As a result, the voltage applied to the circuit element during operation may exceed the withstand voltage. In order to avoid this problem, it is conceivable to provide a circuit element having a higher breakdown voltage. However, in this case, it is necessary to newly add a manufacturing process for forming the high breakdown voltage element, which causes an increase in cost, which is not preferable.

  The present invention has been made in view of the above circumstances, and provides a semiconductor memory device that can cope with a reduction in power supply voltage without adding a manufacturing process for forming a circuit element having a higher breakdown voltage. The purpose is to provide.

  A semiconductor memory device according to the present invention includes at least one word line, at least one memory cell connected to the word line, a first switch element connected to one end of the word line, A second switch element connected in series to the first switch element; a potential fixing circuit for fixing a potential at a connection point between the first switch element and the second switch element; and the first switch element. A decode circuit connected to the word line via the second switch element and outputting a first voltage corresponding to a power supply voltage from an output terminal corresponding to the word line in response to a control input; and the word line A third switch element connected to the other end of the first output terminal, and an output terminal connected to the word line via the third switch element and corresponding to the word line according to the control input From including, a booster circuit for outputting a high voltage level second voltage than the first voltage.

  Another semiconductor memory device according to the present invention includes a plurality of word lines, a plurality of memory cells connected to each of the plurality of word lines, and a first terminal connected to one end of each of the plurality of word lines. 1 switch element, a second switch element connected in series to each of the first switch elements, and a potential at a connection point between the first switch element and the second switch element are fixed. Power supply at an output terminal connected to each of the word lines through the first switch element and the second switch element and corresponding to each of the word lines according to a control input A decode circuit for outputting a first voltage corresponding to the voltage; a third switch element connected to the other end of each of the plurality of word lines; and the word line via the third switch element Is connected to each and response to said control input including a booster circuit that outputs a high voltage level second voltage than the first voltage at the output terminals corresponding to each of said word lines.

  According to the semiconductor memory device of the present invention, the voltage generated between the decode circuit and the word line can be divided and applied to the first and second switch elements. It is possible to cope with the lowering of the power supply voltage without providing it.

FIG. 1 is a diagram showing a configuration of a semiconductor memory device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view showing a configuration of a memory cell provided in the semiconductor memory device according to the embodiment of the present invention. FIG. 3 is a diagram showing a detailed configuration of the semiconductor memory device according to the embodiment of the present invention. FIG. 4 is a diagram showing a configuration of a semiconductor memory device according to a comparative example. FIG. 5A is a timing chart showing the operation of the semiconductor memory device according to the embodiment of the present invention, and FIG. 5B is a timing chart showing the operation of the semiconductor memory device according to the comparative example. FIG. 6 is a diagram showing a configuration of a semiconductor memory device according to the second embodiment of the present invention. FIG. 7 is a diagram illustrating a configuration of a switch circuit according to a modification.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings, substantially the same or equivalent components or parts are denoted by the same reference numerals.

(First embodiment)
FIG. 1 is a diagram showing a configuration of a semiconductor memory device 1 according to the first embodiment of the present invention. The semiconductor memory device 1 has a plurality of bit lines BL arranged in the column direction and a plurality of word lines WL arranged in the row direction so as to intersect with the bit lines BL. A memory cell 10 is provided at each intersection of the bit line BL and the word line WL, and these constitute a memory cell array. Each memory cell 10 has a gate connected to the word line WL and a drain connected to the bit line BL. The source of each memory cell 10 is connected to a source line (not shown), and a predetermined potential is applied to the source terminal.

  Each bit line BL is connected to a bit line decode circuit 20. Each word line WL has one end connected to the word line decode circuit 30 via the switch circuit 50 and the other end connected to the booster circuit 40 via the switch circuit 60. As described above, in the semiconductor memory device 1 according to the present embodiment, the memory cell array is disposed between the word line decode circuit 30 and the booster circuit 40.

The control circuit 70 _applies various control signals S _ER , S _WLISO , / S _WLISO and operation commands (write commands, address information) to the bit line decode circuit 20, the word line decode circuit 30, the booster circuit 40, and the switch circuits 50 and 60. The operation of these circuits is controlled by supplying a read command and an erase command.

Each of the switch circuit 50 is provided for each word line WL, connect between the word line WL and the word line decode circuit 30 in response to the control signal S _WLISO and / S _WLISO supplied from the control circuit 70 / non Switch connection. Each of the switch circuit 60 is provided for each word line WL, the connection / disconnection between the booster circuit 40 and the word lines WL in response to a control signal S _WLISO and / S _WLISO supplied from the control circuit 70 Switch. The control signals S _WLISO and / S _WLISO are, for example, 1-bit signals having logic values inverted from each other.

  Each of the bit line decode circuit 20 and the word line decode circuit 30 has a plurality of output terminals corresponding to each of the word lines WL and each of the bit lines BL, and is given address information supplied from the control circuit 70. Data is written to, read from, and erased from each of the memory cells 10 by selectively applying a predetermined voltage to the word line WL and the bit line BL in response to a write command, a read command, and an erase command. The voltage (selection signal) output from the word line decoding circuit 30 is applied to the word line WL when the switch circuit 50 is in the on state.

Booster circuit 40 has a plurality of output terminals t _pp corresponding to each of word lines WL. When the data stored in the memory cell 10 is read, the booster circuit 40 outputs the power supply voltage VDD from the output terminal t _pp according to the low level control signal S _RE supplied from the control circuit 70. In addition, the booster circuit 40 uses the power supply voltage VDD required for erasing data in accordance with a high-level control signal _SER supplied from the control circuit 70 when erasing data stored in the memory cell 10. also it generates a high voltage VPP voltage levels, and outputs the generated high voltage VPP from the output terminal t _pp. The power supply voltage VDD and the high voltage VPP output from the booster circuit 40 are also supplied to the control circuit 70.

The control circuit 70 generates a low level control signal S _WLISO and a high level control signal / S _WLISO when reading data. At this time, the voltage level of the high level control signal / S _WLISO is set to the power supply voltage VDD level according to the output voltage of the booster circuit 40. On the other hand, the control circuit 70 generates a high-level control signal _SWLISO and a low-level control signal / _SWLISO when erasing data. At this time, the voltage level of the high-level control signal _SWLISO is set to the high voltage VPP level according to the output voltage of the booster circuit 40.

  FIG. 2 is a cross-sectional view showing the configuration of the memory cell 10. Each of the memory cells 10 is composed of a MOS transistor. The memory cell 10 includes a p-type silicon substrate 11, an n-type drain 12 and an n-type source 13 formed on the surface of the silicon substrate 11, a floating gate 14 and a control gate 15 stacked on the silicon substrate 11. And have.

  For example, when data “0” is written in the memory cell 10, a positive voltage is applied to the drain 12 and the control gate 15 via the bit line BL and the word line WL, and the source 12 is set to the ground potential. As a result, hot electrons are injected into the floating gate 14, the electric charge is retained, and data “0” is written.

  When data stored in the memory cell 10 is read, a voltage is applied between the drain 12 and the source 13 via the bit line BL, and a positive voltage (for example, a power source) is applied to the control gate 15 via the word line WL. Voltage VDD). Then, the case where the drain current flows is read as data “1”, and the case where the drain current does not flow is read as data “0”.

  When erasing data stored in the memory cell 10, a high voltage VPP having a voltage level higher than the power supply voltage VDD is applied to the control gate 15 through the word line WL, and draining is performed through the bit line BL. For example, the potential of 12 is a ground potential. As a result, the electric charge accumulated in the floating gate 14 is released onto the word line WL as an FN (Fowler-Nordheim) tunnel current, thereby erasing data. In the semiconductor memory device 1 according to the embodiment of the present invention, data erasure is performed in units of pages composed of a plurality of memory cells, or in units of blocks composed of a plurality of pages, or data stored in all memory cells is Batch erased.

  FIG. 3 is a diagram showing a more detailed configuration of the semiconductor memory device 1. In FIG. 3, only one word line WL is shown.

An inverter circuit 32 is connected to the word line decoding circuit 30. The inverter circuit 32 is a CMOS inverter configured by serially connecting a p-channel transistor _Qp0 connected to the power supply voltage VDD and an n-channel transistor _Qn0 connected to the ground potential GND. When the level of the signal output from the word line decode circuit 30 is low, the output voltage of the inverter circuit 32 becomes the power supply voltage VDD level. On the other hand, when the level of the signal output from word line decode circuit 30 is high, the output voltage of inverter circuit 32 is at the level of ground potential GND. Since a voltage having a voltage level higher than the power supply voltage VDD is not applied to the inverter circuit 32, the p-channel transistor _Qp0 and the n-channel transistor _Qn0 are configured by low breakdown voltage transistors having a relatively low breakdown voltage. Yes. An output terminal of the inverter circuit 32 is connected to the switch circuit 50.

The switch circuit 50 includes two transfer gates TG1 and TG2 connected in series between the output terminal (node n ₁ ) of the inverter circuit 32 and the word line WL, and a connection point (node n) between the transfer gates TG1 and TG2. ₂ ) a potential fixing circuit 52 for fixing the potential of ₂ ). The transfer gate TG1 corresponds to the first switch element in the present invention, and the transfer gate TG2 corresponds to the second switch element in the present invention.

The transfer gate TG2 includes a pair of n-channel transistor _Qnh4 and p-channel transistor _Qph4 . The transfer gate TG1 includes a pair of n-channel transistor Q _nh1 and p-channel transistor Q _ph1 . The gate of the n-channel transistor Q _nh4 of the transfer gate TG2 is connected to the gate of the n-channel transistor Q _nh1 of the transfer gate TG1, and a control signal / S _WLISO output from the control circuit 70 is supplied to these gates. On the other hand, the gate of the p-channel transistor Q _ph4 of the transfer gate TG2 is connected to the gate of the p-channel transistor Q _ph1 of the transfer gate TG1, and the control signal _SWLISO output from the control circuit 70 is supplied to these gates. The That is, transfer gates TG1 and TG2 are simultaneously turned on or turned off according to control signals _SWLISO and / _SWLISO . The transfer gate TG1 is connected to the word line WL. Since the high voltage VPP output from the booster circuit 40 may be applied to the transfer gates TG1 and TG2 via the word line WL, the transistors Q _nh1 , Q _ph1 , Q _nh4 constituting the transfer gates TG1 and TG2 And Q _ph4 is composed of a high breakdown voltage transistor having a relatively high breakdown voltage.

Potential fixing circuit 52 includes a p-channel transistor _{Q ph2} connected to the output terminal _{t pp} of the booster circuit 40, the n-channel transistor _{Q nh2} connected to the ground potential GND, and between these transistors _{Q ph2} and _{Q nh2} The resistor elements R ₁ and R ₂ connected in series and the output terminal t _pl connected to the connection point between the resistor elements R ₁ and R ₂ are included. Output terminal _{t pl} is connected to the node _{n 2} is a connection point of the transfer gates TG1 and TG2. The gate of the p-channel transistor _{Q ph2} is supplied the control signal / S _WLISO, to the gate of n-channel transistors _{Q nh2} control signal S _WLISO is supplied. That is, these transistors _{Q ph2} and _{Q nh2} becomes or off state in the ON state at the same time in response to the control signal S _WLISO and / S _WLISO. When these transistors Q _ph2 and Q _nh2 is turned on, the output voltage of the booster circuit 40 is divided by the resistance elements R ₁ and R _2, is output divided voltage from the output terminal t _pl with node n ₂ . When the output voltage output from the output terminal t _pp of the booster circuit 40 becomes the high voltage VPP, the resistance element R is set so that the potential of the node n ₂ becomes (VPP + VDD) / 2 (the median value of VPP and VDD). it is preferable to set the resistance value of ₁ and R _2. Since the voltage clamp circuit 52 the high voltage VPP is applied to the output from the booster circuit 40, the transistors Q _nh2 and Q _ph2 constituting the potential fixing circuit 52 is composed of a relatively high high-voltage transistor breakdown voltage Yes.

The switch circuit 60 includes a transfer gate TG3 provided between the word line WL and the output terminal t _pp of the booster circuit 40. The transfer gate _{TG3 is} constituted by a pair of n-channel transistor Q _nh3 and p-channel transistor Q _ph3 . The control signal _SWLISO is supplied to the gate of the n-channel transistor _Qnh3 , and the control signal / _SWLISO is supplied to the gate of the p-channel transistor _Qph3 . That is, the on / off state of the transfer gate TG3 is opposite to that of the transfer gates TG1 and TG2. Since the high voltage VPP output from the booster circuit 40 is applied to the transfer gate _TG3, the transistors _Qnh3 and _Qph3 constituting the transfer gate _TG3 are configured with high breakdown voltage transistors having a relatively high breakdown voltage. The transfer gate TG3 corresponds to the third switch element in the present invention.

  Here, FIG. 4 shows a configuration of the semiconductor memory device 100 according to the comparative example. The semiconductor memory device 100 is different from the switch circuit 50 of the semiconductor memory device 1 according to the embodiment of the present invention described above in the configuration of the switch circuit 50a. That is, the switch circuit 50a is different from the switch circuit 50 according to the embodiment of the present invention in that it includes only one transfer gate TG1 and does not include the potential fixing circuit 52. The components other than the switch circuit 50a are the same as those of the semiconductor memory device 1 according to the embodiment of the present invention.

  5A and 5B are timing charts showing operations of the semiconductor memory device 1 according to the embodiment of the present invention and the semiconductor memory device 100 according to the comparative example, respectively. 5A and 5B illustrate a case where the data read operation is shifted to the data erase operation.

  First, the operation of the semiconductor memory device 100 according to the comparative example will be described with reference to FIG.

When the control circuit 70 receives a read command supplied from the outside, the control circuit 70 generates a low-level control signal _SER and supplies it to the booster circuit 40. The booster circuit 40 outputs the power supply voltage VDD from the output terminal t _pp in response to the low level control signal _SER , and supplies the power supply voltage VDD to the control circuit 70.

Upon receiving the supply of the power supply voltage VDD, the control circuit 70 generates a low-level control signal S _WLISO and a high-level (power supply voltage VDD level) control signal / S _WLISO and supplies them to the switch circuits 50 a and 60. As a result, the transfer gate TG1 constituting the switch circuit 50a is turned on, while the transfer gate TG3 constituting the switch circuit 60 is turned off. Thereby, the word line decoding circuit 30 is connected to the word line WL, and the booster circuit 40 is electrically separated from the word line WL. The bit line decode circuit 20 and the word line decode circuit 30 select the bit line BL and the word line WL based on the read command with address information supplied from the control circuit 70, respectively. As a result, the data stored in the memory cell 10 is sequentially read. In FIG. 5B, a non-selected word line is shown. That is, the node n ₀ (output of the word line decoding circuit 30) is high level, the node n ₁ (output of the inverter circuit 32) is low level, and the word line WL is low level.

Thereafter, when the control circuit 70 receives an erase command supplied from the outside, it generates a high-level control signal _SER and supplies it to the booster circuit 40. Booster circuit 40 outputs a high voltage VPP higher voltage level than the power supply voltage VDD from the output terminal _{t pp} in response to the control signal _{S ER} of the high level and supplies the high voltage VPP to the control circuit 70.

The word line decode circuit 30 sets all the word lines to the selected state based on the erase command supplied from the control circuit 70. As a result, the node n ₀ is at the low level, the node n ₁ is at the high level (power supply voltage VDD level), and the word line WL is at the high level (power supply voltage VDD level).

Thereafter, the control circuit 70 generates a high level (high voltage VPP level) control signal S _WLISO and a low level control signal / S _WLISO and supplies them to the switch circuits 50 a and 60. Thereby, the transfer gate TG1 constituting the switch circuit 50a is turned off, while the transfer gate TG3 constituting the switch circuit 60 is turned on. As a result, the word line decode circuit 30 is electrically separated from the word line WL, the booster circuit 40 is connected to the word line WL, and the control gate of the memory cell 10 is output from the booster circuit 40 via the word line WL. The high voltage VPP to be applied is applied. The charge accumulated in the memory cell 10 by the application of the high voltage VPP is discharged onto the word line WL as an FN (Fowler-Nordheim) tunnel current, and the data stored in each memory cell 10 is erased.

At the time of data erasure, the node n ₁ (output of the inverter circuit 32) is at the power supply voltage VDD level, and the word line WL is at the high voltage VPP level, so that both ends of the transfer gate TG1 turned off are A voltage (VPP−VDD) corresponding to the difference between the voltage VPP and the power supply voltage VDD is applied. For example, when VPP = 12V and VDD = 5V, 7V is applied to both ends of the transfer gate TG1. When the high breakdown voltage transistor constituting the transfer gate TG1 is designed to have a breakdown voltage of 8V, for example, when the specification of the power supply voltage VDD is reduced from 5V to 3V, for example, the high breakdown voltage transistor has 9V (12V −3V) is applied, which exceeds the design value of the breakdown voltage. That is, in the semiconductor memory device 100 according to the comparative example, it is difficult to secure a margin of the withstand voltage design value with respect to the operating voltage of the high withstand voltage transistor, and it may not be possible to cope with the lowering of the power supply voltage VDD.

  Next, the operation of the semiconductor memory device 1 according to the embodiment of the present invention will be described with reference to FIG.

  Since the operation at the time of data reading is the same as in the case of the above-described comparative example, the description thereof is omitted.

When receiving the erase command supplied from the outside, the control circuit 70 generates a high-level control signal _SER and supplies it to the booster circuit 40. Booster circuit 40 outputs a high voltage VPP is higher than the voltage level of the power supply voltage VDD from the output terminal _{t pp} in response to the control signal _{S ER} of the high level and supplies the high voltage VPP to the control circuit 70.

The word line decode circuit 30 sets all the word lines to the selected state based on the erase command supplied from the control circuit 70. As a result, the node n ₀ (output of the word line decoding circuit 30) is low level, the node n ₁ (output of the inverter circuit 32) is high level (power supply voltage VDD level), and the word line WL is high level (power supply voltage VDD level). )

Thereafter, the control circuit 70 generates a high level (high voltage VPP level) control signal S _WLISO and a low level control signal / S _WLISO and supplies them to the switch circuits 50 and 60. Thereby, the transfer gates TG1 and TG2 constituting the switch circuit 50 are turned off, while the transfer gate TG3 constituting the switch circuit 60 is turned on. Thereby, the word line decoding circuit 30 is electrically separated from the word line WL, and the booster circuit 40 is connected to the word line WL. Accordingly, the voltage between the word line WL and the node _{n 1} becomes VPP-VDD. Incidentally, the word line decode circuit 30 is the selected state of the word line on the basis of the erase command is to suppress the voltage between the word line WL and the node n _1. Assuming the case where the word line non-selection state, the potential of the node n ₁ becomes the ground potential, the voltage between the word line WL and the node n ₁ becomes VPP.

Transistors _{Q ph2} and _{Q nh2} the potential fixing circuit 52, respectively turned on in response to the control signal _{/ S WLISO} high level control signal _{S WLISO} and low-level, minute high voltage VPP by the resistance element _{R 1} and _{R 2} The pressed voltage is output from the output terminal t _pl . Accordingly, the potential at the connection point of the transfer gates TG1 and TG2 (node _{n 2),} depending on the ratio of the resistance values of the resistance elements _{R 1} and _{R 2} for example (VPP + VDD) / 2, i.e. the median of VPP and VDD Is fixed to a voltage corresponding to.

The high voltage VPP output from the booster circuit 40 is applied to the word line WL, and the charge accumulated in the memory cell 10 is discharged onto the word line WL as an FN (Fowler-Nordheim) tunnel current. The data stored in is erased. At the time of data erase, to supply the control signal _{S WLISO} high voltage VPP level to the transfer gate TG1~TG3 in situations where high voltage VPP is applied to the word line WL, and the transfer gates TG1~TG3 proper This is for driving to an on state or an off state. On the other hand, since the power supply voltage VDD is applied to the selected word line WL at the time of data reading, if the control signal / S _WLISO at the power supply voltage VDD level is supplied to each of the transfer gates TG1 to TG3, these transfer gates. Can be properly driven to an on state or an off state.

Since the potential of the node n ₂ is fixed to (VPP + VDD) / 2 by the potential fixing circuit 52, a voltage corresponding to VPP− (VPP + VDD) / 2 = (VPP−VDD) / 2 is applied to both ends of the transfer gate TG1. Is applied. On the other hand, a voltage corresponding to (VPP + VDD) / 2−VDD = (VPP−VDD) / 2 is applied to both ends of the transfer gate TG2. That, (VPP + VDD) and the potential at the connection point between the transfer gate TG1 and TG2 / 2 by fixing the (median of VPP and VDD), the voltage (VPP applied between the word line WL and the node _{n 1} -VDD) is equally divided, and the divided voltages are applied to the transfer gates TG1 and TG2, respectively.

For example, if the VPP = 12V, VDD = 5V, the potential of the node _{n 2} is fixed to 8.5V by voltage clamp circuit 52, each of the transfer gates TG1 and TG2 3.5 V is applied. That is, at the time of data erasure, the voltage applied to the high voltage transistor can be reduced to half that of the comparative example described above. Therefore, it becomes easy to ensure the margin of the withstand voltage design value with respect to the operating voltage of the high withstand voltage transistor. Further, when the design value of the breakdown voltage of the high breakdown voltage transistor is 8 V as in the case of the comparative example described above, the voltage applied to the transfer gates TG1 and TG2 even if the specification of the power supply voltage VDD is changed from 5 V to 3 V Are 4.5V, respectively, and can be suppressed to a withstand voltage design value or less, and a margin can be secured.

  As described above, according to the semiconductor memory device 1 according to the embodiment of the present invention, even when a high voltage VPP having a voltage level higher than the power supply voltage VDD is applied to the word line WL during data erasure, (VPP−VDD ) Is divided and applied to the two transfer gates TG1 and TG2, so that the voltage applied to the transistor can be kept sufficiently lower than the withstand voltage design value. As a result, even when the power supply voltage VDD is lowered, the number of cases where a transistor with a higher breakdown voltage is required is reduced. That is, according to the semiconductor memory device 1 according to the embodiment of the present invention, it is possible to flexibly cope with the lowering of the power supply voltage VDD without adding a manufacturing process for forming a transistor with a higher breakdown voltage. Become.

  In the above description, the case where the potential of the connection point between the transfer gates TG1 and TG2 is fixed to (VPP + VDD) / 2 (the median value of VPP and VDD) is exemplified. However, the connection point between the transfer gates TG1 and TG2 is illustrated. Can be set to an intermediate value other than the median value of VPP and VDD. In the above description, the inverter circuit 32 is provided outside the word line decoding circuit 30. However, the inverter circuit 32 may be built in the word line decoding circuit 30.

  In the semiconductor memory device 1 according to the embodiment of the present invention, the word line decode circuit 30 and the booster circuit 40 disposed so as to sandwich the memory cell 10 are connected to the end of the word line WL. According to such a configuration, the high voltage VPP output from the booster circuit 40 is not applied to the word line decode circuit 30, so that the word line decode circuit 30 can be configured with a low breakdown voltage transistor. As a result, the circuit scale of the word line decoding circuit 30 can be reduced. Further, with such a configuration, the high breakdown voltage transistor formation region and the low breakdown voltage transistor formation region can be easily separated on the semiconductor chip. For example, when a high breakdown voltage well for forming a high breakdown voltage transistor and a low breakdown voltage well for forming a low breakdown voltage transistor are adjacent to each other on a semiconductor chip, a certain distance or more must be provided between these wells. If there is a design rule that does not have to be, because the high breakdown voltage well formation region and the low breakdown voltage transistor formation region can be clearly separated, the portion where the high breakdown voltage well and the low breakdown voltage well are adjacent can be reduced. The chip area can be reduced.

(Second Embodiment)
FIG. 6 is a diagram showing a configuration of the semiconductor memory device 2 according to the second embodiment of the present invention. In the semiconductor memory device 1 according to the first embodiment described above, the potential fixing circuit 52 is provided for each switch circuit 50, that is, for each word line WL. In the semiconductor memory device 2 according to the second embodiment, the potential fixing circuit 52 is shared by the plurality of switch circuits 50b. That is, the output terminal t _pl of the potential fixing circuit 52 is connected to each connection point of the transfer gates TG1 and TG2 constituting each of the plurality of switch circuits 50b. One potential fixing circuit 52 may be provided, for example, for each page or block as a data erasing unit. Further, when the data of all the memory cells is erased at once, it is possible to connect one potential fixing circuit 52 to all the switch circuits 50b.

(Modification)
FIG. 7 is a diagram illustrating a configuration of a switch circuit 50c according to a modification. The switch circuit 50c according to the present modification includes three transfer gates TG1, TG2, and TG2 ′ connected in series between the output terminal (node n ₁ ) of the inverter circuit 32 and the word line WL, and two fixed points different from each other. And a potential fixing circuit 52c for outputting a voltage. Transfer gates TG1, TG2, and TG2 ′ are connected to each other, and are driven to an on state or an off state simultaneously according to control signals _SWLISO and / _SWLISO .

The potential fixing circuit 52c has resistance elements R1, R2 and R3 connected in series, and an output terminal t _pl1 connected to a connection point between the resistance elements R1 and R2 is a node at a connection point between the transfer gates TG1 and TG2. The output terminal t _pl2 connected to n ₂ and connected to the connection point between the resistance elements R2 and R3 is connected to the node n _2a at the connection point between the transfer gates TG2 and TG2 ′.

The potential fixing circuit 52c outputs two different fixed voltages corresponding to the resistance ratios of the resistance elements R1, R2, and R3 from the output terminals t _pl1 and t _pl2, and _sets the potential of the node n _{2 to} , for example, 2 × (VPP−VDD ) / 3 + VDD and the potential of the node n _2a is fixed to a potential corresponding to, for example, (VPP−VDD) / 3 + VDD. For example, the high voltage VPP is 12V, when the power supply voltage VDD is 3V, the potential fixing circuit 52c fixes the potential of the node _{n 2} to 9V, to fix the node _{n 2a} to 6V. That is, the voltage across the transgates TG1, TG2, and TG2 ′ is 3V.

  Thus, according to the switch circuit 50c according to the present modification, it is possible to further reduce the voltage applied to one transfer gate. By further increasing the number of transfer gates connected in series and appropriately setting the potential at each connection point between the transfer gates by a potential fixing circuit, the voltage applied to each transfer gate can be further reduced.

DESCRIPTION OF SYMBOLS 1, 2 Semiconductor memory device 10 Memory cell 30 Word line decoding circuit 20 Bit line decoding circuit 40 Boosting circuit 50, 60 Switch circuit 70 Control circuit TG1-TG3 Transfer gate WL Word line

Claims (7)

At least one word line;
At least one memory cell connected to the word line;
A first switch element connected to one end of the word line;
A second switch element connected in series to the first switch element;
A potential fixing circuit that fixes a potential at a connection point between the first switch element and the second switch element;
Decoding connected to the word line via the first switch element and the second switch element and outputting a first voltage corresponding to a power supply voltage from an output terminal corresponding to the word line in response to a control input Circuit,
A third switch element connected to the other end of the word line;
A booster that is connected to the word line via the third switch element and outputs a second voltage having a voltage level higher than the first voltage from an output terminal corresponding to the word line in accordance with the control input. Circuit,
A semiconductor memory device. The first switch element and the second switch element are turned off in response to a data erasing command supplied from the outside,
The third switch element is turned on in response to the data erasure command,
The decode circuit outputs the first voltage in response to the data erasure command,
The booster circuit outputs the second voltage in response to the data erasure command,
The potential fixing circuit sets a potential at a connection point between the first switch element and the second switch element to a potential between the first voltage and the second voltage in response to the data erasing command. The semiconductor memory device according to claim 1, which is fixed.   The potential fixing circuit corresponds to a median value of the first voltage and the second voltage at a connection point between the first switch element and the second switch element in response to the data erasing command. The semiconductor memory device according to claim 2, wherein the semiconductor memory device is fixed to a potential. The potential fixing circuit includes a plurality of transistors connected between the first transistor connected to the output terminal of the booster circuit, the second transistor connected to the ground potential, and the first and second transistors. A resistive element, and
4. The semiconductor memory device according to claim 1, wherein a connection point between the plurality of resistance elements is connected to a connection point of the first and second switch elements. 5.   4. The semiconductor memory device according to claim 1, wherein each of the first switch element, the second switch element, and the third switch element includes a transfer gate. 5. The semiconductor memory device has a plurality of word lines,
6. The semiconductor memory device according to claim 1, wherein the first switch element, the second switch element, and the third switch element are connected to each of the word lines. Multiple word lines,
A plurality of memory cells connected to each of the plurality of word lines;
A first switch element connected to one end of each of the plurality of word lines;
A second switch element connected in series to each of the first switch elements;
At least one potential fixing circuit for fixing a potential of each connection point between the first switch element and the second switch element;
A first voltage corresponding to a power supply voltage is connected to each of the word lines via the first switch element and the second switch element and at an output terminal corresponding to each of the word lines according to a control input. An output decoding circuit;
A third switch element connected to the other end of each of the plurality of word lines;
A second voltage connected to each of the word lines via the third switch element and having a voltage level higher than that of the first voltage at an output terminal corresponding to each of the word lines according to the control input; A booster circuit that outputs
A semiconductor memory device.

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