JP2013172069A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable inhibition of warpage and deflection at an overhang part even when semiconductor chips are stacked in an overhang state.SOLUTION: A semiconductor chip in which a plurality of semiconductor chips are stacked on a wiring board such that a part of an upper semiconductor chip overhangs a lower semiconductor chip, comprises: a chip support film provided on the upper semiconductor chip on a surface on the side opposite to the wiring board side for warping the upper semiconductor chip to a direction opposite to the wiring board side.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

In recent years, with the reduction in size and thickness of portable electronic devices, semiconductor devices mounted on portable electronic devices have also been reduced in size and thickness, and the thickness of semiconductor chips incorporated in semiconductor devices has also been reduced.
There is a type of semiconductor device called MCP (Multi Chip Package) (Patent Document 1). In MCP, rectangular, particularly rectangular semiconductor chips are cross-laminated. In the case of a rectangle, a part of the upper semiconductor chip protrudes from the lower semiconductor chip, which is a so-called overhang state.

  Cross lamination is performed by a die bonding collet 500 as shown in FIG. In FIG. 10, the upper semiconductor chip 700 is sucked by a die bonding collet 500 having a rubber layer 510 provided on the suction surface, and is stacked and mounted on the lower semiconductor chip 600 mounted on the wiring substrate 800. Adsorption of the semiconductor chip by the die bonding collet 500 is performed using suction by reduced pressure. The rubber layer 510 is provided to prevent interference between the die bonding collet and the semiconductor chip when the semiconductor chip is picked up from the dicing tape.

JP 2001-217383 A

  In the case of a rectangular semiconductor chip having a thin chip thickness and a large overhang amount, the die bonding collet 500 has a rubber layer 510 as the suction surface, and when the upper semiconductor chip 700 is stacked on the lower semiconductor chip 600. As shown in FIG. 11, there is a problem that the upper semiconductor chip 700 is warped or bent. Further, due to chip warpage or bending when the upper semiconductor chip 700 is stacked, the overhang portion may come into contact with the wiring substrate 800, and this contact may cause cracks in the upper semiconductor chip 700.

  Further, an adhesive member 710 such as DAF (Die Attached Film) is usually attached to the lower surface of the upper semiconductor chip 700. In this case, the wiring board 800 is bent with the overhanging portion bent. There is also a risk of adhesion.

  Accordingly, an object of the present invention is to make it possible to suppress warping and bending at an overhang portion even when semiconductor chips are stacked in an overhang state.

  According to the first aspect of the present invention, in a semiconductor device in which a plurality of semiconductor chips are stacked on a wiring board so that a part of the upper semiconductor chip is overhanged, the wiring board side of the upper semiconductor chip and A semiconductor device is provided in which a chip support film for warping the upper semiconductor chip in a direction opposite to the wiring substrate side is provided on the opposite surface.

  According to the second aspect of the present invention, in the method of manufacturing a semiconductor device in which a plurality of semiconductor chips are stacked on a wiring board so that a part of the upper semiconductor chip is overhanged, the wiring in the upper semiconductor chip is provided. Providing a chip support film on a surface opposite to the substrate side suppresses occurrence of warpage to the wiring substrate side when the upper semiconductor chip is stacked. A manufacturing method is provided.

  In any of the first and second aspects, the chip support film is provided in a region including at least a part of an upper semiconductor chip that overlaps a lower semiconductor chip and at least a part of an overhang portion. Is desirable.

  According to the present invention, in the MCP type semiconductor device that is laminated so that a part of the upper semiconductor chip is overhanged, the chip support film is provided on the surface (upper surface) of the upper semiconductor chip. The chip support film functions to warp the overhang portion of the upper semiconductor chip upward. Thereby, it is possible to suppress warping or bending of the overhang portion toward the wiring mother board when the upper semiconductor chip is stacked, and it is possible to stack the layers satisfactorily. In addition, by suppressing the occurrence of warping and bending in the overhang portion, it is possible to reduce the contact of the overhang portion with the wiring board and chip cracks resulting therefrom.

1 is a plan view showing a schematic configuration of an MCP type semiconductor device according to a first embodiment of the present invention. FIG. 2 is a longitudinal sectional view of the semiconductor device shown in FIG. 1. FIG. 2 is a longitudinal sectional view for explaining an assembly flow of the semiconductor device shown in FIG. 1. It is a longitudinal cross-sectional view for demonstrating the pick-up-chip bonding process from the dicing tape of the semiconductor device shown by FIG. It is a top view which shows schematic structure of the MCP type semiconductor device which concerns on the 2nd Embodiment of this invention. FIG. 6 is a longitudinal sectional view of the semiconductor device shown in FIG. 5. It is a longitudinal cross-sectional view which shows schematic structure of the MCP type semiconductor device which concerns on the 3rd Embodiment of this invention. It is a longitudinal cross-sectional view which shows schematic structure of the MCP type semiconductor device which concerns on the 4th Embodiment of this invention. It is a longitudinal cross-sectional view which shows schematic structure of the MCP type semiconductor device which concerns on the modification of this invention. It is a longitudinal cross-sectional view for demonstrating the lamination | stacking process of the semiconductor chip in a common MCP type semiconductor device. FIG. 11 is a longitudinal sectional view for explaining a semiconductor chip stacking step following FIG. 10;

  Hereinafter, several embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
1 and 2 are a plan view and a longitudinal sectional view showing a schematic configuration of an MCP type semiconductor device according to the first embodiment of the present invention.

  1 and 2, the MCP-type semiconductor device 1 includes a first (lower) and second (upper) semiconductor chips 20 and 30 each having a rectangular shape and electrode pads 21 and 31 formed only on the short side. Are stacked on the wiring board 10 so as to intersect at right angles. The first semiconductor chip 20 is mounted on the wiring board 10 via an adhesive member 22 such as DAF. The second semiconductor chip 30 is mounted on the first semiconductor chip 20 via an adhesive member 32 such as DAF so that both sides thereof overhang from the first semiconductor chip 20. As will be described later, the electrode pads 21 and 31 of the semiconductor chips 20 and 30 are connected to connection pads 11 and 12 formed at corresponding positions on the wiring board 10 by wires 15, respectively. Although not shown in FIG. 1, the entire circuit board side of the wiring substrate 10 including the semiconductor chips 20 and 30 and the wires 15 is molded with a sealing resin 50.

  In the first embodiment, the chip support film 40 is provided on the circuit surface side (upper surface side) of the second semiconductor chip 30. As the chip support film 40, for example, a polyimide film is used.

  The chip support film 40 is configured to have a width larger than the width of the first semiconductor chip 20, and functions to warp the overhang portion of the first semiconductor chip 30 protruding from the first semiconductor chip 20 upward. . For this purpose, the chip support film 40 is provided so as to cover a region where the first semiconductor chip 20 and the second semiconductor chip 30 overlap and a region corresponding to the root portion of the overhang portion. Thereby, when the second semiconductor chip 30 is stacked, warpage and bending of the overhang portion toward the wiring substrate 10 can be suppressed, and the stacking can be performed satisfactorily. By suppressing the occurrence of warping and bending at the overhang portion, it is possible to reduce contact of the overhang portion with the wiring substrate 10 and chip cracks resulting from this.

  FIG. 3 is a longitudinal sectional view for explaining an assembly flow of the semiconductor device according to the first embodiment.

  In assembling a semiconductor device, a so-called wiring mother board is used. The wiring mother board has a plurality of product forming portions arranged in a matrix in a region surrounded by a frame portion in which positioning holes are formed. Semiconductor chips and other components are mounted on the product forming section. Insulating films are formed on both surfaces of the wiring mother board, but the insulating film in the region where the connection pads on one side and the land part on the other side are formed are openings. The plurality of product forming portions are later cut individually along the dicing lines to form wiring boards.

  With reference to FIG. 3, the assembly method of the semiconductor device using the wiring mother board 100 will be described in the order of steps. In FIG. 3, the insulating films formed on both surfaces of the wiring motherboard 100 are not shown.

  First, as shown in FIG. 3A, the first (lower) semiconductor chip 20 and the second (upper) semiconductor chip 30 are sequentially mounted on each product forming portion 110 of the wiring motherboard 100. . The first semiconductor chip 20 is bonded and fixed to the wiring mother board 100 by an adhesive member 22 such as DAF provided on the lower surface thereof. Similarly, the second semiconductor chip 30 is bonded and fixed to the upper surface of the first semiconductor chip 20 by an adhesive member 32 such as DAF provided on the lower surface thereof. At this time, a chip support film 40 is attached to the upper surface of the second semiconductor chip 30.

  The second semiconductor chip 30 is stacked so as to intersect at right angles in order to expose the electrode pads 21 (FIG. 1) formed on the short side of the first semiconductor chip 20. At this time, the direction in which the overhang portion 33 of the second semiconductor chip 30 protrudes from the first semiconductor chip 20 is a direction perpendicular to the injection direction (direction perpendicular to the drawing) of the sealing resin (in the drawing). Left and right direction).

  Next, as shown in FIG. 3B, the electrode pad 21 (FIG. 1) of the first semiconductor chip 20 and the corresponding connection pad 11 (FIG. 1), and the electrode of the second semiconductor chip 30. Each of the pads 31 and the corresponding connection pad 12 is connected by a wire 15. The wire 15 is made of, for example, Au, and a wire bonding apparatus (not shown) can be used for connection using the wire 15. The connection is performed by, for example, ball bonding using an ultrasonic thermocompression bonding method. Specifically, the tip of the wire 15 on which a ball has been formed by melting is ultrasonically thermocompression bonded onto the electrode pad 21 or 31, and the rear end of the wire 15 corresponds so that the wire 15 draws a predetermined loop shape. Ultrasonic thermocompression bonding is performed on the connection pads 11 and 12.

  Next, as shown in FIG. 3C, one surface side of the wiring mother board 100 is molded with the sealing resin 50 by batch molding. For the batch molding, for example, a transfer molding apparatus is used, but since it is well known, description thereof is omitted.

  Next, as shown in FIG. 3D, the wiring mother board 100 is inverted and the solder balls 16 are mounted on the plurality of land portions 13 on the other surface side. These solder balls 16 are used as external terminals of the semiconductor device 1.

  The mounting of the solder balls 16 can be performed, for example, by using a suction mechanism (not shown) including a plurality of suction holes arranged in correspondence with the plurality of land portions 13. In this case, a plurality of solder balls are sucked and held by the suction mechanism, a flux is transferred and formed on the held solder balls, and the solder balls are collectively mounted on the plurality of land portions 13 of the wiring motherboard 100. Thereafter, the solder ball 16 and the land portion 13 are connected and fixed by a reflow process.

  Next, the upper surface side of the sealing resin 50 is bonded to a dicing tape (not shown), and the sealing resin 50 and the wiring mother board 100 are supported by the dicing tape. Then, the wiring mother board 100 and the sealing resin 50 are cut vertically and horizontally along the dicing line DL (FIG. 3d) using a dicing blade (not shown) upside down. Thereby, the wiring mother board 100 is separated into pieces for each product forming unit 110. Thereafter, the separated product forming portion 110 and the sealing resin 50 are picked up from the dicing tape (FIG. 3E), whereby the semiconductor device 1 as shown in FIG. 2 is obtained.

  Note that the chip support film 40 provided on the second semiconductor chip 30 may be mounted on the semiconductor chip after being singulated as a semiconductor chip, or may be configured to be mounted in a wafer state.

  FIG. 4 is a longitudinal sectional view for explaining a semiconductor chip pick-up process to a semiconductor chip bonding process in the semiconductor device assembling process according to the first embodiment. Here, it is assumed that the second semiconductor chip 30 is stacked on the first semiconductor chip 20 that is already bonded to the wiring motherboard 100.

  In FIG. 4A, the semiconductor chips Ti are transported in a state where they are attached to the dicing tape DT in a line at regular intervals. At this time, a chip support film 40 is attached to the upper surface of each semiconductor chip Ti, and an adhesive member 32 such as DAF is attached to the lower surface. At the pickup position of the semiconductor chip, a push-up portion 60 is disposed below the dicing tape DT, and a bonding collet 65 is positioned on the upper side in a standby state. The push-up portion 60 includes a second push-up portion 62 disposed in the center, first push-up portions 61 and 61 disposed on the upstream side and the downstream side in the transport direction of the dicing tape DT, and further upstream in the transport direction. And suction stages 63 and 63 disposed on the downstream side. The bonding collet 65 has a suction part by the second elastic body 67 at the center, and a suction part by the first elastic body 66 on the upstream side and the downstream side in the transport direction.

  In FIG. 4B, when the semiconductor chip Ti reaches the pickup position, the conveyance of the dicing tape DT is temporarily stopped, and the suction stages 63 and 63 suck and hold the dicing tape DT by the suction action by the reduced pressure. Subsequently, the first push-up portions 61 and 61 and the second push-up portion 62 move up. Here, when the amount of protrusion of the second protrusion 62 is slightly larger than the amount of protrusion of the first protrusion 61, both sides in the longitudinal direction of the semiconductor chip Ti are peeled from the dicing tape DT. Then, the bonding collet 65 moves downward, and the semiconductor chip Ti is adsorbed by the adsorbing portion by the first elastic body 66 and the adsorbing portion by the second elastic body 67. Then, the 1st thrusting part 61 and the 2nd thrusting part 62 move down to the original position. Thereby, the semiconductor chip Ti is completely peeled from the dicing tape DT. The bonding collet 65 moves in a state where the semiconductor chip Ti is adsorbed, and transports it to the stacking position on the first semiconductor chip 20.

  In FIG. 4C, when the bonding collet 65 reaches a position directly above the first semiconductor chip 20 bonded on the wiring motherboard 100, the adsorbed semiconductor chip Ti is removed from the first semiconductor chip. After being placed on 20, the suction is released and the next semiconductor chip Ti is picked up.

  As described above, as shown in FIG. 4D, the second semiconductor chip 30 is stacked on the first semiconductor chip 20 in a crossed state.

  According to the first embodiment, in the MCP type semiconductor device in which the first and second semiconductor chips 20 and 30 are stacked so as to intersect at right angles, the surface (upper surface) of the second semiconductor chip 30 is A chip support film 40 having a width larger than the width of the first semiconductor chip 20 is provided. In particular, the chip support film 40 is formed by setting the formation region of the chip support film 40 as a region where the first semiconductor chip 20 and the second semiconductor chip 30 overlap and a partial region on the base side of the overhang portion 33. The overhang portion 33 of the second semiconductor chip 30 protruding from the first semiconductor chip 20 functions to warp upward. Thereby, when the second semiconductor chip 30 is stacked, warping and bending of the overhang portion 33 toward the wiring mother board can be suppressed, and the stacking can be performed satisfactorily. By suppressing the occurrence of warping and bending in the overhang portion 33, contact of the overhang portion 33 with the wiring mother board (wiring substrate) and chip cracks can be reduced.

(Second Embodiment)
5 and 6 are a plan view and a longitudinal sectional view showing a schematic configuration of a semiconductor device according to the second embodiment of the present invention. 5 and 6, the same elements as those shown in FIGS. 1 and 2 are denoted by the same reference numerals, and description thereof is omitted. In FIG. 5, the sealing resin is not shown.

  As shown in FIGS. 5 and 6, the chip support films 40 ′ and 40 ′ are near the root of the overhang portion of the upper second semiconductor chip 30, that is, the first semiconductor chip 20 and the second semiconductor chip. 30 is configured to be provided only in a part of a region overlapping with 30 and a part on the base side of the overhang portion. By providing the chip support film 40 ′ in the vicinity of the base of the overhang portion, the chip support film 40 ′ suppresses the warpage or bending of the overhang portion toward the wiring board as in the first embodiment. In addition, the amount of chip support film used in one semiconductor device can be reduced, and the cost can be reduced as compared with the first embodiment.

(Third embodiment)
FIG. 7 is a longitudinal sectional view showing a schematic configuration of a semiconductor device according to the third embodiment of the present invention. In FIG. 7, the same elements as those shown in FIG. 2 are denoted by the same reference numerals, and the description thereof is omitted.

  The semiconductor device 1-1 shown in FIG. 7 is an example in which four semiconductor chips 20-1, 30-1, 20-2, 30-2 are cross-stacked. Similarly to the first embodiment, chip support films 40-1, 40-2, and 40 are provided on the upper surfaces of the second to fourth stages of semiconductor chips 30-1, 20-2, and 30-2 having overhang portions, respectively. By providing −3, the same effects as those of the first embodiment can be obtained even in the case of stacking three or more semiconductor chips.

(Fourth embodiment)
FIG. 8 is a longitudinal sectional view showing a schematic configuration of a semiconductor device according to the fourth embodiment of the present invention. In FIG. 8, the same elements as those shown in FIG.

  The semiconductor device 1-2 shown in FIG. 8 shifts the second semiconductor chip 30 ′ so that the electrode pad 21 ′ of the first semiconductor chip 20 ′ is exposed on the first semiconductor chip 20 ′. It is the laminated embodiment. That is, only one side of the both ends of the second semiconductor chip 30 'is overhanging from the first semiconductor chip 20'. Also in this case, the chip support film 40 covers a part of the region where the first semiconductor chip 20 ′ and the second semiconductor chip 30 ′ overlap and a part of the region on the base side of the overhang portion. It is formed. As described above, the chip support film 40 is provided on the upper surface of the second semiconductor chip 30 ′ having the overhang portion and in a region overlapping the first semiconductor chip 20 ′ and a part of the base side of the overhang portion. Thus, the same effect as in the first embodiment can be obtained. The fourth embodiment is suitable for the case where the semiconductor chip is a rectangle, in particular, a square, particularly a square.

  As mentioned above, although the invention made by this inventor was demonstrated based on some embodiment, it cannot be overemphasized that this invention is not limited to the said embodiment, In the range which does not deviate from the summary, it can change variously. Yes.

  In the above embodiment, the chip support film has been described with respect to the case where the polyimide tape is disposed in consideration of heat resistance during bonding. However, any material can be used as long as the material can suppress the bending of the overhang portion of the semiconductor chip. A tape may be used.

  In addition, a semiconductor device in which two semiconductor chips are stacked and a semiconductor device in which four semiconductor chips are stacked has been described. However, any semiconductor device in which semiconductor chips are stacked so as to partially hang may be applied to any semiconductor device. Also good. For example, in the MCP type semiconductor device 1-3 shown as a modified example in FIG. 9, the first semiconductor chip 20 and the second semiconductor chip 30 are stacked via the spacer 70. The spacer 70 is also provided on the upper surface of the first semiconductor chip 20 via an adhesive member 71 such as DAF. In this case, since the spacer 70 is smaller than the semiconductor chip and is partially disposed, the region on the upper surface of the second semiconductor chip 30 where the spacer 70 and the second semiconductor chip 30 overlap, and the overhang portion. The effect similar to 1st Embodiment is acquired by arrange | positioning the chip | tip support film 40 in a part of base side. This modification is suitable, for example, when it is difficult to cross-stack rectangular semiconductor chips, or when it is difficult to shift and stack square upper semiconductor chips.

  Moreover, although the said embodiment demonstrated the wiring board which consists of a glass epoxy base material, you may apply to the flexible wiring board etc. which consist of a polyimide base material.

DESCRIPTION OF SYMBOLS 1, 1-1, 1-2, 1-3 Semiconductor device 10 Wiring board 11, 12 Connection pad 13 Land 15 Wire 20 1st semiconductor chip 21, 31 Electrode pad 22, 32 Adhesive member 30 2nd semiconductor chip

Claims (6)

In a semiconductor device in which a plurality of semiconductor chips are stacked on a wiring board so that a part of the upper semiconductor chip is overhanged,
A semiconductor device, wherein a chip support film for warping the upper semiconductor chip in a direction opposite to the wiring substrate side is provided on a surface of the upper semiconductor chip opposite to the wiring substrate side.   The semiconductor device according to claim 1, wherein the chip support film is provided in a region including at least a part of an upper semiconductor chip overlapping with a lower semiconductor chip and at least a part of an overhang portion. .   The semiconductor chip has a rectangular shape, and the upper semiconductor chip is cross-laminated so that both sides thereof overhang from the lower semiconductor chip, and the chip support film has a width larger than the width of the lower semiconductor chip. The semiconductor device according to claim 1, wherein the semiconductor device is provided.   4. The semiconductor device according to claim 1, wherein a spacer having an area smaller than these semiconductor chips is interposed between the upper semiconductor chip and the lower semiconductor chip. 5. In a manufacturing method of a semiconductor device in which a plurality of semiconductor chips are stacked on a wiring board so that a part of the upper semiconductor chip is overhanged.
Providing a chip support film on the surface of the upper semiconductor chip opposite to the wiring board side suppresses the occurrence of warpage to the wiring board side when the upper semiconductor chip is stacked. A method of manufacturing a semiconductor device.   The region where the chip support film is provided is a region including at least a part of a region overlapping the lower semiconductor chip and at least a part of an overhang portion in the upper semiconductor chip. A method for manufacturing a semiconductor device.

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