JP2013150412A - Variable output charger - Google Patents

Abstract

A variable output charging device capable of seamlessly switching between a charging voltage control mode and a charging current control mode is provided.
A variable output charging device includes a high-frequency transformer, a control unit that generates a modulation factor signal, a carrier signal generation unit, a PWM signal generation unit, and a frequency of a three-phase AC power source at both ends of a primary winding. A frequency converter having a plurality of switches for applying a high-frequency AC pulse, and a rectifier that rectifies an AC component generated at both ends of the secondary winding of the high-frequency transformer to obtain DC power. The control unit includes a voltage adjusting unit that generates a charging current target value according to a comparison result between a measured charging voltage value applied to the battery and a target value, and a variable limiter that limits the charging current target value within a variable upper limit value. A current adjusting unit that generates an output voltage target value of the rectifying unit according to a comparison result between the charging current target value and the charging current actual measurement value, and multiplying the output voltage target value of the rectifying unit by a predetermined coefficient, An amplitude value generation unit that generates an amplitude value.
[Selection] Figure 16

Description

  The present invention relates to a variable output charging apparatus that converts three-phase AC power into DC power and outputs variable DC voltage and DC current.

Conventional technology

  2. Description of the Related Art In recent years, expectations for electric vehicles (EVs) have been increasing with the development of lithium ion secondary batteries that have high energy density and little deterioration even after repeated charge and discharge. EV charging methods include normal charging methods that charge for a long time during parking hours such as at night, commercial facilities such as highway service areas, restaurants, shopping centers, and public institutions such as hospitals. There are two methods of quick charging with a quick charger installed in the factory. The quick charger can charge about 80% in about 20 minutes. In order to promote the spread of EVs in the future, it is essential to provide a quick charger that enables supplementary charging on the go. The EV quick charger includes an AC / DC converter for converting electric power (for example, three-phase 200 V) from a commercial power source into DC electric power suitable for charging a battery.

FIG. 1 shows a configuration of a conventional AC / DC converter 1000. The circuit system shown in FIG. 1 is a conversion circuit system that creates a DC power source by controlling high-frequency current of an AC input with one conversion circuit and performing rectification and smoothing by high-frequency insulation at an output unit. The AC / DC converter 1000 is a so-called SMR (Switch Mode Rectifier) converter, and includes inductors L1 to L3 connected to each layer of a three-phase AC power source connected to an AC input terminal and capacitors C1 to C3 connected to each layer. AC filter 1100, frequency converter 1200 including a plurality of switching elements SW1 to SW12 and diodes D1a to D6a, a transformer 1300 that insulates the input side from the output side, and a plurality of diodes D1b connected to the secondary side of the transformer 1300 To R4b and an inductor L4 are provided as basic components. The AC / DC converter 1000 generates desired DC power by performing PWM control of both switches constituting the frequency converter 1200.
Patent Document 1 discloses a drive pulse generation method for generating a drive pulse for a plurality of switch elements of a converter by comparing a current command value of an SMR converter and a carrier signal, and each of the switch elements that should be prevented from being simultaneously turned on. A drive pulse generation method for an SMR converter in which a non-conduction period is provided between drive pulses is described. Specifically, the addition means generates a current command value by adding a signal corresponding to the width of the non-conduction period to the original current command value, and compares the current command value with the carrier signal using a pulse distributor. It is described that the final drive pulse is generated by deleting a portion corresponding to the non-conduction period from the drive pulse obtained by the logical product means.

  Patent Document 2 discloses a single-phase high-frequency inverter in which two bidirectional switching elements (1) and (2) are half-bridge connected, a high-frequency transformer, and two bidirectional switching elements (3) and (4) are half-bridged. In an SMR converter having a connected center tap type single-phase rectifier circuit, the bidirectional switching elements (1) and (2) constituting the single-phase high-frequency inverter are alternately turned on and off, and the single-phase rectifier circuit is configured. The bi-directional switching elements (3) and (4) that perform the on / off control alternately with the on / off control of the switching elements (1) and (2) are turned on and off alternately to bring the input current closer to a sine waveform and the input force It is described that the rate is 1.

JP 2000-32746 A JP-A-8-228484

  The battery charging mode of the EV quick charger includes a charging voltage control mode (cv mode) and a charging current control mode (cc mode). The EV quick charger needs to be able to switch between these two modes seamlessly. Therefore, if a controller for controlling the charging voltage and a controller for controlling the charging current are provided separately, the controller output becomes discontinuous at the time of mode switching, and seamless mode switching becomes difficult.

  The present invention has been made in view of such a point, and an object thereof is to provide a variable output charging apparatus capable of seamlessly switching between a charging voltage control mode and a charging current control mode.

  The variable output charging device of the present invention converts the three-phase AC power supplied to the input end of the three-phase AC channel into DC power, and connects to the output terminal with a charging voltage or charging current of a magnitude according to the control input. A variable output charging device for charging a battery that is generated, a high-frequency transformer, a control unit that generates a modulation factor signal synchronized with a voltage change of a phase voltage of a three-phase AC power source that generates the three-phase AC power, A carrier signal generation unit that generates a carrier signal having a frequency higher than the frequency of the phase AC power supply, and a timing and a period determined according to the comparison result by comparing the signal levels of the carrier signal and the modulation factor signal. A PWM signal generation unit that generates a PWM signal composed of a pulse train; and an output end of the three-phase AC flow path that is turned on and off in accordance with the PWM signal to both the primary windings of the high-frequency transformer. A frequency converter having a plurality of switches that selectively connect to both ends of the primary winding and apply an AC pulse having a frequency higher than the frequency of the three-phase AC power supply to both ends of the primary winding, and a secondary winding of the high-frequency transformer A rectifying unit that rectifies an AC component generated at both ends to obtain the DC power, and the control unit performs charging according to a comparison result between a charging voltage actual value applied to the battery and a charging voltage target value. A voltage adjusting unit for generating a current target value; a variable limiter for limiting the charge current target value within a variable upper limit value of a magnitude corresponding to the control input; the charge current target value that has passed through the variable limiter; and the battery A current adjusting unit that generates an output voltage target value of the rectifying unit according to a comparison result with an actual charging current value supplied to the output, and the modulation factor signal by multiplying the output voltage target value of the rectifying unit by a predetermined coefficient Amplitude of It is characterized in that it comprises an amplitude value generator for generating a.

  According to the variable output charging apparatus of the present invention, it is possible to seamlessly switch between the charging voltage control mode and the charging current control mode by controlling the upper limit value of the charging current target value with the variable limiter.

It is a figure which shows the structure of the conventional AC / DC converter. It is a figure which shows the structure of the AC / DC converter which concerns on the Example of this invention. It is a figure which shows the modulation factor signal based on the Example of this invention. (A)-(f) is a timing chart which shows the PWM signal pattern which concerns on the Example of this invention, respectively. It is a figure which shows the operation | movement waveform of each part of the variable output charging device which concerns on the Example of this invention. It is a figure which shows the operation mode of the variable output charging device which concerns on the Example of this invention. It is a figure which shows the structure of the PWM signal generation part which concerns on the Example of this invention. It is a figure which shows the structure of the short circuit pulse generation part which concerns on the Example of this invention. It is a timing chart which shows operation | movement of the short circuit pulse generation part which concerns on the Example of this invention. (A) is a schematic diagram which shows the electrical connection relationship of a three-phase alternating current power supply and a variable output charging device. (B) is a diagram showing the displayed phase voltages in FIG. 10 (a), the phase currents, line voltage _{v rs,} the phase relationship of the line current _{i rs.} It is a primary side conversion equivalent circuit diagram of the variable output charging apparatus which concerns on the Example of this invention. It is a block diagram which shows the structure of the variable output charging device which concerns on the Example of this invention. It is a figure which shows the structure of the PWM signal generation part to which the protection function based on the Example of this invention was added. It is a figure which shows the protection sequence which concerns on the Example of this invention. It is a figure which shows the protection sequence which concerns on the Example of this invention. 1 is a system configuration diagram of a variable output charging apparatus according to an embodiment of the present invention.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings shown below, substantially the same or equivalent components and parts are denoted by the same reference numerals.

<Basic configuration>
FIG. 2 is a block diagram showing a configuration of the variable output charging device 1 constituting the EV quick charger according to the embodiment of the present invention. The variable output charging device 1 converts the three-phase AC power supplied from the three-phase AC power source E into DC power, and outputs a DC voltage of, for example, 0 to 400 V at the output terminal. The variable output charging device 1 has a so-called SMR (Switch Mode Rectifier) converter as a basic configuration, and constitutes a main part of the EV quick charger.
The three-phase AC channel 10 is connected to the r-phase, s-phase, and t-phase of the three-phase AC power source E at the input end, and each phase voltage is introduced into the variable output charging device 1. The AC filter 12 includes a resistor R _AC , a reactor L _AC , and a capacitor C _AC provided on the three-phase AC channel 10 and removes a high-frequency current component generated by the frequency conversion unit 20.

The frequency conversion unit 20 includes a positive bidirectional switch S _rp , S _sp , S _tp connected to each output end of the three-phase AC flow path 10 corresponding to each phase of the three-phase AC power source E, and a negative side Bidirectional switches S _rn , S _sn , and S _tn are included. Each of the bidirectional switches includes two unidirectional gate trigger switch elements (hereinafter simply referred to as switch elements) that are reversely connected in series to each other and rectifier elements that are connected in parallel to the switch elements. The switch element is, for example, an IGBT (Insulated Gate Bipolar Transistor), and the rectifier element is, for example, a diode. The diode has an anode connected to the IGBT emitter and a cathode connected to the IGBT collector, and forms a current bypass path in a direction in which the switch element does not flow current.

The positive-side and negative-side bidirectional switches are turned on / off according to corresponding PWM signals rp, rn, sp, sn, tp, and tn supplied from the PWM signal generation unit 40, respectively. The output end of the three-phase AC channel 10 connected to the r-phase of the three-phase AC power source E is connected to the positive terminal (p-side terminal) of the high-frequency transformer 30 when the positive bidirectional switch S _rp is turned on. When the negative-side bidirectional switch S _rn is turned on, the negative-side terminal (n-side terminal) of the high-frequency transformer 30 is connected. The output end of the three-phase AC channel 10 connected to the s phase of the three-phase AC power source E is connected to the positive terminal (p-side terminal) of the high-frequency transformer 30 when the positive bidirectional switch _Ssp is turned on. When the negative side bidirectional switch S _sn is turned on, the negative side terminal (n side terminal) of the high frequency transformer 30 is connected. The output end of the three-phase AC channel 10 connected to the t-phase of the three-phase AC power source E is connected to the positive terminal (p-side terminal) of the high-frequency transformer 30 when the positive bidirectional switch _Stp is turned on. When the negative bidirectional switch _Stn is turned on, it is connected to the negative terminal (n terminal) of the transformer 30. The frequency converter 20 turns on and off each bidirectional switch for a predetermined period at a predetermined timing in accordance with the PWM signals rp, rn, sp, sn, tp, and tn, so that the frequency conversion unit 20 uses the frequency of the three-phase AC power supply E. A high frequency AC pulse is applied to both ends of the primary winding of the high frequency transformer 30.

The high-frequency transformer 30 includes a high-frequency AC link unit that insulates the primary side (input side) and the secondary side (output side) and transforms a high-frequency AC pulse applied to the primary side and transmits it to the secondary side. Configure. The rectifier 50 includes a rectifier in which rectifier diodes D1 to D4 are bridge-connected, and converts an AC pulse output from the secondary winding of the high-frequency transformer 30 into a DC. DC filter 60 includes a reactor L _DC connected in series to the positive side of the output terminal, a LC low-pass filter constituted by a capacitor connected C _DC between the positive electrode and the negative electrode output terminal, the output of the rectifier unit 50 The ripple component contained in is removed. An EV battery is connected to the output terminal of the variable output charging device 1 for charging.

The control unit 70 sets the output voltage (charging voltage) v _{o of} the variable output charging device 1 detected by various sensors, the output current (charging current) i _o, and the phase angle ωt of the line voltage of the three-phase AC power source E. Based on this, a sinusoidal PWM command signal (also referred to as a PWM modulation factor) α _rs ^* , α _st ^* , α _tr ^* is generated and supplied to the PWM signal generation unit 40. The controller 70 controls the output voltage (charging voltage) v _o and the output current (charging current) i _o by performing amplitude control of the PWM command signals α _rs ^* , α _st ^* , α _tr ^* .

The PWM signal generator 40 generates PWM signals rp, rn, sp, sn, tp, tn based on the PWM command signals (modulation rate signals) α _rs ^* , α _st ^* , α _tr ^* . The PWM signal generator 40 generates a signal level of the carrier signal Car having a frequency (for example, 15 KHz) sufficiently higher than the frequency of the three-phase AC power supply E generated by the carrier signal generator 41 (see FIG. 7) and the PWM command signal α. The signal levels of _rs ^* , α _st ^* , α _tr ^* are compared, and a pulse train generated at a timing and a period determined according to the comparison result is output as a PWM signal rp, rn, sp, sn, tp, tn. The PWM signals rp, sp, and tp each include a positive-side bidirectional switch drive pulse, and are supplied to the corresponding positive-side bidirectional switches S _rp , S _sp , and S _tp . The PWM signals rn, sn, and tn each include a negative-side bidirectional switch drive pulse, and are respectively supplied to the corresponding negative-side bidirectional switches S _rn , S _sn , and _Stn .

  The PWM signal generation unit 40 includes a pair of positive signals connected to the same three-phase AC channel 10 according to the short-circuit pulses r0, s0, and t0 generated at a predetermined timing within the PWM control cycle in the short-circuit pulse generation unit 90. Positive and negative side switch drive pulses are generated to simultaneously turn on the side and negative side bidirectional switches. That is, both ends of the primary winding of the high-frequency transformer are short-circuited by simultaneously turning on the pair of positive-side and negative-side bidirectional switches according to the short-circuit pulse.

  The carrier signal Car is constituted by a pulse train having an amplitude of 1 that includes a change interval in which the signal level changes at a constant time change rate in a constant cycle. The carrier signal Car preferably has a so-called sawtooth waveform. The control unit 70 and the PWM signal generation unit 40 are configured by, for example, a microcomputer, an FPGA (Field Programmable Gate Array), or a combination thereof.

FIG. 3 is a diagram illustrating waveforms of the PWM command signals α _rs ^* , α _st ^* , α _tr ^* generated by the control unit 70 and supplied to the PWM signal generating unit 40. The PWM command signals α _rs ^* , α _st ^* , and α _tr ^* each have a predetermined phase relationship with respect to the line voltage v _rs of the three-phase AC power supply E and have a sine wave having the same frequency as the power supply frequency. It is. That is, the PWM command signals α _rs ^* , α _st ^* , α _tr ^* are synchronized with voltage changes of the respective phase voltages and line voltages of the three-phase AC power supply E.

<PWM signal pattern>
The PWM signal generated by the PWM signal generation unit 40 will be described. As shown in FIG. 3, one cycle of the PWM command signals α _rs ^* , α _st ^* , α _tr ^* corresponding to one cycle of the power source fundamental wave is 6 depending on the magnitude relationship of the signal levels between the PWM command signals. Can be divided into two periods. The PWM signal generator 40 generates PWM signals having different patterns in the six periods. 4A to 4F show PWM signal patterns in each of the six periods.

  One period of the PWM coincides with one period of the square-wave toggle signal T output from the toggle signal generation unit 42 (see FIG. 7). The toggle signal T divides the PWM control period into a first half period (first period) and a second half period (second period) according to the signal level. That is, the period in which the toggle signal T exhibits a high level is the first half period, and the period in which the toggle signal T exhibits a low level is the second half period. The carrier signal Car is synchronized with the toggle signal T, and the pulse width of the sawtooth pulse coincides with the time width of the first half period and the second half period of the PWM control cycle.

In the first period within one cycle of the PWM command signal shown in FIG. 3, among the PWM command signals, the level of α _rs ^* is the largest, the level of α _st ^* is the smallest, and the level of α _tr ^* is the other level. Between the two. In the first period, the PWM signal generation unit 40 generates a PWM signal having the following pattern (see FIG. 4A).

In the first half period of the PWM control cycle, the PWM signal rp continuously exhibits a high level. The PWM signal sn exhibits a high level over a period from when the level of the carrier signal Car reaches the level of α _st ^* until it reaches the level of α _tr ^* . The PWM signal tn exhibits a high level over a period from when the level of the carrier signal reaches the level of α _tr ^* until it reaches the level of α _rs ^* .

In the latter half of the PWM control cycle, the PWM signal rn continuously exhibits a high level. The PWM signal sp exhibits a high level over a period from when the level of the carrier signal reaches the level of α _st ^* until it reaches the level of α _tr ^* . In the latter half of the PWM control cycle, the PWM signal tp exhibits a high level over a period from when the carrier signal level reaches the α _tr ^* level until it reaches the α _rs ^* level.

Before and after the transition from the first half period of the PWM control cycle to the second half period (that is, after the level of the carrier signal Car generated in the first half period reaches the level of α _rs ^* , the level of the carrier signal generated in the second half period is the period until the level of α _st ^* is reached) and the period before and after transition from the latter half of the PWM control cycle to the first half of the next control cycle (that is, the level of the carrier signal Car generated in the second half is α _rs ^* The PWM signal rp and the PWM signal rn are both high in response to the short-circuit pulse r0 in the period from when the level is reached until the level of the carrier signal generated in the first half of the next control cycle reaches the α _st ^* level). Presents a level.

That is, in the first period, the PWM signal generation unit 40 generates a positive switch drive pulse that drives the positive bidirectional switch S _rp over the first half period corresponding to one change interval of the carrier signal Car. and outputting the results as a PWM signal rp and negative bidirectional switch _S rn within the first half _period, S _sn, sequentially produced in different time zones negative side switch driving pulses for driving the _{S tn,} respectively, which each PWM signal Output as rn, sn, tn. On the other hand, the PWM signal generation unit 40 generates a negative switch driving pulse for driving the negative bidirectional switch S _rn over the latter half period, and outputs this as a PWM signal rn. A positive-side switch drive pulse for driving each of the positive-side bidirectional switches S _rp , S _sp , S _tp paired with the switches S _rn , S _sn , S _{tn in} the same order as that of the switches S _rn , S _sn , S _tn is generated, Are output as PWM signals rp, sp, and tp, respectively.

As described above, the PWM signal is generated by the positive side switch drive pulse and the negative side switch drive pulse generated at the timing and period determined according to the comparison result of the carrier signal Car and the PWM command signals α _rs ^* , α _st ^* , α _tr ^*. Composed of pulses.

<Operation mode>
FIG. 5 shows a waveform of each part of the variable output charging device 1 in the first period, and FIG. 6 shows an operation mode corresponding to the PWM signal pattern in the first period. Hereinafter, operation modes A to H in the first period will be described with reference to FIGS. 5 and 6.

(Mode A)
It is generated in a predetermined period immediately after the start and end of the PWM control cycle, that is, a period until the signal level of the carrier signal Car generated in the first half period from the start of the PWM control period reaches the level of α _st ^* , and in the second half period. A positive bidirectional switch S _rp connected to the r-phase via the three-phase AC channel 10 during the period from when the signal level of the carrier signal Car exceeds the level of α _rs ^* to the end of the PWM control cycle; The negative bidirectional switch S _rn is turned on in response to the short circuit pulse r0. As a result, a loop passing through the positive-side bidirectional switch S _rp , the high-frequency transformer 30, and the negative-side bidirectional switch S _rn is formed, and both ends of the high-frequency transformer 30 are short-circuited. An excitation current flows through the loop as the primary current i _pn . On the secondary side, the output current i _o continues to flow.

(Mode B)
The positive bidirectional switch S _rp connected to the r phase via the three-phase alternating current flow path 10 is turned on over the first half period (from mode A to mode E) of the PWM control cycle according to the PWM signal rp. Let it continue. The negative bidirectional switch S _rn connected to the r phase is turned off in response to the PWM signal rn, while the negative bidirectional switch S _sn connected to the s phase is turned on in response to the PWM signal sn. . As a result, a loop is formed through the power source r-phase, positive-side bidirectional switch S _rp , high-frequency transformer 30, negative-side bidirectional switch S _sn , and power source s-phase, and commutation of the primary current i _pn occurs. The line voltage v _rs of the three-phase AC power supply E is applied to both ends of the high-frequency transformer 30, and the primary current in the positive direction from the positive side (p side) terminal to the negative side (n side) terminal of the high frequency transformer 30. i _pn flows. As a result, a secondary current is induced in the secondary winding of the high-frequency transformer 30. The secondary current is rectified by the rectifying unit 50 and the output current i _o flows.

(Mode C)
The negative bidirectional switch S _sn connected to the s phase is turned off in response to the PWM signal sn, while the negative bidirectional switch S _tn connected to the t phase is turned on in response to the PWM signal tn. . As a result, a loop is formed through the power source r phase, the positive side bidirectional switch S _rp , the high frequency transformer 30, the negative side bidirectional switch S _tn , and the power source t phase, and commutation of the primary side current i _pn occurs. The line voltage v _tr of the three-phase AC power source E is applied to both ends of the high-frequency transformer 30, and the primary current in the positive direction from the positive side (p side) terminal to the negative side (n side) terminal of the high frequency transformer 30. i _pn flows. As a result, a secondary current is induced in the secondary winding of the high-frequency transformer 30. The secondary current is rectified by the rectifying unit 50 and the output current i _o flows.

(Mode D, E)
The negative bidirectional switch S _tn connected to the t phase is turned off in response to the PWM signal tn, while the positive bidirectional switch S _rp and the negative bidirectional switch S _rn connected to the r phase are short-circuit pulses. It is turned on in response to r0. As a result, a loop passing through the positive-side bidirectional switch S _rp , the high-frequency transformer 30, and the negative-side bidirectional switch S _rn is formed, and both ends of the high-frequency transformer 30 are short-circuited. An excitation current flows through the loop as the primary current i _pn . On the secondary side, the output current i _o continues to flow.

(Mode F)
The negative bidirectional switch S _rn connected to the r phase is kept on for the second half of the PWM control cycle (from mode E to mode H) in accordance with the PWM signal rn. The positive bidirectional switch S _rp is turned off in response to the PWM signal rp, while the positive bidirectional switch S _sp connected to the s phase is turned on in response to the PWM signal sp. As a result, a loop is formed through the power supply r-phase, negative-side bidirectional switch S _rn , high-frequency transformer 30, positive-side bidirectional switch S _sp , and power supply s-phase, and commutation of the primary current i _pn occurs. A line voltage v _rs of the three-phase AC power source E is applied to both ends of the high-frequency transformer 30 in the reverse direction, and the negative-direction (n-side) terminal of the high-frequency transformer 30 is directed toward the positive (p-side) terminal. A primary current i _pn flows. As a result, a secondary current is induced in the secondary winding of the high-frequency transformer 30. The secondary side current is rectified by the rectifying unit 50 and the output current i _o flows.

(Mode G)
The positive-side bidirectional switch _Ssp connected to the s-phase is turned off in response to the PWM signal sp, while the positive-side switch _Stp connected to the t-phase is turned on in response to the PWM signal tp. As a result, a loop is formed through the power supply r phase, the negative bidirectional switch S _rn , the high frequency transformer 30, the positive bidirectional switch S _tp , and the power supply t phase, and commutation of the primary current i _pn occurs. A line voltage v _tr of the three-phase AC power source E is applied to both ends of the high-frequency transformer 30 in the reverse direction, and the negative-direction (n-side) terminal of the high-frequency transformer 30 is directed toward the positive (p-side) terminal. A primary current i _pn flows. As a result, a secondary current is induced in the secondary winding of the high-frequency transformer 30. The secondary side current is rectified by the rectifying unit 50 and the output current i _o flows.

(Mode H)
The operation mode H is the same as the operation mode A described above. After the operation mode H ends, the operation mode A is restored. In the period 1 shown in FIGS. 3 and 4A, the above-described operation modes A to H are repeated.

As described above, in the first period within one cycle of the PWM command signal, the r phase is set as the reference phase, and the primary current i _pn is changed from the s phase to the t phase while forming a current loop passing through the r phase. A bidirectional switch is driven to commutate. Further, the pair of positive side bidirectional switches and negative side bidirectional switches connected to the output end of the common three-phase AC flow path 10 are driven so as to be switched in the first half period and the second half period of the PWM control cycle, and a pair of positive side bidirectional switches. The side and negative side bidirectional switches are driven so that the driving order is the same in the first half period and the second half period. Thereby, positive and negative voltage pulses with good symmetry are alternately applied to both ends of the high-frequency transformer 30. Here, if the symmetry of the positive and negative voltage pulses applied to the high-frequency transformer 30 is lost, a DC bias is generated and magnetic saturation is likely to occur. According to the PWM signal pattern according to the present embodiment, the symmetry of the positive and negative voltage pulses applied to the high-frequency transformer 30 is extremely good, and the amount of current flowing in the positive direction and the negative direction in the primary side current i _pn . It is possible to make the total amount of current flowing through the current uniform. That is, it is possible to improve the symmetry of the primary current i _pn and to prevent the occurrence of DC bias. This also can reduce the harmonic components of the secondary-side current generated in the secondary side of the high-frequency transformer 30, it is possible to reduce the size of the reactor L _DC.

Further, according to the PWM signal pattern according to the present embodiment, a short-circuit pulse is generated in a period between the application period of the positive voltage pulse and the application period of the negative voltage pulse with respect to the primary winding of the high-frequency transformer 30, and accordingly The positive side and negative side bidirectional switches connected to the common three-phase AC channel 10 are simultaneously turned on. As a result, both ends of the high-frequency transformer 30 are short-circuited during the above period, and a voltage applied to both ends of the high-frequency transformer 30 is zero while ensuring the continuity of the primary current i _pn by flowing an exciting current on the short-circuited loop. Is generated. In the first period, the r phase is set as a reference phase, and a current loop passing through the r phase is formed. Therefore, either the positive-side bidirectional switch S _rp or the negative-side bidirectional switch S _rn connected to the r-phase in the first half period or the second half period can be always turned on. Thus, in the first period, by generating a short pulse r0 so as to obtain simultaneously ON state is connected to the r-phase positive side bidirectional switch S _rp and negative bidirectional switch S _rn, efficient switching It is possible to provide a short-circuit period of the high-frequency transformer 30 within the PWM control period while realizing the operation.

In the second period within one cycle of the PWM command signal shown in FIG. 3, among the PWM command signals, the level of α _rs ^* is the largest, the level of α _tr ^* is the smallest, and the level of α _st ^* is the other level. Between the two. As shown in FIG. 4B, the PWM signal generation unit 40 drives the negative bidirectional switch _Stn for the first half period corresponding to one change period of the carrier signal Car in the second period. A switch drive pulse is generated and output as a PWM signal tn, and negative switch drive pulses for driving the positive bidirectional switches S _tp , S _sp , S _rp in the first half period are sequentially generated in different time zones. These are output as PWM signals tp, rp, and sp, respectively. On the other hand, the PWM signal generation unit 40 generates a positive-side switch drive pulse for driving the positive-side bidirectional switch _Stp over the latter half period, and outputs this as a PWM signal tp, and the positive-side bidirectional pulse in the first half period. A negative switch driving pulse for driving each of the negative bidirectional switches S _tn , S _sn , S _rn paired with the switches S _tp , S _sp , S _{rp in} the same order as the driving order of the switches S _tp , S _sp , S _rp , Are output as PWM signals tn, sn, and rn, respectively. In the second period, the t-phase is the reference phase, and the bidirectional switch is driven so that the primary current i _pn is commutated from the s-phase to the r-phase while forming a current loop passing through the t-phase. Further, the positive bidirectional switch and the negative bidirectional switch connected to the output end of the common three-phase AC channel 10 are driven so as to be switched in the first half period and the second half period of the PWM control cycle, and a pair of positive side and The negative-side bidirectional switch is driven so that the driving order matches in the first half period and the second half period. Thereby, positive and negative voltage pulses with good symmetry are alternately applied to both ends of the high-frequency transformer 30. Similarly to the case of the first period described above, a short-circuit pulse is generated in a period between the application period of the positive voltage pulse and the application period of the negative voltage pulse with respect to the primary winding of the high-frequency transformer 30, and based on the short-circuit pulse. By simultaneously turning on the pair of positive-side and negative-side bidirectional switches, both ends of the high-frequency transformer 30 are short-circuited, and an excitation current is passed on the short-circuited loop to ensure continuity of the primary-side current i _pn while ensuring the continuity of the primary-side current i _pn. A period in which the voltage applied to both ends of the circuit is zero is generated. In the second period, the t phase is set as the reference phase, and a current loop passing through the t phase is formed. Therefore, either the positive-side bidirectional switch S _tp or the negative-side bidirectional switch S _tn connected to the t-phase in the first half period or the second half period can be always turned on. Therefore, in the second period, PWM is generated while realizing an efficient switching operation by generating a short-circuit pulse t0 to simultaneously turn on the positive bidirectional switch _Stp and the negative bidirectional switch _Stn. It is possible to provide a short-circuit period for the high-frequency transformer 30 within the control cycle.

In the third period in one cycle of the PWM command signal shown in FIG. 3, among the PWM command signals synchronized with the voltage change of the line voltage of the power supply, the level of α _st ^* is the largest, and the level of α _tr ^* Is the smallest, and the level of α _rs ^* is in the middle of the other two. As shown in FIG. 4 (c), PWM signal generating unit 40, in the third period, the positive side over the first half period corresponding to one variation period of the carrier signal Car drive the positive side bidirectional switch S _sp A switch drive pulse is generated and output as a PWM signal sp, and negative switch drive pulses for driving the negative bidirectional switches S _sn , S _tn , and S _rn in the first half period are sequentially generated in different time zones. These are output as PWM signals sn, tn, and rn, respectively. On the other hand, the PWM signal generation unit 40 generates a negative side switch drive pulse for driving the negative side bidirectional switch S _sn over the latter half period, and outputs this as a PWM signal sn. The positive-side switch drive pulse for driving each of the positive-side bidirectional switches S _sp , S _tp , S _rp paired with the negative-side bidirectional switches S _sn , S _tn , S _{rn in} the same order as that of the negative-side bidirectional switches S _sn , S _tn , S _rn These are output as PWM signals sp, tp, and rp, respectively. In the third period, the s phase is the reference phase, and the bidirectional switch is driven so that the primary current i _pn is commutated from the t phase to the r phase while forming a current loop passing through the s phase. Further, the positive bidirectional switch and the negative bidirectional switch connected to the output end of the common three-phase AC channel 10 are driven so as to be switched in the first half period and the second half period of the PWM control cycle, and a pair of positive sides The negative bidirectional switch is driven so that the driving order is the same in the first half period and the second half period. Thereby, positive and negative voltage pulses with good symmetry are alternately applied to both ends of the high-frequency transformer 30. Similarly to the case of the first period described above, a short-circuit pulse is generated in a period between the application period of the positive voltage pulse and the application period of the negative voltage pulse with respect to the primary winding of the high-frequency transformer 30, and based on the short-circuit pulse. By simultaneously turning on the pair of positive-side and negative-side bidirectional switches, both ends of the high-frequency transformer 30 are short-circuited, and an excitation current is passed on the short-circuited loop to ensure continuity of the primary-side current i _pn while ensuring the continuity of the primary-side current i _pn. A period in which the voltage applied to both ends of the circuit is zero is generated. In the third period, the s phase is set as a reference phase, and a current loop passing through the s phase is formed. Therefore, either the positive-side bidirectional switch S _tp or the negative-side bidirectional switch S _tn connected to the s phase in the first half period or the second half period can be always turned on. Therefore, by the third period to generate a short pulse s0 so as to obtain at the same time turning on the positive side bidirectional switch S _sp and negative bidirectional switch S _sn, PWM cycle while providing an efficient switching operation It is possible to provide a short-circuit period for the high-frequency transformer 30 inside.

In the fourth to sixth periods within one cycle of the PWM command signal shown in FIG. 3, as shown in FIGS. 4 (d) to (f), the operation conforms to the operation in the first to third periods. Therefore, the description is omitted. Thus, in the variable output charging device 1 according to the present embodiment, the reference phase is sequentially switched during the first to sixth periods, a current loop passing through the reference phase is formed, and the primary current i _pn The positive and negative bidirectional switches are driven to commutate between the loops passing through the two phases. The positive and negative bidirectional switches corresponding to the reference phase are simultaneously turned on according to the short-circuit pulse, and both ends of the high-frequency transformer 30 are short-circuited. The short-circuit pulse is generated during a period between the application period of the positive voltage pulse and the application period of the negative voltage pulse with respect to the primary winding of the high-frequency transformer 30, and both ends of the high-frequency transformer 30 are secured while ensuring the continuity of the primary-side current _ipn. A period in which the voltage applied to is zero is generated.

<Configuration of PWM signal generator>
FIG. 7 is a logic circuit diagram showing a configuration of the PWM signal generation unit 40 that generates the PWM signal having the pattern described above. The comparators 401 to 403 compare the signal level of the carrier signal Car generated by the carrier signal generation unit 41 with the signal levels of the PWM command signals α _rs ^* , α _st ^* , α _tr ^* , and Level display pulses rs, st, tr having a pulse width corresponding to the signal level are output. The level display pulse is branched into a route that is logically inverted and a route that is not logically inverted, and is input to AND gates 411 to 416, respectively. The AND gates 411 and 412 calculate the logical product of the level display pulses rs and st and their logical inversion pulses, and generate the positive side and negative side switch drive pulses constituting the PWM signals rp and rn and the timings thereof. Timing pulses rp ′ and rn ′ that determine the pulse width are output. The AND gates 413 and 414 calculate the logical product of the level display pulses st and tr and their logical inversion pulses to generate the positive side and negative side switch drive pulses constituting the PWM signals sp and sn and the pulses thereof. Timing pulses sp ′ and sn ′ for determining the width are output. The AND gates 415 and 416 calculate the logical product of the level display pulses rs and tr and their logical inversion pulses to generate the positive side and negative side switch drive pulses constituting the PWM signals tp and tn and the timings thereof. Timing pulses tp ′ and tn ′ that determine the pulse width are output.

  Timing pulses rp ′, rn ′, sp ′, sn ′, tp ′, and tn ′ are input to one input terminals of the OR gates 421 to 426, respectively. The other input terminals of the OR gates 421 and 422, 423 and 424, 425 and 426 are supplied with the short-circuit pulses r0, s0 and t0 generated in the short-circuit pulse generator 90, respectively. The OR gates 421 to 426 calculate the logical sum of the timing pulse and the short-circuit pulse, and output synthesized pulses rp ″, rn ″, sp ″, sn ″, tp ″, tn ″ obtained by synthesizing the timing pulse and the short-circuit pulse. .

  The synthesized pulses rp ″, rn ″, sp ″, sn ″, tp ″, tn ″ are the toggle signal T generated in the toggle signal generation unit 42 by the AND gates 431 to 442 and the OR gates 451 to 456 and the logical inversion signal thereof. And is logically synthesized. The toggle signal T exhibits different signal levels in the first half period and the second half period of the PWM cycle. The AND gates 431 to 442 and the OR gates 451 to 456 divide the combined pulse into a positive bidirectional switch and a negative bidirectional switch according to the signal level of the toggle signal T, and divide the positive and negative bidirectional switches. The positive side and negative side switch drive pulses corresponding to each of these are generated and output as PWM signals. The PWM signal pattern described above can be generated by such a relatively small logic circuit.

<Configuration of short-circuit pulse generator>
FIG. 8 is a circuit block diagram of the short-circuit pulse generation unit 90 that generates the short-circuit pulses r0, s0, and t0. FIG. 9 illustrates the operation of the short-circuit pulse generation unit 90 in the first period shown in FIG. It is a timing chart. Level display pulses rs, st, and tr generated by the PWM signal generation unit 40 are input to the short-circuit pulse generation unit 90. The level display pulse and its logic inversion pulse are logically synthesized by AND gates 901 and 902 and an OR gate 903 to generate a short circuit timing pulse A that determines the generation timing and pulse width of the short circuit pulse. The short circuit timing pulse A compares the carrier signal Car signal level with the PWM command signals α _rs ^* , α _st ^* , α _tr ^* and compares all the PWM command signals α _rs ^* , α _st ^* , α _tr ^* . A period during which the signal is large or small with respect to the signal level of the carrier signal Car is displayed. The short-circuit timing pulse A displays a zero voltage application period between a positive voltage pulse application period and a negative voltage pulse application period for the primary winding of the high-frequency transformer 30.

The short-circuit timing pulse A is input to the clock input terminals of the D flip-flops 906 and 907 via the NOT gate 904 and the shift register 905. A logic inversion pulse of the level display pulse rs is input to the D terminal of the D flip-flop 906, and a logic inversion pulse of the level display pulse tr is input to the D terminal of the D flip-flop 907. The output values of the D flip-flops 906 and 907 are logically synthesized by AND gates 908 and 909 to generate the minimum display pulses rs _min , st _min , and tr _min . The minimum display pulses rs _min , st _min , tr _min indicate the lowest signal level of the PWM command signals α _rs ^* , α _st ^* , α _tr ^* . That is, as shown in FIG. 9, since α _st ^* is minimum in the first period, the minimum display pulse st _min is generated in the first period.

On the other hand, the level display pulses rs, st, tr and their logic inversion pulses are logically synthesized by AND gates 910, 911, 912 and an OR gate 913, and a trigger signal B is generated. The trigger signal B is input to the clock input terminals of the D-flip flops 915 and 916 via the shift register 914. A level display pulse rs is input to the D terminal of the D-flip flop 915, and a level display pulse tr is input to the D terminal of the D-flip flop 916. The output values of the D flip-flops 915 and 916 are logically synthesized by AND gates 917 and 918 to generate maximum display pulses rs _max , st _max , and tr _max . The maximum display pulses rs _max , st _max , tr _max display the highest signal level of the PWM command signals α _rs ^* , α _st ^* , α _tr ^* . That is, as shown in FIG. 9, since α _rs ^* is the maximum in the first period, the maximum display pulse rs _max is generated in the first period.

The minimum display pulses rs _min , st _min , tr _min and the maximum display pulses rs _max , st _max , tr _max are logically synthesized by NOT gates 920 to 922, AND gates 931 to 936, and OR gates 941 to 943, and the reference phase is determined. A reference phase display pulse to be displayed is generated. The reference phase display pulse and the short circuit timing pulse A are input to AND gates 951 to 953. The AND gates 951 to 953 output the logical product of these input signals as short-circuit pulses r0, s0, and t0.

By configuring the short-circuit pulse generator 90 in this way, a positive voltage pulse application period for the primary winding of the high-frequency transformer 30 is changed between the pair of positive and negative bidirectional switches connected to the phase to be the reference phase. And a short-circuit pulse that is turned on in a period between the application period of the negative voltage pulse and the negative voltage pulse. As shown in FIG. 9, in the first period, a short circuit that forms a short circuit loop by turning on the positive and negative bidirectional switches S _rp and S _rn corresponding to the reference phase (r phase) in the same time zone. The pulse r0 is generated at the above timing. According to the configuration of the short-circuit pulse generation unit 90 described above, the positive-side and negative-side bidirectional switches S _rp and S _rn connected to the r-phase serving as the reference phase in the first period and the fourth period are simultaneously turned on. Is generated at the above timing. In the second period and the fifth period, the short-circuit pulse s0 that simultaneously turns on the positive-side and negative-side bidirectional switches S _sp and S _sn connected to the s phase that is the reference phase is generated at the above timing. . In the third period and the sixth period, the short-circuit pulse t0 that simultaneously turns on the positive and negative bidirectional switches S _tp and S _tn connected to the t-phase that is the reference phase is generated at the above timing. .

<PWM command signal>
The phase relationship between the sinusoidal PWM command signals α _rs ^* , α _st ^* , α _tr ^* and the three-phase AC power supply E will be described. FIG. 10A is a schematic diagram showing an electrical connection relationship between the three-phase AC power supply E and the variable output charging device 1. FIG. 10B is a diagram illustrating a phase relationship among the phase voltages, the phase currents, the line voltage v _rs , and the line current i _rs displayed in FIG. In variable output charging apparatus 1, the three-phase AC power supply phase voltage _v r of _E, v s, _{v t} and the phase current _{i r,} i s, so that _{i t} is in phase, respectively, i.e., so that the power factor 1 To control. In order to set the power factor to 1, for example, the line current i _rs may be controlled to be delayed by 60 ° with respect to the line voltage v _rs . Accordingly, assuming that the phase angle of the line voltage v _rs is ωt and α ^* is the amplitude command value of the PWM command signal, the PWM command signals α _rs ^* , α _st ^* and α _tr ^* are given by the following equations, respectively.
α _rs ^* = α ^* sin (ωt−60 °) (1)
α _st ^* = α ^* sin (ωt−120 ° −60 °) (2)
α _tr ^* = α ^* sin (ωt−240 ° −60 °) (3)
The amplitude command value α ^* is generated so that the control unit 70 monitors the output voltage (charging voltage) v _o and the output current (charging current) i _o and matches these with target values supplied from a host controller (not shown). The The phase angle ωt of the line voltage v _rs can be detected by a known phase detector.

FIG. 11 is a primary side conversion equivalent circuit diagram in which the variable output charging apparatus 1 according to the present embodiment is converted to the primary side of the high-frequency transformer 30. From the primary side conversion equivalent circuit, the following equation showing the relationship between the PWM command signals α _rs ^* , α _st ^* , α _tr ^* and the input current can be derived.
i _rs = 2i _o · α _rs ^* / 2 = i _o · α _rs ^* (4)
i _st = 2i _o · α _st ^* / 2 = i _o · α _st ^* (5)
i _tr = 2i _o · α _st ^* / 2 = i _o · α _tr ^* (6)
Further, the effective value V _m of Δ-connected line-to-line _voltage, the effective value I _m of the Δ-connected line-to-line _current, when the input power and P _in,
I _m = i _o · α ^* / √2 (7)
P _in = 3V _m · I _m = 2i _o · | v _pn | (8)
From this, the following equation showing the relationship between the amplitude command value α ^* and the output voltage _vo can be derived.
v _o = 3V _m · α ^* / √2 (9)
<Protection sequence 1>
FIG. 12 is a block diagram showing a configuration of a variable output charging apparatus 1a having a protection function for forcibly stopping the system when an abnormality occurs in the system. FIG. 13 is a circuit block diagram showing a configuration of the PWM signal generation unit 40a and the short-circuit pulse generation unit 90a having a protection circuit for realizing the protection function. The PWM signal generation unit 40a is different from the PWM signal generation unit 40 shown in FIG. 7 in that AND gates 501 to 506 are inserted between the AND gates 411 to 416 and the OR gates 421 to 426. The short-circuit pulse generator 90a is additionally provided with a forced stop pulse generator 200 that generates forced stop pulses r0 ′, s0 ′, and t0 ′ after the AND gates 951 to 953 that output the short-circuit pulses r0, s0, and t0. This is different from the short-circuit pulse generator 90 shown in FIG. Hereinafter, parts different from the variable output charging device 1 described above will be described in detail. In addition, about the part which is common in the above-mentioned variable output charging device 1, suppose that the same reference mark is attached | subjected and the description is abbreviate | omitted.

The values of the output voltage v _o , the output current i _o , and the primary side current i _pn of the variable output charging device 1a are detected by a sensor and monitored by the control unit 70a. When any of these values is not within the predetermined range, the controller 70a determines that an abnormality has occurred in the system and generates an error detection signal err. The error detection signal err is supplied to one input terminal of the AND gate 210 of the forced stop pulse generation unit 200. A short-circuit timing pulse A is input to the other input terminal of the AND gate 210. The AND gate 210 calculates the logical product of the error detection signal err and the short-circuit timing pulse A, and supplies the calculation result to the set input of the RS flip-flop 211. The reset signal res generated when the system is restarted from the emergency stop state is input to the reset input of the RS flip-flop 211. The stop trigger signal F, which is the output value of the RS flip-flop 211, is input to each clock input terminal of the D-flip flops 212 to 214 and also input to the NOT gate 215. Short-circuit pulses r0, s0, and t0 are input to the D terminals of the D flip-flops 212 to 214, respectively. Output values of the D flip-flops 212 to 214 are input to one input terminals of the OR gates 219 to 221, respectively. The AND gates 216 to 218 calculate the logical product of the short-circuit pulses r0, s0, and t0 and the inverted output values of the D-flip flops 212 to 214, respectively, and calculate the results of the other of the OR gates 219 to 221, respectively. Input to the input terminal. The OR gates 219 to 221 calculate the logical sum of the input signals and output the calculation results as forced stop pulses r0 ′, s0 ′, and t0 ′. The forced stop pulses r0 ′, s0 ′, t0 ′ are input to one input terminal of the OR gates 421 to 426.

  The NOT gate 215 logically inverts the stop trigger signal F, which is the output value of the RS flip-flop, and supplies it to one input terminal of the AND gates 501 to 506. The AND gates 501 to 506 are stopped with timing pulses rp ′, rn ′, sp ′, sn ′, tp ′, tn ′ that determine the generation timing and the pulse width of the positive side and negative side switch drive pulses constituting the PWM signal. The logical product of the trigger signal F and the logical inversion signal is calculated, and the calculation result is supplied to the other input terminals of the OR gates 421 to 426.

FIG. 14 is a timing chart illustrating the operation of the PWM signal generation unit 40a having the above-described configuration. For example, when the control unit 70a detects that the values of the output voltage v _o , the output current i _o , and the primary side current i _pn are not within predetermined ranges, the control unit 70a outputs a high-level error detection signal err. The stop trigger signal F becomes high level when the first short-circuit pulse (r0 in the example of FIG. 14) is generated after the error detection signal err becomes high level. The variable output charging device 1a enters the forced stop mode when the stop trigger signal F becomes a high level. In other words, the period after the error detection signal err becomes high level until the stop trigger signal F becomes high level (that is, after the error detection signal err becomes high level, the next short-circuit pulse is generated. The system operates in the normal operation mode.
The forced stop pulse generation unit 200 outputs a forced stop pulse (r0 ′ in the example of FIG. 14) at the generation timing of the first short-circuit pulse after the error detection signal err becomes high level. The forced stop pulses (r0 ′, s0 ′, t0 ′) are pulses that hold the short circuit pulses (r0, s0, t0). That is, the forcible stop pulse generation unit 200 latches the short-circuit pulse that is first generated after the error detection signal err becomes high level, and continuously outputs the short-circuit pulse. Therefore, the forced stop pulses (r0 ′, s0 ′, t0 ′) are generated at the same timing as the timing at which the short-circuit pulses (r0, s0, t0) are generated in the normal operation. The forced stop pulses (r0 ′, s0 ′, t0 ′) are input to one input terminal of the OR gates 421 to 426.

On the other hand, when the stop trigger signal F becomes high level, the timing pulse rp ′, which is generated according to the comparison result between the carrier signal Car and the PWM command signals (modulation rate signals) α _rs ^* , α _st ^* , α _tr ^* , rn ′, sp ′, sn ′, tp ′, and tn ′ go to the low level by passing through the AND gates 501 to 506. Therefore, after the error detection signal err becomes high level, the PWM signal generation unit 40a generates a forced stop pulse (r0 ′, s0 ′, or t0 ′) at the generation timing of the first short circuit pulse (r0, s0, or t0). Output as PWM signal. Thereby, since the simultaneous ON state of the pair of positive side and negative side bidirectional switches connected to the same three-phase AC channel 10 is continued, the short-circuit state at both ends of the high-frequency transformer 30 is also continued. Accordingly, the power supply to the high frequency transformer 30 is cut off and the system is stopped.

As described above, the PWM signal generation unit 40a generates the forced stop pulses r0 ′, s0 ′, and t0 ′ when the system abnormality is detected, and stops the system by continuously short-circuiting both ends of the high-frequency transformer 30. The forced stop pulses r0 ′, s0 ′, and t0 ′ are generated at the same timing as the generation timing of the short-circuit pulses r0, s0, and t0 generated in the normal operation, so that the system can be operated without changing the flow of the normal operation sequence. It can be stopped. That is, according to the protection sequence according to the present embodiment, the system can be forcibly stopped without imposing a burden on the system. The protection sequence realized by such hardware is effective when it is desired to immediately stop the system when an abnormality is detected. In the above embodiment, the control unit 70a detects an abnormality based on the values of the output voltage v _o , the output current i _o , and the primary side current i _pn , and shifts to the forced stop mode when an abnormality is detected. Although explained, it is good also as shifting to forced stop mode by a user's manual operation.

<Protection sequence 2>
A method for realizing the forced stop operation on the software when an abnormality occurs in the system will be described below. FIG. 15A is a diagram showing a change in the amplitude command value α ^* of the PWM command signal when the system abnormality occurs in the variable output charging devices 1 and 1a described above. FIG. 15B exemplifies signals when the amplitude command value α ^* is zero. As shown in equation (9) described above, PWM command signal _{^{α rs *, α st *,}} α tr * amplitude command value indicating the amplitude value of alpha ^* and variable output between the output voltage _{v o} of the charging device 1 or 1a The relationship can be expressed as v _o = (3 / √2) V _m α ^* . Therefore, the output voltage _vo can gradually approach zero by gradually approaching the amplitude command value α ^* to zero.

For example, the values of the output voltage v _o , the output current i _o , and the primary side current i _pn are detected by sensors and monitored by the control units 70 and 70a. If any of these values is not within the predetermined range, the control units 70 and 70a determine that an abnormality has occurred in the system, and decrease the amplitude command value α ^* at a constant time change rate Δk. As a result, the amplitude command value α ^* gradually decreases from the time when the abnormality is detected, and becomes zero when the shutdown period Δt has elapsed. Such control of the amplitude command value α ^* is realized by executing a control program stored in the control units 70 and 70a. The time change rate of the amplitude command value α ^* is not necessarily linear.
According to the configuration of the PWM signal generation units 40 and 40a and the short circuit pulse generation units 90 and 90a according to the present embodiment, as the amplitude command value α ^* decreases, the pulse width of the short circuit pulse gradually increases and the output The voltage _vo gradually decreases. As shown in FIG. 15B, when the amplitude command value α ^* becomes zero, the amplitudes of the PWM command signals α _rs ^* , α _st ^* , α _tr ^* become zero, and the PWM signal generation units 40, 40a A short-circuit pulse (r0 in the example of FIG. 15B) is output over the entire period. Thereby, since the simultaneous ON state of the pair of positive side and negative side bidirectional switches connected to the same three-phase AC channel 10 is continued, the short-circuit state at both ends of the high-frequency transformer 30 is also continued. Accordingly, the power supply to the high frequency transformer 30 is cut off and the system is stopped.

In this manner, when the system abnormality is detected, the amplitude command value α ^* is gradually decreased until it becomes zero, so that the system is finally stopped while gradually decreasing the output voltage _vo of the variable output charging device 1 or 1a. Can be made. That is, according to the protection sequence according to the present embodiment, the system can be stopped without imposing a burden on the system. The protection sequence realized by such software is effective when it is desired to stop the system over a certain period of time. The hardware protection sequence and the software protection sequence described above are preferably used in accordance with the content of the abnormality that has occurred on the system. For example, if an abnormality that could cause serious damage to the system is detected, the hardware protection sequence described above is executed to urgently stop the system, and normal operation is continued for a short time. If an abnormality that is considered to be satisfactory is detected, the above-described protection sequence by software is executed, and the system is gently stopped over a certain period. In the above embodiment, the control unit 70, 70a detects an abnormality based on the values of the output voltage v _o , the output current i _o , and the primary side current i _pn , and shifts to the forced stop mode when the abnormality is detected. However, it is also possible to shift to the forced stop mode by a user's manual operation.

<Output control method>
The battery charging mode of the EV quick charger includes a charging voltage control mode (cv mode) and a charging current control mode (cc mode). The EV quick charger needs to be able to switch between these two modes seamlessly. Therefore, if a controller for controlling the charging voltage and a controller for controlling the charging current are provided separately, it is necessary to stop the other controller when operating one controller, making seamless mode switching difficult. .

  In the variable output charging device 1 constituting the EV quick charger according to the present embodiment, switching of the charging mode is performed without stopping one of the controller for controlling the charging voltage and the controller for controlling the charging current at the time of mode switching. By making it possible, seamless mode switching is realized.

  FIG. 16 is a system configuration diagram of the AC / DC conversion circuit 1 constituting the EV quick charger according to the embodiment of the present invention. In the present system, control of the charging voltage control, charging current control and control mode is performed by the control unit 70 based on a control input from a host controller (not shown).

The controller 70 is provided with a target value v _o ^{* of a} charging voltage (output voltage) to be applied to the battery from a host controller (not shown). The subtractor 701 generates a difference value between the charging voltage target value v _o ^* and the actually measured value of the charging voltage (output voltage) v _o actually applied to the battery, and supplies this to the voltage adjustment unit 702. Voltage adjusting unit 702 outputs the target value i _o of the charging current according to the difference value so as to match the charging voltage v _o to the charging voltage target value v _o ^{* *.} The variable limiter 703 limits the charging current target value i _o ^* within an upper limit value that is appropriately set by a host controller (not shown). That is, when the charging current target value i _o ^* generated by the voltage adjustment unit 702 is smaller than the upper limit value set by the variable limiter 703, the generated target value i _o ^* passes through the variable limiter 703 as it is. . On the other hand, when the charging current target value i _o ^* generated by the voltage adjustment unit 702 is larger than the upper limit value set by the variable limiter 703, the charging current target value i _o ^* limited to the upper limit value is variable. Output from the limiter 703.

The charging current target value i _o ^* is supplied to the subtractor 704. The subtractor 704 generates a difference value between the charging current target value i _o ^* and the actually measured value of the charging current (output current) i _o actually supplied to the battery, and supplies this to the current adjustment unit 705. The current adjusting unit 705 generates a temporary target value v _ab ^* ′ of the output voltage of the rectifying unit 50 according to the difference value so as to make the charging current i _o coincide with the charging current target value i _o ^* . On the other hand, the correction value generation unit 800 multiplies the value of the current i _L flowing through the reactor L _DC constituting the DC filter 60 by a predetermined coefficient kp, and outputs this as the correction value m. The subtractor (correction unit) 706 subtracts the correction value m from the provisional target value v _ab ^* ′ to generate the output voltage target value v _ab ^* of the rectification unit 50.

The primary side conversion unit 707 multiplies the target value v _ab ^* by 1/2 to generate a target value | v _pn | ^* of the absolute value of the voltage across the transformer. The amplitude value generation unit 708 generates the amplitude command value α ^* indicating the amplitude value of the PWM command signal by dividing the target value | v _pn | ^* by 3V _m / 2√2 (see Expression (9)). . V _m is the effective value of the line voltage of the three-phase AC power source E. The upper limit value of the amplitude command value α ^* is limited to 1 by the limiter 709. This prevents so-called overmodulation in which the amplitude of the PWM command signal is larger than the amplitude of the carrier signal Car. Based on the phase angle ωt of the line voltage v _rs of the three-phase AC power source E and the amplitude command value α ^* , the waveform shaping unit 710 is a sinusoidal PWM command signal α represented by the above formulas (1) to (3). _rs ^* , α _st ^* , α _tr ^* are generated.

In this system, switching between the charging voltage control mode (cv mode) and the charging current control mode (cc mode) is realized by controlling the upper limit value set by the variable limiter 703. In other words, when the charging current target value i _o ^* generated by the voltage adjustment unit 702 is smaller than the upper limit value set by the variable limiter 703, the charging current target value i _o ^* remains as it is without any limitation. It passes through the variable limiter 703. In this case, since the control unit 70 generates the amplitude command value α ^* so that the charge voltage target value v _o ^* and the measured value of the charge voltage v _o coincide with each other, the present system operates in the charge voltage control mode (cv mode). ). In other words, by releasing the restriction by the variable limiter 703, the system operates in the charge voltage control mode (cv mode).

On the other hand, when the charging current target value i _o ^* generated by the voltage adjustment unit 702 is larger than the upper limit value set by the variable limiter 703, the charging current target value i _o ^* is limited to the upper limit value. . In this case, the voltage adjustment unit 702 can be regarded as no longer functioning. In this case, the control unit 70 generates the amplitude command value α ^* so that the charging current target value i _o ^* limited to the upper limit value by the variable limiter 703 matches the measured value of the charging current i _o. The system operates in the charge current control mode (cc mode). That is, by setting the upper limit value of the variable limiter 703 to the charging current target value i _o ^* , the system operates in the charging current control mode (cc mode).

Thus, in this system, the charge voltage control mode and the charge current control mode can be switched by controlling the upper limit value of the charge current target value i _o ^* with the variable limiter 703. Thus, there is no need to stop the voltage adjustment unit 702 or the current adjustment unit 705, and seamless mode switching can be realized.

In addition, the variable output charging apparatus 1 according to the present embodiment includes a DC filter 60 including a reactor L _DC and a capacitor C _DC between the rectifying unit 50 and the output terminal. For this reason, LC resonance occurs, and the charging voltage _vo and the charging voltage _io become unstable. Therefore, in this system, a correction value is generated by multiplying the value of the current i _L flowing through the reactor L _DC by kp, and the correction value is subtracted from the provisional target value v _ab ^* ′ of the output voltage of the rectifier 50 to obtain the target A value v _ab ^* is generated, and an amplitude command value α ^* is generated based on the corrected target value v _ab ^* . Thus, the same effect as the case where the resistance element in the reactor L _DC are connected in series can be obtained, it is possible to prevent the occurrence of the LC resonance.

Claims (3)

Variable output charging that converts the three-phase AC power supplied to the input end of the three-phase AC channel to DC power and charges the battery connected to the output terminal with a charging voltage or charging current of a magnitude according to the control input A device,
A high-frequency transformer,
A control unit that generates a modulation factor signal synchronized with a voltage change of a phase voltage of a three-phase AC power source that generates the three-phase AC power;
A carrier signal generator for generating a carrier signal having a frequency higher than the frequency of the three-phase AC power supply;
A PWM signal generation unit that compares the signal levels of the carrier signal and the modulation factor signal and generates a PWM signal including a pulse train generated at a timing and a period determined according to a comparison result;
In response to the PWM signal, the output end of the three-phase AC channel is selectively connected to both ends of the primary winding of the high-frequency transformer, and the frequency of the three-phase AC power source is connected to both ends of the primary winding. A frequency converter having a plurality of switches for applying a high-frequency AC pulse;
A rectifying unit that rectifies an AC component generated at both ends of the secondary winding of the high-frequency transformer to obtain the DC power, and
The control unit includes a voltage adjustment unit that generates a charging current target value according to a comparison result between an actual charging voltage value applied to the battery and a charging voltage target value, and a variable upper limit of a size according to the control input. A variable limiter that limits the charging current target value within a value, and an output voltage target of the rectifier unit according to a comparison result between the charging current target value that has passed through the variable limiter and an actual charging current value that is supplied to the battery A variable output charging comprising: a current adjusting unit that generates a value; and an amplitude value generating unit that generates an amplitude value of the modulation factor signal by multiplying a predetermined coefficient by an output voltage target value of the rectifying unit apparatus.   The control unit further includes a waveform shaping unit that generates a sine wave having an amplitude corresponding to the amplitude value and a phase corresponding to a phase angle of a line voltage of the three-phase AC power supply. apparatus.   A filter unit including a reactor connected between the rectifier unit and the output terminal; a correction value generating unit that generates a correction value by multiplying a value of a current flowing through the reactor by a predetermined coefficient; and the correction value. The variable output charging device according to claim 1, further comprising: a correction unit that corrects an output voltage target value of the rectification unit based on the correction value.

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