JP2013149845A - Semiconductor wafer, method for manufacturing semiconductor wafer, semiconductor light emitting element, and method of manufacturing semiconductor light emitting element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor wafer which suppresses variations in a thickness of a metal layer formed by an electroplating method between chips, and can improve a manufacturing yield of a semiconductor light emitting element.SOLUTION: A semiconductor wafer 10 has a number of chips 12 for a ridge type semiconductor light emitting element formed therein. The chip 12 has a semiconductor laminated structure formed on a substrate, two trench grooves 14 and 16 extending in a Y direction from the surface side of the semiconductor laminated structure, a ridge portion 18 formed between the two trench grooves 14 and 16, an electrode which is formed on the ridge portion 18 and is independent for each chip, and a metal layer formed on the electrode by electroplating. Each of the chips 12 are formed side by side with chips adjacent in an X direction, are formed so that the chips 12 and chips adjacent in the Y direction are shifted in the X direction, and the trench grooves of each of the chips 12 and the trench grooves of the chips adjacent to the chips in the Y direction are separated from each other.

Description

  The present invention relates to a semiconductor wafer on which a plurality of ridge-type semiconductor light emitting device chips are formed, a method for manufacturing the semiconductor wafer, a semiconductor light emitting device manufactured from the semiconductor wafer, and a method for manufacturing the semiconductor light emitting device. .

  Conventionally, as a ridge type semiconductor light emitting element, for example, a semiconductor laser element having a ridge waveguide extending in a predetermined direction is known. For example, Patent Document 1 describes a semiconductor element having two trench grooves and a striped ridge waveguide formed between the two trench grooves.

  Such a semiconductor laser device is formed as a chip on a semiconductor wafer in the same manner as a normal semiconductor device. First, a semiconductor wafer in which a large number of chips for a semiconductor laser element are arranged in a matrix on a circular substrate is manufactured, the semiconductor wafer is divided into chips, and then a semiconductor laser element is manufactured by performing end face processing. The FIG. 16 shows a schematic top view of such a semiconductor wafer 60. FIG. 17 shows a schematic diagram of the chip 62 formed on the semiconductor wafer 60. As shown in FIG. 16, a large number of chips 62 are arranged in a matrix on a semiconductor wafer 60. As shown in FIG. 17, each chip 62 has two trench grooves 64 and 66, a ridge waveguide 68 sandwiched between the trench grooves 64 and 66, and a groove outside the trench grooves 64 and 66. A support portion 70 that is not formed is provided.

  Such a conventional semiconductor wafer 60 for a semiconductor laser device is manufactured, for example, by the following process. First, an n-side semiconductor substrate, a lower clad layer, an active layer, an upper clad layer, and a contact layer are laminated in this order by epitaxial growth on a semiconductor substrate using a metal organic chemical vapor deposition (MOCVD) method or the like. Then, trench grooves 64 and 66 are formed by etching and removing predetermined portions on both sides of the stripe-shaped region (portion to become the ridge waveguide 68) of the semiconductor laminated structure. Further, by forming the trench grooves 64 and 66, a ridge waveguide 68 which is a striped convex portion sandwiched between the trench grooves 64 and 66 is formed, and further, a ridge is formed outside the trench grooves 64 and 66. A support portion 70 having a height substantially equal to that of the waveguide 68 is formed. Normally, the trench grooves 64 and 66, the ridge waveguide 68, and the support portion 70 are continuously formed across many chips in the Y direction in FIG. Next, a p-side electrode is formed on the contact layer of the ridge waveguide 68 by vapor deposition or the like. Further, a metal layer, for example, an Au plating layer is formed on the p-side electrode by using an electrolytic plating method. Such a metal layer is formed on the p-side electrode, for example, and functions as an electrode pad. Thereafter, an n-side electrode is formed on the back surface of the n-type semiconductor substrate.

  Next, the semiconductor wafer 60 is cleaved along a direction orthogonal to the direction in which the ridge waveguide 68 extends. That is, the semiconductor wafer 60 in which a large number of semiconductor laser device chips 62 are arranged in a matrix is divided into bars, and a structure in which the chips 62 are arranged in a horizontal row is generated. Thereafter, the bar-like structure is divided and divided into individual chips 62. Thereafter, a reflective film is formed on the end face of each chip 62 to form a semiconductor laser element.

  The inventor has also proposed an integrated semiconductor array element in which ridge waveguides as described in Patent Document 2 are arranged in an array as a ridge semiconductor light emitting element.

JP 2006-173275 A Japanese Patent Application No. 2010-214262

  The present inventor has analyzed the characteristics of the semiconductor light emitting device formed by the process as described above. As a result, in the semiconductor light emitting device formed by the process as described above, there is a problem that there is a large variation in electrical characteristics or thermal resistance between the light emitting devices, which may deteriorate the manufacturing yield of the light emitting device. I understood. The inventor has repeatedly studied the cause, and as a result, the variation in the thickness of the metal layer plated on each chip produced by dividing the semiconductor wafer is large. It was found that the variation in thermal characteristics was large.

  That is, in the manufacturing process of the semiconductor wafer, the metal layer is formed by electroplating after the ridge waveguide and the electrode are manufactured. The thickness of this metal layer may vary greatly depending on the location within the semiconductor wafer. In such a case, it has been found that the thickness of the metal layer varies greatly between the divided chips, and as a result, the electrical characteristics or thermal resistance of the light emitting element also varies greatly. In view of the above problems, the present invention suppresses a variation in the thickness of a metal layer between chips and improves the manufacturing yield of a semiconductor light emitting device, and the semiconductor wafer for a semiconductor light emitting device It is an object of the present invention to provide a method for manufacturing the semiconductor light emitting device, a semiconductor light emitting device manufactured from the semiconductor wafer, and a method for manufacturing the semiconductor light emitting device.

According to one aspect of the present invention, there is provided a semiconductor wafer on which a plurality of ridge-type semiconductor light emitting device chips are formed, the semiconductor stacked structure in which the chips are formed on a substrate, and the semiconductor At least two trench grooves formed so as to extend in the first direction on the surface from the surface side of the laminated structure, a ridge portion formed between the trench grooves, and on the ridge portion An electrode formed and separated in at least a second direction perpendicular to the first direction, and a metal layer formed by electroplating on the electrode;
Each chip is formed side by side with the chip adjacent to the chip in the second direction, and is formed to be shifted in the second direction from the chip adjacent to the chip in the first direction. A semiconductor wafer is provided in which a trench groove of a chip and a trench groove of a chip adjacent to the chip in the first direction are separated.
Here, the “trench groove” is a groove that reaches from the surface side of the semiconductor multilayer structure to the depth of at least two layers of the multilayer structure, and the shape thereof may be any shape. For example, a quadrangular shape, a triangular shape, or an elliptical shape may be used.
In addition, “an electrode separated in at least a second direction perpendicular to the first direction” means an electrode separated from an electrode adjacent in at least the second direction. It also includes electrodes that are separated from adjacent electrodes in the second direction, that is, electrodes that are electrically independent for each chip.

If the semiconductor light emitting element is a laser array element having at least three trench grooves and two ridges, the width of each chip in the second direction is Sa and the width of each chip in the first direction is When the width of the element region provided with the trench groove and the ridge portion is the element region width S1 and S2 at both ends,
The deviation width Ta between each chip and the chip adjacent to the chip in the first direction is:
S1 / 2 + S2 / 2 <Ta ≦ Sa / 2
The semiconductor wafer according to claim 1, wherein:
Note that the shift width between each chip and the chip adjacent to the chip in the first direction includes a shift width in the second positive direction and a shift width in the negative direction. The smaller one of the deviation width and the deviation width in the negative direction is referred to as “deviation width Ta”.

If the semiconductor light emitting device is a single stripe laser device having two trench grooves and one ridge portion, the width in the second direction of each chip is St and the width in the second direction of the trench grooves. Where Sd is the deviation width Ts between each chip and the chip adjacent to the chip in the first direction,
Sd <Ts ≦ St / 2
It may be.
Note that the shift width between each chip and the chip adjacent to the chip in the first direction includes a shift width in the second positive direction and a shift width in the negative direction. The smaller one of the deviation width and the deviation width in the negative direction is defined as “deviation width Ts”.

In the single stripe laser element, when the width of the ridge portion in the second direction is Sr, the deviation width Ts is:
Ts ≦ Sr / 2 + Sd / 2
It may be.

  Each of the chips is preferably formed in the same direction in the first direction.

  According to another aspect of the present invention, there is provided a semiconductor light emitting device that is divided into chips from the semiconductor wafer and that is subjected to end face processing on the end face in the first direction of the chip.

  According to still another aspect of the present invention, there is provided a semiconductor wafer manufacturing method in which a plurality of ridge-type semiconductor light emitting device chips are formed, the semiconductor multilayer structure formed on a substrate, At least two trench grooves formed so as to extend in the first direction on the surface from the surface side of the semiconductor multilayer structure; a ridge portion formed between the trench grooves; and And forming a chip having an electrode separated in at least a second direction perpendicular to the first direction and a metal layer formed by electroplating on the electrode, In the step of forming the chip, each chip is formed side by side with the chip adjacent to the chip in the second direction perpendicular to the first direction, and the chip adjacent to the chip in the first direction; Is Provided is a method for manufacturing a semiconductor wafer formed so as to be shifted in the second direction so that the trench groove of each chip is separated from the trench groove of a chip adjacent to the chip in the first direction. The

  According to still another aspect of the present invention, there is provided a semiconductor light emitting device comprising: a step of dividing the semiconductor wafer manufactured by the above method into chips; and a step of manufacturing a semiconductor light emitting device by subjecting the chip to an end face treatment. A manufacturing method is provided.

  In the process of manufacturing a semiconductor wafer on which a chip for a ridge-type semiconductor light-emitting element is formed, the inventor forms a metal layer by electroplating after forming a ridge waveguide and an electrode. The cause of the large difference in location within the semiconductor wafer was investigated. As a result, on the semiconductor wafer, each chip is electrically connected in the first direction (Y direction), but is electrically insulated in the second direction (X direction). It was elucidated that one of the causes was a large variation in the resistance distribution.

  When performing electroplating, for example, a ring-shaped plating electrode provided on the outer peripheral portion of the semiconductor wafer and connected to the contact layer is grounded, so that the wafer side serves as a cathode and the plating solution side serves as a direct current. Shed. The thickness of the metal layer formed during electroplating is proportional to the cathode current density (A / m 2). For this reason, if there is a large variation in the resistance distribution within the semiconductor wafer, a large variation will also occur in the cathode current density, and a large variation will also occur in the thickness of the metal layer.

  The inventor has repeatedly studied the resistance distribution of a semiconductor wafer in which chips for a ridge-type semiconductor light-emitting element are formed in a grid pattern as in the prior art. As a result, the region from which the contact layer has been removed to form a trench groove or the like extends in the first direction (Y direction) across a large number of chips, so that light is emitted between the trench grooves. The element region where the element is formed and the support region provided outside the trench groove extend in the first direction (Y direction) across a large number of chips, and this first direction ( The element region extending in the Y direction) and the support region extending in the first direction (Y direction) are electrically insulated by the region from which the contact layer has been removed (drain groove). It was clarified that this is one of the causes of the large variation in resistance distribution in the wafer. In such a semiconductor wafer, when the electrodes are also electrically separated from the adjacent electrodes in the second direction perpendicular to the first direction, that is, each chip is electrically insulated in the X direction. In this case, when performing electroplating, the resistance distribution in the wafer surface varies greatly, the potential difference between chips increases, and the cathode current density (A / m2) also varies greatly. As a result, the thickness of the metal layer formed varies greatly.

  According to one aspect of the present invention, in a semiconductor wafer on which a plurality of ridge-type semiconductor light emitting device chips are formed, the chip has a semiconductor multilayer structure formed on a substrate, and the semiconductor multilayer structure. At least two trench grooves formed so as to extend in the first direction on the surface from the surface side, a ridge portion formed between the trench grooves, and formed on the ridge portion, Each chip has an independent electrode and a metal layer formed by electroplating on the electrode, and each chip is adjacent to the chip in a second direction perpendicular to the first direction. And the chip adjacent to the chip in the first direction is shifted in the second direction, and the trench groove of each chip and the chip in the first direction. And adjacent Since each chip formed on the semiconductor wafer is electrically connected in the second direction since the trench groove of the chip to be separated is separated, the resistance distribution in the semiconductor wafer when performing electroplating Variation is suppressed, and the potential difference is also reduced. If the potential difference in the wafer plane is reduced, variations in the cathode current density (A / m 2) are suppressed, and variations in the thickness of the formed metal layer are also suppressed.

  For this reason, variation in the thickness of the metal layer is suppressed even between the divided chips, and as a result, variation in electrical characteristics or thermal resistance between light emitting elements manufactured by dividing from one semiconductor wafer is also suppressed. The For this reason, the manufacturing yield of the semiconductor light emitting device is also improved.

1 is a schematic plan view of a semiconductor wafer according to a first preferred embodiment of the present invention. It is a schematic plan view of the chip | tip formed in the semiconductor wafer of 1st Embodiment. It is the elements on larger scale of the semiconductor wafer of a 1st embodiment. It is a schematic sectional drawing of the chip | tip formed in the semiconductor wafer of 1st Embodiment. It is a schematic sectional drawing for demonstrating the manufacturing method of the semiconductor wafer of 1st Embodiment. FIG. 6 is a schematic plan view of a semiconductor wafer according to a second preferred embodiment of the present invention. It is a schematic plan view of the chip | tip formed in the semiconductor wafer of 2nd Embodiment. It is the elements on larger scale of the semiconductor wafer of 2nd Embodiment. It is an AA line schematic longitudinal cross-sectional view of FIG. It is a BB line schematic longitudinal cross-sectional view of FIG. FIG. 8 is a schematic longitudinal sectional view taken along line CC of FIG. 7. It is a schematic sectional drawing for demonstrating the manufacturing method of the semiconductor wafer of 2nd Embodiment. It is a schematic sectional drawing for demonstrating the manufacturing method of the semiconductor wafer of 2nd Embodiment. It is a schematic sectional drawing for demonstrating the manufacturing method of the semiconductor wafer of 2nd Embodiment. It is a figure which shows the relationship between the distance between the chip | tip and a plating electrode in the 2nd Embodiment of this invention, the resistance between a chip | tip and a plating electrode, and the thickness of Au plating layer. It is a schematic plan view of the semiconductor wafer of the conventional form. It is the elements on larger scale of the semiconductor wafer of the conventional form.

  Hereinafter, embodiments of a semiconductor wafer for a semiconductor light emitting device and a method for manufacturing the same according to the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding components are denoted by the same reference numerals. Each drawing is schematic, and the dimensions and the like are different from the actual ones.

  First, a semiconductor wafer for a semiconductor light emitting device and a method for manufacturing the same according to a first embodiment of the present invention will be described. FIG. 1 is a schematic plan view of a semiconductor wafer 10 according to the first embodiment of the present invention. FIG. 2 is a schematic plan view of the chip 12 formed on the semiconductor wafer 10. FIG. 3 is a schematic plan view in which a part of the semiconductor wafer 10 shown in FIG. 1 is enlarged.

As shown in FIG. 1, a semiconductor wafer 10 is a semiconductor wafer for a single stripe laser element, and a large number of chips 12 are formed on the semiconductor wafer 10. As shown in FIG. 2, each chip 12 includes two trench grooves 14 and 16 extending in the Y direction in FIG. 2, a ridge waveguide 18 sandwiched between the trench grooves 14 and 16, and a trench groove. Support portions 20 and 22 formed outside 14 and 16 are provided. The width of the trench groove 14 and the width of the trench groove 16 are substantially equal.
As shown in FIG. 3, the chips 12 are formed side by side in the X direction perpendicular to the Y direction. Each chip is formed so as to be shifted from the adjacent chip in the Y direction by a shift width Ts in the X direction. When the width of the trench groove 16 in the X direction is Sd and the width of the ridge waveguide 18 in the X direction is Sr, the deviation width Ts can be expressed by the following equation.
Ts = Sd / 2 + Sr / 2

  That is, in FIG. 3, each chip 12 formed in the third row from the bottom shifts by Ts in the X direction (right direction) in FIG. 3 with respect to each chip 12 formed in the two cross sections from the bottom. Is formed. Further, the chips 12 formed in the fourth stage from the bottom are formed by shifting Ts in the −X direction (left direction) in FIG. 3 with respect to the chips 12 formed in the third stage from the bottom. Has been. In this way, all the chips are formed so as to be shifted in the X direction from the adjacent chips in the Y direction by a shift width Ts. For this reason, the trench grooves 14 and 16 of each chip 12 are separated from the trench grooves 14 and 16 of the chip adjacent to this chip in the Y direction.

  FIG. 4 is a cross-sectional view of the chip 12. As shown in FIG. 4, the chip 12 includes an n-InP substrate 110, an n-InP clad layer 112 on the n-InP substrate 110, and a SCH-MQW (Separate Confinement Heterostructure Multiple on the n-InP clad layer 112. Quantum Well) active layer 114, first P-InP cladding layer 116 on SCH-MQW active layer 114, layer 119 containing p-AlInAs on first P-InP cladding layer 116, and p-AlInAs A second P-InP clad layer 122 on the layer 119 containing p-GaInAs and a p-GaInAs contact layer 124 on the second P-InP clad layer 122. For the SCH-MQW active layer 114, for example, a GaInAsP well layer or an AlGaInAs well layer is used when the laser oscillation wavelength is in the 1.25 to 1.6 μm band.

  Trench grooves 14 and 16 are provided on the upper surface 101 side of the chip 12. The trench grooves 14 and 16 are provided deeper than the layer 119 containing p-AlInAs and reach the first P-InP cladding layer 116.

  A striped ridge waveguide 18 is formed between the trench groove 14 and the trench groove 16, and support portions 20 and 22 are formed outside the trench groove 14 and the trench groove 16. The trench grooves 14 and 16 and the ridge waveguide 18 extend in a direction perpendicular to the plane of FIG. The ridge waveguide 18 and the support portions 20 and 22 include an upper portion of the first P-InP clad layer 116, a layer 119 containing p-AlInAs, a second P-InP clad layer 122, and a p-GaInAs contact layer. 124.

  The layer 119 containing p-AlInAs includes a p-AlInAs layer 118 and an oxide insulator layer 120 obtained by oxidizing AlInAs.

  Since a striped ridge waveguide 18 is formed between the trench groove 14 and the groove 16, the inner side surface of the trench groove 14 and the inner side surface of the trench groove 16 are on both sides of the ridge waveguide 18. The end portions of the oxide insulator layer 120 are exposed on the side surfaces on both sides of the ridge waveguide 18, and the oxide insulator layer 120 includes p-AlInAs from the side surfaces on both sides toward the inside of the ridge waveguide 18. Extending into layer 119 is provided. In the central region of the ridge waveguide 18 of the layer 19 containing p-AlInAs, a p-AlInAs layer 118 is provided between the oxide insulator layers 120 on both sides.

  A SiNx film 126 is provided on the p-GaInAs contact layer 124, on the side and bottom surfaces of the trench groove 14, on the side and bottom surfaces of the trench groove 16, and on the support portions 20 and 22. The SiNx film 126 functions as a passivation film.

  A window 26 is provided in the center of the SiNx film 126 on the ridge waveguide 18 along the Y direction. The window 26 exposes the p-GaInAs contact layer 124 of the ridge waveguide 18.

  A p-side electrode 128 is provided on the SiNx film 126 of the ridge waveguide 18. The p-side electrode 128 is connected to the p-GaInAs contact layer 124 of the ridge waveguide 18 through the window 26. An Au plating layer 129 that functions as an electrode pad is provided on the p-side electrode 128. An n-side electrode 130 is provided on the bottom surface 102 side of the substrate 110.

  In the layer 119 containing p-AlInAs in the ridge waveguide 18, the central p-AlInAs layer 118 is provided between the oxide insulator layers 120 on both sides. Therefore, the oxide insulator layers 120 on both sides function as a current confinement structure that constricts the current flowing in the vertical direction between the p-side electrode 128 provided on the window 26 and the n-side electrode 130 on the bottom surface. The end face of the chip intersecting with the Y direction becomes the laser light oscillation face. After being manufactured as a laser element, laser light is emitted from the SCH-MQW active layer 114 exposed at the end face.

  Next, with reference to FIG. 5, the manufacturing method of the semiconductor wafer 10 of 1st Embodiment is demonstrated. First, as shown in FIG. 5A, an n-InP clad layer 112 is formed on an n-InP substrate 110 and an SCH-MQW active layer 114 is formed on the n-InP clad layer 112 by MOCVD. Then, the first P-InP cladding layer 116 is formed on the SCH-MQW active layer 114, the p-AlInAs layer 117 is formed on the first P-InP cladding layer 116, and the p-AlInAs layer 117 is formed. A second P-InP cladding layer 122 is formed, and a p-GaInAs contact layer 124 is formed on the second P-InP cladding layer 122.

  After that, as shown in FIG. 5B, a mask 140 made of SiO 2 is selectively formed, and using the mask 140 as an etching mask, the p-GaInAs contact layer 124, the second P-InP cladding layer 122, p- The AlInAs layer 117 is removed by etching, and the first P-InP cladding layer 116 is removed by etching halfway to form a plurality of pairs of trench grooves 14 and grooves 16 in the Y direction and the X direction, respectively. The trench grooves 14 and 16 have the crystal orientation of the semiconductor cleavage plane. The cleaved end face is formed to be a (100), (110) or (111) face. That is, the X direction is a (100), (110) or (111) direction, and the Y direction is a direction orthogonal to the X direction.

  3, the position of the trench grooves 14 and 16 formed in the third step from the bottom in FIG. 3 is different from the trench grooves 14 and 16 formed in the second step from the bottom in FIG. It is formed to be shifted in the direction (right direction) by a shift width Ts = Sd / 2 + Sr / 2 (Sd is the width of the drain groove and Sr is the width of the ridge waveguide 18). Similarly, in the mask 140, the position of the trench grooves 14 and 16 formed in the fourth step from the bottom is different from the trench grooves 14 and 16 formed in the third step from the bottom in FIG. It is formed so as to be shifted by the width Ts in the X direction (left direction).

That is, the mask 140 is formed such that the trench groove of each chip 12 is shifted in the X direction from the trench groove of the adjacent chip in the Y direction. Therefore, the etched trench grooves 14 and 16 of the respective chips 12 are not connected in a straight line with the trench grooves 14 and 16 of the chips adjacent to this chip in the Y direction. Are individually separated grooves.
As described above, for example, in FIG. 3, the contact layer of the chip formed in the second stage from the bottom is connected to the contact layer of the two chips formed in the bottom stage, and the third stage from the bottom. It is also connected to the contact layers of the two chips formed on the substrate. For this reason, each chip 12 is electrically connected to the four chips 12 adjacent in the vertical direction in FIG. 3 in the Y direction. Each chip 12 is electrically connected to the chip 12 adjacent in the X direction via the chip 12 adjacent in the Y direction. That is, each chip is electrically connected to an adjacent chip both in the Y direction and in the X direction.

  Further, by etching each pair of trench grooves 14 and 16, a striped ridge waveguide 18 extending in the Y direction is formed between the trench grooves 14 and 16. The trench grooves 14 and 16 are provided so as to extend along the Y direction. The striped ridge waveguide 18 includes an upper portion of the first P-InP cladding layer 116, a p-AlInAs layer 117, a second P-InP cladding layer 122, and a p-GaInAs contact layer 124. Yes.

  The first P-InP cladding layer 116, the p-AlInAs layer 117, the second P-InP cladding layer 122, and the p-GaInAs contact layer 124 are exposed at the sides of the trench grooves 14 and 16. ing.

  Next, as shown in FIG. 5C, the mask 140 is removed. Thereafter, oxidation is performed at about 450 ° C. in water vapor by an oxidation apparatus (not shown) that oxidizes using water vapor, so that the p-AlInAs layer 117 exposed on the sides of the trench grooves 14 and 16 is removed from the trench groove. The p-AlInAs layer 117 is oxidized from the side portions 14 and 16 to form a p-AlInAs-containing layer 119 including the p-AlInAs layer 18 and an oxide insulator layer 120 obtained by oxidizing AlInAs.

  Since the striped ridge waveguide 18 is formed between the trench groove 14 and the groove 16, the end portions of the oxide insulator layer 120 are exposed on the side surfaces on both sides of the ridge waveguide 18, and the oxide insulation The material layer 120 extends in the layer 19 containing p-AlInAs from the side surfaces on both sides of the ridge waveguide 18 toward the inside of the ridge waveguide 18, and the center of the ridge waveguide 18 of the layer 119 containing p-AlInAs. In this region, the p-AlInAs layer 118 is left sandwiched between the oxide insulator layers 120 on both sides.

  After the oxidation treatment at about 450 ° C. in water vapor, the temperature of the substrate 110 is lowered to stop the oxidation, but the temperature is not lower than 100 ° C., and the substrate 110 is kept at a temperature of 100 ° C. or higher, for example, 250 ° C. In this state, it is unloaded from an oxidation apparatus (not shown) and then loaded into a plasma CVD apparatus (not shown). Alternatively, a load lock chamber (not shown) is connected between an oxidizer (not shown) and a plasma CVD device (not shown), and the substrate 110 is oxidized in a nitrogen atmosphere or a vacuum atmosphere ( It is transferred from a not-shown plasma plasma apparatus (not shown) via a load lock chamber (not shown). In this case, the substrate 110 may be transported at a temperature lower than 100 ° C.

  Next, as shown in FIG. 5D, a plasma CVD apparatus (not shown) is used and a trench CVD 14 is formed on the p-GaInAs contact layer 124 by plasma CVD using monosilane gas and nitrogen gas. A SiNx film 126 is formed on the side and bottom surfaces of the trench groove 16, on the side and bottom surfaces of the trench groove 16, and on the support portions 20 and 22. The SiNx film 126 functions as a passivation film.

  Next, a window 26 is formed along the Y direction at the center of the SiNx film 126 on the ridge waveguide 18. The p-GaInAs contact layer 124 of the ridge waveguide 18 is exposed through the window 26. Next, the bottom surface 102 of the n-InP substrate 110 is polished so that the n-InP substrate 110 has a predetermined thickness.

Thereafter, the p-side electrode 128 is provided on the ridge waveguide 18. The p-side electrode 128 is connected to the p-GaInAs contact layer 124 of the ridge waveguide 18 through the window 26.
Further, a thick Au plating layer 129 that functions as an electrode pad is formed on the p-side electrode 128 by electrolytic plating. First, the semiconductor wafer 10 is immersed in a plating solution, a disc electrode is disposed as a positive plating electrode in the upper solution of the semiconductor wafer 10, and a ring electrode is brought into contact with the outer peripheral portion of the semiconductor wafer as a negative plating electrode. In this state, a direct current is passed and electrolytic plating is performed to deposit an Au film.
After the formation of the Au plating layer 129, the n-side electrode 130 is formed on the bottom surface 102 side of the substrate 110.

  Next, the semiconductor wafer 10 is cleaved along a direction orthogonal to the direction in which the ridge waveguide 18 extends. First, the semiconductor wafer 10 is divided into bars in the X direction, and a structure in which chips 12 are arranged in a horizontal row is generated. Thereafter, the bar-like structure is divided into individual chips 12. Thereafter, a reflective film is formed on the end face of each chip 12 to form a semiconductor laser element.

As described above, since the trench grooves 14 and 16 of each chip 12 are separated from the trench grooves 14 and 16 of other chips, the contact layer of each chip is adjacent to the Y direction at one end in the Y direction. Are connected to the contact layers of two chips adjacent to each other in the Y direction at the other end, so that each chip is also adjacent in the X direction via the adjacent chips in the Y direction. Is electrically connected to the chip. For this reason, when forming the Au plating layer 129 by electroplating, the resistance distribution variation is reduced and the potential difference between the chips is reduced as compared with the conventional semiconductor wafer in which each chip is electrically insulated in the X direction. As a result, the variation in cathode current density is also reduced. When the Au plating layer 129 is formed by electrolytic plating, the film thickness of the Au plating layer to be formed is proportional to the cathode current density (A / m ² ), so that variation in the film thickness of the Au plating layer 129 is also reduced. Is done.

  In addition, variation in the thickness of the Au plating layer 129 is also suppressed between the divided chips 12. As a result, variation in electrical characteristics or thermal resistance between light emitting elements manufactured by dividing from one semiconductor wafer is also suppressed. For this reason, the manufacturing yield of the semiconductor light emitting device is also improved.

In the first embodiment, each chip 12 is different from the adjacent chip in the Y direction by a deviation width Ts (Ts = Sd / 2 + Sr / 2, the width of the trench groove 14 in the X direction is Sd, The width of the waveguide 18 in the X direction is defined as Sr), but is alternately shifted in the X direction and the −X direction. However, the present invention is not limited to this.
For example, instead of being alternately arranged, the chips 12 may be sequentially shifted by the shift width Ts only in the X direction.
Further, assuming that the width of each chip 12 in the X direction is St, the deviation width Ts only needs to satisfy the following expression.
Sd <Ts ≦ St / 2

(Embodiment 2)
Ridge Waveguide Next, a semiconductor wafer for a semiconductor light emitting device and a method for manufacturing the same according to Embodiment 2 of the present invention will be described. FIG. 6 is a schematic plan view of the semiconductor wafer 40 according to the second embodiment. FIG. 7 is a schematic plan view of an integrated semiconductor laser element chip 42 which is a laser array element provided on the semiconductor wafer 40 shown in FIG. FIG. 8 is a schematic plan view in which a part of the semiconductor wafer 40 shown in FIG. 5 is enlarged.

  As shown in FIG. 6, the semiconductor wafer 40 is a semiconductor wafer for an integrated semiconductor laser element, and a large number of chips 42 are formed on the semiconductor wafer 40.

  As shown in FIG. 7, this integrated semiconductor laser element chip 42 includes a DFB laser array 51 and a multi-mode interference (MMI) type optical combiner 52 connected to the DFB laser array 51. The semiconductor optical amplifier 53 connected to the optical combiner 52 and the semiconductor optical modulator 54 connected to the semiconductor optical amplifier are monolithically integrated on the substrate. The DFB laser array 51 is configured by alternately arranging DFB lasers 51a-1 to 51a-6 and support mesas 51b-1 to 51b-5 having different laser oscillation wavelengths at wavelengths of 1530 nm to 1630 nm. is there. The DFB lasers 51a-1 to 51a-6, the support mesas 51b-1 to 51b-5, the optical combiner 52, the semiconductor optical amplifier 53, and the semiconductor optical modulator 54 are configured by ridge type optical waveguides. Next to each ridge type optical waveguide, trench grooves 55, 56, 58 and 59 for forming the ridge type optical waveguide are provided. A support portion 57 is provided outside the trench grooves 55, 58 and 59.

As shown in FIG. 8, the chips 42 are formed side by side in the X direction. Each chip is formed so as to be shifted from the adjacent chip in the Y direction perpendicular to the X direction by a shift width Ta in the X direction. When the width of each chip 42 in the X direction is Sa, the deviation width Ta can be expressed by the following equation.
Ta = Sa / 2

  The chip 42 formed on the semiconductor wafer 40 is divided and subjected to end face processing to become an integrated semiconductor laser element. This integrated semiconductor laser device operates as follows. First, any one selected from the DFB lasers 51a-1 to 51a-6 is injected with a current and outputs a laser beam. The laser beam output from the optical combiner 52 is input to the semiconductor optical amplifier 53. The semiconductor optical amplifier 53 amplifies the input laser beam. The laser light amplified by the semiconductor optical modulator 54 is modulated and output as laser signal light. The integrated semiconductor laser element functions as a wavelength tunable optical transmitter by changing the selected DFB lasers 51a-1 to 51a-6.

  FIG. 9 is a cross-sectional view taken along line AA of the chip 42 shown in FIG. 7 and shows a cross-sectional structure of the DFB laser array 51. As shown in FIG. 9, the DFB laser array 51 has an n-type InP in which an n-side electrode 201 is formed on the back surface, and a lower cladding layer made of n-type InP that also serves as a buffer layer is formed on the surface. An active core layer 203, an upper cladding layer 204 made of p-type InP, an etch stop layer 205 made of 1.15Q GaInAsP, a p-type InP layer and a 1.25Q GaInAsP layer on a substrate 202 made of The semiconductor layer structure is formed by laminating a grating layer 206 in which the periodic structure is formed in the length direction, an upper cladding layer 207 made of p-type InP, and a contact layer 208 made of p-type InGaAsP. . Here, 1.15Q means a composition having a band gap wavelength of 1.15 μm. Further, the period of the periodic structure of the grating layer 206 is different from each other in each of the DFB lasers 51a-1 to 51a-6. As a result, the DFB lasers 51 a-1 to 51 a-6 can output laser beams having different wavelengths determined by the period of the grating layer 206.

  In the region between the DFB lasers 51a-1 to 51a-6 and the support mesas 51b-1 to 51b-5, a trench groove 56 is formed to a depth from the contact layer 208 to the surface of the etch stop layer 205. ing. The trench groove 56 separates the DFB lasers 51a-1 to 51a-6 and the support mesas 51b-1 to 51b-5 and forms a ridge shape thereof. A trench groove located on the outermost side in the width direction of the DFB laser array 51 is referred to as an outermost trench groove 55, and a trench groove located inside the outermost trench groove 55 is referred to as an inner trench groove 56. The outer side of the outermost trench groove 55 is a support portion 57 having no groove structure. The width of the outermost trench groove 55 is wider than the width of the inner trench groove 56.

  The surface of the semiconductor multilayer structure including the inner walls of the trench grooves 55 and 56 is covered with a protective film 209 made of SiN. The trench grooves 55 and 56 are filled with polyimide 210 which is an organic insulating material. In the upper part of the DFB lasers 51 a-1 to 51 a-6, the protective film 209 is removed to expose the contact layer 208, and the p-side electrode 211 is formed so as to contact the contact layer 208 there. The p-side electrode 211 extends until it reaches the surface of the polyimide 210. Further, an electrode pad 212 and an Au plating layer 213 are sequentially stacked on the p-side electrode 211. The electrode pad 212 and the Au plating layer 213 extend through the surface of the polyimide 110 to reach the upper portions of the adjacent support mesas 51b-1 to 51b-5, and the polyimide 210 and the support mesas 51b-1 to 51b- 5 is held.

  FIG. 10 is a cross-sectional view of the main part of the chip 42 shown in FIG. As shown in FIG. 10, the semiconductor optical amplifier 3 includes an active core layer 203, an upper cladding layer 204, an etch stop layer on a substrate 202 on which an n-side electrode 201 is formed on the back surface and a lower cladding layer is formed on the surface. 205 has a semiconductor laminated structure in which an upper cladding layer 207 and a contact layer 208 are laminated. In addition, trench grooves 58 are formed on both sides of the semiconductor optical amplifier 53 at a depth from the contact layer 208 to the surface of the etch stop layer 205. The trench groove 58 forms a ridge shape of the semiconductor optical amplifier 53.

  The surface of the semiconductor stacked structure including the inner wall of the trench groove 58 is covered with a protective film 209. The trench groove 58 is filled with polyimide 210. In the upper part of the semiconductor optical amplifier 53, the protective film 209 is removed to expose the contact layer 208, and a p-side electrode 211 is formed so as to be in contact with the contact layer 208 there. The p-side electrode 211 extends until it reaches the surface of the polyimide 210. Further, an electrode pad 212 and an Au plating layer 213 are sequentially stacked on the p-side electrode 211. The electrode pad 212 and the Au plating layer 213 are extended through the surface of the polyimide 210 to reach the upper part of the adjacent support part 57, and are held by the polyimide 210 and the support part 57.

  FIG. 11 is a cross-sectional view of the main portion of the chip 42 shown in FIG. 7 taken along the line CC, and shows a cross-sectional structure of the optical combiner 52. As shown in FIG. 11, the optical combiner 52 has a lower clad layer 214 made of non-doped InP and a passive core layer 215 made of 1.35Q GaInAsP on a substrate 202 having an n-side electrode 201 formed on the back surface. The upper cladding layer 216 made of non-doped InP, the etch stop layer 205, and the upper cladding layer 207 are stacked. In addition, trench grooves 59 are formed on both sides of the optical combiner 52 to a depth from the upper cladding layer 207 to the surface of the etch stop layer 205. The trench groove 59 forms the ridge shape of the optical combiner 52. A support portion 57 in which an upper cladding layer 207 and a contact layer 208 are stacked is formed on the etch stop layer 205 outside the trench groove 59. Further, the surface of the semiconductor stacked structure including the inner wall of the trench groove 59 is covered with a protective film 209. The trench groove 59 is filled with polyimide 210. The semiconductor optical modulator 54 has the same cross-sectional structure as the semiconductor optical amplifier 53.

(Production method)
Next, a method for manufacturing the chip 42 for the integrated semiconductor laser device will be described with reference to FIGS.

First, using a MOCVD (Metal Organic Chemical Vapor Deposition) crystal growth apparatus, a buffer layer is grown on the substrate 202 at a growth temperature of 600 degrees, and further, an active core layer 203, an upper clad layer 204, an etch stop layer 205, GaInAsP Layer 2
20 and a cap protective layer 221 made of p-type InP are sequentially grown (see FIG. 12A).

As an example of the characteristics of each semiconductor layer, the active core layer 203 is made of InGaAsP, and a three-stage separate confinement heterostructure (SCH) is formed above and below a multi quantum well (MQW) structure. It has a formed MQW-SCH structure. The MQW has, for example, a so-called 6QW structure in which six well layers with a thickness of 6 nm and barrier layers with a thickness of 10 nm are alternately stacked. Further, the thicknesses of the upper cladding layer 204, the etch stop layer 205, the GaInAsP layer 220, and the cap protection layer 221 are 30 nm, 10 nm, 20 nm, and 10 nm, respectively.

Next, in a region where the DFB lasers 51a-1 to 51a-6 are to be formed, diffraction with a period of about 240 nm is performed by ICP (Inductive Coupling Plasma) -RIE (Reactive Ion Etcher) to a depth reaching the bottom surface of the GaInAsP layer 220. Etching is performed in a lattice pattern (see FIG. 12B). The period is made different depending on each region in which the DFB lasers 51a-1 to 51a-6 are formed.
In addition, as shown in FIG. 8, each chip | tip 42 is formed along with the X direction. Each chip is formed so as to be shifted from the adjacent chip in the Y direction perpendicular to the X direction by a shift width Ta (Ta = Sa / 2, Sa is the width of the chip 42 in the X direction) in the X direction. Yes.

That is, when ICP-RIE is used to etch a diffraction grating having a period of about 240 nm to a depth reaching the bottom surface of the GaInAsP layer 220, each chip 42 is displaced in the X direction from the adjacent chip in the Y direction. It is formed so as to be shifted by Ta. Therefore, the etched trench grooves 55 and 56 of each chip are not connected to the trench groove 58 of the chip adjacent to this chip in the Y direction, and each trench groove is an individually separated groove.
As described above, for example, in FIG. 8, the contact layer of the chip 42 formed in the second stage from the bottom is connected to the contact layers of the two chips formed in the bottom stage, and 3 from the bottom. It is also connected to the contact layer of the two chips 42 formed at the stage. Therefore, each chip 42 is electrically connected to the four chips 42 adjacent in the vertical direction in FIG. 8 in the Y direction. Each chip 42 is electrically connected to the chip 42 adjacent in the X direction via the chip 42 adjacent in the Y direction. That is, each chip is electrically connected to an adjacent chip in the X direction in addition to the Y direction.

  Next, an active region for forming the DFB lasers 51a-1 to 51a-6, the semiconductor optical amplifier 53, and the semiconductor optical modulator 54 is covered with a protective mask M1 made of SiN, and a region other than the active region (hereinafter referred to as a passive region). Is etched to a depth reaching the bottom surface of the active core layer 203 by ICP-RIE and wet etching with sulfuric acid to remove the active core layer 203 (see FIG. 12C).

  Next, a semiconductor stacked structure for forming the optical combiner 52 is formed in the passive region. Specifically, the lower cladding layer 214, the passive core layer 215, the upper cladding layer 216, and the etch stop layer 205 are sequentially regrown by butt joint growth (see FIG. 12D). Note that the passive core layer 215 has a thickness of, for example, 300 nm, and is connected to the active core layer 203 with the center in the thickness direction aligned.

  Next, after removing the protective mask M1, an upper cladding layer 207 and a contact layer 208 are sequentially grown on the entire surface. As a result, a slab optical waveguide for forming a ridge optical waveguide constituting the DFB laser array 51, the optical combiner 52, the semiconductor optical amplifier 53, and the semiconductor optical modulator 54 is formed. Thereafter, the contact layer 208 on the optical combiner 52 is removed (see FIGS. 12E and 12F). The contact layer 208 in the support region 57 is not removed.

  Next, a description will be given with reference to FIG. 13 corresponding to the cross section taken along the line AA of FIG. First, a protective mask M2 for forming a trench is formed, and dry etching is performed by ICP-RIE (see FIG. 13A). At this time, the etch stop layer 205 is not etched. Next, the surface of the etch stop layer 205 is isotropically etched with an etchant of hydrochloric acid: phosphoric acid = 1: 3, and then the protective mask M2 is removed with buffered hydrofluoric acid (see FIG. 13B). . As a result, trench grooves 45 to be the trench grooves 55, 56, 58, 59 are formed in the subsequent process, and the ridge-type optical waveguide for forming the DFB laser array 51 in the subsequent process, and the optical combiner 52, A ridge-type optical waveguide 46 that is a ridge-type optical waveguide for forming the semiconductor optical amplifier 53 and the semiconductor optical modulator 54 is formed. Thereafter, a protective film 209 is formed on the entire surface (see FIG. 13C). The outermost trench groove 55 is formed so that its width is wider than that of the inner trench groove 56. The width of the trench grooves 58 and 59 is made the same as that of the outermost trench groove 55, for example.

  Next, polyimide 210 is applied to the entire surface. Thereafter, wet etching is performed with 2.38% by mass of tetramethylammonium oxide (TMAH) to perform so-called cueing that exposes the upper portion of the ridge type optical waveguide for forming the DFB lasers 51a-1 to 51a-6. Thereafter, the polyimide 210 left in each trench groove 55, 56, 58, 59 is cured and thermally cured (see FIG. 14A).

  Next, regions other than the ridge type optical waveguide for forming the DFB lasers 51a-1 to 51a-6 and the ridge type optical waveguide for forming the semiconductor optical amplifier 53 and the semiconductor optical modulator 54 are formed by photolithography. The protective film 209 on the upper portion of the ridge-type optical waveguide covered with the resist and not covered with the resist is etched away by RIE. As a result, the contact layer 208 is exposed. Thereafter, the resist is removed (see FIG. 14B).

Next, a resist having a pattern for forming the p-side electrode 211 is formed by a photolithography technique, an AuZn film is deposited on the entire surface, and then lift-off with acetone is performed. Thus, the p-side electrode 211 is formed (see FIG. 14C).

Next, an electrode pad 212 having a two-layer structure of Ti / Pt, and an Au plating layer 213 for reducing the contact resistance between the p-side electrode 211 and the electrode pad 212 are formed (FIGS. 14D and 14E).
)reference)). When forming the Au plating layer 213, first, the semiconductor wafer 40 is immersed in a plating solution, a disk electrode is disposed as a positive plating electrode in the upper solution of the semiconductor wafer 40, and a negative electrode is formed on the outer periphery of the semiconductor wafer 40. A ring electrode is brought into contact as a plating electrode. In this state, a direct current is passed and electrolytic plating is performed to deposit an Au film. The p-side electrode 211, the electrode pad 212, and the Au plating layer 213 are also formed on the ridge type optical waveguide for forming the semiconductor optical amplifier 53 and the semiconductor optical modulator 54.

  Thereafter, the entire back surface of the substrate 202 is polished, an AuGeNi / Au film is deposited on the polished back surface to form an n-side electrode 201, and then sintered (sintered) at 430 ° C. to make ohmic contact. Finally, the integrated semiconductor laser element is completed by separating the elements.

  As described above, since the trench grooves 55, 56 and 59 of each chip 42 are separated from the trench grooves of other chips, the contact layer of each chip is adjacent to the Y direction at one end in the Y direction. Since it is connected to the contact layer of the two chips and also connected to the contact layer of the two chips at the other end, each chip is electrically connected also in the X direction via a chip adjacent to the Y direction. . For this reason, when forming the Au plating layer 213 by electroplating, the resistance distribution variation is reduced and the potential difference between the chips is reduced as compared with the conventional semiconductor wafer in which each chip is electrically insulated in the X direction. Therefore, the variation in cathode current density is also reduced. When the Au plating layer 213 is formed by electrolytic plating, the thickness of the Au plating layer to be formed is proportional to the cathode current density (A / m 2), so that the variation in the thickness of the Au plating layer 129 is also reduced. The

  FIG. 15 shows the relationship between the distance between the chip and the plating electrode, the resistance between the chip and the plating electrode, and the thickness of the Au plating layer in the present embodiment. The variation in the thickness of the Au plating layer is 2.5 μm to 11 μm, and the ratio of the maximum Au plating layer thickness to the minimum Au plating layer thickness is 4.4. On the other hand, in the conventional form in which the chips are arranged in a grid pattern, the variation in the thickness of the Au plating layer is 0.5 μm to 10 μm, and the thickness of the maximum Au plating layer with respect to the thickness of the minimum Au plating layer The ratio is 20. That is, in this embodiment, the ratio of the thickness of the maximum Au plating layer to the thickness of the minimum Au plating layer is 5, which indicates that the ratio is reduced to ¼ or less compared to the conventional case.

  In addition, variation in the thickness of the Au plating layer 213 is also suppressed between the divided chips 12. As a result, variation in electrical characteristics or thermal resistance between light emitting elements manufactured by dividing from one semiconductor wafer is also suppressed. For this reason, the manufacturing yield of the semiconductor light emitting device is also improved.

In the second embodiment, each chip 42 is shifted in the X direction from the adjacent chip in the Y direction by a shift width Ta = Sa / 2 (Sa is a width in the X direction of the chip). Although formed, it is not limited to this.
As shown in FIG. 7, when the widths of the element regions where the trench grooves and the ridge portions are provided at both ends in the Y direction of each chip are S1 and S2, the deviation width Ta satisfies the following formula. I just need it.
S1 / 2 + S2 / 2 <Ta ≦ Sa / 2

  Note that the DFB laser array and the integrated semiconductor laser element including the DFB laser array according to the above-described embodiment have materials, sizes, and the like such as compound semiconductors and electrodes for wavelengths of 1550 nm. However, each material, size, and the like can be appropriately set according to the wavelength of light to be amplified within the optical communication wavelength band, and are not particularly limited.

  In the above embodiment, the width of each ridge type optical waveguide and the depth of each trench groove constituting the semiconductor optical waveguide array element are equal, but the width of each ridge type optical waveguide or the depth of each trench groove is May be different.

  In the above embodiment, polyimide is used as the organic insulating material, but other organic insulating materials such as benzocyclobutene (BCB) resin may be used.

  In the above embodiment, the semiconductor waveguide array element is a DFB laser array. However, the present invention is applicable to any semiconductor optical waveguide array element in which ridge-type optical waveguides are arranged in an array. For example, the present invention manufactures a semiconductor waveguide array element, a semiconductor optical amplifier array, or a semiconductor optical modulator array that guides a plurality of optical signals in parallel by arranging passive ridge-type optical waveguides in an array. It can also be applied to cases. In the above embodiment, the ridge type optical waveguide has a low mesa structure in which the trench groove is formed at a depth that does not reach the core layer, but the high mesas in which the trench groove is formed deeper than the core layer. The present invention can also be applied to a ridge type optical waveguide having a structure.

10, 40, 60 Semiconductor wafers 12, 42, 62 Chips 14, 16, 55, 56, 58, 59, 64, 66 Trench grooves 18, 46, 68 Ridge waveguides 20, 22, 57, 70 Support portion 26 Window 51 DFB laser arrays 51a-1 to 51a-6 DFB lasers 51b-1 to 51b-5 Support mesa 52 Optical combiner 53 Semiconductor optical amplifier 54 Semiconductor optical modulator 101 Chip top surface 102 Chip bottom surface 110 n-InP substrate 112 n- InP clad layer 114 SCH-MQW active layer 116 First P-InP clad layer 117 p-AlInAs layer 118 p-AlInAs layer 119 p-AlInAs-containing layer 120 Oxide insulator layer 122 obtained by oxidizing AlInAs Second P- InP cladding layer 124 p-GaInAs contact layer 126 SiNx film 28 p-side electrode 129 Au plating layer 130 n-side electrode 140 mask 201 n-side electrode 202 substrate 203 active core layers 204 and 207 upper cladding layer 205 etch stop layer 206 grating layer 208 contact layer 209 protective film 210 polyimide 211 p-side electrode 212 Electrode pad 213 Au plating layer 214 Lower cladding layer 215 Passive core layer 216 Upper cladding layer 220 GaInAsP layer 221 Cap protection layer M1, M2 Protection mask

Claims (8)

A plurality of semiconductor wafers on which chips for a ridge type semiconductor light emitting element are formed,
A semiconductor multilayer structure formed on a substrate; and at least two trench grooves formed so as to extend from a surface side of the semiconductor multilayer structure in a first direction on the surface; A ridge formed between the trench grooves, an electrode formed on the ridge and separated in at least a second direction perpendicular to the first direction, and electroplating on the electrode Having a formed metal layer,
Each chip is formed side by side with the chip adjacent to the chip in the second direction, and formed to be shifted in the second direction from the chip adjacent to the chip in the first direction,
A semiconductor wafer, wherein a trench groove of each chip is separated from a trench groove of a chip adjacent to the chip in the first direction. The semiconductor light emitting element is a laser array element having at least three trench grooves and two ridge portions, and the width of each chip in the second direction is Sa, and both ends of each chip in the first direction are In the portion, when the width of the element region provided with the trench groove and the ridge portion is S1 and S2,
The deviation width Ta between each chip and the chip adjacent to the chip in the first direction is:
S1 / 2 + S2 / 2 <Ta ≦ St / 2
The semiconductor wafer according to claim 1, wherein: The semiconductor light emitting device is a single stripe laser device having two trench grooves and one ridge portion, and when the width in the second direction of each chip is St and the width of the trench groove is Sd, The shift width Ts between each chip and the chip adjacent to the chip in the first direction is:
Sd <Ts ≦ St / 2
The semiconductor wafer according to claim 1, wherein: When the width of the ridge portion is Sr, the deviation width Ts is:
Ts ≦ Sr / 2 + Sd / 2
The semiconductor wafer according to claim 3, wherein:   5. The semiconductor wafer according to claim 1, wherein each of the chips is formed so as to face the same direction in the first direction. The semiconductor wafer according to any one of claims 1 to 5 is divided into chips,
A semiconductor light emitting device, wherein an end surface treatment is applied to an end surface of the chip in the first direction. A method of manufacturing a semiconductor wafer in which a plurality of chips for a ridge type semiconductor light emitting device are formed,
A semiconductor multilayer structure formed on the substrate; at least two trench grooves formed to extend in a first direction on the surface from a surface side of the semiconductor multilayer structure; and between the trench grooves A ridge formed on the ridge, an electrode formed on the ridge and separated in at least a second direction perpendicular to the first direction, and a metal formed on the electrode by electroplating Forming a chip having a layer,
In the step of forming the chip, each chip is formed side by side with the chip adjacent to the chip in the second direction perpendicular to the first direction, and the chip adjacent to the chip in the first direction; Is formed shifted in the second direction,
A method of manufacturing a semiconductor wafer, wherein the trench groove of each chip and the trench groove of a chip adjacent to the chip in the first direction are separated. Dividing the semiconductor wafer manufactured by the method according to claim 7 into chips;
And a step of manufacturing a semiconductor light emitting device by subjecting the chip to an end face treatment.

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