JP2013042270A - Transistor circuit, bidirectional switch circuit, diode circuit, and method of manufacturing transistor circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a current to a gate of a transistor.SOLUTION: A transistor circuit provided comprises: a first, normally on transistor; a second, normally off transistor having a drain connected to a source of the first transistor, and cascode-connected to the first transistor; and a first current suppression section disposed between a source of the second transistor and a gate of the first transistor to suppress a current flowing from the source of the second transistor to the gate of the first transistor.

Description

  The present invention relates to a transistor circuit, a bidirectional switch circuit, a diode circuit, and a method for manufacturing a transistor circuit.

Conventionally, normally-on transistors and normally-off transistors have been cascode-connected for the purpose of using normally-on transistors such as HEMTs as normally-off devices (for example, Patent Documents). 1).
Patent Document 1 JP 2001-29386 A

  When a normally-on transistor and a normally-off transistor are cascode-connected, the drain terminal of the normally-off transistor is connected to the source terminal of the normally-on transistor, and the source of the normally-off transistor is The terminal is connected to the gate terminal of the normally-on transistor. In general, in a normally-off transistor such as a MOSFET, a parasitic diode is formed between a source and a drain.

  However, if the voltage applied between the source of the normally-off transistor and the drain of the normally-on transistor becomes larger than the built-in voltage of the normally-on transistor, a current is supplied to the gate of the normally-on transistor. Will flow. Here, when the built-in voltage of the diode included in the normally-off transistor is higher than the built-in voltage at the gate portion of the normally-on transistor, current easily flows to the gate electrode of the normally-on transistor. For this reason, when the built-in voltage at the gate portion of the normally-on transistor is small, current tends to flow through the gate, and the gate of the normally-on transistor may be destroyed by overcurrent.

  In the first aspect of the present invention, a normally-on type first transistor, a normally-off type second transistor having a drain connected to the source of the first transistor and cascode-connected to the first transistor, Provided is a transistor circuit comprising: a first current suppression unit provided between a source of a second transistor and a gate of the first transistor that suppresses a current flowing from the source of the second transistor to the gate of the first transistor. . As an example, the first current suppressing unit includes at least one of a resistor and a first diode.

  For example, the first current control unit includes a first diode having a cathode connected to the gate of the first transistor and an anode connected to the source of the second transistor. The first current suppressing unit may include a resistor and a first diode connected in series to the resistor. The first current suppressing unit may include a resistor and a first diode connected in parallel to the resistor.

  The first current suppression unit may include a plurality of first diodes connected in series or in parallel. As an example, the plurality of first diodes are connected in series in the same direction. The plurality of first diodes may be connected in parallel in opposite directions.

  For example, the first diode is formed of polysilicon on the gate electrode pad of the first transistor. The first transistor has one gate electrode pad with an extended gate wiring or a plurality of gate electrode pads connected to each other through the gate wiring. The anode and the cathode of the first diode are in the middle of the gate wiring. It may be provided.

  In the second aspect of the present invention, a normally-off type third transistor, a normally-on type first bidirectional switch, and a normally-off type second transistor, which are cascode-connected in order, A first current that is provided between a source / drain terminal that is not connected to the first bidirectional switch of the two transistors and a first gate of the first bidirectional switch and suppresses a current flowing from the source / drain terminal to the first gate. The current flowing from the source / drain terminal to the second gate is provided between the suppression unit, the source / drain terminal not connected to the first bidirectional switch of the third transistor, and the second gate of the first bidirectional switch. A bidirectional switch circuit further comprising a second current suppressing unit for suppressing.

  For example, the first current suppressing unit includes a first diode having a cathode connected to the first gate of the first bidirectional switch and an anode connected to a source / drain terminal not connected to the first bidirectional switch of the second transistor. The second current suppressing unit includes a second diode having a cathode connected to the second gate of the first bidirectional switch and an anode connected to a source / drain terminal not connected to the first bidirectional switch of the third transistor. .

  The bidirectional switch circuit includes a first bias diode having a cathode connected to a source / drain terminal connected to the first bidirectional switch of the second transistor and an anode connected to a substrate of the first bidirectional switch; A second bias diode having a cathode connected to a source / drain terminal connected to the first bidirectional switch of the three transistors and an anode connected to a substrate of the first bidirectional switch may be further included.

  In the third aspect of the present invention, the normally-on type first transistor and the cathode are provided between the diode connected to the source of the first transistor, the anode of the diode, and the gate of the first transistor. In addition, a diode circuit is provided that includes a current suppressing unit that suppresses a current flowing from the anode of the diode to the gate of the first transistor.

  In the fourth aspect of the present invention, a step of forming a normally-on type first transistor, a step of forming a first polysilicon film on a gate electrode pad of the first transistor, and a step of forming a first polysilicon film on the first polysilicon film A step of implanting a dopant of a first conductivity type, a step of forming a second polysilicon film on the first polysilicon film, and a second conductivity of a conductivity type opposite to the first conductivity type on the second polysilicon film. A method of manufacturing a transistor circuit comprising: implanting a dopant of a type; connecting a drain of a second transistor to a source of the first transistor; and connecting a source of the second transistor to a second polysilicon film. I will provide a.

  It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

2 shows a configuration example of a transistor circuit according to the present embodiment. The other structural example of the transistor circuit which concerns on this embodiment is shown. The other example of a structure of the transistor circuit which concerns on this embodiment is shown. The other structural example of the transistor circuit which concerns on this embodiment is shown. The other structural example of the transistor circuit which concerns on this embodiment is shown. The other structural example of the transistor circuit which concerns on this embodiment is shown. The other structural example of the transistor circuit which concerns on this embodiment is shown. An example of mounting a transistor circuit according to this embodiment will be described. A configuration example of the diode 132 provided in the middle of the gate wiring is shown. Another configuration example of the diode 132 provided in the middle of the gate wiring is shown. The structure of the transistor which concerns on other embodiment is shown. The structure of the transistor which concerns on other embodiment is shown. The structure of the transistor which concerns on other embodiment is shown.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

  FIG. 1 shows a configuration example of a transistor circuit 100 according to the present embodiment. The transistor circuit 100 includes a first transistor 110, a second transistor 120, and a current suppressing unit 130. The first transistor 110 is a normally-on transistor, and allows a current to flow between the source and the drain in a state where no voltage is applied to the gate. The first transistor 110 is, for example, a HEMT (High Electron Mobility Transistor). The first transistor 110 may be a HEMT having a Schottky junction or a HEMT having a MIS (Metal Insulator Semiconductor) structure. A terminal 210 is connected to the drain of the first transistor 110.

  The second transistor 120 is a normally-off transistor, and does not pass a current between the source and the drain when no voltage is applied to the gate. The second transistor 120 is, for example, a field effect transistor. A terminal 230 is connected to the gate of the second transistor 120, and a terminal 220 is connected to the source of the second transistor 120.

  The second transistor 120 is cascode connected to the first transistor 110. Specifically, the drain of the second transistor 120 and the source of the first transistor 110 are connected. The source of the second transistor 120 is connected to the gate of the first transistor 110 through the current suppressing unit 130.

  The second transistor 120 includes a parasitic diode 122 between the source and the drain. The second transistor 120 is, for example, a field effect transistor, and the diode 122 is a pn junction formed between the source and drain of the second transistor 120. When the voltage applied to the terminal 220 is larger than the built-in voltage, the diode 122 becomes conductive, so that a current flows from the source to the drain of the second transistor 120.

  The current suppression unit 130 is provided between the source of the second transistor 120 and the gate of the first transistor 110. The current suppressing unit 130 suppresses a current flowing from the source of the second transistor 120 to the gate of the first transistor 110. The current suppressing unit 130 preferably does not flow current from the source of the second transistor 120 to the gate of the first transistor 110.

  Note that the second transistor 120 and the current suppression unit 130 may be formed in one chip. For example, the second transistor 120 and the current suppression unit 130 may be formed on the same silicon chip, and the first transistor 110 may be formed of a nitride semiconductor.

  FIG. 2 shows another configuration example of the transistor circuit 100 according to the present embodiment. The current suppression unit 130 in FIG. The diode 132 has an anode connected to the terminal 220 and a cathode connected to the gate of the first transistor 110. The diode 132 is a diode other than a Zener diode. For example, the diode 132 does not have a breakdown voltage within the operating voltage range of the transistor circuit 100. The operating voltage range of the transistor circuit 100 may be a product specification value of the transistor circuit 100. Specifically, the built-in voltage of the diode 132 may be 1.2 V or more.

  Since the current suppression unit 130 includes the diode 132, the first voltage from the terminal 220 is increased until the voltage applied to the terminal 220 becomes larger than the sum of the built-in voltage of the diode 132 and the built-in voltage at the gate of the first transistor 110. No current flows to the gate of the transistor 110.

  The reverse voltage of the diode 132 is preferably smaller than the sum of the threshold voltage of the first transistor 110 and the source-drain breakdown voltage of the second transistor 120. Note that the reverse voltage of the diode 132 indicates a voltage at which the leakage current of the diode 132 and the gate leakage current of the first transistor 110 are equal. In this case, since an electric current flows from the gate of the first transistor 110 to the terminal 220 via the diode 132 before an excessive voltage is applied to the second transistor 120, the second transistor 120 is destroyed. Can be prevented.

  FIG. 3 shows another configuration example of the transistor circuit 100 according to the present embodiment. The current suppression unit 130 in FIG. 3 includes a resistor 134 connected in series with the diode 132. Since the current suppressing unit 130 includes the resistor 134, when a voltage larger than the sum of the built-in voltage of the diode 132 and the built-in voltage at the gate of the first transistor 110 is applied to the terminal 220, the terminal 220 to the first transistor The current flowing into the gate 110 can be suppressed.

  FIG. 4 shows another configuration example of the transistor circuit 100 according to the present embodiment. The current suppression unit 130 in FIG. 4 has a resistor 134 connected in parallel with the diode 132. Since the current suppressing unit 130 has the resistor 134 in parallel with the diode 132, even when the diode 132 fails in the open mode, the connection between the source of the second transistor 120 and the gate of the first transistor 110 is maintained. By suppressing the current flowing into the gate of the first transistor 110, the destruction of the first transistor 110 can be prevented.

  FIG. 5 shows another configuration example of the transistor circuit 100 according to the present embodiment. The first current suppressing unit 130 may include a plurality of diodes connected in parallel to each other. The current suppressing unit 130 illustrated in FIG. 5 further includes a diode 136 connected in parallel with the diode 132. The cathode of the diode 136 is connected to the anode of the diode 132 and the source of the second transistor 120. The anode of the diode 136 is connected to the cathode of the diode 132 and the gate of the first transistor 110.

  Since the current suppression unit 130 further includes the diode 136, the reverse voltage of the current suppression unit 130 can be reduced. For this reason, it becomes easy to make the reverse voltage of the current suppressing unit 130 smaller than the sum of the threshold voltage of the first transistor 110 and the source-drain breakdown voltage of the second transistor 120. For this reason, it is possible to prevent the second transistor 120 from being damaged by being applied with an excessive voltage.

  FIG. 6 shows another configuration example of the transistor circuit 100 according to the present embodiment. The current suppression unit 130 may include a plurality of diodes connected in series with each other. The current suppressing unit 130 illustrated in FIG. 6 further includes a diode 138 connected in series with the diode 132 with respect to the current suppressing unit 130 illustrated in FIG. The anode of the diode 138 is connected to the terminal 220, and the cathode of the diode 138 is connected to the anode of the diode 132. The current suppression unit 130 may include more diodes connected in series.

  Since the current suppression unit 130 includes a plurality of diodes connected in series, the built-in voltage of the current suppression unit 130 can be increased. Therefore, compared to the case where the current suppression unit 130 includes only the diode 132, the current suppression unit 130 suppresses the current from flowing through the first transistor 110 even when a higher voltage is applied to the terminal 220. be able to. In addition, the current suppression unit 130 may include a plurality of diodes connected in series, the cathodes being disposed on the first transistor 110 side in any of the configurations illustrated in FIGS. 3 to 5.

  FIG. 7 shows another configuration example of the transistor circuit 100 according to the present embodiment. The current suppression unit 130 illustrated in FIG. 7 further includes a capacitor 140 connected in parallel to the diode 132, as compared with the current suppression unit 130 illustrated in FIG. When the transistor circuit 100 changes from the off state to the on state, the gate potential of the first transistor 110 may become unstable if the capacitance of the diode 132 is small. On the other hand, providing the capacitor 140 can prevent the gate potential of the first transistor 110 from becoming unstable.

  FIG. 8A shows an implementation example of the transistor circuit 100 according to the present embodiment. In FIG. 8A, a transistor circuit 100 includes a gate electrode pad 112, a gate electrode pad 113, a gate wiring 109, a gate electrode 108, an auxiliary wiring 111, a source electrode pad 116, a plurality of comb-type source electrodes 117, a drain electrode pad 118, and a plurality. The comb-shaped drain electrode 119 and the diode 132 are provided.

  The source electrode pad 116 and the drain electrode pad 118 are disposed to face each other. Each comb source electrode 117 is formed by extending in parallel from the source electrode pad 116 toward the drain electrode pad 118. Each comb drain electrode 119 is formed by extending in parallel from the drain electrode pad 118 toward the source electrode pad 116. The comb drain electrode 119 and the comb source electrode 117 are alternately provided with a predetermined distance apart in the horizontal direction perpendicular to the extending direction.

  The gate electrode pad 112 and the gate electrode pad 113 are gate electrode pads of the first transistor 110 illustrated in FIG. The gate electrode pad 112 and the gate electrode pad 113 are connected to each other through the gate wiring 109, the gate electrode 108, and the auxiliary wiring 111. Further, when the length of the gate electrode 108 is short, the gate electrode pad 113 may not be provided. In this example, the gate electrode pad 112 and the gate electrode pad 113 are formed on both sides of the source electrode pad 116 in the horizontal direction.

  The gate wiring 109 is formed along the source electrode pad 116, one end is connected to the gate electrode pad 112 or the gate electrode pad 113, and the other end is connected to the gate electrode 108 and the auxiliary wiring 111. The gate wiring 109 is connected to the gate electrode 108 and the auxiliary wiring 111 at the branch point 115. The branch point 115 is provided at a position where a straight line extending in the horizontal direction intersects the comb source electrode 117 and does not intersect the comb drain electrode 119.

  The gate electrode 108 is provided between the comb source electrode 117 and the comb drain electrode 119. The gate electrode 108 is also formed on the outer side of the outermost comb source electrode 117 and the comb drain electrode 119. The gate electrode 108 is formed to maintain a predetermined constant distance from the comb source electrode 117 and the comb drain electrode 119.

  The auxiliary wiring 111 is connected to the gate electrode 108 for each predetermined length of the gate electrode 108. The auxiliary wiring 111 of this example connects the two branch points 115 with a straight line. The auxiliary wiring 111 in this example is insulated from the comb source electrode 117 by an interlayer insulating film or the like.

  The diode 132 may be formed on the gate electrode pad 112 or 113 or may be formed in the middle of the gate wiring 109. In FIG. 8A, the diode 132 is formed on the gate electrode pad 112 and in the middle of the gate wiring 109, but the diode 132 may be formed only on one of them. As an example, the diode 132 is made of polysilicon. In the case where the diode 132 is formed of polysilicon, the diode 132 can be easily formed by forming polysilicon on the gate electrode pad 112 or 113. A silicon chip including the diode 132 may be placed on the gate electrode pad 112 or 113.

  Specifically, the diode 132 on the gate electrode pad 112 includes a first polysilicon film in which a first conductivity type dopant is implanted, and a second conductivity type dopant formed on the first polysilicon film. And a second polysilicon film in which is implanted. By sequentially forming the first polysilicon film and the second polysilicon film on the gate electrode pad 112, the diode 132 having a vertical structure can be formed.

  More specifically, an n-type dopant is implanted into the first polysilicon film in contact with the gate electrode pad 112, and a p-type dopant is implanted into the second polysilicon film formed on the first polysilicon film. Thus, the transistor circuit 100 and the diode 132 connected in the state shown in FIG. 2 can be manufactured.

  A third polysilicon film in which an n-type dopant is implanted is formed on the second polysilicon film, and a fourth polysilicon film in which a p-type dopant is implanted is formed on the third polysilicon film. Thus, the current suppressing unit 130 in which the diode 132 and the diode 138 illustrated in FIG. 6 are connected in series can be manufactured.

  Further, as described above, a diode may be formed on the gate electrode pad 113. For example, in addition to the configuration shown in FIG. 8A, a diode in which two polysilicon films having different conductivity types are formed on the gate electrode pad 113 in the reverse stacking order of the diode 132. The current suppressing unit 130 shown in FIG. 6 can be formed. Specifically, when an n-type dopant is implanted into the first polysilicon film in contact with the gate electrode pad 112, a p-type dopant may be implanted into the polysilicon film in contact with the gate electrode pad 113.

  After forming the diode 132 by the above procedure, the drain of the second transistor 120 shown in FIG. 2 is connected to the source electrode pad 116, and the source of the second transistor 120 is connected to the second polysilicon film of the diode 132. For example, the transistor circuit 100 can be manufactured by connecting by wire bonding.

  The diode 132 may be provided in the middle of the gate wiring 109. A polysilicon film in which an n-type dopant is implanted is formed in contact with the gate wiring 109, and a polysilicon film in which a p-type dopant is implanted is formed on the polysilicon film, whereby the diode shown in FIG. 132 may be formed.

  FIG. 8B shows a configuration example of the diode 132 provided in the middle of the gate wiring 109. FIG. 8B shows an AA ′ cross section in FIG. 8A. The diode 132 has an anode 131 and a cathode 133. The anode 131 is formed between the gate wiring 109 connected to the gate electrode pad 113 and the cathode 133. The cathode 133 is formed between the gate wiring 109 connected to the branch point 115 and the anode 131. The diode 132 of this example may also be formed of polysilicon.

  FIG. 8C shows another configuration example of the diode 132 provided in the middle of the gate wiring 109. FIG. 8C shows an AA ′ cross section in FIG. 8A. The diode 132 has an anode electrode 135 and a cathode electrode 137. The first transistor 110 in this example has a GaN layer 126 and an AlGaN layer 124, and a two-dimensional electron gas generated by a heterojunction of the GaN layer 126 and the AlGaN layer 124 functions as a channel.

  The anode electrode 135 is provided in connection with the gate wiring 109 connected to the gate electrode pad 113. The anode electrode 135 is formed of a material that is in Schottky contact with the AlGaN layer 124. For example, a stacked structure of Ni / Au can be used as the anode electrode 135.

  The cathode electrode 137 is connected to the gate wiring 109 connected to the branch point 115 and is provided apart from the anode electrode 135. The cathode electrode 137 is formed of a material that makes ohmic contact with the GaN layer 126. For example, a Ti / Al laminated structure can be used as the cathode electrode 137. An insulating film 114 is disposed between the gate wiring 109 and the AlGaN layer 124.

  FIG. 9 shows a configuration of a bidirectional switch circuit 200 according to another embodiment. The bidirectional switch circuit 200 further includes a third transistor 150 and a current suppressing unit 160 with respect to the transistor circuit 100 shown in FIG. The first transistor 110 is an example of a bidirectional switch. The first transistor 110 is a MOS transistor in which the functions and structures of the source terminal and the drain terminal are symmetrical, for example. The source and drain terminals of each transistor are referred to as a source / drain terminal (SD terminal). The second transistor 120 and the third transistor 150 are, for example, vertical Si-MOSFETs.

  The third transistor 150, the first transistor 110, and the second transistor 120 are cascode-connected in order. That is, one SD terminal A of the third transistor 150 is connected to the terminal 240, and the other SD terminal B is connected to the first transistor 110. One SD terminal C of the first transistor 110 is connected to the SD terminal B of the third transistor 150, and the other SD terminal D is connected to the SD terminal E of the second transistor 120. One SD terminal E of the second transistor 120 is connected to the SD terminal D of the first transistor, and the other SD terminal F is connected to the terminal 220. The gate of the second transistor 120 is connected to the terminal 230, and the gate of the third transistor 150 is connected to the terminal 250.

  The current suppression unit 130 is provided between the SD terminal F of the second transistor 120 and the first gate of the first transistor 110. The current suppression unit 160 is provided between the SD terminal A of the third transistor 150 and the second gate of the first transistor 110. The current suppressing unit 160 suppresses a current flowing from the SD terminal A of the third transistor 150 to the second gate of the first transistor 110. The current suppression unit 160 has the same configuration as any of the configurations of the current suppression unit 130 described with reference to FIGS.

  The bidirectional switch circuit 200 operates as a bidirectional switch according to the voltage applied to the terminal 220 and the voltage applied to the terminal 240. That is, when the voltage applied to the terminal 220 is larger than the voltage applied to the terminal 240, a current flows from the terminal 220 to the terminal 240. In this case, the current suppressing unit 130 suppresses the current flowing through the gate of the first transistor 110. When the voltage applied to the terminal 220 is smaller than the voltage applied to the terminal 240, a current flows from the terminal 240 to the terminal 220. In this case, the current suppressing unit 160 suppresses the current flowing through the gate of the first transistor 110.

  FIG. 10 shows a configuration of a bidirectional switch circuit 300 according to another embodiment. The bidirectional switch circuit 300 further includes a bias circuit 180 with respect to the bidirectional switch circuit 200 shown in FIG. Note that the first transistor 110 illustrated in FIG. 10 has the same function and configuration as the first transistor 110 illustrated in FIG. 9, but the substrate 172 of the first transistor 110 is also illustrated in FIG. 10.

  The bias circuit 180 includes a bias diode 182 and a bias diode 184. The bias diode 182 has a cathode connected to the SD terminal E of the second transistor 120 on the first transistor 110 side, and an anode connected to the substrate 172 of the first transistor 110. The bias diode 184 has a cathode connected to the SD terminal B of the third transistor 150 on the first transistor 110 side, and an anode connected to the substrate 172 of the first transistor 110. Since the bidirectional switch circuit 300 includes the bias circuit 180 connected to the substrate 172, the potential of the first transistor 170 is fixed, so that the substrate potential can be prevented from fluctuating when switching is performed.

  FIG. 11 shows a configuration of a diode circuit 400 according to another embodiment. The diode circuit 400 includes a diode 190 instead of the second transistor 120 in the transistor circuit 100 illustrated in FIG. The diode 190 has a cathode connected to the source of the first transistor 110. The current suppression unit 130 is provided between the anode of the diode 190 and the gate of the first transistor 110, and suppresses the current flowing from the anode of the diode 190 to the gate of the first transistor 110. The diode 190 is a silicon diode, for example. The diode 190 may be a polysilicon diode.

  Since the forward characteristic of the diode circuit 400 is determined by the diode 190, a forward characteristic with a large current can be obtained by using silicon having a low built-in voltage. In addition, since the reverse characteristics are determined by the first transistor 110, it is possible to increase the breakdown voltage by using high breakdown voltage GaN or the like. That is, a circuit with a large current and a high breakdown voltage can be realized.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

  The execution order of each process such as operation, procedure, step, and stage in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before” or “prior to”. It should be noted that the output can be realized in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the specification, and the drawings, even if it is described using “first”, “next”, etc. for the sake of convenience, it means that it is essential to carry out in this order. It is not a thing.

100 transistor circuit, 108 gate electrode, 109 gate wiring, 110 first transistor, 111 auxiliary wiring, 112 gate electrode pad, 113 gate electrode pad, 114 insulating film, 115 branch point, 116 source electrode pad, 117 comb source electrode, 118 drain electrode pad, 119 comb drain electrode, 120 second transistor, 122 diode, 124 AlGaN layer, 126 GaN layer, 130 current suppression unit, 131 anode, 132 diode, 133 cathode, 134 resistance, 135 anode electrode, 136 diode 137 cathode electrode, 138 diode, 140 capacitor, 150 third transistor, 160 current suppression unit, 170 first transistor, 172 substrate, 180 bias circuit, 1 82 Bias Diode, 184 Bias Diode, 190 Diode, 200 Bidirectional Switch Circuit, 210 Terminal, 220 Terminal, 230 Terminal, 240 Terminal, 250 Terminal, 300 Bidirectional Switch Circuit, 400 Diode Circuit

Claims (18)

A normally-on type first transistor;
A normally-off second transistor having a drain connected to the source of the first transistor and cascode-connected to the first transistor;
A transistor provided between the source of the second transistor and the gate of the first transistor, and a first current suppressing unit that suppresses a current flowing from the source of the second transistor to the gate of the first transistor. circuit.   The transistor circuit according to claim 1, wherein the first current suppressing unit includes at least one of a resistor and a first diode.   3. The transistor circuit according to claim 2, wherein the first current suppressing unit includes the first diode having a cathode connected to a gate of the first transistor and an anode connected to a source of the second transistor.   The transistor circuit according to claim 3, wherein the first current suppressing unit includes the resistor and the first diode connected in series to the resistor.   4. The transistor circuit according to claim 3, wherein the first current suppressing unit includes the resistor and the first diode connected in parallel to the resistor.   6. The transistor circuit according to claim 2, wherein the first current suppressing unit includes a plurality of the first diodes connected to each other in series or in parallel.   The transistor circuit according to claim 6, wherein the plurality of first diodes are connected in series in the same direction.   The transistor circuit according to claim 6, wherein the plurality of first diodes are connected in parallel in opposite directions.   The transistor circuit according to claim 2, wherein the first diode is formed of polysilicon on a gate electrode pad of the first transistor. The transistor circuit according to claim 2, wherein the first diode is formed on a silicon chip placed on a gate electrode pad of the first transistor. The first transistor has a plurality of gate electrode pads connected to each other by gate wiring,
The transistor circuit according to claim 2, wherein an anode and a cathode of the first diode are provided in the middle of the gate wiring. The transistor circuit according to any one of claims 2 to 11, wherein a reverse voltage of the first diode is smaller than a sum of a threshold voltage of the first transistor and a source-drain breakdown voltage of the second transistor. The transistor circuit according to claim 1, wherein the second transistor and the current suppression unit are formed on the same silicon chip. A normally-off type third transistor, a normally-on type first bidirectional switch, and a normally-off type second transistor, which are cascode-connected in order,
A current that is provided between a source / drain terminal of the second transistor that is not connected to the first bidirectional switch and a first gate of the first bidirectional switch, and that flows from the source / drain terminal to the first gate. A first current suppressing unit for suppressing,
A current that is provided between a source / drain terminal of the third transistor that is not connected to the first bidirectional switch and a second gate of the first bidirectional switch, and that flows from the source / drain terminal to the second gate. A bidirectional switch circuit further comprising: a second current suppressing unit for suppressing. The first current suppressing unit has a cathode connected to the first gate of the first bidirectional switch, and an anode connected to a source / drain terminal not connected to the first bidirectional switch of the second transistor. Having a diode,
The second current suppressing unit has a cathode connected to the second gate of the first bidirectional switch, and an anode connected to a source / drain terminal not connected to the first bidirectional switch of the third transistor. The bidirectional switch circuit according to claim 14, comprising a diode. A first bias diode having a cathode connected to a source / drain terminal connected to the first bidirectional switch of the second transistor and an anode connected to a substrate of the first bidirectional switch;
2. A second bias diode having a cathode connected to a source / drain terminal connected to the first bidirectional switch of the third transistor and an anode connected to a substrate of the first bidirectional switch. The bidirectional switch circuit according to 14 or 15. A normally-on type first transistor;
A diode having a cathode connected to a source of the first transistor;
A diode circuit comprising: a current suppressing unit that is provided between the anode of the diode and the gate of the first transistor and suppresses a current flowing from the anode of the diode to the gate of the first transistor. Forming a normally-on type first transistor;
Forming a first polysilicon film on the gate electrode pad of the first transistor;
Implanting a first conductivity type dopant into the first polysilicon film;
Forming a second polysilicon film on the first polysilicon film;
Implanting a second conductivity type dopant of a conductivity type opposite to the first conductivity type on the second polysilicon film;
Connecting a drain of a second transistor to a source of the first transistor;
Connecting a source of the second transistor to the second polysilicon film.

Images