JP2012142505A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having an element isolation structure capable of achieving an element with further reduced parasitic capacitance and to provide a method of manufacturing the same.SOLUTION: A semiconductor device formed on an SOI substrate comprises: an element isolation trench (cavity) 17 formed in an element isolation region; and a cavity region 20 that is formed in a portion of a buried insulating layer interposed between a semiconductor layer 11 and a supporting substrate 13 and contacts the element isolation trench (cavity) 17. This structure can reduce parasitic capacitance and can improve the breakdown voltage of the element.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, for example, an element isolation structure of a semiconductor device.

  In recent years, with increasing demands for higher integration, higher speed, and lower power consumption in semiconductor devices, higher withstand voltages are also becoming increasingly necessary. Among them, the performance is improved by an SOI (Silicon on Insulator) substrate and element isolation trench (DTI (Deep Trench Isolation), STI (Shallow Trench Isolation), etc.), while the element is surrounded by an oxide film to reduce parasitic capacitance. There is concern about the increase. The present invention provides a semiconductor device and a manufacturing method thereof in which the parasitic capacitance is greatly reduced.

JP 2006-49828 A JP 2006-237455 A

  In a semiconductor device using an SOI (silicon on insulator) substrate, a semiconductor element is formed in a semiconductor layer on an insulating film (oxide film) provided on the semiconductor substrate. In this structure, the semiconductor substrate and the semiconductor layer are completely separated and a pn junction is not formed below the element region. Further, by forming the element isolation films (DTI, STI), it is possible to realize almost complete electrical isolation from other elements and a reduction in capacitance due to the pn junction. However, the capacitance formed by the semiconductor layer, the insulating film, and the semiconductor substrate, and the capacitance between the semiconductor layers via the DTI insulating film still exist according to the relative dielectric constant (about 3.9) of the oxide film.

  An example of a representative one of the present invention is as follows.

  A semiconductor device of the present invention is formed in a semiconductor substrate, a buried insulating layer formed on the semiconductor substrate, a semiconductor layer formed on the buried insulating layer and having an element formed therein, and an element isolation region of the semiconductor layer, A groove reaching the buried insulating layer, and a partial region of the buried insulating layer in contact with the groove is a cavity.

  Alternatively, as a method for manufacturing a semiconductor device having a semiconductor substrate, a buried insulating layer formed on the semiconductor substrate, and a semiconductor layer formed on the buried insulating layer, a groove reaching the buried insulating layer is formed in an element isolation region of the semiconductor layer. Then, an oxide film is formed so as to fill the trench, a through hole reaching the buried insulating layer is formed in the semiconductor substrate, and a part of the buried insulating layer and the oxide film buried in the trench are removed from the through hole. To.

  According to the present invention, a reduction in source-drain capacitance and a reduction in substrate capacitance can be realized at the same time, which is effective in improving response speed and reducing power consumption. Further, since the element isolation trench is not buried, the process can be simplified.

3 is a cross-sectional view of an element isolation groove portion of the semiconductor device of Example 1. FIG. FIGS. 2A to 2I are views for explaining a process for manufacturing the element isolation trench portion of the first embodiment. 3 is a cross-sectional view of an element isolation groove portion of the semiconductor device of Example 1. FIG. 1 is a cross-sectional view of a semiconductor device of Example 1. FIG. In the present invention, it is a diagram for explaining a unit to be separated by a hollow element isolation groove. 6 is a cross-sectional view of an element isolation groove portion of a semiconductor device of Example 2. FIG. FIGS. 7A to 7F are diagrams for explaining the manufacturing process of the element isolation trench portion of the second embodiment. 8A to 8D are diagrams for explaining the manufacturing process of the semiconductor device of the present invention. 6 is an example of a cross-sectional view of an element isolation groove portion of a semiconductor device of Example 2. FIG. 6 is a cross-sectional view of an element isolation groove portion of a semiconductor device of Example 2. FIG. 6 is a cross-sectional view of an element isolation groove portion of a semiconductor device of Example 2. FIG.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, components having substantially the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary.

FIG. 1 is a cross-sectional view of an element isolation trench portion of a semiconductor device according to the present invention (Example 1). 13 is a semiconductor support substrate (thickness t3 is about 600 to 700 μm), 12 is a buried insulating layer (thickness t2 is about 2.5 μm), 20 is a buried insulating layer cavity region, and 11 is a semiconductor layer (thickness) made of silicon. t1 is approximately 5 μm), 17 is a separation groove (cavity), 18 is an insulating film, 14 is a field insulating film made of an oxide film (SiO ₂ film), and 21 is a surface protective film. The buried insulating layer 12 and the semiconductor layer 11 formed on the semiconductor support substrate 13 constitute an SOI substrate, and the element is formed on the SOI substrate. As shown in FIG. 1, element isolation is performed by an isolation groove cavity 17 formed so as to penetrate the semiconductor layer 11 from the field insulating film 14 to reach the embedded insulating layer 12, and the isolation groove cavity 17 is further embedded and insulated. Coupled to the layer cavity region 20. Thus, by reducing the relative dielectric constant of the element isolation trench and the buried insulating layer, the capacitance between the semiconductor layers can be reduced. The separation groove cavity 17 is closed by an insulating film 18 formed so as to cover the cavity 17 and a surface protective film 19 formed on the upper surface of the insulating film 18.

  A manufacturing process of the element isolation trench portion in FIG. 1 will be described with reference to FIGS. 2 (a) to 2 (i). First, as shown in FIG. 2A, a field insulating film 14 is formed on a semiconductor layer 11 of an SOI substrate over a region including an element isolation formation region. The field insulating film 14 is formed of, for example, a so-called LOCOS oxide film that is selectively formed using a thermal oxidation method. An opening (a portion where the semiconductor layer 11 is exposed) of the field insulating film 14 becomes an element formation region. The field insulating film is not limited to the LOCOS oxide film, but a buried insulating film (STI) may be formed in the element isolation formation region. Thereafter, an SiN insulating film 15 is formed so as to cover the field insulating film 14 and the semiconductor layer 11 exposed in the opening.

  Next, as shown in FIG. 2B, after forming a resist pattern (not shown) on the SiN insulating film 15 using photolithography, the SiN insulating film 15 is formed using the resist pattern as an etching mask. By selectively etching, an opening is formed in the inner region of the separation groove forming region. Thereafter, the resist pattern is removed. Further, as shown in FIG. 2C, the field oxide film 14 is anisotropically etched using the SiN insulating film 15 as a hard mask to form an opening. Next, as shown in FIG. 2D, a SiN insulating film 16 of the same quality as the SiN insulating film 15 is formed on the SiN insulating film 15 having the opening.

  Next, as shown in FIG. 2E, anisotropic etching of the SiN insulating film 16 is performed to form SW (sidewall) on the side surface of the opening of the field oxide film 14. As a result, the field oxide film 14 is protected by the SiN layers 15 and 16 in the subsequent step of etching the semiconductor layer 11 and the buried insulating layer 12.

  Next, as shown in FIG. 2F, the semiconductor layer 11 is anisotropically etched using the insulating film 15 having the opening as an etching mask, and the isolation groove reaching the buried insulating layer 12 in the semiconductor layer 11. 17 is formed.

  Next, as shown in FIG. 2G, the buried insulating layer 12 is removed by isotropic etching. For removal, wet etching such as hydrofluoric acid is desirable.

  Next, as shown in FIG. 2H, the SiN insulating film 15 is removed by isotropic etching. At that time, the side surface of the semiconductor layer 11 is similarly etched.

  Next, as shown in FIG. 2I, the opening of the element isolation trench is closed by the insulating film 18 having low coverage and low fluidity, and a cavity is formed in the element isolation trench 17. The insulating film 18 is TEOS (Tetra Ethyl) which is not doped with impurities and has low fluidity in consideration of the reliability of electrical insulation on the element surface and heat treatment at the time of reflow of the surface protection film formed in the subsequent process. It is desirable to use a CVD oxide film such as Ortho Silicate.

  The reason why the SiN insulating film is removed in the example of FIG. 2 (FIG. 2 (h)) is that the SiN layer may be a variation factor of the threshold characteristics of the element. When such influence on the element can be ignored, the insulating film 18 is laminated without removing the SiN insulating films 15 and 16 formed around the field oxide film 14 as shown in FIG. Is possible. This can reduce the number of processes.

  FIG. 4 is a cross-sectional view of an example of a semiconductor device to which the separation groove of the present invention is applied. In addition, what is shown is a base layer, and a wiring layer is formed thereon via an interlayer insulating film. A high breakdown voltage transistor is formed in region A, and a low breakdown voltage transistor is formed in region B.

  The gate polysilicon 41 which is the gate of the high breakdown voltage transistor has an elongated ring shape as a planar shape, and is formed so as to surround the source / drain layer 43a via the gate oxide film 44. A gate cap oxide film 42 is formed on the gate polysilicon 41. In addition, stripe-like source / drain layers 43 b are formed on both sides (or one side) of the gate polysilicon 41. The source / drain layers are separated from each other by a field insulating film 45. Further, a high breakdown voltage buffer layer 47 is formed so as to cover the source / drain layer 43b, and a high breakdown voltage channel layer 46 is formed so as to cover the source / drain layer 43a. A source / drain layer 43 is provided on both sides of the gate polysilicon 41 which is the gate of the low breakdown voltage transistor. Thus, the elements are separated by the element isolation trench (cavity) 48, and the inter-element capacitance is reduced by the buried insulating layer cavity region 52. The mechanical strength of the element is maintained by the remaining buried insulating layer 51.

  In particular, in a high breakdown voltage transistor, elements are separated from the conventional silicon oxide film having a relative dielectric constant of about 3.9 by air having a relative dielectric constant of 1, thereby further separating the elements 48 (cavity). Since the withstand voltage can be shared by this, the withstand voltage is also improved.

  Note that the unit of isolation by the hollow element isolation groove and the buried insulating layer cavity region in contact with the hollow element isolation groove may not be the element unit isolation as shown in FIG. FIG. 5 is a perspective view for schematically explaining the separation method. The element isolation groove (cavity) 48 is indicated by a solid line. FIG. 5A shows an element isolation groove (cavity) 48 for each element as shown in FIG. On the other hand, in FIG. 5B, isolation grooves (cavities) 48 are provided for a plurality of element groups, and isolation for each element is performed by a LOCOS oxide film or STI. In FIG. 5B, such element separation is indicated by a dotted line 55. The unit for separating into the element isolation trenches is the same as in Example 2 described below.

FIG. 6 is a cross-sectional view of the element isolation trench portion of the semiconductor device of the present invention (Example 2). 13 is a semiconductor support substrate (thickness t3 is about 400 μm), 12 is a buried insulating layer (thickness t2 is about 2.5 μm), 20 is a buried insulating layer cavity region, 11 is a semiconductor layer made of silicon (thickness t1 is 17 is a separation groove (cavity), 14 is a field insulating film made of an oxide film (SiO ₂ film), 19 and 23 are insulating films, and 21 is a surface protective film. The buried insulating layer 12 and the semiconductor layer 11 formed on the semiconductor support substrate 13 constitute an SOI substrate, and the element is formed on the SOI substrate. As shown in FIG. 6, element isolation is performed by an isolation groove cavity 17 formed so as to penetrate the semiconductor layer 11 from the field insulating film 14 to reach the embedded insulating layer 12, and the isolation groove cavity 17 is further embedded and insulated. Coupled to the layer cavity region 20. Thus, by reducing the relative dielectric constant of the element isolation trench and the buried insulating layer, the capacitance between the semiconductor layers can be reduced.

  A method of manufacturing the element isolation trench portion in FIG. 6 will be described with reference to FIGS. 7 (a) to 7 (f). First, as shown in FIG. 7A, a field oxide film 14 having an opening on a region including an element isolation formation region is formed on a semiconductor layer 11 of an SOI substrate. The field insulating film 14 is formed of, for example, a so-called LOCOS oxide film that is selectively formed using a thermal oxidation method. Thereafter, an insulating film 19 made of a CVD oxide film is formed so as to cover the field insulating film 14 and the semiconductor layer 11 exposed in the opening. The insulating film 19 is made of TEOS (Tetra Ethyl which is not doped with impurities and has low fluidity in consideration of reliability of electrical insulation on the element surface and heat treatment during reflow of a surface protection film formed in a later step. It is desirable to use a CVD oxide film such as Ortho Silicate.

  Next, as shown in FIG. 7B, after forming a resist pattern (not shown) on the insulating film 19 using photolithography, the insulating film 19 is selectively used using the resist pattern as an etching mask. Etching is performed to form an opening in the inner region of the separation groove forming region. Thereafter, the resist pattern is removed. Thereafter, as shown in FIG. 7C, the element isolation trench is penetrated to the insulating layer 12 using the insulating film 19 as a hard mask.

  Next, as shown in FIG. 7D, an insulating film (oxide film) 23 is embedded in the element isolation trench 17 and a protective film 21 is further formed. Next, as illustrated in FIG. 7E, the through hole 22 is formed so as to reach the buried insulating layer 12 from the back surface of the semiconductor support substrate 13. The through hole is appropriately provided in a region where the buried insulating layer cavity region 20 is formed.

  Next, as shown in FIG. 7F, the buried insulating layer 12 and the oxide film 23 in the element isolation trench are removed from the through hole 22 by isotropic etching. At this time, it is desirable to remove the oxide film 23 in the element isolation trench to the vicinity of the bottom of the field insulating film. In this case, if the buried oxide film is removed after the wiring forming process as will be described later, the wiring structure is shown in FIG. 9 (in the figure, the metal wiring layers 25 and 26 and vias connecting them are shown). The buried oxide film having a relatively large area as shown in FIG. 5B can be removed.

  Further, as shown in FIG. 10, it is possible to etch back once when embedding the element isolation trench, and then form a SiN insulating film 29 to form a SiO wet etch stopper as shown in FIG.

  FIG. 8 shows a manufacturing method according to the semiconductor device of Example 1 or Example 2. 8A and 8B, the element isolation groove forming step 93 is performed before the element forming step 95. In the case of Example 1, it is desirable to perform the buried oxide film removing step 94 before the element forming step 95 as shown in FIG. By performing the process before forming the element, it is possible to eliminate the influence on the element due to the thermal load due to the element isolation trench formation and the removal of the buried oxide film. On the other hand, in the case of Example 2, since the buried oxide film is removed from the back surface, it is desirable to perform the buried oxide film removing step 94 after the completion of the wiring forming step 97 as shown in FIG. 8C and 8D, an element isolation groove forming step 93 is performed after the element forming step 95 and the contact forming step 96. In this case, in the first embodiment, the wiring process 97 is performed after the buried oxide film removing process 94. In the case of Example 2, since the buried oxide film is removed from the back surface, it is desirable to perform the buried oxide film removing step 94 after the completion of the wiring forming step 97 as shown in FIG.

  Although the embodiments of the present invention have been described above, the dimensions, shapes, arrangements, materials, and the like shown in the embodiments are examples, and the present invention is not limited to the embodiments, and is described in the claims. Various modifications can be made within the scope of the present invention.

11: Semiconductor layer, 12: Embedded insulating layer, 13: Semiconductor support substrate, 14: Field insulating film, 15: SiN insulating film, 17: Element isolation trench (cavity), 18: Insulating film, 20: Embedded insulating layer cavity region , 21: protective film, 22: through hole, 25/26: metal wiring layer, 27: interlayer insulating film, 28: via, 29: SiN insulating film.

Claims (9)

A semiconductor substrate;
A buried insulating layer formed on the semiconductor substrate;
A semiconductor layer formed on the buried insulating layer and on which an element is formed;
A groove formed in the element isolation region of the semiconductor layer and reaching the buried insulating layer;
A semiconductor device in which the groove and a partial region of the buried insulating layer in contact with the groove are hollow. In claim 1,
A semiconductor device in which one element is formed in the semiconductor layer surrounded by the hollowed groove and a partial region of the buried insulating layer. In claim 1,
A semiconductor device in which a plurality of elements are formed in the semiconductor layer surrounded by the hollowed groove and a partial region of the buried insulating layer. In claim 1,
A semiconductor device in which the groove is closed by an insulating film formed on the semiconductor layer. A method for manufacturing a semiconductor device having a semiconductor substrate, a buried insulating layer formed on the semiconductor substrate, and a semiconductor layer formed on the buried insulating layer,
Forming a trench reaching the buried insulating layer in the element isolation region of the semiconductor layer;
An oxide film is formed so as to fill the groove,
Forming a through hole reaching the buried insulating layer in the semiconductor substrate;
A method for manufacturing a semiconductor device, wherein a part of the buried insulating layer and an oxide film buried in the trench are removed from the through hole. In claim 5,
An SiN layer is provided in the groove,
A method of manufacturing a semiconductor device using the SiN layer as a stopper. In claim 5,
A method for manufacturing a semiconductor device, comprising: forming a wiring layer on the semiconductor layer; and removing a portion of the buried insulating layer and the oxide film buried in the trench. In claim 5,
A method of manufacturing a semiconductor device, wherein one element is formed in the semiconductor layer surrounded by the trench from which the oxide film has been removed and a partial region of the buried insulating layer. In claim 5,
A method of manufacturing a semiconductor device, wherein a plurality of elements are formed in the semiconductor layer surrounded by the trench from which the oxide film has been removed and a part of the buried insulating layer.