JP2011242838A - Memory interface circuit - Google Patents

Abstract

A circuit scale for controlling mask timing is realized with a small configuration.
A first element whose drive characteristics change according to a drive control code is compared with a second element whose drive characteristics are proportional to the characteristics of an I / O buffer, and whether the characteristics of both elements match. A drive adjustment buffer 20 that outputs an adjustment monitor signal indicating whether or not, a drive capability control circuit 14 that outputs a drive control code proportional to the characteristics of the I / O buffer according to the adjustment monitor signal, A delay control circuit 13 that outputs a delay control code corresponding to a delay value corresponding to one clock of the system clock according to the system clock, and a delay calculation circuit that calculates delay data based on the drive control code and the delay control code 16 and a mask control circuit 17 for controlling the mask timing of the data strobe signal at the time of reading based on the delay data. That.
[Selection] Figure 1

Description

  The present invention relates to a memory interface circuit, and more particularly to an interface circuit that performs read control of an SDRAM having a double data rate (hereinafter referred to as DDR) such as DDR, DDR2, and DDR3.

  In the semiconductor market, there is an increasing demand for low cost in every field, and the realization of a reduction in the scale of a circuit mounted on a chip is an issue. Memory interface circuits are used in a wide range of fields. Particularly, DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) occupies a high share in the memory market in recent years. Memory interface circuits are also expanding.

  However, as the memory speed has been increased, the memory scale of the DDR memory interface circuit has been increased in order to realize the required performance of the memory interface circuit. ) In the high impedance state, it is necessary to prevent data destruction due to the input of a glitch, but there was sufficient timing before, so the period of DQS high impedance state is simply masked. However, in recent years, the timing between the DQS at the time of reading and the clock for reading out has become stricter due to the speeding up of the memory. Therefore, the timing of the DQS and the clock has been increased. Masks the period of high-impedance state of DQS that accurately matches Signal generation of it has become necessary.

  As a memory interface circuit that masks the period of DQS in a high impedance state, for example, in Patent Document 1, an input receiver (buffer) 102 that receives a data strobe signal DQS and a mask control signal generation circuit 107 that generates a mask control signal REN. A delay circuit 104 that delays the input DQS and outputs it as a delay signal DQSD, an I / O replica circuit 103 that delays and outputs REN by an amount of delay corresponding to the input / output delay characteristics of the input / output buffer, and a replica circuit RENFB is output as a signal REND subjected to delay control following the DQS delay, and a mask signal is generated using REND as a reference timing, and the delay signal DQSD is masked for a predetermined period in accordance with the mask signal and a glitch Generates data strobe signal with removal of Memory interface circuit and a mask circuit 106 is disclosed that (see FIG. 9). That is, in the memory interface circuit described in Patent Document 1, the DQS input delay is realized by masking the high-impedance state of the DQS before and after reading and causing the I / O replica circuit 103 and the delay circuit 105 to follow. .

Japanese Patent Laying-Open No. 2009-9621 (FIG. 8)

  However, the memory interface circuit described in Patent Document 1 has a problem that the circuit scale increases. That is, in order to generate timing for performing mask control of the DQS of the memory, an I delay for following the output delay of the I / O buffer 109 for clock transmission of the controller and the input delay of the I / O buffer 102 for DQS reception. The / O replica circuit 103 and the variable delay circuit 104 that generates a delay corresponding to an external DQS delay are used. Since the I / O replica circuit 103 is composed of the same as the I / O buffers 102 and 109 and the variable delay circuit 104 needs to be composed of a large number of delay gates, the circuit scale becomes large.

  In the prior art, the circuit scale for controlling the mask timing cannot be realized with a small configuration.

  In one aspect of the present invention, in a memory interface circuit, a first element whose drive characteristics change according to a drive control code is compared with a second element whose drive characteristics are proportional to the characteristics of an I / O buffer. A drive adjustment buffer that outputs an adjustment monitor signal indicating whether or not the characteristics of the two elements match, and the characteristics of the I / O buffer according to the adjustment monitor signal from the drive adjustment buffer; A drive capability control circuit for outputting a drive control code in a proportional relationship; a delay control circuit for outputting a delay control code corresponding to a delay value corresponding to one clock of the system clock according to a system clock; and the drive capability A delay data based on the drive control code from the control circuit and the delay control code from the delay control circuit; And a mask control circuit for controlling a mask timing of a data strobe signal at the time of reading based on the delay data from the delay calculation circuit, and the first element includes the drive The drive characteristics vary according to the drive control code from the capability control circuit.

  In the memory interface circuit of the present invention, the delay calculation circuit includes an internal delay conversion table in which an internal delay value corresponding to a delay control code is set, and the delay control circuit outputs the internal delay conversion table based on the internal delay conversion table. A delay control code conversion circuit for converting a delay control code into the internal delay value and outputting the internal delay value; an I / O buffer delay conversion table in which an I / O buffer delay value corresponding to the drive control code is set; Drive control code conversion for converting the drive control code from the drive capability control circuit into the I / O buffer delay value and outputting the I / O buffer delay value based on the I / O buffer delay conversion table Circuit, the internal delay value from the delay control code conversion circuit, and the drive control code conversion circuit An adder for outputting the delayed data by adding the I / O buffer delay value, it is preferably provided with a.

  In the memory interface circuit of the present invention, the delay control circuit receives the system clock as an input, sequentially changes the delay of an internal variable delay circuit, and sets a delay corresponding to one clock of the system clock as an internal phase. Preferably, it is determined by comparison and detected and output as the delay control code.

  In the memory interface circuit of the present invention, the drive capability control circuit may output the drive control code when the characteristics of the input drive adjustment buffer match to the delay calculation circuit. preferable.

  In the memory interface circuit of the present invention, when the delay data from the delay calculation circuit is compared with a reference delay value from a clock, and the delay data is larger than the reference delay value, the data at the time of reading It is preferable to provide a mask control circuit that outputs a mask control signal for controlling the mask timing of the strobe signal with a delay by the reference delay value.

  In the memory interface circuit of the present invention, it is preferable that the reference delay value from the clock is a time of a half cycle unit from the system clock or an externally supplied clock signal.

  In the memory interface circuit of the present invention, it is preferable that the mask control circuit outputs the mask control signal in accordance with a frequency setting given from the outside.

  In the memory interface circuit of the present invention, it is preferable that the delay calculation circuit outputs a result of adding a flight time delay to the delay data in accordance with a flight time setting given from the outside.

  In the memory interface circuit of the present invention, the mask control signal is input from the mask control circuit, and the mask control signal is set to a mask release state in which the mask of the data strobe signal is released at the rising edge of the mask control signal. A mask signal generation circuit that outputs a mask signal for masking the data strobe signal at the falling edge of the next data strobe signal after the falling edge of the signal, and a clock signal obtained by inverting the system clock A clock generation circuit that outputs the data, a clock output buffer that receives the clock signal from the clock generation circuit and outputs the clock signal to the memory, and a data strobe that receives and outputs the data strobe signal output from the memory An input buffer and the mask signal Based on the mask signal from the generating circuit is preferably provided with an AND gate mask for masking the data strobe signal from the data strobe input buffer.

  In the memory interface circuit of the present invention, the internal delay value includes a delay value between the clock generation circuit and the clock output buffer, and a delay value between the data strobe input buffer and the mask AND gate. Preferably, the I / O buffer delay value is a total value of the delay value in the clock output buffer and the delay value in the data strobe input buffer.

  According to the present invention, the circuit scale can be reduced. The reason is that the mask timing is controlled by the delay calculation circuit without using the I / O replica circuit and the variable delay circuit having large circuit elements configured in the prior art. Further, according to the present invention, it is possible to prevent an increase in power consumption. The reason is that a plurality of I / O replica circuits and variable delay circuits mounted in the prior art must be mounted according to the bus width of the memory interface (usually one per 8 bits). This is because the circuit scale is constant regardless of the width.

1 is a block diagram schematically showing a configuration example of a memory interface circuit according to Embodiment 1 of the present invention. FIG. 3 is a block diagram schematically illustrating a configuration example of a delay calculation circuit in the memory interface circuit according to the first embodiment of the invention. FIG. 3 is a schematic diagram illustrating a configuration example of a mask signal generation circuit in the memory interface circuit according to the first embodiment of the invention. 4 is a graph schematically showing (A) an example of I / O delay characteristics for a drive control code and (B) an example of internal delay characteristics for a delay control code used in the memory interface circuit according to the first embodiment of the present invention. . 4 is a timing chart in an ideal state with no internal delay during an 8-burst read operation in the memory interface circuit according to the first embodiment of the invention. 5 is a timing chart showing mask operation timing when a delay A occurs in the memory interface circuit according to the first embodiment of the present invention. 3 is a timing chart showing mask operation timing when a delay B occurs in the memory interface circuit according to the first embodiment of the present invention. It is the block diagram which showed typically the example of 1 structure of the memory interface circuit based on Example 2 of this invention. It is the block diagram which showed typically the example of 1 structure of the memory interface circuit concerning a prior art example.

  In the memory interface circuit according to the embodiment of the present invention, the first element whose drive characteristics change according to the drive control code is compared with the second element whose drive characteristics are proportional to the characteristics of the I / O buffer, A drive adjustment buffer (20 in FIG. 1) that outputs an adjustment monitor signal indicating whether or not the characteristics of both elements match, and the I / O in accordance with the adjustment monitor signal from the drive adjustment buffer A drive capability control circuit (14 in FIG. 1) for outputting a drive control code proportional to the characteristics of the O buffer, and a delay control code corresponding to a delay value corresponding to one system clock according to the system clock Delay control circuit (13 in FIG. 1), the drive control code from the drive capability control circuit and the front from the delay control circuit A delay calculation circuit (16 in FIG. 1) that calculates delay data based on the delay control code, and a mask control that controls the mask timing of the data strobe signal at the time of reading based on the delay data from the delay calculation circuit Circuit (17 in FIG. 1), and the drive characteristics of the first element change according to the drive control code from the drive capability control circuit.

  A memory interface circuit according to a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram schematically showing a configuration example of the memory interface circuit according to the first embodiment of the present invention.

  The memory interface circuit 10 is a circuit for controlling reading (reading) of data from a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory; DDR2 SDRAM 24 in FIG. 1), and a data strobe for informing the timing of transferring the data DQ. The signal DQS is received, and data is received according to the data strobe signal DQS. The memory interface circuit 10 includes, as main components, a CK generation circuit 11, a read data capture circuit 12, a delay control circuit 13, a drive capability control circuit 14, a strobe signal variable delay circuit 15, and a delay calculation. A circuit 16, a mask control circuit 17, a mask signal generation circuit 18, a mask AND gate 19, a drive adjustment buffer 20, a DQS input buffer 21, a DQ input buffer 22, and a CK output buffer 23; Have.

  The CK generation circuit 11 receives the system clock, generates a CK signal based on the system clock, and outputs the generated CK signal to the CK output buffer 23. The system clock is a periodic signal used for timing (synchronization) in the system. The CK signal is a clock signal obtained by inverting the system clock.

  The read data fetch circuit 12 receives the DQIN signal from the DQ input buffer 22 and the DQSC signal from the strobe signal variable delay circuit 15 and outputs the DQIN signal to the RD1 terminal or the RD2 terminal according to the DQSC signal. . The read data fetch circuit 12 is a latch circuit composed of a D flip-flop circuit. The DQSC signal is input to the clock input terminal, the DQIN signal is latched at the rising edge of the DQSC signal, and output to the RD1 terminal. The DQIN signal is latched at the falling edge and output to the RD2 terminal (see FIG. 5).

  The delay control circuit 13 receives the system clock, generates a delay control code based on the system clock, and outputs the generated delay control code toward the strobe signal variable delay circuit 15 and the delay calculation circuit 16. The delay control circuit 13 sequentially changes the delay of the variable delay circuit inside the delay control circuit 13 and detects the delay by the internal phase comparison, thereby determining a delay corresponding to one system clock. The delay control circuit 13 outputs a delay control code corresponding to a delay value corresponding to one system clock to the strobe signal variable delay circuit 15. The delay control circuit 13 increases the delay control code when the delay of the circuit element of the strobe signal variable delay circuit 15 is small, and increases the delay of the circuit element of the strobe signal variable delay circuit 15 when the delay of the circuit element of the strobe signal variable delay circuit 15 is large. By setting the delay control code to a small value, the delay is controlled to be constant. The delay control code is a code for keeping the delay and phase of the strobe signal variable delay circuit 15 constant. Details of the delay control code will be described later (see FIG. 4B).

  The drive capacity control circuit 14 receives the adjustment monitor signal from the drive adjustment buffer 20, generates a drive control code in accordance with the adjustment monitor signal, and uses the generated drive control code as a delay calculation circuit 16 and a drive adjustment code. To the buffer 20 for output. The drive capability control circuit 14 sequentially changes the drive control code set in its own circuit in accordance with the adjustment monitor signal and outputs it to the delay calculation circuit 16 and the drive adjustment buffer 20. The drive capability control circuit 14 is characterized in that the characteristics of the first element whose drive characteristics change in the drive adjustment buffer 20 according to the drive control code and the second element of the drive characteristics proportional to the characteristics of the I / O buffer. The drive control code at the time of matching is output to the delay calculation circuit 16. The drive control code is a code for changing the drive adjustment buffer 20 so as to coincide with the second element having the drive characteristic proportional to the characteristic of the I / O buffer. Details of the drive control code will be described later (see FIG. 4A).

  The strobe signal variable delay circuit 15 receives the DQSM signal from the mask AND gate 19 and the delay control code from the delay control circuit 13, generates a DQSC signal based on the delay control code, and generates the generated DQSC. The signal is output to the read data fetch circuit 12. The DQSC signal is input to the read data fetch circuit 12 together with the DQIN signal from the DQ input buffer 22. The DQSC signal is a data strobe signal obtained by delaying the DQSM signal in accordance with the delay control code, and is a signal for latching the DQIN signal in the read data fetch circuit 12.

  The delay calculation circuit 16 receives the delay control code from the delay control circuit 13 and the drive control code from the drive capability control circuit 14 and calculates the delay data based on the delay control code and the drive control code. The delayed data is output to the mask control circuit 17. Details of the delay calculation circuit 16 will be described later (see FIG. 2). The delay data is data necessary for determining the mask timing of the DQSIN signal, and is a delay value corresponding to the internal delay of the memory interface circuit 10.

  The mask control circuit 17 receives the READ_RQ signal from the outside, the delay data from the delay calculation circuit 16, and the system clock, and generates and generates the MSKCTR signal based on the READ_RQ signal, the delay data, and the system clock. The MSKCTR signal is output to the mask signal generation circuit 18. The mask control circuit 17 controls the timing of the DQS mask according to the delay data. The mask control circuit 17 compares the delay data from the delay calculation circuit 16 with a reference delay value from the system clock (time in half cycle units from the system clock), and when the delay data is larger than the reference delay value, The MSKCTR signal is output after being delayed by the reference delay value. The READ_RQ signal is a read request signal input from the outside. The MSKCTR signal is a signal for controlling the timing for masking the high impedance state of the DQSIN signal.

  The mask signal generation circuit 18 receives an external RSTB signal, a DQSM signal from the mask AND gate 19, and an MSKCTR signal from the mask control circuit 17, and based on the RSTB signal, the DQSM signal, and the MSKCTR signal. A MASKB signal is generated, and the generated MASKB signal is output to the masking AND gate 19. The RSTB signal is a reset signal input from the outside, and is a signal for forcibly returning the internal state register of the mask signal generation circuit 18 to the initial state when it is “L”. The MASKB signal is a signal for masking the high impedance state of the DQSIN signal when it is “L”.

  The mask AND gate 19 receives the DQSIN signal from the DQS input buffer 21 and the MASKB signal from the mask signal generation circuit 18 and outputs a DQSM signal based on the DQSIN signal and the MASKB signal. The DQSM signal output from the mask AND gate 19 is fed back to the mask signal generation circuit 18 and input to the strobe signal variable delay circuit 15. The DQSM signal is a data strobe signal that masks the high impedance state in the DQSIN signal.

  The drive adjustment buffer 20 receives the drive control code from the drive capability control circuit 14, generates an adjustment monitor signal based on the drive control code, and directs the generated adjustment monitor signal to the drive capability control circuit 14. Output. The drive adjustment buffer 20 compares the first element whose drive characteristics change according to the drive control code with the second element whose drive characteristics are proportional to the characteristics of the I / O buffer, and the characteristics match. Is fed back to the drive capability control circuit 14 as an adjustment monitor signal. The adjustment monitor signal compares the characteristics of the first element whose drive characteristics change according to the drive control code with the second element whose drive characteristics are proportional to the characteristics of the I / O buffer. It is a signal for indicating whether or not.

  The DQS input buffer 21 receives the data strobe signal output from the DQS terminal of the DDR2 SDRAM 24 and outputs the DQSIN signal to the masking AND gate 19. The DQSIN signal is a data strobe signal for notifying the timing for transferring the data DQ output from the DQS terminal of the DDR2 SDRAM 24 via the DQS input buffer 21.

  The DQ input buffer 22 receives the data signal output from the DQ terminal of the DDR2 SDRAM 24 and outputs the DQIN signal to the read data fetch circuit 12. The DQIN signal is a data signal output from the DQ terminal of the DDR2 SDRAM 24 via the DQ input buffer 22.

  The CK output buffer 23 receives the CK signal from the CK generation circuit 11 and outputs the received CK signal toward the CK terminal of the DDR2 SDRAM 24.

  The DDR2 SDRAM 24 reads the data stored in the memory in response to the CK signal from the memory interface circuit 10, and outputs the data strobe signal DQS for notifying the timing of transferring the data DQ together with the read data DQ to the memory interface circuit. Output to 10.

  Next, a delay calculation circuit in the memory interface circuit according to the first embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a block diagram schematically showing a configuration example of the delay calculation circuit in the memory interface circuit according to the first embodiment of the present invention.

  The delay calculation circuit 16 includes an internal delay conversion table 31, a delay control code conversion circuit 32, a drive control code conversion circuit 33, an I / O buffer delay conversion table 34, and an adder 35 as components. .

  The drive control code conversion circuit 33 receives the drive control code (corresponding to the I / O delay) from the drive capability control circuit (14 in FIG. 1), and converts the input drive control code into the I / O buffer delay conversion table 34. Output to.

  In the I / O buffer delay conversion table 34, an I / O buffer delay value corresponding to the drive control code is set in advance, the drive control code from the drive control code conversion circuit 33 is input, and the input drive control code is input. I / O buffer delay value (corresponding to the sum of the I / O delay in the CK output buffer (23 in FIG. 1) and the I / O delay in the DQS input buffer (21 in FIG. 1) corresponding to I / O delay ”is extracted, and the extracted I / O buffer delay value is output to the drive control code conversion circuit 33.

  The drive control code conversion circuit 33 outputs the I / O buffer delay value from the I / O buffer delay conversion table 34 to the adder 35.

  The delay control code conversion circuit 32 receives the delay control code (code proportional to the internal delay) from the delay control circuit (13 in FIG. 1) and outputs the input delay control code toward the internal delay conversion table 31. To do.

  In the internal delay conversion table 31, an internal delay value corresponding to the delay control code is set in advance, the delay control code from the delay control code conversion circuit 32 is input, and the internal delay value corresponding to the input delay control code (Corresponding to the sum of the delay from the output of the CK generation circuit (11 in FIG. 1) to the CK output buffer (23 in FIG. 1) and the delay from the DQS input buffer 21 to the masking AND gate 19) And the extracted internal delay value is output to the delay control code conversion circuit 32.

  The delay control code conversion circuit 32 outputs the internal delay value from the internal delay conversion table 31 to the adder 35.

  The adder 35 is a delay data obtained by adding the I / O buffer delay value corresponding to the I / O delay from the drive control code conversion circuit 33 and the internal delay value corresponding to the internal delay from the delay control code conversion circuit 32. And the calculated delay data is output to the mask control circuit (17 in FIG. 1).

  Next, a mask signal generation circuit in the memory interface circuit according to the first embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a schematic diagram illustrating a configuration example of the mask signal generation circuit in the memory interface circuit according to the first embodiment of the present invention.

  The mask signal generation circuit 18 includes a flip-flop 41. In the flip-flop 41, the MSKCTR signal from the mask control circuit (17 in FIG. 1) is input to the S input terminal (set input terminal), the “L” state signal is input to the D input terminal, and the clock input terminal The DQSM signal from the mask AND gate (19 in FIG. 1) is input, the RSTB signal from the outside is input to the RB input terminal (reset terminal), and the mask AND gate (19 in FIG. 1) is input from the Q output terminal. ) To output a MASKB signal. When the MSKCTR signal is input to the S input terminal of the flip-flop 41, the DQS mask is released with the MASKB signal being “H” at the rise of the MSKCTR signal, and at the fall of the next DQSM signal after the fall of the MSKCTR signal. The DQS mask state in which the MASKB signal is “L” is entered (see FIG. 5).

  Next, drive control codes and delay control codes used in the memory interface circuit according to the first embodiment of the present invention will be described with reference to the drawings. FIG. 4 schematically shows (A) an example of I / O delay characteristics for the drive control code and (B) an example of internal delay characteristics for the delay control code used in the memory interface circuit according to the first embodiment of the invention. It is a graph.

  The drive control code is changed in the drive adjustment buffer (20 in FIG. 1) so as to coincide with the second element of the drive characteristic proportional to the characteristic of the I / O buffer. Therefore, the drive control code and the I / O buffer delay value (I / O delay value) have a proportional relationship as shown in the graph of FIG. An I / O buffer delay value can be obtained by obtaining a drive control code that matches the second element having a drive characteristic proportional to the I / O buffer characteristic.

  The delay control code is set to a large value when the delay of the circuit element of the strobe signal variable delay circuit (15 in FIG. 1) becomes small, and the delay of the circuit element of the strobe signal variable delay circuit (15 of FIG. 1) is reduced. If it becomes larger, the value is made smaller. Thus, since the delay is controlled to be constant, the delay control code and the delay value of the internal circuit are the delay control code and the delay value of the internal circuit (internal delay value) as shown in the graph of FIG. ) Relationship is obtained. Thereby, the delay value of the internal circuit can be obtained from the delay control code.

  The delay control circuit (13 in FIG. 1) outputs a delay control code so as to keep the delay and phase of the strobe signal variable delay circuit (15 in FIG. 1) constant. Therefore, if the delay of the DQS path route required for mask control and the delay of the variable delay circuit are compared, the relationship of the delay value of the path route to the delay control code is shown in FIG. It can be obtained like a graph of control code and internal delay value.

  Similarly, the portion of the CK output buffer (23 in FIG. 1) and the DQS input buffer (21 in FIG. 1) with respect to the I / O buffer delay shows the relationship of the I / O buffer delay value to the drive adjustment code in FIG. It is obtained like the graph of A) drive control code and I / O delay value.

  These delays can be calculated by the delay calculation circuit (16 in FIG. 1) to obtain the sum of the path delay values of the DQS, and the high impedance of the DQS can be obtained from the sum of the path delay values by the mask control circuit (17 in FIG. 1). The MASKB signal that masks the state can be controlled.

  Next, the operation of the memory interface circuit according to the first embodiment of the present invention will be described.

  First, the operation of an ideal state memory interface circuit without internal delay during burst read operation will be described with reference to the drawings. FIG. 5 is a timing chart in an ideal state with no internal delay during the burst read operation in the memory interface circuit according to the first embodiment of the present invention.

  The READ_RQ signal becomes “H” in accordance with the read burst length from the timing T1 of the system clock (CLK). As a result, the mask control circuit (17 in FIG. 1) outputs the MSKCTR signal from the READ_RQ signal. The MSKCTR signal becomes “H” at the timing T2 of the system clock (CLK), which is the middle of the read DQS preamble period, and becomes “L” at the timing T5 of the system clock (CLK).

  In the variable delay circuit for strobe signal (15 in FIG. 1), the DQSC signal obtained by delaying the DQSM signal by 1/4 clock so that the change of the DQSC signal becomes the center of the data change of the DQIN signal is input to the read data fetch circuit 12. Output toward. The read data fetch circuit (12 in FIG. 1) latches the DQIN signal at the rising edge of the DQSC signal and outputs it to RD1, latches the DQIN signal at the falling edge of the DQSC signal, and outputs it to RD2.

  In an ideal state, a DQSC signal is generated by delaying the DQSM signal output from the mask AND gate (19 in FIG. 1) by 1/4 clock by the strobe signal variable delay circuit (15 in FIG. 1). Accordingly, the correct data can be output by latching the DQIN signal output from the DQ input buffer 22 by the read data fetch circuit (12 in FIG. 1).

  Next, an operation when a delay occurs in the DQS signal due to an internal delay and an I / O delay will be described with reference to the drawings. FIG. 6 is a timing chart showing mask operation timings when a delay A occurs in the memory interface circuit according to the first embodiment of the present invention. FIG. 7 is a timing chart showing the mask operation timing when the delay B occurs in the memory interface circuit according to the first embodiment of the present invention.

  When the delay A, which is the sum of the delay value corresponding to the internal delay and the delay value corresponding to the I / O delay, is smaller than ½ period of the system clock CLK, that is, the delay of the delay calculation circuit (16 in FIG. 1). When the data has a value smaller than the delay of a half cycle of the system clock, the timing of the MSKCTR signal output from the mask control circuit (17 in FIG. 1) is made the same as the ideal state. At this time, the time Y1 which is the interval between the mask release timing of FIG. 6 and the high impedance state of DQS (delay A) is smaller than the ideal state of FIG. There is no propagation of impedance inside.

  When the delay B, which is the sum of the delay value corresponding to the internal delay and the delay value corresponding to the I / O delay, is larger than ½ period of the system clock, that is, the delay data of the delay calculation circuit (16 in FIG. 1). Is larger than the delay of 1/2 cycle of the system clock CLK, the timing of the MSKCTR signal output from the mask control circuit (17 in FIG. 1) is delayed from the ideal state by 1/2 clock of the system clock CLK. By setting the timing, the MSKCTR signal rises at the timing T3 and falls at the timing T6. In this case, since there is a margin indicated by time Y2 between the mask release timing of T3 when the MASKB signal rises and the high impedance state of DQS (delay B), there is no propagation of high impedance inside.

  As described above, the mask control circuit (17 in FIG. 1) generates the mask release timing in accordance with the DQS delay, whereby the DQS can be masked in the high impedance state at the time of reading.

  Further, as in the operation timing of FIG. 7, the mask release timing of the MASKB signal can be controlled to the center side of the preamble period so as not to be in the high impedance state of the DQS. (103 in FIG. 9), mask timing control can be realized with a small circuit scale without using a large circuit element such as a variable delay circuit (105 in FIG. 9).

  In the mask release timing adjustment step, the clock is 1/2 of the system clock CLK, but the clock may be controlled in finer steps by using a clock faster than the system clock CLK. It is also possible to increase the adjustment range by increasing the number of steps.

  According to the first embodiment, the following effects can be obtained.

  As a first effect, the circuit scale can be reduced. The reason is that a delay calculation circuit (16 in FIG. 1) is used without using an I / O replica circuit (103 in FIG. 9) and a variable delay circuit (105 in FIG. 9) having a large circuit element configured in the conventional example. This is because the timing of the mask control circuit (17 in FIG. 1) is controlled by.

  As a second effect, an increase in power consumption can be prevented. The reason is that a plurality of I / O replica circuits (103 in FIG. 9) and variable delay circuits (105 in FIG. 9) mounted in the conventional example are mounted according to the memory interface bus width (usually one per 8-bit). This is because the circuit scale is constant regardless of the bus width in the first embodiment.

  A memory interface circuit according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 8 is a block diagram schematically showing a configuration example of the memory interface circuit according to the second embodiment of the present invention.

  The second embodiment is a modification of the first embodiment. In the mask control circuit (17 in FIG. 1) of the first embodiment, an MCLK signal for a mask timing adjustment clock provided from the outside and an input terminal for frequency setting are added. Using the mask control circuit 37, a delay calculation circuit 36 in which an input terminal for setting a flight time is added to the delay calculation circuit (16 in FIG. 1) of the first embodiment is used. Other configurations are the same as those of the first embodiment.

  The flight time is a transmission path delay on a printed circuit board (not shown) from the CK terminal of the memory interface circuit 10 to the CK terminal of the DDR2 SDRAM 24 and from the DQS terminal of the DDR2 SDRAM 24 to the DQS terminal of the memory interface circuit 10. Refers to the sum of

  The mask control circuit 37 operates the MSKCTR signal at a timing synchronized with the MCLK signal instead of the system clock. Further, the mask control circuit 37 enables selection of control at the timing step of the MSKCTR signal according to the setting by inputting the frequency setting.

  The delay calculation circuit 36 outputs the result of adding the flight time delay to the delay data in the first embodiment.

  According to the second embodiment, the same effect as that of the first embodiment can be obtained, and the MSKCTR signal can operate in synchronization with the MCLK signal. Therefore, by inputting a frequency higher than the system clock to the MCLK signal. The control step of the MSKCTR signal can be set in detail. Therefore, it can cope with high-speed operation. In addition, by inputting the frequency setting to the mask control circuit 37, the control of the MSKCTR signal can be made at an optimal timing according to the operating frequency, so that it is possible to deal with systems having various operating frequencies. Further, by adding a flight time setting to the delay calculation circuit 36, it is possible to deal with a system having various flight times.

DESCRIPTION OF SYMBOLS 10 Memory interface circuit 11 CK generation circuit 12 Read data taking-in circuit 13 Delay control circuit 14 Drive capability control circuit 15 Strobe signal variable delay circuit 16 Delay calculation circuit 17 Mask control circuit 18 Mask signal generation circuit 19 Mask AND gate 20 Drive Adjustment buffer 21 DQS input buffer 22 DQ input buffer 23 CK output buffer 24 DDR2 SDRAM
31 Internal delay conversion table 32 Delay control code conversion circuit 33 Drive control code conversion circuit 34 I / O buffer delay conversion table 35 Adder 36 Delay calculation circuit 37 Mask control circuit 41 Flip-flop 100 Memory interface circuit 101 Data input / output (I / O) O) Receiver (buffer)
102 Data strobe signal I / O receiver (buffer)
103 I / O replica circuit 104, 105 Variable delay circuit 106 Data strobe signal (DQS) mask circuit 1061 AND circuit 1062 Mask signal generation circuit 107 Mask control signal generation circuit 108 Read data resynchronization circuit 1081 FIFO write strobe generation circuit 1082 Synchronous strobe control circuit 1083 FIFO register 1084 Resynchronization register 109 Clock transmission I / O buffer 110 Clock generation circuit

Claims (10)

The first element whose drive characteristics change according to the drive control code is compared with the second element whose drive characteristics are proportional to the characteristics of the I / O buffer, and indicates whether or not the characteristics of both elements match. A drive adjustment buffer for outputting an adjustment monitor signal;
A drive capability control circuit for outputting a drive control code proportional to the characteristics of the I / O buffer in response to the adjustment monitor signal from the drive adjustment buffer;
A delay control circuit that outputs a delay control code corresponding to a delay value corresponding to one clock of the system clock according to a system clock;
A delay calculation circuit for calculating delay data based on the drive control code from the drive capability control circuit and the delay control code from the delay control circuit;
A mask control circuit for controlling a mask timing of a data strobe signal at the time of reading based on the delay data from the delay calculation circuit;
With
The memory interface circuit according to claim 1, wherein a drive characteristic of the first element changes according to the drive control code from the drive capability control circuit. The delay calculation circuit includes:
An internal delay conversion table in which an internal delay value corresponding to the delay control code is set;
A delay control code conversion circuit that converts the delay control code from the delay control circuit into the internal delay value based on the internal delay conversion table and outputs the internal delay value;
An I / O buffer delay conversion table in which an I / O buffer delay value corresponding to the drive control code is set;
Drive control code conversion circuit for converting the drive control code from the drive capability control circuit into the I / O buffer delay value based on the I / O buffer delay conversion table and outputting the I / O buffer delay value When,
An adder that adds the internal delay value from the delay control code conversion circuit and the I / O buffer delay value from the drive control code conversion circuit to output the delay data;
The memory interface circuit according to claim 1, further comprising:   The delay control circuit is determined by detecting the delay corresponding to one clock of the system clock by comparing with the internal phase by sequentially changing the delay of the internal variable delay circuit with the system clock as an input. 3. The memory interface circuit according to claim 1, wherein the memory interface circuit outputs the delay control code.   4. The drive capability control circuit according to claim 1, wherein the drive control code is output to the delay calculation circuit when the characteristics of the input drive adjustment buffer are the same. The memory interface circuit according to any one of the above.   A mask that controls the mask timing of the data strobe signal at the time of reading when the delay data from the delay calculation circuit is compared with a reference delay value from a clock and the delay data is larger than the reference delay value. 5. The memory interface circuit according to claim 1, further comprising a mask control circuit that outputs a control signal delayed by the reference delay value. 6.   6. The memory interface circuit according to claim 5, wherein the reference delay value from the clock is a time of a half cycle unit from the system clock or an externally applied clock signal.   7. The memory interface circuit according to claim 5, wherein the mask control circuit outputs the mask control signal in accordance with a frequency setting given from outside.   8. The delay calculation circuit according to claim 1, wherein the delay calculation circuit outputs a result obtained by adding a flight time delay to the delay data according to a flight time setting given from the outside. Memory interface circuit. The mask control signal from the mask control circuit is input, the mask of the data strobe signal is canceled at the rising edge of the mask control signal, and the next data after the falling edge of the mask control signal is set. A mask signal generation circuit that outputs a mask signal for masking the data strobe signal at the falling edge of the strobe signal; and
A clock generation circuit that generates and outputs a clock signal obtained by inverting the system clock; and
A clock output buffer that receives the clock signal from the clock generation circuit and outputs the clock signal to a memory;
A data strobe input buffer for receiving and outputting the data strobe signal output from the memory;
A mask AND gate for masking the data strobe signal from the data strobe input buffer based on the mask signal from the mask signal generation circuit;
The memory interface circuit according to claim 5, further comprising: The internal delay value is a total value of a delay value between the clock generation circuit and the clock output buffer and a delay value between the data strobe input buffer and the mask AND gate,
10. The memory interface circuit according to claim 9, wherein the I / O buffer delay value is a total value of a delay value in the clock output buffer and a delay value in the data strobe input buffer.

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