CN1983446A - Memory controller and its control method - Google Patents

Abstract

A memory controller and a control method thereof. The memory controller includes a control logic circuit, a phase-locked loop and a multiplexer. The phase-locked loop generates a plurality of phase clock signals according to the system clock signal, the phase clock signals have the same frequency as the system clock signal, and the phase clock signals have different phase differences. The multiplexer receives the phase clock signals, and selects one of the phase clock signals to output under the control of the control logic circuit so as to generate a selected phase clock signal.

Description

Memory controller and its control method

technical field

The present invention relates to a memory controller and its method, and in particular to a DDR SDRAM memory controller and its method.

Background technique

Please refer to FIG. 1 , which shows a block diagram of a known memory controller. The memory controller 100 includes a control logic circuit 110 , flip-flops 120 , 130 and buffers 141 - 143 . When data is transmitted, the content of the transmitted data needs to be captured, and corresponding capture signals must be generated accordingly. The acquisition signal needs to be delayed according to the demand.

The control logic circuit 110 outputs a control signal C011. The flip-flop 120 receives the control signal C011 and the system clock signal Clk11 to generate the control signal C012 to the flip-flop 130 . The flip-flop 120 receives the control signal C012 and the delayed system clock signal Clk12 to generate the control signal C012 for output.

The delayed system clock signal Clk12 is generated by the system clock signal Clk11 through the buffers 141 to 143 . Taking the system clock signal of 100Mhz as an example, if the delayed system clock signal Clk12 has a 1/4 cycle delay, that is, 2.5ns. Need to adjust the buffer, and consider the delay caused by the line itself. And every fine-tuning requires precise simulation and circuit layout. If the frequency is changed to 80Mhz, the original 2.5ns is not applicable. Therefore, the frequency of this known memory controller cannot be changed arbitrarily.

Please refer to FIG. 2 , which shows a block diagram of another known memory controller. The difference between the memory controller 200 and the memory controller 100 in FIG. 1 is that the generation of the system clock signal Clk13 after the delay of the input flip-flop 130 is to make the system clock signal Clk11 pass through the buffers 241 to 244 and then pass through the multiplexer. 245 selects how many buffers to delay the generated clock signal to output the delayed system clock signal Clk13 to the flip-flop 130 . Although the degree of delay of the system clock signal can be selected through the multiplexer, the accuracy of the delay phase is still determined by the buffering time and quantity of the buffer itself, and the effect is not as expected. Moreover, the above-mentioned known technologies are easily affected by variables such as manufacturing process, temperature, and voltage, and it is difficult to increase the speed.

Contents of the invention

In view of this, the object of the present invention is to provide a memory controller and a control method thereof. The signal delay phase can be adjusted according to the system requirements. And the main frequency can be changed according to the system requirements without resetting the delay phase.

According to the object of the present invention, a memory controller is proposed, including a control logic circuit, a phase-locked loop and a multiplexer. The phase-locked loop generates a plurality of phase clock signals according to the system clock signal. These phase clock signals have the same frequency as the system clock signal, and these phase clock signals have different phase differences. The multiplexer receives these phase clock signals, and under the control of the control logic circuit, selects an output of these phase clock signals to generate a selected phase clock signal.

According to another object of the present invention, a memory control method for a memory controller is provided. Firstly, a phase-locked loop is used to generate multiple phase clock signals according to the system clock signal. These phase clock signals have the same frequency as the system clock signal, and these phase clock signals have different phase differences from each other. Afterwards, an output of the phase clock signals is selected to generate a selected phase clock signal.

In order to make the above-mentioned purposes, features, and advantages of the present invention more comprehensible, a preferred embodiment is specifically cited below, together with the accompanying drawings, as follows:

Description of drawings

FIG. 1 shows a block diagram of a known memory controller. .

FIG. 2 is a block diagram of another known memory controller.

FIG. 3 is a block diagram of a memory controller according to a preferred embodiment of the present invention.

FIG. 4 is a block diagram of a memory controller according to a second embodiment of the present invention.

Detailed ways

Please refer to FIG. 3 , which shows a block diagram of a memory controller according to a preferred embodiment of the present invention. The memory controller 300 includes a control logic circuit 310 , a phase locked loop 320 (Phase Locked Loop, PLL) and a multiplexer 330 . The phase locked loop 320 generates a plurality of phase clock signals Cmp according to the system clock signal Clk31. The phase clock signals Cmp and the system clock signal Clk31 have the same frequency, and the phase clock signals have different phase differences. The multiplexer 330 receives the phase clock signal Cmp, and under the control of the signal Clkse of the control logic circuit 310 , selects one of the phase clock signals Cmp to output to generate a selected phase clock signal Clk32.

The selected post-phase clock signal Clk32 is used as a clock signal, or used as a strobe signal. The output of the multiplexer 330 can be adjusted according to the required delay of the clock signal or the required delay period of the flash control signal.

The memory controller 300 is used, for example, in a double synchronous dynamic random access memory (Double Data Rate SDRAM, DDR SDRAM). If the rear-phase clock signal Clk32 is selected as the flash control signal, in the demand of DDRSDRAM, the middle segment of the data signal is required to retrieve data, and the system clock signal is delayed by 1/4 period. Because DDR SDRAM uses double-edge clock conversion (Double Transitlon Clocking) technology, the trigger transmission is triggered on the rising edge (Raising edge) and the falling edge (Falling edge) of the system clock signal, that is, it needs to be triggered about every 1/2 cycle. The flash control signal needs to be in the middle of the data, that is, 1/4 cycle to acquire data.

DDR SDRAM is the memory architecture of the next generation of Synchronized Dynamic Random Access Memory (SDRAM). Compared with DDR SDRAM and SDRAM, the transmission speed of DDR SDRAM is twice that of SDRAM. If the clock frequency of SDRAM is 66Mhz, and the transmission time interval is 15ns. For DDR SDRAM, the interval of data transmission time is 7.5ns, and the transmission frequency can reach 133Mhz.

The principle of DDR SDRAM is as mentioned above, the transmission data is collected in the same clock cycle, and both the upper and lower bands are doing data transmission work, and compared with SDRAM, which only transmits data once in the same clock cycle, the efficiency of DDR SDRAM is Twice that of SDRAM.

The phase-locked loop 320 pulls out the multiple phases inside it to generate a clock signal with multiple phases but still the same frequency, that is, the above-mentioned clock signal Cmp of each phase. In this embodiment, there are eight phase clock signals Cmp, which are respectively delayed by 1/8 cycle, 2/8 cycle to 7/8 cycle. All the phase relationships in the phase-locked loop 320 are always fixed regardless of any frequency, so the selected phase clock signal will not be affected by the frequency. The frequency of the phase clock signal Cmp is equal to that of the system clock signal Clk31.

If the frequency of the memory must correspond to the replacement of the system, or when the frequency is increased or decreased due to environmental influences, the relative phase of the signal will not be affected. And the system will automatically align the phase required by the control signal without software re-adjustment.

Please refer to FIG. 4 , which shows a block diagram of a memory controller according to a second embodiment of the present invention. The difference from the previous embodiment is that this embodiment further includes triggers 410 and 420 . The flip-flop 410 receives the system clock signal Clk31 and the first signal Co31 of the control logic circuit 310 to output the second signal Co32. The flip-flop 420 receives the second signal Co32 and the selected phase clock signal Clk32 to generate the third signal S3. The third signal S3 is, for example, used as a control signal, such as a read signal, a write signal or an address signal.

The memory controller and its control method disclosed in the above embodiments of the present invention can adjust the signal delay phase according to the system requirements. Moreover, the main frequency can be changed according to the system requirements without resetting the delay phase, and it is not necessary to cooperate with different frequencies to change the delay time required for the signal as in the known practice.

In summary, although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Anyone familiar with the technical field may make various modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the scope of the appended patent application.

Claims (10)

1. A memory controller, comprising: a control logic circuit; a phase-locked loop for generating a plurality of phase clock signals based on a system clock signal, the phase clock signals having the same frequency as the system clock signal, and the phase clock signals having different phase differences from each other; and A multiplexer receives the phase clock signals, and under the control of the control logic circuit, selects one of the phase clock signals to output to generate a selected phase clock signal. 2. The controller of claim 1, wherein the selected phase clock signal is used as a clock signal. 3. The controller according to claim 1, wherein the selected phase clock signal is used as a flash control signal. 4. The controller of claim 1, further comprising: a first flip-flop receives the system clock signal and a first signal of the control logic circuit to output a second signal; and A second flip-flop receives the second signal and the selected phase clock signal to generate a third signal. 5. The controller as claimed in claim 1, wherein the third signal is used as a control signal. 6. The controller according to claim 1, wherein it is used in double synchronous dynamic random access memory. 7. A memory control method for a memory controller, comprising: using a phase-locked loop to generate a plurality of phase clock signals according to a system clock signal, these phase clock signals have the same frequency as the system clock signal, and these phase clock signals have different phase differences from each other; and One of the phase clock signals is selected for output to generate a selected phase clock signal. 8. The control method according to claim 7, wherein the selected phase clock signal is used as a clock signal. 9. The control method according to claim 7, wherein the selected phase clock signal is used as a flash control signal. 10. The control method according to claim 7, wherein the memory controller is used in DDR SDRAM.

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