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JP2011199187A - Gallium nitride based semiconductor diode - Google Patents

Gallium nitride based semiconductor diode Download PDF

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JP2011199187A
JP2011199187A JP2010066803A JP2010066803A JP2011199187A JP 2011199187 A JP2011199187 A JP 2011199187A JP 2010066803 A JP2010066803 A JP 2010066803A JP 2010066803 A JP2010066803 A JP 2010066803A JP 2011199187 A JP2011199187 A JP 2011199187A
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gallium nitride
resistivity
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semiconductor diode
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Naoki Kaneda
直樹 金田
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Hitachi Cable Ltd
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Abstract

【課題】面内の抵抗率が不均一である窒化ガリウム基板上に形成したダイオード構造の耐圧を向上させることができる窒化ガリウム系半導体ダイオードを提供する。
【解決手段】半導体ダイオード1は、主面がC面である窒化ガリウム自立基板10と、pn接合16a又はショットキー接合16を含む接合領域と、窒化ガリウム自立基板と接合領域との間に設けられ、窒化ガリウム自立基板表面の基板面内での最小抵抗率より低い抵抗率を有し、窒化ガリウム自立基板の導電型と同一の導電型の半導体層14とを備える。
【選択図】図3
Disclosed is a gallium nitride based semiconductor diode capable of improving the breakdown voltage of a diode structure formed on a gallium nitride substrate having nonuniform in-plane resistivity.
A semiconductor diode 1 is provided between a gallium nitride free-standing substrate 10 whose main surface is a C-plane, a junction region including a pn junction 16a or a Schottky junction 16, and a gallium nitride free-standing substrate and the junction region. And a semiconductor layer 14 having a conductivity lower than the minimum resistivity of the surface of the gallium nitride free-standing substrate in the substrate plane and having the same conductivity type as that of the gallium nitride free-standing substrate.
[Selection] Figure 3

Description

本発明は、窒化ガリウム系半導体ダイオードに関する。特に、本発明は、耐圧を向上させた窒化ガリウム系半導体ダイオードに関する。   The present invention relates to a gallium nitride based semiconductor diode. In particular, the present invention relates to a gallium nitride based semiconductor diode with improved breakdown voltage.

従来、窒化ガリウム基板であって、基板表面において、基板面を貫通して伸びる多数の欠陥の集合した芯を内部に含み結晶粒界により区別される閉じた領域である閉鎖欠陥集合領域と、閉鎖欠陥集合領域に随伴しその周囲に形成された単結晶低転位随伴領域と、単結晶低転位随伴領域の外部に存在し同一の結晶方位を有する単結晶低転位余領域とを有する単結晶窒化ガリウム基板が知られている(例えば、特許文献1参照。)。   2. Description of the Related Art Conventionally, a gallium nitride substrate is a closed defect collection region that is a closed region that includes a core in which a large number of defects extending through the substrate surface are aggregated and is distinguished by a grain boundary on the substrate surface, Single-crystal gallium nitride having a single-crystal low dislocation-accompaniment region associated with a defect-gathering region and a single-crystal low-dislocation residual region existing outside the single-crystal low-dislocation accompaniment region and having the same crystal orientation A substrate is known (for example, refer to Patent Document 1).

また、III族窒化物半導体からなる下地層と、下地層の上に形成された空隙形成阻止層と、空隙形成阻止層の上に形成された多孔質III族窒化物半導体層と、多孔質III族窒化物半導体層の上に形成された多孔質金属層とを有するエピタキシャル成長用多孔質基板が知られている(例えば、特許文献2参照。)。   Also, a base layer made of a group III nitride semiconductor, a void formation blocking layer formed on the base layer, a porous group III nitride semiconductor layer formed on the void formation blocking layer, and a porous III A porous substrate for epitaxial growth having a porous metal layer formed on a group nitride semiconductor layer is known (see, for example, Patent Document 2).

特許文献1に記載の単結晶窒化ガリウム基板によれば、ファセット面からなるピット中央の転位集合部の面状欠陥を消滅させること等ができる。また、特許文献2に記載のエピタキシャル成長用多孔質基板によれば、低転位密度のエピタキシャル結晶成長を実現することができる。   According to the single-crystal gallium nitride substrate described in Patent Document 1, it is possible to eliminate the planar defects at the dislocation gathering portion at the center of the pit composed of the facet surface. Moreover, according to the porous substrate for epitaxial growth described in Patent Document 2, epitaxial crystal growth with a low dislocation density can be realized.

特開2003−165799号公報JP 2003-165799 A 特開2004−319711号公報JP 2004-319711 A

現在、入手可能な窒化ガリウム基板は転位密度が比較的高く、その上、転位密度が基板面内に不均一に分布している。更に、当該窒化ガリウム基板は、導電性基板であるにもかかわらず、基板面内で導電率がやや不均一である。   Currently available gallium nitride substrates have a relatively high dislocation density, and in addition, the dislocation density is unevenly distributed in the substrate plane. Furthermore, although the gallium nitride substrate is a conductive substrate, the conductivity is slightly nonuniform within the substrate surface.

本発明者が特許文献1に記載されている方法を参考に塩化物気相成長法(HVPE法)によって窒化ガリウム基板を作製したところ、C面成長している箇所と、C面成長していない箇所(ファセットを形成しながら成長している箇所)とでは、結晶中の不純物濃度が大きく異なることを発見した。一般に、成長面が異なることで不純物濃度の取り込み効率は大きく異なることが知られている。そして、HVPE法で成長した窒化ガリウムの場合は、特に酸素(O)の取り込みの効率に大きな差異が認められた。中でもC面成長していない箇所では酸素(O)濃度は約0.1〜1E19cm−3になっていることが測定された。この箇所の電気的特性を測定したところ、この箇所はn型導電性を示し、抵抗率は約0.02〜0.003Ω・cmであった。 The inventor made a gallium nitride substrate by the chloride vapor phase epitaxy method (HVPE method) with reference to the method described in Patent Document 1. As a result, the C plane was not grown and the C plane was not grown. It was discovered that the concentration of impurities in the crystal was significantly different from the location (location growing while forming facets). In general, it is known that the impurity concentration incorporation efficiency varies greatly depending on the growth surface. In the case of gallium nitride grown by the HVPE method, a large difference was observed particularly in the efficiency of oxygen (O) incorporation. In particular, it was measured that the oxygen (O) concentration was about 0.1 to 1E19 cm −3 at a location where the C-plane was not grown. When the electrical characteristics of this part were measured, this part showed n-type conductivity and the resistivity was about 0.02 to 0.003 Ω · cm.

一方、C面成長している箇所での酸素濃度は約1E17cm−3以下であり、ゲルマニウム(Ge)やシリコン(Si)等の他のドナー不純物濃度が低い場合には、この箇所の抵抗率は約0.1Ω・cm以上に達する場合もあることが測定された。GeやSi等のドナー不純物濃度を上昇させて抵抗を下げようとした場合、ファセット成長している箇所の成長モードの制御が難しく、また欠陥密度が増加するので、ファセット面を維持しつつ窒化ガリウム基板を成長する方法においては、基板面内で抵抗率が不均一になることは避けられなかった。 On the other hand, the oxygen concentration at the C-plane grown location is about 1E17 cm −3 or less, and when other donor impurity concentrations such as germanium (Ge) and silicon (Si) are low, the resistivity at this location is It was measured that it may reach about 0.1 Ω · cm or more. When trying to lower the resistance by increasing the concentration of donor impurities such as Ge and Si, it is difficult to control the growth mode of the facet grown part and the defect density increases, so gallium nitride while maintaining the facet surface In the method of growing a substrate, it is inevitable that the resistivity becomes non-uniform within the substrate surface.

一方、本発明者が特許文献2に記載の方法を参考に窒化ガリウム基板を作製した場合においては、意図的にファセット面を形成しながらの成長ではないため、酸素(O)濃度は低くなった。しかしながら、ごく一部ではあるが、一部の領域に抵抗率が不均一である箇所が認められ、基板面内において部分的に抵抗率が異なる領域が混在した。本発明者の検討によれば、この一部領域での酸素(O)濃度は約5E18cm−3であり、抵抗率は約0.005Ω・cmであった。また、他の領域の酸素濃度は約1E17cm−3以下であったものの、他のドナー不純物であるゲルマニウム(Ge)やシリコン(Si)濃度を制御することにより、大部分の場所の抵抗率を約0.005〜0.02Ω・cmにすることができた。しかしながら、微細に観察すれば抵抗率が基板面内においてやや不均一な領域が存在しており、抵抗率の不均一性の改善には余地がある。 On the other hand, in the case where the inventor fabricated a gallium nitride substrate with reference to the method described in Patent Document 2, the oxygen (O) concentration was low because it was not growth while intentionally forming a facet plane. . However, although it is only a small part, a portion where the resistivity is non-uniform is recognized in a part of the region, and a region where the resistivity is partially different is mixed in the substrate surface. According to the study by the present inventor, the oxygen (O) concentration in this partial region was about 5E18 cm −3 and the resistivity was about 0.005 Ω · cm. Further, although the oxygen concentration in other regions was about 1E17 cm −3 or less, the resistivity in most places was reduced by controlling the concentration of other donor impurities such as germanium (Ge) and silicon (Si). It was able to be 0.005-0.02 ohm * cm. However, when observed finely, there is a region where the resistivity is slightly non-uniform in the substrate surface, and there is room for improvement in non-uniformity of the resistivity.

すなわち、上記のように特許文献1及び特許文献2に記載のn型の導電型を有する窒化ガリウム基板は、基板面内において抵抗率が不均一であることが認められた。このため、窒化ガリウム基板上に高電圧・大電流で駆動させるダイオード構造で、しかも面積が大きいデバイスを作製した場合、基板面内での抵抗率が不均一である影響でダイオード内部での電界分布に予期せぬ偏りが生じ、その結果として絶縁破壊を誘発し、十分なデバイス耐圧が得られない場合があり、材料物性的に期待される値(数百ボルト以上)よりも大幅に低下してしまう場合がある。   That is, as described above, it was recognized that the gallium nitride substrate having the n-type conductivity described in Patent Document 1 and Patent Document 2 has non-uniform resistivity within the substrate surface. For this reason, when a device with a diode structure driven on a gallium nitride substrate with a high voltage and a large current and a large area is manufactured, the electric field distribution inside the diode is affected by the non-uniform resistivity in the substrate surface. As a result, an unexpected bias occurs, and as a result, dielectric breakdown is induced, and sufficient device breakdown voltage may not be obtained, which is significantly lower than the expected value (several hundred volts or more) of material properties. May end up.

したがって、本発明の目的は、面内の抵抗率が不均一である窒化ガリウム基板上に形成したダイオード構造の耐圧を向上させることができる窒化ガリウム系半導体ダイオードを提供することにある。   Accordingly, an object of the present invention is to provide a gallium nitride based semiconductor diode capable of improving the breakdown voltage of a diode structure formed on a gallium nitride substrate having non-uniform in-plane resistivity.

本発明は、上記目的を達成するため、主面がC面である窒化ガリウム自立基板と、pn接合又はショットキー接合を含む接合領域と、窒化ガリウム自立基板と接合領域との間に設けられ、窒化ガリウム自立基板表面の基板面内での最小抵抗率より低い抵抗率を有し、窒化ガリウム自立基板の導電型と同一の導電型の半導体層とを備える窒化ガリウム系半導体ダイオードが提供される。   In order to achieve the above object, the present invention is provided between a gallium nitride free-standing substrate whose principal surface is a C-plane, a junction region including a pn junction or a Schottky junction, and a gallium nitride free-standing substrate and the junction region, There is provided a gallium nitride based semiconductor diode having a resistivity lower than the minimum resistivity in the substrate surface of the gallium nitride free-standing substrate surface and having a semiconductor layer having the same conductivity type as that of the gallium nitride free-standing substrate.

また、上記窒化ガリウム系半導体ダイオードにおいて、半導体層が、超格子構造からなることが好ましい。   In the gallium nitride semiconductor diode, the semiconductor layer preferably has a superlattice structure.

また、上記窒化ガリウム系半導体ダイオードにおいて、窒化ガリウム自立基板が、主面の反対側の表面にオーミック電極を有することができる。   In the gallium nitride based semiconductor diode, the gallium nitride free-standing substrate can have an ohmic electrode on the surface opposite to the main surface.

本発明に係る窒化ガリウム系半導体ダイオードによれば、面内の抵抗率が不均一である窒化ガリウム基板上に形成したダイオード構造の耐圧を向上させることができる窒化ガリウム系半導体ダイオードを提供できる。   The gallium nitride semiconductor diode according to the present invention can provide a gallium nitride semiconductor diode capable of improving the breakdown voltage of a diode structure formed on a gallium nitride substrate having non-uniform in-plane resistivity.

本発明の第1の実施の形態に係る半導体ダイオードの断面図である。1 is a cross-sectional view of a semiconductor diode according to a first embodiment of the present invention. 本発明の第2の実施の形態に係る半導体ダイオードの断面図である。It is sectional drawing of the semiconductor diode which concerns on the 2nd Embodiment of this invention. 本発明の第3の実施の形態に係る半導体ダイオードの断面図である。It is sectional drawing of the semiconductor diode which concerns on the 3rd Embodiment of this invention.

[発明者が得た知見]
本発明者は、鋭意検討した結果、抵抗率が面内で均一ではない窒化ガリウム基板を成長用基板として用いた場合であっても、窒化ガリウム自立基板上の最も抵抗率の低い領域よりも抵抗率の低いn型の導電型の層(すなわち、窒化ガリウム自立基板表面の基板面内での最小抵抗率より低い抵抗率を有する半導体層)を、pn接合又はショットキー接合と、窒化ガリウム基板上との間に設けることにより、半導体ダイオードの耐圧を向上させることができることを見出した。
[Knowledge obtained by the inventor]
As a result of intensive studies, the present inventor has found that even when a gallium nitride substrate whose resistivity is not uniform in the plane is used as a growth substrate, the resistance is lower than that of the lowest resistivity region on the gallium nitride free-standing substrate. An n-type conductivity type layer having a low rate (that is, a semiconductor layer having a resistivity lower than the minimum resistivity in the substrate surface of the gallium nitride free-standing substrate surface), a pn junction or a Schottky junction, and a gallium nitride substrate It was found that the withstand voltage of the semiconductor diode can be improved by providing it between the two.

半導体ダイオードの耐圧は、抵抗率が均一な半導体で形成された理想的な半導体ダイオードの場合においては、逆方向バイアス電圧を上昇させたときに降伏現象が開始するときの電圧(降伏電圧)で決定される。しかしながら、現実の半導体ダイオードの場合、半導体の層が完全には均一でないことに起因して、半導体ダイオードの一部に大きな電界が印加される。これにより、例えば、転位がやや集中している領域等の電流が流れやすい経路に電界が集中する。すると、材料物性から期待される降伏電圧以下で逆方向電流が急激に増加してしまうことがある。つまり、均一な半導体層を得ること、あるいは部分的に電界が集中しない素子構造にすることが半導体ダイオードの耐圧を向上させる方策となる。   The breakdown voltage of a semiconductor diode is determined by the voltage (breakdown voltage) when the breakdown phenomenon starts when the reverse bias voltage is increased in the case of an ideal semiconductor diode formed of a semiconductor with uniform resistivity. Is done. However, in the case of an actual semiconductor diode, a large electric field is applied to a part of the semiconductor diode because the semiconductor layer is not completely uniform. Thereby, for example, the electric field concentrates on a path through which current easily flows, such as a region where dislocations are slightly concentrated. Then, the reverse current may suddenly increase below the breakdown voltage expected from the material properties. That is, obtaining a uniform semiconductor layer or making an element structure in which an electric field is not partially concentrated is a measure for improving the breakdown voltage of the semiconductor diode.

本発明者は、窒化ガリウム自立基板のすべての箇所に比べ、十分に抵抗率が小さい層を窒化ガリウム自立基板とpn接合又はショットキー接合を含む接合領域との間に挿入することで、窒化ガリウム自立基板の抵抗率の不均一性に起因する電界集中を抑制できること、及び窒化ガリウム自立基板上に形成されたダイオード構造の耐圧を高めることができることを見出した。なお、pn接合の代わりにpin接合又はnpn接合等を設けた場合であって、窒化ガリウム自立基板側にn型層を有するダイオード構造又はトランジスタ構造であれば、同様に電界集中を抑制とダイオード構造の耐圧の向上とを実現することができる。   The present inventor inserts a layer having a sufficiently low resistivity as compared with all portions of the gallium nitride free-standing substrate between the gallium nitride free-standing substrate and a junction region including a pn junction or a Schottky junction, thereby obtaining gallium nitride. It has been found that the electric field concentration caused by the non-uniformity of the resistivity of the free-standing substrate can be suppressed, and that the withstand voltage of the diode structure formed on the gallium nitride free-standing substrate can be increased. In the case where a pin junction or an npn junction is provided instead of the pn junction and the diode structure or the transistor structure has an n-type layer on the gallium nitride free-standing substrate side, the electric field concentration is similarly suppressed and the diode structure. It is possible to improve the breakdown voltage.

ここで、窒化ガリウム自立基板のすべての箇所に比べて十分に抵抗率が小さい層は、ゲルマニウム又はシリコン等のドナー不純物を十分に添加したGaN層が最も簡単な層として考えられる。また、例えば、ドナー不純物を十分に添加することで低抵抗化した超格子構造を、窒化ガリウム自立基板のすべての箇所に比べ十分に抵抗率が小さい層にすることが好ましい。超格子構造にすることが好ましい理由は、当該層を設ける目的が、窒化ガリウム自立基板と接合領域との間に抵抗が十分に低い層を挿入することによって、窒化ガリウム自立基板の抵抗率の不均一性に起因する電界集中を抑制するためだからである。   Here, a GaN layer to which a donor impurity such as germanium or silicon is sufficiently added is considered as the simplest layer as the layer having a sufficiently low resistivity as compared with all the portions of the gallium nitride free-standing substrate. In addition, for example, it is preferable that a superlattice structure whose resistance is reduced by sufficiently adding a donor impurity be a layer having a sufficiently low resistivity as compared with all the portions of the gallium nitride free-standing substrate. The reason why the superlattice structure is preferable is that the purpose of providing the layer is to reduce the resistivity of the gallium nitride free-standing substrate by inserting a layer having a sufficiently low resistance between the gallium nitride free-standing substrate and the junction region. This is because electric field concentration caused by uniformity is suppressed.

また、超格子構造を形成する場合、超格子構造は、窒化ガリウム基板からpn接合又はショットキー接合側に延伸している貫通転位の少なくとも一部を、成長方向の外へ(すなわち、窒化ガリウム自立基板の表面に平行な方向に沿った方向に向けて)曲げる効果と、成長面内での電流分散を促進させる効果とを発揮することができる。したがって、十分抵抗が低く、しかも適度な層数を有する超格子構造を設けることがより好ましい。   When a superlattice structure is formed, the superlattice structure has at least a part of threading dislocations extending from the gallium nitride substrate to the pn junction or Schottky junction side to the outside of the growth direction (that is, gallium nitride self-supporting). An effect of bending (toward a direction along a direction parallel to the surface of the substrate) and an effect of promoting current dispersion in the growth plane can be exhibited. Therefore, it is more preferable to provide a superlattice structure having a sufficiently low resistance and an appropriate number of layers.

[実施の形態の要約]
主面がC面である窒化ガリウム自立基板と、pn接合又はショットキー接合を含む接合領域とを備える窒化ガリウム系半導体ダイオードにおいて、前記窒化ガリウム自立基板と前記接合領域との間に設けられ、前記窒化ガリウム自立基板表面の基板面内での最小抵抗率より低い抵抗率を有し、前記窒化ガリウム自立基板の導電型と同一の導電型の半導体層とを備える窒化ガリウム系半導体ダイオードが提供される。
[Summary of embodiment]
In a gallium nitride based semiconductor diode comprising a gallium nitride free-standing substrate whose main surface is a C-plane and a junction region including a pn junction or a Schottky junction, the gallium nitride-based semiconductor diode is provided between the gallium nitride free-standing substrate and the junction region, There is provided a gallium nitride based semiconductor diode having a resistivity lower than the minimum resistivity of the surface of the gallium nitride free-standing substrate in the substrate plane and having a semiconductor layer having the same conductivity type as that of the gallium nitride free-standing substrate. .

[第1の実施の形態]
図1は、本発明の第1の実施の形態に係る半導体ダイオードの断面の概要を示す。
[First Embodiment]
FIG. 1 shows an outline of a cross section of a semiconductor diode according to a first embodiment of the present invention.

第1の実施の形態に係る窒化ガリウム(GaN)系半導体ダイオードとしての半導体ダイオード1は、基板10と、基板10上に設けられる半導体層12と、半導体層12上に設けられるドリフト層14とを備える。更に、半導体ダイオード1は、基板10の半導体層12の反対側の表面に設けられ、基板10にオーミック接合するオーミック電極20と、ドリフト層14の半導体層12の反対側の表面に設けられるショットキー電極22とを備える。   A semiconductor diode 1 as a gallium nitride (GaN) semiconductor diode according to the first embodiment includes a substrate 10, a semiconductor layer 12 provided on the substrate 10, and a drift layer 14 provided on the semiconductor layer 12. Prepare. Furthermore, the semiconductor diode 1 is provided on the surface of the substrate 10 on the opposite side of the semiconductor layer 12, the ohmic electrode 20 that is in ohmic contact with the substrate 10, and the Schottky provided on the surface of the drift layer 14 on the opposite side of the semiconductor layer 12. And an electrode 22.

半導体ダイオード1は、例えば、以下のように製造される。まず、有機金属気相成長(MOVPE)法等により基板10上に半導体層12及びドリフト層14をエピタキシャル成長させることによりエピタキシャル基板を製造する。次に、フォトリソグラフィー法、真空蒸着法等を利用してエピタキシャル基板の一方の面にオーミック電極20を形成すると共に、他方の面にショットキー電極22を形成する。これにより、半導体ダイオード1を製造することができる。なお、半導体ダイオード1は、半導体層12等の成長方向へ電流を流す縦型のダイオード構造を有する。   The semiconductor diode 1 is manufactured as follows, for example. First, an epitaxial substrate is manufactured by epitaxially growing the semiconductor layer 12 and the drift layer 14 on the substrate 10 by a metal organic chemical vapor deposition (MOVPE) method or the like. Next, the ohmic electrode 20 is formed on one surface of the epitaxial substrate using a photolithography method, a vacuum deposition method, or the like, and the Schottky electrode 22 is formed on the other surface. Thereby, the semiconductor diode 1 can be manufactured. The semiconductor diode 1 has a vertical diode structure that allows current to flow in the growth direction of the semiconductor layer 12 and the like.

本実施の形態では、主面がC面である窒化ガリウム自立基板を基板10として用いることができる。したがって、主面上に半導体層12が形成され、主面の反対側の表面にオーミック電極20が形成されることになる。基板10は、ドナーとしての所定の不純物を所定量含むことにより、n型の導電型を有する。   In the present embodiment, a gallium nitride free-standing substrate whose main surface is a C-plane can be used as the substrate 10. Therefore, the semiconductor layer 12 is formed on the main surface, and the ohmic electrode 20 is formed on the surface opposite to the main surface. The substrate 10 has an n-type conductivity by containing a predetermined amount of a predetermined impurity as a donor.

また、半導体層12及びドリフト層14は、基板10と同一の導電型を有する半導体から形成される。半導体層12及びドリフト層14は、例えば、窒化ガリウムから形成される。そして、ショットキー電極22は、ドリフト層14とショットキー電極22との界面14aにおいてドリフト層14にショットキー接合する。本実施の形態では、ドリフト層14と当該ショットキー接合とを含む領域を接合領域16と称する。なお、接合領域16は、半導体からなる一つの層、又は半導体からなる複数の層と、当該一つの層若しくは当該複数の層の最表面に設けられるショットキー電極とを含んで形成することができる。   Further, the semiconductor layer 12 and the drift layer 14 are formed of a semiconductor having the same conductivity type as that of the substrate 10. The semiconductor layer 12 and the drift layer 14 are made of, for example, gallium nitride. The Schottky electrode 22 is in Schottky junction with the drift layer 14 at the interface 14 a between the drift layer 14 and the Schottky electrode 22. In the present embodiment, a region including the drift layer 14 and the Schottky junction is referred to as a junction region 16. Note that the junction region 16 can be formed to include one layer made of a semiconductor or a plurality of layers made of a semiconductor and a Schottky electrode provided on the outermost surface of the one layer or the plurality of layers. .

ここで、半導体層12は、基板10と接合領域16との間に設けられる。そして、半導体層12は、基板10表面の基板面内での最小抵抗率より低い抵抗率を有する。具体的に、半導体層12は、基板10の表面(すなわち、接合領域16と対向する面)において基板面内で最も抵抗率の低い領域の抵抗率より低い抵抗率を層全体にわたり有する。すなわち、半導体層12に添加する不純物の量等を制御することにより、半導体層12の抵抗率を、基板10の表面のいずれの領域における抵抗率よりも低く調整する。   Here, the semiconductor layer 12 is provided between the substrate 10 and the bonding region 16. The semiconductor layer 12 has a resistivity lower than the minimum resistivity within the substrate surface of the substrate 10 surface. Specifically, the semiconductor layer 12 has a resistivity that is lower than the resistivity of the region having the lowest resistivity on the surface of the substrate 10 (that is, the surface facing the bonding region 16) over the entire layer. That is, the resistivity of the semiconductor layer 12 is adjusted to be lower than the resistivity in any region of the surface of the substrate 10 by controlling the amount of impurities added to the semiconductor layer 12.

なお、ショットキー電極22の平面視における形状を真円形にすることにより、半導体ダイオード1のダイオード構造の一部の領域への電界集中を更に抑制できる。また、ショットキー電極22の周辺部に水素等のイオンを打ち込むことにより、当該周辺部の抵抗を高め、電界集中を緩和させることもできる。更に、ショットキー電極22の周辺部の下部の領域に絶縁膜を挟み込むフィールドプレート構造を構成することにより電界集中を緩和させることもできる。   In addition, by making the shape of the Schottky electrode 22 in plan view a perfect circle, electric field concentration on a partial region of the diode structure of the semiconductor diode 1 can be further suppressed. Further, by implanting ions such as hydrogen into the periphery of the Schottky electrode 22, the resistance of the periphery can be increased and the electric field concentration can be reduced. Further, by forming a field plate structure in which an insulating film is sandwiched in a region below the periphery of the Schottky electrode 22, electric field concentration can be reduced.

(第1の実施の形態の効果)
本発明の第1実施の形態に係る半導体ダイオード1は、基板10とドリフト層14との間に基板10の最も抵抗率の低い領域より低い抵抗率を有する半導体層12(すなわち、基板10表面の基板面内での最小抵抗率より低い抵抗率を有する半導体層12)を設けたので、基板10の抵抗率の不均一性に起因する電界集中を抑制することができ、ショットキーダイオードとしての半導体ダイオード1の耐圧を向上させることができる。
(Effects of the first embodiment)
In the semiconductor diode 1 according to the first embodiment of the present invention, the semiconductor layer 12 having a lower resistivity than the lowest resistivity region of the substrate 10 between the substrate 10 and the drift layer 14 (that is, the surface of the substrate 10). Since the semiconductor layer 12) having a resistivity lower than the minimum resistivity in the substrate plane is provided, electric field concentration due to the non-uniformity of the resistivity of the substrate 10 can be suppressed, and the semiconductor as a Schottky diode The breakdown voltage of the diode 1 can be improved.

[第2の実施の形態]
図2は、本発明の第2の実施の形態に係る半導体ダイオードの断面の概要を示す。
[Second Embodiment]
FIG. 2 shows an outline of a cross section of a semiconductor diode according to the second embodiment of the present invention.

第2の実施の形態に係る半導体ダイオード2は、第1の実施の形態に係る半導体ダイオード1に比べ、半導体層12aが超格子構造を有している点を除き、半導体ダイオード1と同一の構成、機能を有する。したがって、相違点を除き詳細な説明は省略する。   The semiconductor diode 2 according to the second embodiment has the same configuration as the semiconductor diode 1 except that the semiconductor layer 12a has a superlattice structure compared to the semiconductor diode 1 according to the first embodiment. , Have function. Therefore, a detailed description is omitted except for differences.

半導体ダイオード2が備える半導体層12aは、超格子構造を有して形成される。具体的に、半導体層12aは、n型の導電型のドナーを所定の濃度添加された複数の窒化物系化合物半導体層からなる超格子低抵抗多層膜である。より具体的に、半導体層12aは、第1の半導体膜と、第1の半導体膜とは異なる第2の半導体膜とのペアからなるペア層が複数、積層されて形成される。この場合において、第1の半導体膜及び第2の半導体膜のいずれか一方、又は双方に、所定量の所定のドナー不純物が添加される。   The semiconductor layer 12a included in the semiconductor diode 2 is formed to have a superlattice structure. Specifically, the semiconductor layer 12a is a superlattice low resistance multilayer film composed of a plurality of nitride compound semiconductor layers to which n-type conductivity type donors are added at a predetermined concentration. More specifically, the semiconductor layer 12a is formed by laminating a plurality of pair layers including pairs of a first semiconductor film and a second semiconductor film different from the first semiconductor film. In this case, a predetermined amount of a predetermined donor impurity is added to one or both of the first semiconductor film and the second semiconductor film.

(第2の実施の形態の効果)
本発明の第2実施の形態に係る半導体ダイオード2は、基板10とドリフト層14との間に基板10の最も抵抗率の低い領域より低い抵抗率を有する超格子構造の半導体層12aを設けたので、基板10の抵抗率の不均一性に起因する電界集中を抑制することができ、ショットキーダイオードとしての半導体ダイオード1の耐圧を向上させることができる。
(Effect of the second embodiment)
In the semiconductor diode 2 according to the second embodiment of the present invention, a semiconductor layer 12a having a superlattice structure having a resistivity lower than that of the lowest resistivity region of the substrate 10 is provided between the substrate 10 and the drift layer 14. Therefore, electric field concentration resulting from the non-uniformity of the resistivity of the substrate 10 can be suppressed, and the breakdown voltage of the semiconductor diode 1 as a Schottky diode can be improved.

[第3の実施の形態]
図3は、本発明の第3の実施の形態に係る半導体ダイオードの断面の概要を示す。
[Third Embodiment]
FIG. 3 shows an outline of a cross section of a semiconductor diode according to the third embodiment of the present invention.

第3の実施の形態に係る半導体ダイオード3は、第1の実施の形態に係る半導体ダイオード1に比べ、接合領域16aがpn接合を有している点を除き、半導体ダイオード1とほぼ同一の構成、機能を有する。したがって、相違点を除き詳細な説明は省略する。   The semiconductor diode 3 according to the third embodiment has substantially the same configuration as that of the semiconductor diode 1 except that the junction region 16a has a pn junction as compared to the semiconductor diode 1 according to the first embodiment. , Have function. Therefore, a detailed description is omitted except for differences.

半導体ダイオード3は、基板10と、基板10上に設けられる半導体層12と、半導体層12上に設けられるドリフト層14と、ドリフト層14上に設けられ、ドリフト層14の導電型とは異なる導電型の半導体層18とを備える。更に、半導体ダイオード3は、基板10の半導体層12の反対側の表面に設けられ、基板10にオーミック接合するオーミック電極20と、半導体層18のドリフト層14の反対側の表面に設けられるオーミック電極24とを備える。なお、半導体層12は、第2の実施の形態と同様に、超格子構造を有する半導体層12aにすることもできる。   The semiconductor diode 3 includes a substrate 10, a semiconductor layer 12 provided on the substrate 10, a drift layer 14 provided on the semiconductor layer 12, and a conductivity different from the conductivity type of the drift layer 14 provided on the drift layer 14. And a semiconductor layer 18 of a type. Further, the semiconductor diode 3 is provided on the surface of the substrate 10 on the opposite side of the semiconductor layer 12, the ohmic electrode 20 that is in ohmic contact with the substrate 10, and the ohmic electrode provided on the surface of the semiconductor layer 18 on the opposite side of the drift layer 14. 24. The semiconductor layer 12 can also be a semiconductor layer 12a having a superlattice structure, as in the second embodiment.

(第3の実施の形態の効果)
本発明の第3実施の形態に係る半導体ダイオード3は、基板10とドリフト層14との間に基板10の最も抵抗率の低い領域より低い抵抗率を有する半導体層12を設けたので、基板10の抵抗率の不均一性に起因する電界集中を抑制することができ、pnダイオードとしての半導体ダイオード3の耐圧を向上させることができる。
(Effect of the third embodiment)
In the semiconductor diode 3 according to the third embodiment of the present invention, the semiconductor layer 12 having a lower resistivity than the lowest resistivity region of the substrate 10 is provided between the substrate 10 and the drift layer 14. The electric field concentration caused by the non-uniformity of the resistivity can be suppressed, and the breakdown voltage of the semiconductor diode 3 as the pn diode can be improved.

実施例1に係る半導体ダイオードとして、第1の実施の形態に係る半導体ダイオード1の構造を備える半導体ダイオードを製造した。   As a semiconductor diode according to Example 1, a semiconductor diode having the structure of the semiconductor diode 1 according to the first embodiment was manufactured.

具体的に、まず、有機金属気相成長(MOVPE)法により、C面の窒化ガリウム(GaN)基板上に、成長面内で均一な抵抗を有すると共に厚さが1μmのn型導電型のGaN層を成長した。実施例1に用いたGaN基板の最も抵抗率が低い箇所の抵抗率は、約0.005Ω・cmであった。なお、GaN層の成長は、基板温度を1100℃に設定して実施すると共に、ドナー不純物としてゲルマニウム又はシリコンを添加した。また、GaN層の抵抗率がGaN基板の抵抗率より小さくなるように、ドナー不純物の添加量を調整した。具体的に、GaN層の成長中にドナー濃度を調整することでGaN層の抵抗率を0.001Ω・cm以上0.004Ω・cm以下の範囲に調整した。   Specifically, first, an n-type conductivity type GaN having a uniform resistance in the growth plane and a thickness of 1 μm on a C-plane gallium nitride (GaN) substrate by metal organic vapor phase epitaxy (MOVPE). Growing layer. The resistivity of the portion with the lowest resistivity of the GaN substrate used in Example 1 was about 0.005 Ω · cm. The growth of the GaN layer was performed with the substrate temperature set to 1100 ° C., and germanium or silicon was added as a donor impurity. Also, the amount of donor impurity added was adjusted so that the resistivity of the GaN layer was smaller than the resistivity of the GaN substrate. Specifically, the resistivity of the GaN layer was adjusted in the range of 0.001 Ω · cm to 0.004 Ω · cm by adjusting the donor concentration during the growth of the GaN layer.

なお、当該GaN基板の抵抗率が面内で均一でないことは、当該GaN基板に紫外線を照射したときのルミネッセンス光の強度分布で間接的に確認した。また、GaN基板表面の基板面内での最小抵抗率の測定は、当該GaN基板の微小領域(具体的には、被測定対象物の体積として0.005〜0.05mmの領域)をイオンミリングによって切り出し、ルミネッセンス光強度分布から抵抗率の異なる領域の体積の概略値を求め、当該微小領域の抵抗値の測定値からその体積分を計算で補正することによって求めた。ほぼ同等の品質を有する複数のGaN基板を用い、多数の箇所で測定することで、GaN基板の最も抵抗率が低い箇所の抵抗率は概ね0.005Ω・cm付近であることを確認した。 In addition, it was indirectly confirmed from the intensity distribution of the luminescence light when the GaN substrate was irradiated with ultraviolet rays that the resistivity of the GaN substrate was not uniform in the plane. In addition, the measurement of the minimum resistivity within the substrate surface of the GaN substrate surface is performed by ionizing a minute region of the GaN substrate (specifically, a region of 0.005 to 0.05 mm 3 as the volume of the object to be measured). It cut out by milling, calculated | required the approximate value of the volume of the area | region where a resistivity differs from luminescence light intensity distribution, and calculated | required by correcting the volume fraction by calculation from the measured value of the resistance value of the said micro area | region. By using a plurality of GaN substrates having substantially the same quality and measuring at a number of locations, it was confirmed that the resistivity at the lowest resistivity of the GaN substrate was approximately around 0.005 Ω · cm.

更に、比較のため、GaN層のドナー濃度を下げ、GaN層の抵抗率が0.005Ω・cm以上0.1Ω・cm以下になる試料(比較例)も作製した。なお、GaN層の抵抗率は、実施例1及び比較例1共に、サファイア基板上に実施例1又は比較例1と同一の条件で成長した試料(ただし、厚さは1000nmである)について四探針法を用いて測定した。   For comparison, a sample (comparative example) in which the donor concentration of the GaN layer was lowered and the resistivity of the GaN layer was 0.005 Ω · cm or more and 0.1 Ω · cm or less was also produced. Note that the resistivity of the GaN layer is the same as that of Example 1 and Comparative Example 1 for the sample (thickness is 1000 nm) grown on the sapphire substrate under the same conditions as in Example 1 or Comparative Example 1. Measurements were made using the needle method.

続いて、成長温度を1100℃に設定したまま、ドナー不純物の固相濃度が約2E16cm−3になるようにドナー不純物の供給量を抑え、10μmの厚さを有するn型GaNからなるドリフト層をGaN層の上に成長した。半導体ダイオードの動作原理上、n型GaNからなるドリフト層の膜厚を厚くすることで半導体ダイオードの耐圧を大きくすることができるので、n型GaNからなるドリフト層の膜厚を10μm以上にすることもできる。また、成長温度は1100℃に限定されない(なお、他の成長条件も限定されない。)。 Subsequently, with the growth temperature set at 1100 ° C., the supply amount of the donor impurity is suppressed so that the solid phase concentration of the donor impurity is about 2E16 cm −3 , and a drift layer made of n-type GaN having a thickness of 10 μm is formed. Grown on the GaN layer. Because of the operating principle of the semiconductor diode, the breakdown voltage of the semiconductor diode can be increased by increasing the thickness of the drift layer made of n-type GaN. Therefore, the thickness of the drift layer made of n-type GaN should be 10 μm or more. You can also. The growth temperature is not limited to 1100 ° C. (other growth conditions are not limited).

n型GaNからなるドリフト層の上に、平面視にて真円形を有し、直径が100μm以上800μm以下のショットキー電極を形成した。ショットキー電極は、ニッケル及びアルミニウムを含む金属から形成した。なお、ショットキー電極の材質は、ドリフト層との間で良好なショットキー接触が得られるその他の材質を用いることもできる。また、ショットキー電極の周辺領域に水素(H)等のイオンを注入することで、高電圧印加時にショットキー電極の周辺部に電界が集中することを抑制した。GaN基板の裏面(すなわち、−C面)のオーミック電極は、アルミ及び金を含む材料から形成した。オーミック電極の材質は、GaN基板との間で良好なオーミック接触が得られる限り、他の材質を用いることもできる。   On the drift layer made of n-type GaN, a Schottky electrode having a true circle in plan view and a diameter of 100 μm or more and 800 μm or less was formed. The Schottky electrode was formed from a metal containing nickel and aluminum. Note that the Schottky electrode can be made of any other material that provides good Schottky contact with the drift layer. Further, by implanting ions such as hydrogen (H) into the peripheral region of the Schottky electrode, the electric field is prevented from concentrating on the peripheral portion of the Schottky electrode when a high voltage is applied. The ohmic electrode on the back surface of the GaN substrate (that is, the -C surface) was formed from a material containing aluminum and gold. As the material of the ohmic electrode, other materials can be used as long as a good ohmic contact with the GaN substrate can be obtained.

このようにして作製した実施例1に係るGaN基板上のショットキーダイオードの電流電圧(IV)特性を測定した。そして、逆方向電流が急激に増加する電圧(耐圧)を調べたところ、GaN層の抵抗率が0.1Ω・cmのときの耐圧は約540V、抵抗率が0.01Ω・cmのときの耐圧は約540Vであった。   The current-voltage (IV) characteristics of the Schottky diode on the GaN substrate according to Example 1 manufactured as described above were measured. Then, when the voltage (withstand voltage) at which the reverse current rapidly increases was examined, the withstand voltage when the resistivity of the GaN layer was 0.1 Ω · cm was about 540 V, and the withstand voltage when the resistivity was 0.01 Ω · cm. Was about 540V.

一方、抵抗率が0.004Ω・cmのときの耐圧は約720Vであり、0.002Ω・cmのときの耐圧は約760Vであった。したがって、GaN層の抵抗率が、GaN基板の最も抵抗率が低い箇所よりも小さい場合には耐圧が大きくなることが確認された。GaN基板の最も抵抗率が低い箇所が0.01Ω・cmである基板を使用した場合においても、傾向に変化は認められなかった。   On the other hand, the withstand voltage when the resistivity was 0.004 Ω · cm was about 720 V, and the withstand voltage when the resistivity was 0.002 Ω · cm was about 760 V. Therefore, it was confirmed that the breakdown voltage increases when the resistivity of the GaN layer is smaller than the lowest resistivity portion of the GaN substrate. Even when the substrate having the lowest resistivity of the GaN substrate of 0.01 Ω · cm was used, no change was observed in the tendency.

つまり、GaN基板のすべての箇所に比べて十分に抵抗率が小さい層を挿入することで、基板の抵抗率の不均一性に起因する電界集中を抑制することができ、GaN基板上に形成されたショットキーダイオードの耐圧を高めることができることが示された。   In other words, by inserting a layer having a sufficiently low resistivity compared to all locations on the GaN substrate, electric field concentration due to the non-uniformity of the resistivity of the substrate can be suppressed and formed on the GaN substrate. It was shown that the breakdown voltage of the Schottky diode can be increased.

実施例2に係る半導体ダイオードとして、第2の実施の形態に係る半導体ダイオード2の構造を備える半導体ダイオードを製造した。   As the semiconductor diode according to Example 2, a semiconductor diode having the structure of the semiconductor diode 2 according to the second embodiment was manufactured.

実施例2においては、実施例1に係る半導体ダイオードのGaN層の代わりに、n型の導電型を有する超格子低抵抗多層膜をGaN基板上に形成した。具体的に、アルミ組成が約10%のAlGaN層とGaN層とからなるペアをペア層にし、20〜100ペアのペア層を含む多層膜をGaN基板上に形成することにより超格子低抵抗多層膜を形成した。その他の構成は実施例1に係る半導体ダイオードと同一である。   In Example 2, instead of the GaN layer of the semiconductor diode according to Example 1, a superlattice low resistance multilayer film having n-type conductivity was formed on a GaN substrate. Specifically, a superlattice low-resistance multilayer is formed by forming a pair of AlGaN layers and GaN layers having an aluminum composition of about 10% as a pair layer and forming a multilayer film including 20 to 100 pair layers on a GaN substrate. A film was formed. Other configurations are the same as those of the semiconductor diode according to the first embodiment.

また、AlGaN層及びGaN層それぞれの膜厚は2.0nm〜3.5nmにした。実施例2においては、GaN層にドナー不純物を添加することで超格子低抵抗多層膜の抵抗率を制御した。なお、ドナーの添加方法は実施例2の例に限定されず、AlGaN層にドナー不純物を添加すること、あるいはGaN層及びAlGaN層の双方に均一にドナー不純物を添加することもできる。   The film thickness of each of the AlGaN layer and the GaN layer was 2.0 nm to 3.5 nm. In Example 2, the resistivity of the superlattice low resistance multilayer film was controlled by adding a donor impurity to the GaN layer. Note that the donor addition method is not limited to the example in Example 2, and donor impurities can be added to the AlGaN layer, or donor impurities can be uniformly added to both the GaN layer and the AlGaN layer.

実施例2に係る半導体ダイオードの耐圧を測定したところ、超格子低抵抗多層膜の抵抗率が0.1Ω・cmのときの耐圧は約580Vであり、抵抗率が0.01Ω・cmのときの耐圧は約590Vであった。一方、超格子低抵抗多層膜の抵抗率が0.004Ω・cmのときの耐圧は約810V、抵抗率が0.002Ω・cmのときの耐圧は約820Vであった。以上のことから、GaN基板の最も抵抗率が低い箇所よりも小さい抵抗率を有する超格子低抵抗多層膜を用いる場合には、半導体ダイオードの耐圧が大きくなることが示された。なお、最も抵抗率が低い箇所が0.01Ω・cmであるGaN基板を用いた場合においても、この傾向に変化は見られなかった。   When the breakdown voltage of the semiconductor diode according to Example 2 was measured, the breakdown voltage when the resistivity of the superlattice low resistance multilayer film was 0.1 Ω · cm was about 580 V, and when the resistivity was 0.01 Ω · cm. The breakdown voltage was about 590V. On the other hand, the breakdown voltage when the resistivity of the superlattice low resistance multilayer film was 0.004 Ω · cm was about 810 V, and the breakdown voltage when the resistivity was 0.002 Ω · cm was about 820 V. From the above, it was shown that when a superlattice low resistance multilayer film having a resistivity lower than that of the lowest resistivity of the GaN substrate is used, the breakdown voltage of the semiconductor diode is increased. Even when the GaN substrate having the lowest resistivity of 0.01 Ω · cm was used, this tendency was not changed.

つまり、GaN基板のすべての箇所と比べて十分に抵抗率が小さい層を挿入することで、基板の抵抗率の不均一性に起因する電界集中を抑制することができ、GaN基板上に形成されたショットキーダイオードの耐圧を高めることができることが示された。   In other words, by inserting a layer having a sufficiently low resistivity as compared to all locations on the GaN substrate, electric field concentration due to the non-uniformity of the resistivity of the substrate can be suppressed and formed on the GaN substrate. It was shown that the breakdown voltage of the Schottky diode can be increased.

実施例3に係る半導体ダイオードとして、第3の実施の形態に係る半導体ダイオード3の構造を備える半導体ダイオードを製造した。   As the semiconductor diode according to Example 3, a semiconductor diode having the structure of the semiconductor diode 3 according to the third embodiment was manufactured.

実施例3においては、実施例1及び実施例2においてn型GaNからなるドリフト層の上に、500nmの厚さを有し、Mg等のアクセプタを添加したp型の導電型のGaN層を成長した。また、p型のGaN層の上に、パラジウム系の材料からなるオーミック電極を形成した。これにより、実施例3に係る半導体ダイオードを製造した。   In Example 3, a p-type conductivity type GaN layer having a thickness of 500 nm and added with an acceptor such as Mg is grown on the drift layer made of n-type GaN in Example 1 and Example 2. did. An ohmic electrode made of a palladium-based material was formed on the p-type GaN layer. Thus, the semiconductor diode according to Example 3 was manufactured.

そして、実施例1及び実施例2と同様に、電流電圧(IV)特性から、逆方向電流が急激に増加する電圧(耐圧)を測定した。その結果、GaN層又は超格子低抵抗多層膜の抵抗率が、GaN基板の最も抵抗率が低い箇所よりも大きい場合は耐圧が720〜790Vであり、GaN基板の最も抵抗率が低い箇所よりも小さい場合は耐圧が830〜1040Vであった。つまりpnダイオード構造の場合においても、GaN層又は超格子低抵抗多層膜の抵抗率が、GaN基板の最も抵抗率が低い箇所よりも小さい場合には、半導体ダイオードの耐圧が大きくなることが示された。   Then, similarly to Example 1 and Example 2, the voltage (withstand voltage) at which the reverse current suddenly increased was measured from the current-voltage (IV) characteristics. As a result, when the resistivity of the GaN layer or the superlattice low-resistance multilayer film is larger than the portion with the lowest resistivity of the GaN substrate, the breakdown voltage is 720 to 790 V, which is lower than the portion with the lowest resistivity of the GaN substrate. When it was small, the withstand voltage was 830 to 1040V. That is, even in the case of the pn diode structure, it is shown that the breakdown voltage of the semiconductor diode increases when the resistivity of the GaN layer or the superlattice low-resistance multilayer film is smaller than the lowest resistivity portion of the GaN substrate. It was.

つまり、GaN基板のすべての箇所と比べて十分に抵抗率が小さい層を挿入することで、基板の抵抗率の不均一性に起因する電界集中を抑制することができ、GaN基板上に形成されたpnダイオードの耐圧を高めることができることが示された。   In other words, by inserting a layer having a sufficiently low resistivity as compared to all locations on the GaN substrate, electric field concentration due to the non-uniformity of the resistivity of the substrate can be suppressed and formed on the GaN substrate. It was shown that the breakdown voltage of the pn diode can be increased.

以上、本発明の実施の形態及び実施例を説明したが、上記に記載した実施の形態及び実施例は特許請求の範囲に係る発明を限定するものではない。また、実施の形態及び実施例の中で説明した特徴の組合せの全てが発明の課題を解決するための手段に必須であるとは限らない点に留意すべきである。   While the embodiments and examples of the present invention have been described above, the embodiments and examples described above do not limit the invention according to the claims. It should be noted that not all combinations of features described in the embodiments and examples are necessarily essential to the means for solving the problems of the invention.

1、2、3 半導体ダイオード
10 基板
12、12a 半導体層
14 ドリフト層
14a 界面
16、16a 接合領域
18 半導体層
20、24 オーミック電極
22 ショットキー電極
1, 2, 3 Semiconductor diode 10 Substrate 12, 12a Semiconductor layer 14 Drift layer 14a Interface 16, 16a Junction region 18 Semiconductor layer 20, 24 Ohmic electrode 22 Schottky electrode

Claims (3)

主面がC面である窒化ガリウム自立基板と、
pn接合又はショットキー接合を含む接合領域と、
前記窒化ガリウム自立基板と前記接合領域との間に設けられ、前記窒化ガリウム自立基板表面の基板面内での最小抵抗率より低い抵抗率を有し、前記窒化ガリウム自立基板の導電型と同一の導電型の半導体層と
を備える窒化ガリウム系半導体ダイオード。
A gallium nitride free-standing substrate whose main surface is a C-plane;
a junction region including a pn junction or a Schottky junction;
The gallium nitride free-standing substrate is provided between the junction region and the gallium nitride free-standing substrate, and has a resistivity lower than the minimum resistivity in the substrate surface of the gallium nitride free-standing substrate, and has the same conductivity type as the gallium nitride free-standing substrate A gallium nitride based semiconductor diode comprising a conductive semiconductor layer.
前記半導体層が、超格子構造からなる請求項1に記載の窒化ガリウム系半導体ダイオード。   The gallium nitride based semiconductor diode according to claim 1, wherein the semiconductor layer has a superlattice structure. 前記窒化ガリウム自立基板が、前記主面の反対側の表面にオーミック電極を有する請求項2に記載の窒化ガリウム系半導体ダイオード。   The gallium nitride based semiconductor diode according to claim 2, wherein the gallium nitride free-standing substrate has an ohmic electrode on a surface opposite to the main surface.
JP2010066803A 2010-03-23 2010-03-23 Gallium nitride based semiconductor diode Pending JP2011199187A (en)

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Citations (5)

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JP2006279021A (en) * 2005-03-04 2006-10-12 Sumitomo Electric Ind Ltd Vertical gallium nitride semiconductor device and epitaxial substrate
JP2006290676A (en) * 2005-04-11 2006-10-26 Hitachi Cable Ltd III-V nitride semiconductor substrate and manufacturing method thereof
JP2007149985A (en) * 2005-11-28 2007-06-14 Sumitomo Electric Ind Ltd Nitride semiconductor device, epitaxial substrate and method for forming gallium nitride based epitaxial film
JP2009126723A (en) * 2007-11-20 2009-06-11 Sumitomo Electric Ind Ltd Group III nitride semiconductor crystal growth method, group III nitride semiconductor crystal substrate manufacturing method, and group III nitride semiconductor crystal substrate
JP2009126722A (en) * 2007-11-20 2009-06-11 Sumitomo Electric Ind Ltd Group III nitride semiconductor crystal substrate and semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006279021A (en) * 2005-03-04 2006-10-12 Sumitomo Electric Ind Ltd Vertical gallium nitride semiconductor device and epitaxial substrate
JP2006290676A (en) * 2005-04-11 2006-10-26 Hitachi Cable Ltd III-V nitride semiconductor substrate and manufacturing method thereof
JP2007149985A (en) * 2005-11-28 2007-06-14 Sumitomo Electric Ind Ltd Nitride semiconductor device, epitaxial substrate and method for forming gallium nitride based epitaxial film
JP2009126723A (en) * 2007-11-20 2009-06-11 Sumitomo Electric Ind Ltd Group III nitride semiconductor crystal growth method, group III nitride semiconductor crystal substrate manufacturing method, and group III nitride semiconductor crystal substrate
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