JP2011146718A - Method of forming semiconductor die - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that it is absolutely necessary for semiconductor dies to have regular shapes of squares and rectangles before since a singulation line which axially extends is used. <P>SOLUTION: In one embodiment, semiconductor dies having non-rectangular shapes and dies having various different shapes are formed and singulated from a semiconductor wafer. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates generally to electronics, and more particularly to semiconductors, their structures, and methods of forming semiconductor devices.

  In the past, singulation lines were generally formed as a plurality of parallel lines, and each singulation line was aligned with the long axis of the singulation line across the wafer from one side of the wafer. Straight in the direction, the wafer saw or scribe line could travel in a straight line across the wafer. Each of the conventional singulation lines generally extends straight from end to end of the wafer and has no curvature, bends, angles, or other shapes other than a single continuous line . In order to facilitate the use of this linear singulation line, conventional semiconductor dies are generally regular in shape where all dies have the same area and shape (usually square or rectangular). Met. Furthermore, since the regularly shaped dies were arranged on the wafer in a regular pattern, the singulation lines extended between the dies, and the dies could be singulated. It was possible to use straight singulation lines because the rectangle or square was composed of straight lines, the dies had the same area, and were arranged in a regular pattern . In order to use these axially extending singulation lines, the dies were forced to have regular shapes, square and rectangular.

  Accordingly, a method of forming a semiconductor die that does not require axial singulation lines is desired.

FIG. 3 shows a reduced plan view of one embodiment of a semiconductor wafer in accordance with the present invention. FIG. 2 shows an enlarged plan view of one embodiment of a plurality of dies on the wafer of FIG. 1 in accordance with the present invention. FIG. 2 shows an enlarged plan view of one embodiment of a plurality of dies on the wafer of FIG. 1 in accordance with the present invention. FIG. 2 shows an enlarged plan view of one embodiment of a plurality of dies on the wafer of FIG. 1 in accordance with the present invention. FIG. 2 shows an enlarged plan view of one embodiment of a plurality of dies on the wafer of FIG. 1 in accordance with the present invention. FIG. 2 shows an enlarged plan view of one embodiment of a plurality of dies on the wafer of FIG. 1 in accordance with the present invention. FIG. 2 shows an enlarged plan view of one embodiment of a plurality of dies on the wafer of FIG. 1 in accordance with the present invention. FIG. 2 shows an enlarged plan view of one embodiment of a plurality of dies on the wafer of FIG. 1 in accordance with the present invention. FIG. 2 shows an enlarged plan view of one embodiment of a plurality of dies on the wafer of FIG. 1 in accordance with the present invention. FIG. 2 shows an enlarged plan view of one embodiment of a plurality of dies on the wafer of FIG. 1 in accordance with the present invention. FIG. 2 shows an enlarged cross-sectional view of one embodiment of the portion of the semiconductor wafer of FIG. 1 in one stage of one embodiment of a process for singulating dies from a wafer in accordance with the present invention. FIG. 12 illustrates the die of FIG. 11 in a subsequent stage of one embodiment of a process for singulating the die in accordance with the present invention. FIG. 12 illustrates the die of FIG. 11 in a subsequent stage of one embodiment of a process for singulating the die in accordance with the present invention. FIG. 12 illustrates the die of FIG. 11 in a subsequent stage of one embodiment of a process for singulating the die in accordance with the present invention. FIG. 3 shows an enlarged cross-sectional view of one embodiment of the portion of the semiconductor wafer of FIG. 1 at one stage of another embodiment of the process of singulating dies from the wafer in accordance with the present invention. FIG. 16 illustrates the die of FIG. 15 in a subsequent stage of one embodiment of a process for singulating the die in accordance with the present invention. FIG. 16 illustrates the die of FIG. 15 in a subsequent stage of one embodiment of a process for singulating the die in accordance with the present invention. FIG. 16 illustrates the die of FIG. 15 in a subsequent stage of one embodiment of a process for singulating the die in accordance with the present invention. FIG. 16 illustrates the die of FIG. 15 in a subsequent stage of one embodiment of a process for singulating the die in accordance with the present invention. FIG. 3 shows an enlarged cross-sectional view of one embodiment of the portion of the semiconductor wafer of FIG. 1 at one stage of another embodiment of the process of singulating dies from the wafer in accordance with the present invention. FIG. 21 shows the die of FIG. 20 in a subsequent stage of one embodiment of a process for singulating the die in accordance with the present invention. FIG. 21 shows the die of FIG. 20 in a subsequent stage of one embodiment of a process for singulating the die in accordance with the present invention. FIG. 2 shows an enlarged plan view of one embodiment of a plurality of dies on the wafer of FIG. 1 in accordance with the present invention. FIG. 4 shows a top view of one embodiment of a semiconductor device having a semiconductor die with a receptacle in accordance with the present invention. FIG. 25 shows a cross-sectional view of the apparatus of FIG. 24 in accordance with the present invention. FIG. 25 shows a top view of one embodiment of a semiconductor device in another embodiment of the apparatus of FIG. 24 in accordance with the present invention. FIG. 6 shows a top view of a portion of another embodiment of a semiconductor device including a semiconductor device having a receptacle in accordance with the present invention. FIG. 3 shows an enlarged plan view of a multi-connected die in accordance with the present invention.

  For simplicity and clarity of illustration, elements in the figures are not necessarily to scale, and identical reference numerals in different figures denote identical elements. Moreover, descriptions and details of well-known processes and elements are omitted for the sake of brevity. As used herein, current transport electrode means an element of a device that transports current through a device such as the source or drain of a MOS transistor, the emitter or collector of a bipolar transistor, or the cathode or anode of a diode. In addition, the control electrode means an element of a device that controls current through a device such as the gate of a MOS transistor or the base of a bipolar transistor. Although the device is described herein as an N-channel or P-channel device, or as an N-type or P-type doped region, those skilled in the art will recognize additional devices in accordance with the present invention. It will also be understood that it can be used. Here, the terms “during”, “while” and “when” used in relation to circuit operation mean the operation that occurs immediately by the first operation. There may be some slight but reasonable delay, such as a propagation delay, between the reaction starting with the first action, not the term.

  When the terms “approximately” or “substantially” are used, it means that the value of the element has a parameter that is expected to be very close to the stated value or position. However, as is well known in the art, there will always be a slight variance that prevents a value or position exactly as described. It is well established in the art that a dispersion of at least 10% and a semiconductor doping concentration of 20% or less is reasonable dispersion to the ideal goal as described. Yes. For clarity of the drawing, the doped regions of the device structure are generally drawn to have straight edges and precisely angled corners. However, those skilled in the art will understand that due to dopant diffusion and activation, the edge of the doped region may not be generally straight and the corners may not be at the exact angle.

  As used herein, “symmetrical shape” means at least two such that the size, shape, and relative position of a boundary line or median plane, or a portion that is opposite to the center or axis, match. Means one shape and if the shape does not change by flipping or rotating, the shape is symmetric. The term “asymmetric” means a shape that is not symmetric, and when the shape changes upon reversal or rotation, the shape is asymmetric. The term “rectangular” means a closed planar quadrilateral with opposite lengths and four right angles of equal length. “Non-rectangular” means a closed geometric figure that is not rectangular. The term “multiply-connected” means an open set in a plane with holes in it. For example, in the case of having a hole penetrating the shape, such as a donut shape, the shape is a multiple connection.

  FIG. 1 shows a reduced plan view of one embodiment of a semiconductor wafer 30 on which a plurality of semiconductor dies are formed. The semiconductor dies on the wafer 30 may all have the same shape or different shapes. The dies are isolated from each other by a portion of the wafer 30 such as a singulation area, which portions are later removed to singulate each die. Since the singulation area surrounds each die on the wafer 30, the singulation area on the wafer 30 is removed to singulate the die. As is well known in the art, all of the plurality of semiconductor dies on the wafer 30 are generally isolated from each other by the portion of the wafer 30 where the singulation regions are formed. The dies on the wafer 30 can be formed as any type of semiconductor die, including diodes, vertical transistors, horizontal transistors, or integrated circuits including various types of semiconductor devices.

  As will be clarified below, the dies formed on the wafer 30 are generally those portions of the wafer 30 that do not extend so that the singulation area of the wafer 30 crosses the surface of the wafer 30 axially or in a straight line. Need to be. Those skilled in the art will have some singulation lines extending axially across wafer 30 from one end of wafer 30 to the other end of wafer 30 as shown in FIG. You will understand. An example of such a singulation line is indicated by line 31. In general, in other embodiments, the wafer 30 is axially transverse to a portion of the wafer 30, such as a singulation line 32 that ends in a singulation region indicated by dashed lines 33, 112. And singulation lines that extend at the boundaries of the singulation regions of the wafer 30 and are further described below. In other embodiments, the wafer 30 may not have any singulation lines extending axially across a portion of the wafer 30.

  FIG. 2 shows an enlarged plan view of an embodiment of a plurality of dies having protrusions, such as dies 34-42, which are formed on the portion of wafer 30 indicated by dashed line 33 in FIGS. Is done.

  Since the dies 34-42 all have protrusions or fingers that extend from the die on at least one side, the shape of the outer periphery of the plan view (or top surface) of the dies 34-42 has both protrusions. . The external perimeter of the plan view (or top surface) of the die 34-42 is not only the active area of the die, but the actual perimeter of the die after the die is singulated. For example, the die 35 is shown as having a right side 44, a bottom side 45, and an upper side 46, each formed by a single straight line. However, the left side of the die 35 has a protrusion instead of a straight line. Accordingly, the periphery of the die 35 includes a plurality of sides that do not all have the same shape and dimensions. The left side of the die 35 includes a plurality of protrusions (protrusions or fingers 183, 184, 185) that extend outward from the innermost part (side 182) of the left side of the die 35. Each of the protrusions or fingers forms a part of the periphery of the die 35, and each protrusion has a side that is part of the periphery (eg, sides 180, 181 of the protrusion 183). The protrusion forms some portion of the periphery (eg, side 180) and protrudes from the other side or portion (eg, side 181 or side 182) that forms the periphery. Accordingly, the die 35 has a protrusion that extends outward along the periphery of the die 35. The die 36 also has similar protrusions 199, 200, 201. As shown in FIG. 2, the dimensions of the die 35 show three or more values depending on where the dimensions are measured. For example, although the length value along the side edge 44 is one, the width value is the width value from the side edge 44 to the side edge 180 and the width value from the side edge 44 to the side edge 182. As such, there are two or more values. Thus, the width has at least one local maximum and one minimum.

  Die 34 not only has a different shape than die 35, but also has protrusions such as protrusions 196 and 197. In the embodiment shown in FIG. 2, the protrusion 196 of the die 34 extends between the protrusions 183 and 184 of the die 35 and within a recess formed between the protrusions 183 and 184 of the die 35. Be placed. The space or positional relationship between the die 34 and the die 35 is often referred to as inter-digitated.

  The dies 34-42 are neither quadrilateral in the shape of the outer periphery of the plan view of the dies and do not have four congruent angles. Will be understood to be non-rectangular.

  Further, since the dies 34-42 all have irregular shapes, the shape of the outer periphery of the upper surface of the die causes an axial direction between any one of the dies 35-42 and the adjacent die. Singing of the die using an axial singulation line extending to For example, an axial singulation line that extends axially through the portion of the wafer 30 between the die 36 and the die 37 cannot be used to singulate the die 36. Because the outer periphery of the die 36 has protrusions, the portion of the wafer 30 that exists between the protrusions 200 and 201 of the die and between the protrusions 199 and 200 is such an axial singing. This is because it cannot be removed by the transmission line. Therefore, the irregular shape prevents the singulation of dies 34-42 using axial singulation lines.

  Further, the dies 35-42 can be considered to be arranged in an irregular pattern on the wafer 30. This is because a singulation line extending axially along at least a portion of the singulation region 49 along one side of the die 35-42 (eg, parallel to the side 44 of the die 35), This is because it intersects with the inner part of a nearby die (for example, die 40). Thus, because of the irregular pattern, such an axial singulation line will traverse at least one internal portion of the die, so some of the dies 35-42 may be singulated. Cannot be singulated from the wafer 30 using an axial singulation line that extends axially across a portion of the wafer 30 containing the die to be processed. Accordingly, the singulation region 49 surrounding the die 35-42 cannot form a continuous straight line extending axially across the portion of the wafer 30 where the die 35-42 is located.

  After forming the dies 34-42, the portion of the wafer 30 that surrounds the dies 36-42, such as part of the singulation region 49, can be simultaneously singulated to singulate the dies 36-42 into individual dies. Are removed at the same time. The portion of the wafer 30 that is typically removed is indicated by the hatched line 48. The oblique lines have no meaning other than showing the portion of the wafer 30 to be removed. One skilled in the art will appreciate that in order to singulate the die, it is not necessary to remove all of the region 49, only the portion surrounding the outer periphery. More on that below.

  Due to the protrusion of the die 34-42, or because of the irregular shape of the die 34-42 or the irregular pattern of the die 34-42, the singulation region 49 surrounding the die 34-42 may be It is impossible to form a continuous straight line that extends in the axial direction across the wafer 30 on which −42 is disposed, or extends through a part of the wafer 30 in the axial direction. A singulation line that is such a continuous straight line in the singulation region will extend through a portion of the die 34-42 and will break into the die. Alternatively, in order to have a straight singulation line, a portion of the wafer 30 would have to be left along one side of the die (eg, the protrusions 183, 184, 185 of the die 35). Such extra portions of the wafer 30 will waste part of the wafer 30 and reduce the number of dies formed in a given area of the wafer 30. However, since the simultaneous singulation method is used to remove at least a portion of the singulation region 49, the number of dies that maximizes the use of the wafer 30 and can be formed on the wafer 30. The dies 34-42 can be arranged and arranged on the wafer 30 in a configuration that increases

  In order to maximize the number of dies of this type that can be placed in a given area, such as an area of the wafer 30, the dies are either dies 39 and 40 or dies 37 and 38 and 41 and 42. As shown in FIG. As a result of being arranged in the interdigitated position, the singulation region 49 surrounding the die protrusion cannot form a continuous straight line extending in the axial direction across the wafer 30. A continuous straight singulation line extending axially across the portion of the wafer 30 where the dies 34-42 are located is from one side of the die (eg, along the side 44 of the die 35) and the other. Will form a line that extends through the portion of the die (e.g., through the interior of die 40) and breaks the die.

  Further, among the plurality of semiconductor dies, the center of the first die (for example, the center of the die 35) is arranged so as to be shifted from the center of the adjacent semiconductor die (for example, the center of the die 39 or the die 40) ( The dies 34-42 are arranged on the wafer 30 in a non-centric pattern.

  A simultaneous singulation method that simultaneously removes at least a portion of region 49 as a singulation region is typically described in US Patent Publication No. 2009/0042366 published on Feb. 12, 2009 (inventor: hryvnia). , Gordon M.), including the use of dry etching. By using a dry etching method to simultaneously singulate the dies 34-42, it is possible to form dies 34-42 having protrusions and / or irregular shapes. And / or die 34-42 can be formed in an irregular pattern on wafer 30 and / or die 34-42 is formed in a non-centric pattern on wafer 30. Is possible. Other methods for simultaneously singulating dies from the wafer, such as dies 34-42, are described below with respect to FIGS. 11-22, for example.

  In some embodiments, those skilled in the art will appreciate that region 49 further includes an etch-enhanced section 67 that assists in increasing the etch rate when singulating a semiconductor die. Section 67 is a portion of region 49, ie, a portion of wafer 30, that is not removed when dies 34-42 are singulated. In some embodiments, section 67 can increase the etch rate within the equipment used to singulate die 34-42. Section 67 can be formed in any part of region 49 if there is a space between any of dies 34-42.

  In one example of the configuration of the dies 34, 35, the dies 34, 35 have different shapes. The dies 34 and 35 are singulated together. After singulation, the dies 34, 35 are assembled into a single package and placed in an interdigitated position within the package. This interdigitated location can be used to provide a low inductance interconnect between two different types of dies. In another example, such two dies are formed on different wafers as two different types of dies, such as low power logic and high power transistors. The close proximity of the dies will allow short interconnects to be used to form interconnect paths from one die to the other. The result is a low inductance connection that can improve the operating characteristics of the two dies.

  FIG. 3 shows an enlarged plan view of an embodiment of a plurality of non-rectangular dies, such as dies 51-56, which are on the portion of wafer 30 indicated by dashed line 50 in FIGS. It is formed. The dies 51 to 56 are all non-rectangular because the outer peripheral shape of the die plan view is not a quadrilateral having four congruent angles. Furthermore, any perimeter of the dies 51-56 has at least one curved shape instead of a perimeter formed by a straight line. Thus, any perimeter of the dies 51-56 includes a plurality of sides that include at least one side that is curved and includes a non-straight portion. For example, the die 54 is illustrated as having a straight side 205. The die 54 further has another side 206 indicated in a general manner by an arrow, which includes a curved portion 207. Accordingly, the perimeter of the dies 51-56 has a non-rectangular shape and includes at least one side having a curved shape.

  Furthermore, since the dies 51-55 are formed with openings (for example, holes or openings 58, 61) through the dies, the outer peripheral shape of the dies 51-55 is a multiple connection. As used herein, multiple connection means an open set in a plane with holes. Thus, since all of the dies 51-55 have holes through the dies, they are multi-connected. For example, the die 51 has two different sized holes 58, 59, and the die 52 has holes 61 that are both the same size. The die therefore has a multi-connected topology.

  After forming the dies 51-56, the portion of the wafer 30 surrounding the dies 51-56 is removed simultaneously to singulate the dies 51-56 into individual dies. The portion of the wafer 30 that is normally removed is indicated by diagonal lines 64. Since the shape is non-rectangular, the use of the simultaneous singulation method maximizes the use of the wafer 30 and increases the number of dies that can be formed on the wafer 30. 51-56 can be arranged and arranged on the wafer 30. Through the simultaneous singulation method, holes through the dies 51-56 can also be formed during singulation. A person skilled in the art will recognize that the opening formed through any of the dies 51-56 during singulation does not split the die apart, for example to cut the die in half, for example in FIG. It will be appreciated that an opening is formed through a portion of the die, as shown, or an opening is formed along the peripheral edge of the die, as shown in FIG. Alternatively, the holes may be formed prior to singulation.

  In one embodiment (not necessarily all embodiments), in order to maximize the number of such dies that can be placed in a given area, such as one area of the wafer 30, the dies are 1 The dies are arranged in a staggered manner so that the narrow portions of one die are located next to the wide portions of adjacent dies. Due to the staggered pattern and arrangement of dies 51-56, one side of one die will traverse the inner portion of at least one adjacent die when extended. For example, extending the side 208 of the die 54 will cause the side 208 to intersect across the interior of the die 52. This staggered arrangement can increase the number of non-rectangular dies that can be formed in a given area of the wafer 30. As a result of the staggered arrangement, the singulation regions 65 surrounding the die cannot form a continuous straight line extending axially across the wafer 30. A continuous straight singulation line extending axially across a portion of the wafer 30 on which the dies 51-56 are located is from one side of the die (eg, along the side 208 of the die 54), It will form lines that extend through other die portions (eg, the interior portion of die 52) and will break the die.

  Further, since the dies 51-56 have an irregular shape, the shape of the outer periphery of the die is an axial thinning that extends axially between one of the dies 51-56 and one adjacent to the dies 51-56. Use the regulation line to prevent the die from being singulated. For example, a straight singulation line cannot remove the surrounding curved portion, so an axial singulation line extending axially between dies 51 and 52 singulates die 52. Can not be used to.

  In addition, singulation lines along one side of die 51-56 (eg, parallel to side 208 of die 54) cross internal portions of adjacent dies (eg, die 52) so that the die 51-56 can be considered to be arranged in an irregular pattern on the wafer 30. Thus, because of an irregular pattern, such a singulation line traverses through at least one of the dies so that it traverses the wafer 30 on which the dies 51-56 are located or a portion of the wafer 30. Some of the dies 51-56 cannot be singulated from the wafer 30 using axial singulation lines extending axially across the wafer. Accordingly, the singulation region 65 surrounding the dies 51-56 cannot form a continuous straight line extending axially across the portion of the wafer 30 when the dies 51-56 are placed.

  One skilled in the art will appreciate that in some embodiments, region 65 may further include an etch enhancement section 68 to increase the etch rate when singulating the semiconductor die. Section 68 is part of region 65, ie, part of wafer 30, but it is not removed when dies 51-56 are singulated, similar to section 67 of FIG. Section 68 can be formed in any portion of region 65 when there is a space between any of dies 51-56.

  FIG. 4 shows an enlarged plan view of an embodiment of a plurality of dies having protrusions such as dies 86-91, which are formed on the portion of wafer 30 indicated by dashed line 85 in FIGS. The The dies 86-91 have protrusions or fingers extending from the dies on at least one of the perimeters of the plan view of the dies. For example, the die 88 is shown having an upper side 211 and a bottom side 212 each formed by a single straight line. However, the left and right sides around the die 88 each have a protrusion instead of a single straight line. Accordingly, the periphery of the die 88 includes a plurality of sides that do not all have the same shape and dimensions. The left side of die 88 includes a plurality of protrusions (eg, protrusions or fingers 213, 217) extending outwardly from the innermost portion of the left side of die 88, such as side 216. The protrusions form some portion around the die (eg, side 214 of die 88) and protrude from other surrounding sides or nearby sides (eg, side 215 or side 216). Each of the protrusions or fingers forms a peripheral portion of the die 88, and each protrusion has a side that is the peripheral portion (eg, the sides 214, 215 of the protrusion 213). Further, the die 88 has a similar protrusion on the right side of the die 88. Thus, the perimeter of die 86-91 includes a plurality of sides, such that at least one side has a protrusion or finger that extends from at least one portion of the die.

  In order to maximize the number of such dies that can be placed in a given area, such as the area of the wafer 30, the dies are represented by dies 88, 89 and dies 88, 90, as shown in FIG. They are arranged at positions where they are interfitted.

  Further, since die 86-91 is believed to have an irregular shape, the shape of the upper surface of the die or the outer perimeter of the plan view is one of die 86-91 and one adjacent to die 86-91. The use of axial singulation lines extending axially therebetween prevents singulation of at least a portion of one of the dies. For example, an axial singulation line extending axially along the side 214 of the die 88 will not remove the portion of the wafer 30 adjacent to the side 216 of the die 88. Thus, the irregular shape prevents singulation of any one of the dies 86-91 by using axial singulation lines.

  In addition, singulation lines along one side of die 86-91 (eg, parallel to side 214 of die 88) are connected to internal portions of adjacent dies (eg, die 86 or die 89). Since they intersect, the dies 86-91 can be considered to be arranged in an irregular pattern on the wafer 30. Thus, because of the irregular pattern, such an axial singulation line will traverse at least one of the dies, so that some of the dies 86-91 are located in the dies 86-91. The wafer 30 cannot be singulated by using an axial singulation line that extends axially across the wafer 30 or a portion of the wafer 30. Accordingly, the singulation region 94 surrounding the die 86-91 does not form a continuous straight line extending axially across the wafer 30 or a portion of the wafer 30 where the die 86-91 is located. Further, those skilled in the art will appreciate that any of the dies 86-91 are non-rectangular.

  After forming the dies 86-91, portions of the wafer 30 that surround the dies 86-91, such as portions of the singulation region 94, are removed simultaneously to singulate the dies 86-91 into individual dies. The portion of the wafer 30 that is normally removed is indicated by hatched lines 93. As a result of the interdigitated arrangement, the singulation region 94 surrounding the die protrusions does not form a continuous straight line that extends axially across the wafer 30. A continuous straight singulation line extends from one side of the die, for example, along the side 216 of the die 88, passes through a portion of the die 88, and then another portion such as a portion of the die 91. It will form a line through the die and break the die.

  FIG. 5 shows an enlarged plan view of an embodiment of a plurality of multiple connected dies, such as dies 99-102, which are formed on the portion of wafer 30 indicated by dashed line 108 in FIGS. . Because the top surface of die 99-102 has a hole therethrough, die 99-102 is multi-connected. In addition, die 99-102 has a non-rectangular shape because the outer perimeter of the upper surface of die 71-74 is non-rectangular. A singulation area 109 of the wafer 30 surrounds each of the dies 99-102. Dies 99-102 are shown as parallelograms having at least one opening or hole through the die. In addition, the die 102 has openings 105 and 106 formed through the die 102. Since the openings 105, 106 have different shapes, the die 102 is asymmetric.

  After forming the die 99-102, the portion of the wafer 30 that surrounds the die 99-102, such as the portion of the singulation region 109, is removed simultaneously to singulate the die 99-102 into individual dies. . The portion of the wafer 30 that is normally removed is indicated by the hatched line 108. Even if the sides of the die 99-102 are straight, the sides do not intersect at right angles. Thus, the dies 99-102 are arranged in a staggered pattern to maximize the number of dies that can be formed in a given area, such as the surface of the wafer 30. Due to the staggered pattern or arrangement of dies 99-102, when one side of one die is extended, it will traverse the internal portion of at least one adjacent die. For example, if the side 209 of the die 99 is extended, the side 209 will intersect or cross the interior of the die 101. Due to the offset pattern, the singulation region 109 surrounding the die 99-102 does not form a continuous straight line extending axially across the portion of the wafer 30 that includes the die 99-102. A continuous straight singulation region extending axially across the portion of the wafer 30 on which the die 99-102 is located will extend through the portion of the die 99-102 and break the die. Alternatively, to allow a linear continuous singulation line to extend between the dies, between the dies (eg, between the sides of die 99 and die 100). The distance must be extended, but this will reduce the number of dies that can be formed on the wafer.

  In addition, dies 99-102 have singulation lines along one side of die 99-102 (e.g., parallel to side 209 of die 99) within the adjacent die (e.g., die 101). Since it intersects with the part, it can be regarded as being arranged on the wafer 30 in an irregular pattern. Accordingly, because some of the dies 99-102 are irregular patterns, such singulation lines traverse at least one of the dies, so a portion of the wafer 30 that includes the dies 99-102. Cannot be singulated from the wafer 30 using singulation lines extending axially across the wafer. Thus, the singulation region 109 surrounding the die 99-102 extends axially across the wafer 30 or across a portion of the wafer 30 that includes the die 99-102, such as region 109. A continuous straight line cannot be formed.

  Since a simultaneous singulation method is used to remove the singulation region 109, the dies 99-102 maximize the use of the wafer 30 and the number of dies that can be formed on the wafer 30. Is arranged on the wafer 30 in such a configuration as to increase.

  After the dies 99-102 are singulated, the dies are assembled with the other dies, including placing other dies in openings formed through each of the dies 99-102. For example, the die 99 may be formed as a low power theoretical circuit for the control circuit, and the other die may be formed as a high power device such as a power transistor. The power transistor may be placed inside the opening of the die 99 and the two dies may operate together. Alternatively, die 99-102 may be a power transistor, and other types of dies may be assembled in either opening of die 99-102. This allows for the formation of very close and short interconnects and further minimizes parasitic resistance and inductance within the connection. Alternatively, a heat sink may be assembled within the opening of die 99 to help dissipate the power generated during operation of die 99. Alternatively, to improve the efficiency of a device such as providing a heat sink, or to provide a low resistance electrical connection from an element formed on the top surface of the die to an element formed on the bottom surface of the die A dielectric or metallic material may be selectively assembled in the openings.

  FIG. 6 is an enlarged plan view of an embodiment of a plurality of irregularly shaped dies, such as dies 71-74, which are on the portion of wafer 30 indicated by dashed line 70 in FIGS. It is formed. Further, the dies 71-74 include a curved shape along a portion of the outer perimeter of the top surface of the die. As with die 99-102, instead of having an opening through the interior of die 71-74, die 71-74 has a perimeter that includes a curved portion that can be applied similarly to the opening of die 99-102. . Because of the curved portion around the dies 71-74, the dies 71-74 cannot be singulated by singulation lines that extend axially across the portion of the wafer 30 that includes the dies 71-74. The curved shape of dies 71-74 prevents the use of axial singulation lines to remove the portion of wafer 30 adjacent to the dies. For example, an axial singulation line cannot remove the portion of the wafer 30 adjacent to the side 77 of the die 71. Further, the die 74 has an asymmetric shape because the arrangement of the side edges 75 makes the plan view of the die 74 or the shape around the top surface asymmetric. Accordingly, the singulation region 80 is formed so as to surround the dies 71-74 in order to promote the singulation of the dies 71-74 from the wafer 30. The normally removed portion of the wafer 30 is indicated by hatched lines 79. Due to the surrounding curved portion, the singulation region 80 may not form a continuous straight line extending axially across the wafer 30 or across a portion of the wafer 30 including the dies 71-74. . Dies 71-74 are singulated as described with respect to dies 99-102.

  FIG. 7 shows an enlarged plan view of an embodiment of a plurality of dies 124-127 having a perimeter of the top surface of a non-rectangular die. The dies 124-127 are formed on the portion of the wafer 30 indicated by the dashed line 123 in FIGS. Dies 124-127 are similar to dies 99-102 of FIG. 5, and have the same die shape and similar arrangement, except that dies 124-127 are not multiple connected. A singulation region 130 of the wafer 30 surrounds each of the dies 124-127. The portion of the wafer 30 that is normally removed is indicated by the hatched line 129.

  Since the sides of die 124-127 do not intersect at right angles, a straight line extending from any one side of die 124-127 will traverse the other one of dies 124-127. Because of this configuration, the dies 124-127 use singulation lines that extend axially across the wafer 30 where the dies 124-127 are located or across a portion of the wafer 30. Can't sing. Accordingly, the singulation region 130 surrounding the dies 124-127 cannot form a continuous straight line extending axially across the portion of the wafer 30 where the dies 124-127 are disposed or formed.

  Further, since singulation lines along one side of die 124-127 (eg, parallel to side 210 of die 124) intersect the internal portion of an adjacent die (eg, die 126), The dies 124-127 can be considered to be arranged on the wafer 30 in an irregular pattern. Thus, because irregular patterns will cause such singulation lines to traverse through at least one of the dies, some of the dies 124-127 may have a wafer on which the dies 124-127 are formed. It cannot be singulated from wafer 30 by using a singulation line that extends axially across a portion of 30. Accordingly, the singulation region 130 surrounding the dies 124-127 cannot form a continuous straight line that extends axially across the wafer 30. Those skilled in the art can arrange the dies 124-127 on the wafer 30 in different patterns that allow the dies 124-127 to be removed by using axial singulation lines. You will understand that.

  The dies 124-127 are shown in a non-centered pattern on the wafer 30, but the centers of the dies 124-127 may be aligned or non-centered. However, such a configuration nevertheless singulates the dies 124-127 using axial singulation lines extending axially across the portion of the wafer 30 where the dies 124-127 are formed. Prevent you from doing.

  FIG. 8 shows an enlarged plan view of an embodiment of a plurality of non-rectangular dies, such as dies 113-116, which are formed on the portion of wafer 30 indicated by dashed line 112 in FIGS. Is done. Since each of the dies 113 to 116 has a triangular shape around the upper surface and is not a rectangular shape, the dies 113 to 116 are non-rectangular. A singulation region 119 of the wafer 30 surrounds each of the dies 113-116.

  Even if the sides of the dies 113-116 are straight, the sides do not intersect at a right angle. In order to maximize the number of dies of this type that can be placed in a given area, such as the area of the wafer 30, the dies are separated from the adjacent die by one extension of one side of the die. They are arranged in a shifted pattern so that they intersect. For example, if the side 117 of the die 114 is extended, the extension will intersect the die 113. Further, the dies 114-115 may be non-centered so that the centers of the dies 114-115 along at least one direction are not aligned. For example, dies 113-116 indicate that the centers of dies 114, 116 are aligned along a horizontal line. However, even if other dies (not shown) on the wafer 30 are aligned with the die 114 along the normal, the die 113 and the center of the die 114 are not aligned along the normal and pass through the center of the die 113. The normal will pass through the die 114. Due to the non-rectangular shape or staggered pattern, the singulation region 119 surrounding the dies 113-116 cannot form a continuous straight line that extends axially across the wafer 30. In addition, axial singulation lines extending axially across a portion of the wafer 30 on which the dies 113-116 are placed or formed extend through some interior of the dies 113-116 and break the dies. As such, the dies 114-116 can be considered to be disposed on the wafer 30 in an irregular pattern. Those skilled in the art will appreciate that the dies 113-116 can be arranged in different patterns on the wafer 30, but it is possible to use axial singulation lines to take out the dies 113-116 with that pattern. Become.

  After forming the dies 113-116, the portion of the wafer 30 surrounding the dies 113-116, such as the portion of the singulation region 119, is dry etched to singulate the dies 113-116 into individual dies. Are removed at the same time. The removed portion of the wafer 30 that is typically removed is indicated by hatched lines 118.

  The conventional die singulation method is such that a linear continuous singulation line can extend between the die 114 and the die 115 and the sides of the die 115. There was a need to increase the distance between dies, such as Thus, the placement of dies 114-116 or the arrangement of the spaces can improve wafer utilization and increase the number of dies formed on the wafer.

  FIG. 9 shows an enlarged plan view that is an example of a die having a plurality of non-rectangular shapes, such as dies 136-142, which are portions of wafer 30 indicated by dashed lines 135 in FIGS. Formed on top. The die 136-142 has a non-rectangular shape, such as an octagon, because the top surface of the die 136-142 or the outer perimeter of the plan view has a non-rectangular shape. The octagonal shape is an example of a non-rectangular shape, and the dies 136-142 may have other non-rectangular shapes. A singulation area 145 of the wafer 30 surrounds each of the dies 136-142.

  In order to maximize the number of dies that are non-rectangular shapes that can be placed in a given area, such as the area of wafer 30, dies 136-142 are placed on wafer 30 in a generally irregular pattern. Is done. In one example of an irregular pattern, the singulation region 145 surrounding the die 136-142 does not form a continuous straight line extending axially across the portion of the wafer 30 where the die 136-142 is formed. A die 136-142 is disposed.

  In addition, the outer perimeter shape of the top surface of the die is shaped using an axial singulation line extending axially between one of the dies 35-42 and one of the adjacent dies 35-42. The die 136-142 has an irregular shape. For example, the outer perimeter of die 136 has a side 143 that cannot be removed by such an axial singulation line so that it passes through the portion of wafer 30 between die 136 and die 137. An axial singulation line extending in the axial direction cannot be used to singulate the die 136. As shown, the die 136 has other sides that contribute to this irregular shape. Thus, the irregular shape prevents any of the dies 136-142 from being singulated by using axial singulation lines. Thus, the irregular shape prevents the use of axial singulation lines to singulate the die 136-142.

  Further, any of the dies 136-142 can be placed in a non-centered position relative to adjacent dies by placing the dies so that the centers of the dies are not aligned with the adjacent dies. Further, the dies 136-142 are arranged on the wafer 30 at positions shifted with respect to adjacent dies. This arrangement generally increases the number of polygonal shaped dies that can be formed in a given area of the wafer 30, so this staggered pattern is generally used. As a result of the offset pattern, a straight line extending from either side of the die 136-142 will traverse through the other one of the dies 136-142. Because of this arrangement, the dies 136-142 cannot be singulated using singulation lines that extend axially across the portion of the wafer 30 on which the dies 136-142 are formed. Accordingly, the singulation region 145 surrounding the die 136-142 does not form a continuous straight line that extends axially across the portion of the wafer 30 where the die 136-142 is formed.

  Further, any of the dies 136-142 has an axial singulation line along one side of the die 136-142 (eg, parallel to the side 221 of the die 136). Since it intersects with the part (for example, die 138), it can be considered that the wafer 30 is arranged in an irregular pattern. Thus, some of the dies 136-142 singulate from the wafer 30 by using axial singulation lines that extend axially across the portion of the wafer 30 where the dies 136-142 are formed. I can't. Accordingly, the singulation region 145 surrounding the die 136-142 does not form a continuous straight line that extends axially across the wafer 30 on which the die 136-142 is formed or across a portion of the wafer 30.

  Further, any of the dies 136-142 has an axial singulation line extending axially along one side of the die 136-142 through at least a portion of the singulation region 145. Since it intersects with the inner part of the adjacent die, it can be regarded as being arranged on the wafer 30 in an irregular pattern. Thus, some of the dies 35-42 traverse such axial singulation lines through at least one interior of the die in an irregular pattern, so It cannot be singulated from wafer 30 using an axial singulation line that extends axially across the portion of wafer 30 that it contains. Accordingly, the singulation region 49 surrounding the dies 35-42 cannot form a continuous straight line extending axially across the portion of the wafer 30 where the dies 51-56 are located.

  After forming die 136-142, the portion of wafer 30 surrounding die 136-142, such as the portion of singulation region 145, is removed simultaneously to singulate die 136-142 into individual dies. . The portion of the wafer 30 that is typically removed is indicated by hatched lines 144. Since the simultaneous singulation method is used to remove the singulation region 145 or a portion thereof, the dies 136-142 are formed in the described shape or on the wafer 30 in the described configuration. Arranged and arranged to maximize use of the wafer 30 and increase the number of dies that can be formed on the wafer 30.

  In the preceding singulation method that formed a straight singulation line extending axially across the wafer, the continuous straight singulation line would extend through the portion of die 136-142, so that the die Would be damaged. For example, such a continuous straight singulation line extends from one side of the die along the side 221 of the die 136 and extends to other die portions, such as the interior portion of the die 138. It would have broken the die 138 by forming a singulation line extending therethrough. Alternatively, the distance between dies, such as between the sides of die 136 and 138, must be increased in order for a straight continuous singulation line to extend between the dies. This will reduce the number of dies that can be formed on the wafer.

  FIG. 10 shows an enlarged plan view of an embodiment of a plurality of dies, such as dies 151-157, which are formed on the portion of wafer 30 indicated by dashed line 150 in FIGS. Like dies 156, 157, some of the dies are on the top surface of the die that is larger than the area and distance around the outer periphery of the top surface of other dies on wafer 30, such as dies 151, 154. Having an area and distance around the external perimeter. A singulation area 160 of the wafer 30 surrounds each of the dies 151-157. For the embodiment shown in FIG. 10, dies 151-157 are shown as rectangular. Since the dies have different areas and perimeters, the dies are arranged in a staggered pattern to maximize the number of dies that can be formed in a given area, such as on the surface of the wafer 30. The Thus, the area of die 151 is not very equal to the area of either die 154 or 156, and the area of die 154 is not very equal to the area of die 156. Further, a singulation line along one side of die 151-157 (eg, parallel to side 219 of die 154) intersects an internal portion of an adjacent die (eg, die 152, 156). Therefore, it can be considered that the dies 151-157 are arranged on the wafer 30 in an irregular pattern. Thus, either die 151-153 or 154-155 or 156-157 uses an axial singulation line that extends axially across the portion of wafer 30 on which die 151-157 is formed. Cannot singulate from the wafer 30 because such an axial singulation line traverses through at least one of the dies. Accordingly, the singulation region 160 surrounding the dies 151-157 forms a continuous straight line extending axially across the wafer 30 on which the dies 151-157 are formed or across a portion of the wafer 30. I don't get it.

  Since a simultaneous singulation method is used to remove at least a portion of the singulation region 160, the die 151-157 should maximize the use of the wafer 30 and be formed on the wafer 30. Are arranged or arranged on the wafer 30 in a staggered configuration or in an irregular pattern so that the number of dies that can be produced is increased.

  Those skilled in the art have at least two different die sizes, such as a die having a region of dies 153, 155, which is a single die having a region different from that of other dies on the wafer 30. You will understand that there may be. In some embodiments, different size dies are singulated from the wafer 30, the periphery of the first and second semiconductor dies have the same shape, such as a rectangle, and the first and second semiconductor dies Both are singulated from wafer 30 as two complete dies. In other embodiments, one of the different sized dies may be a test structure formed on the wafer 30 to test processing parameters or other parameters during a manufacturing operation. For such an embodiment, the test structure die may not be singulated from the wafer 30.

  FIG. 11 shows an enlarged cross-sectional portion of the wafer 30 cut along the cutting line 2-2 in FIGS. For clarity of the drawings and description, this section line 2-2 is shown only for the die 36 and die portions 35,37. The semiconductor die 35-37 generally includes a semiconductor substrate 318, which has doped regions formed in the substrate 318 to form active and passive portions of the semiconductor die. The cross-sectional portion shown in FIG. 11 is cut along each contact pad 324 of die 35-37. Contact pad 324 is typically a metal formed on a semiconductor die to provide electrical contact between the semiconductor die and elements external to the semiconductor die. For example, contact pad 324 may be formed to receive a bonding wire that is bonded to pad 324 in a subsequent process, or a solder ball or other type of interconnect structure that is bonded to pad 324 in a subsequent process. Formed to receive. The substrate 318 includes a bulk substrate 319, and the bulk substrate 319 has an epitaxial layer 320 formed on the surface thereof. A portion of the epitaxial layer 320 is doped to form a doped region 321 that is used to form the active and passive portions of the semiconductor die 35 or 36 or 37. Layer 320 and / or region 321 may be omitted in some embodiments, or may be in other regions of die 35 or 36 or 37.

  Typically, a dielectric 323 is formed on the top surface of the substrate 318 to separate the pads 324 from other parts of the individual semiconductor die and each pad 324 from adjacent semiconductor dies. . Dielectric 323 is typically a thin layer of silicon dioxide formed on the surface of substrate 318. Contact pad 324 is generally metal and has a portion of contact pad 324 that is in electrical contact with substrate 318 and another portion formed over a portion of dielectric 323. After the dies 35-37 are formed, including the metal contacts and associated interlayer dielectric (not shown), the dielectric 326 is formed over all of the plurality of semiconductor dies, and the wafer 30 and individual semiconductors. Serves as a passivation layer for dies 35-37. The dielectric 326 is typically formed on the entire surface of the wafer 30 by, for example, depositing a dielectric over the entire surface. The thickness of the dielectric 326 is generally greater than the thickness of the dielectric 323.

  After forming the dielectric 326, a singulation mask is formed to form an opening through the substrate 318 without etching the underlying layer, such as a portion of the dielectric 326. In the preferred embodiment, the singulation mask is formed of aluminum nitride (AlN). In this preferred embodiment, the AlN layer 391 is formed on at least the dielectric 326. Layer 391 is generally provided to cover all of wafer 30.

  FIG. 12 shows a cross-sectional portion of wafer 30 in the subsequent stage of FIG. 11 for a preferred embodiment of a method for singulating irregularly shaped dies, such as dies 35-37, from wafer 30. FIG. After the AlN layer 391 is formed, a mask 332 is applied to the surface of the substrate 318 and patterned to cover a portion of the dielectric 326 overlying each pad 324 (ie, over a portion of the wafer 30). An opening for exposure is formed, and a singulation region (for example, singulation region 49) is formed there.

  To form the mask 332, photographic mask material is applied to the wafer 30, and then a light beam such as ultraviolet light is irradiated to form the locations where the singulation lines are to be formed and the pads 324. The chemical composition of the exposed portion of the mask material changes so that a mask 332 having an opening over the location is formed. A developer is then used to remove unexposed portions of the mask material, thereby opening openings 328, 329 over the locations where each singulation region (eg, singulation region 49) is to be formed. The mask 332 is left. It will be appreciated by those skilled in the art that openings 328 and 329 are typically two portions of a single opening that surrounds die 35-37, but are shown as two openings for cross-sectional view. Will understand. Furthermore, it has been found that the portion of the AlN layer 391 under the unexposed portion of the mask material can be removed by using a developer based on ammonium hydroxide. The removed portion of layer 391 is indicated by dashed line 392 and the remaining portion of layer 391 is indicated as AlN 393. AlN 393 functions as a singulation mask, which will be described later.

  FIG. 13 shows a cross-sectional portion of wafer 30 in the subsequent stage of FIG. Dielectrics 326 and 323 are etched through the openings in mask 332 and AlN 393 to expose the underlying substrate 318 and pad 324 surfaces. In a region where a singulation region such as the region 49 is formed, the openings formed by the AlN 393 and the dielectrics 326 and 323 function as the singulation openings 328 and 329. The opening formed through the dielectric 326 on the pad 324 functions as a contact opening. In the etching step, it is preferable that the step of selectively etching the dielectric is performed faster than the step of etching the metal. The etching process generally etches the dielectric at least 10 times faster than the metal is etched. The metal of the pad 324 functions to stop the etching, and the exposed portion of the pad 324 is not removed by the etching. In the preferred embodiment, a fluorine-based anisotropic reactive ion etching process is used.

  After forming openings through the dielectrics 326, 323, the mask 332 is typically removed as indicated by the dashed lines. Subsequently, the substrate 318 is generally thinned to remove material from the bottom surface of the substrate 318 and reduce the thickness of the substrate 318 as indicated by the dashed line. In general, substrate 318 is thinned to a thickness of less than about 25-400 microns, preferably between about 50-250 microns. Such thinning procedures are well known to those skilled in the art. After the wafer 30 is thinned, the back surface of the wafer 30 may be metallized with a metal layer 327. This metallization step may be omitted in some embodiments. The wafer 30 is then typically attached to a transport or carrier tape 330 to support the dies after the dies are singulated. In some embodiments, the tape 330 is omitted or replaced with a different carrier device.

  FIG. 14 shows the wafer 30 in a subsequent stage for an embodiment of a method for singulating semiconductor dies 35-37 from the wafer 30. FIG. AlN 393 is used as a mask for etching the substrate 318 through the singulation openings 328,329. AlN 393 protects dielectric 326 from being affected by etching. AlN 393 is approximately 50-300 angstroms thick but still protects the dielectric 326. AlN 393 is preferably about 200 angstroms thick. The etching process extends the singulation openings 328 and 329 from the upper surface of the substrate 318 through the substrate 318, removes the singulation region 49 from the wafer 30, and singulates the dies 35-37. The etching process is usually performed using a chemistry that selectively etches silicon at a much faster rate than etching dielectrics or metals. The etching process generally etches silicon at least 50 times, preferably 100 times faster than the dielectric or metal is etched. To form the singulation region 49, a deep reactive ion etching system, typically using a combination of isotropic and anisotropic etching conditions, is performed on the top surface of the substrate 318 (eg, the die 36). Used to etch openings 328, 329 passing from surface 11) to the bottom surface of substrate 318. In the preferred embodiment, a process commonly referred to as the BOSCH method is used to anisotropically etch the singulation openings 328 and 329 through the substrate 318. In one example, the wafer 30 is etched using a Bosch process with an Alcatel deep reactive ion etching system.

  The width of the singulation openings 328,329 is generally 5-10 microns. Such a width is small enough to ensure that the openings 328 and 329 are formed completely through the substrate 318 and that the openings can be formed in a short time. Typically, the openings 328 and 329 can extend through the substrate 318 like the opening 49 in about 15-30 minutes. Since all the singulation regions of the wafer 30 are formed simultaneously, all the singulation regions are formed over the entire wafer 30 within the same time of about 15-30 minutes.

  Thereafter, the die of wafer 30 is supported by carrier tape 330 and the die is sent to subsequent assembly operations.

  Since AlN 393 is a dielectric, it remains on the dies 35-37. In other embodiments, AlN 393 is removed after etching through substrate 318, for example by using a developer, but this requires additional processing steps. By using a developer to remove the exposed portion of layer 319, processing steps are reduced, thereby reducing manufacturing costs. Further, by using AlN393 as a mask, the dielectric 326 can be protected from the influence of the etching operation.

  In other embodiments, the singulation mask may be formed of other materials instead of AlN. Other materials for the singulation mask are materials that are hardly etched by the process used to etch the silicon of the substrate 318. Since the etching procedure used to etch the substrate 318 etches silicon faster than the metal, a metal compound can be used as a material to form a singulation mask. Examples of such metal compounds include AlN, titanium nitride, titanium oxide, titanium oxynitride, and other metal compounds. In examples using metal compounds other than AlN, a layer of metal compound is provided in the same manner as layer 391. A mask 332 is then used to pattern the metal compound layer and openings are formed in the metal compound. Thereafter, the mask 332 is removed and the remainder of the metal compound protects the underlying layer, such as the dielectric 326, during the etching of the substrate 318. The metal compound may be left on the die after singulation or may be removed prior to complete singulation (eg, before separating the die from tape 330).

  Furthermore, since the metal in the metal-silicon compound prevents the progress of the etching into the metal-silicon material, the metal-silicon compound can also be used to form a singulation mask. Some examples of metal-silicon compounds include metal silicides such as titanium silicide and cobalt silicide. With respect to the metal-silicon compound embodiment, the metal-silicon compound layer is formed and patterned in the same manner as the metal compound example. However, since the metal-silicon compound is generally a conductor, it must be removed from the die, for example, prior to fully singulating the die from tape 330, the metal-silicon compound is removed.

  In addition, polymers may be used for singulation masks. One example of a suitable polymer is polyimide. Other well known polymers may be used. The polymer is patterned like the metal compound and then removed or left on the die.

  FIG. 15 illustrates a stage in an embodiment of another method for singulating an irregularly shaped semiconductor die, such as dies 35-37, from a semiconductor wafer, such as wafer 30. FIG. This singulation method forms an angled sidewall on the singulated die. The stage shown in FIG. 15 begins after forming the openings 328-329 described with respect to FIG. The AlN 393 is used as a mask for etching the substrate 318 through the singulation openings 328 and 329 and removing the singulation region 49 from the wafer 30. After the surface of the substrate 318 is exposed, the substrate 318 and all exposed pads 324 are etched with an isotropic etch process, which is a much faster rate (generally at least 50 times, preferably The silicon is selectively etched at least 100 times faster). Typically, a downstream etchant with fluorine chemistry is used for this etch. For example, the wafer 30 is etched with an Alcatel deep reactive ion etching system that uses sufficient isotropic etching. This etching step is performed to extend the openings 328 and 329 into the substrate 318 to a depth that expands the width of the opening in the lateral direction, while expanding the depth into the substrate 318 to form the opening 400. It is. This process is used to form angled or inclined sidewalls in the die 35-37, so that a number of isotropic etches extend the opening depth into the substrate 318 and It will be used to continuously increase the width of 328,329. After the width of the opening 400 becomes larger than the width of the openings 328 and 329 on the surface 11 of the die 36 and the substrate 318, the isotropic etching is finished.

  A carbon-based polymer 401 is then added to the portion of the substrate 318 exposed in the opening 400.

  FIG. 16 shows a subsequent stage of the stage described with respect to FIG. An anisotropic etch is used to remove the portion of polymer 401 at the bottom of opening 400 while leaving a portion of polymer 401 on the sidewall of opening 400.

  FIG. 17 shows a subsequent stage of the stage described with respect to FIG. The exposed surface of substrate 318 in opening 400 and all exposed pads 324 are etched in an isotropic etching process similar to the process described with respect to FIG. Isotropic etching will again widen the width of the singulation openings 328 and 329 while also expanding the depth to form the opening 404 in the substrate 318. The isotropic etching usually ends after the width of the opening 404 becomes larger than the width of the opening 400 by increasing the width of the opening as the depth increases. The portion of polymer 401 left on the sidewall of opening 400 protects the sidewall of opening 400 so that etching of opening 404 does not affect the width of opening 400. Typically, substantially all of the polymer 401 is removed from the sidewalls of the opening 400 during the etching of the opening 404.

  Thereafter, a carbon-based polymer 405 similar to polymer 401 is added to the portion of substrate 318 exposed in opening 404. During the formation of the polymer 405, the process typically forms the polymer 401 again on the sidewalls of the opening 400.

  FIG. 18 shows a subsequent stage of the stage described with respect to FIG. An anisotropic etch is used to remove the portion of polymer 405 at the bottom of opening 404 while leaving the portion of polymer 405 on the sidewall of opening 404. The stages of this process are similar to the steps described with respect to FIG.

  FIG. 19 shows that this sequence is repeated until the singulation region 49 is formed to extend completely through the substrate 318. An anisotropic etching sequence to form openings (eg, openings 408, 412), ie, forming a polymer (eg, polymer 409) on the sidewall of the opening, and a portion of the polymer (eg, polymer) on the sidewall The sequence of removing the polymer from the bottom of the openings while leaving 409) is repeated until the openings 328, 329 extend through the substrate 318 and the singulation region 49 is removed from the substrate 30.

  After the last isotropic etch, such as the etch to form the opening 412, the polymer is generally not deposited because it is not needed to protect the substrate 318 during subsequent operations. Polymers 401, 405, and 409 are shown on the respective sidewalls of openings 400, 404, and 408, but after all steps are complete, to substantially remove these polymers from the corresponding opening sidewalls. Those skilled in the art will appreciate that a final isotropic etch step, such as an etch to form the opening 412, may be used. Accordingly, these polymers are shown only for clarity of explanation.

  As can be seen from FIG. 19, the sidewalls 336 of the die 36 and the sidewalls 335 of the die 37 are inclined inwardly from the top surface 11 to the bottom, so that the die width at the bottom of each die is that of the die. Narrower than the die width at the top. Thus, the outer edge of the die at the top of the substrate 318 extends beyond the outer edge of the die at the bottom of the substrate 318 by a distance 416 and the top surface of the die 35 overhangs the bottom by a distance 416. The distance 416 is considered to be about 5-10 percent of the thickness of the die 35-37. In one embodiment, the distance 416 is about 1-5 microns, so the width of the die 35 at the bottom of the substrate 318 is about 2-10 microns narrower than the width at the top of the die 35 on the surface 11. In general, the top of the opening in singulation region 49 is about 2-40 microns narrower than the bottom of the opening in singulation region 49. In other embodiments, the sidewall 336 may form an angle 417 of about 15-40 degrees between the sidewall 336 and a normal, such as a line perpendicular to the top surface of the substrate 318. Thus, the amount each etch expands the opening 329 width should be sufficient to form the angle 417. Those skilled in the art will have a rough sidewall formed on each of the dies 35-37 by a plurality of anisotropic etching steps, so that the sidewall has jagged edges along the sidewall. Will understand. However, the degree of jagged edges is exaggerated in FIGS. 15-19 for clarity of explanation. These sidewalls are generally considered to be substantially smooth sidewalls.

  One skilled in the art will appreciate that the singulation mask layer is omitted in other embodiments of the method of singulating dies 35-37. In such a case, the isotropic and / or anisotropic etch procedure uses an etch that etches silicon faster than the dielectric or metal, so that the dielectric 326 is in each of the dies 35-37. Provides protection for the underlying part (see US Patent Publication No. 2009/0042366, published February 12, 2009 (inventor: Gordon M. Gryvna)).

  FIG. 20 shows the stages for another method embodiment that singulates irregular semiconductor dies, eg, 35-37, from a semiconductor wafer, such as wafer 30. FIG. 20 shows an enlarged cross-sectional portion of the die 35-37 in a manufacturing state (see FIG. 11) after the dielectric 323 is formed on the upper surface of the substrate 318 and before the pad 324 is formed. With respect to the singulation method shown in FIG. 20, dies 35-37 have a single isolation trench 379 on wafer 30 that surrounds each die. Further, as will be described later, the trench 379 is used to form the singulation region 49 and to remove the region 49 from the wafer 30.

  Trench 379 is formed as an opening into substrate 30 and dielectric liner 380 is formed in the sidewalls and bottom of the opening. The dielectric liner is typically a dielectric material such as silicon dioxide. The remainder of the opening is generally filled with filler material 381 (see FIG. 21). In the preferred embodiment, the bottom of the dielectric liner 380 is removed so that the bottom of the trench 379 is open as indicated by the dashed line 384. An example of a method for removing the bottom of the liner 380 is to apply a mask 385 having an opening to expose the trench 379, and to etch through the bottom of the liner 380, such as a spacer etch. A method of performing isotropic etching is included. Etching is selectively performed on the dielectric on the silicon to prevent damage to the portion of the substrate 318 under the trench 379. Mask 385 is typically removed after the bottom of liner 380 is removed. After removing the bottom of the trench 379, the remaining opening of the trench 379 is filled with a filling material 381. Filler material 381 is typically a silicon-based material, such as polysilicon, to facilitate subsequent process steps, as will be described later.

  Those skilled in the art will appreciate that any of the dies 35-37 further have other trenches (eg, trench 378) in the die, and these trenches are similar to the process used to form the trench 379. It will be understood that it is formed using the above process. The trench 378 may retain or remove the bottom oxide, depending on whether the bottom oxide has a useful effect. For example, the trench 378 is filled with doped polysilicon, for example, a metal layer 327 (not shown in FIG. 20), or a low resistance substrate contact or back contact to other contacts at the bottom or back of the substrate 318. I will provide a. However, in the preferred embodiment of the trench 378, the bottom is not removed, and preferably the trench 378 is inside the die and does not surround the outside perimeter of the die. In this way, trench 379 can be formed simultaneously with trench 378 or other similar trenches, thereby reducing manufacturing costs. As will be appreciated by those skilled in the art, the dies 35-37 have various active or passive elements formed on or in the substrate 318.

  The trench 379 is formed in the singulation region 49, preferably in the center of the singulation region, so that at any point in the region 49, the center of the trench 379 is a region such as the midpoint of the two dies. 49, approximately in the middle. As described further below, singulation will occur through approximately the center of the trench 379.

  FIG. 21 shows the wafer 30 in a subsequent stage for an example method for singulating semiconductor dies 35-37 from the wafer 30. FIG. After trench 379 is formed, other portions of die 35-37 are formed, including the formation of contact pads 324 and the formation of dielectric 326 that covers die 35-37. The dielectric 326 generally further covers other portions of the wafer 30 including the portion of the substrate 318 in which singulation regions such as region 49 are formed. A mask 387 is then provided and patterned to expose the underlying dielectric 326, where singulation regions 49 and contact openings are formed. The mask 387 is similar to the mask 332 shown in FIG. 12, but typically the position of the mask 387 is slightly different. The opening in the mask 387 in which the singulation region 49 is formed is further located above the trench 379. The dielectric 326 is etched through the opening in the mask 387 to expose the fill material 381 in the underlying trench 379. Typically, the etching further exposes a pad 324 under the dielectric 326. An opening formed through the dielectric 326 in a region where a singulation region is formed, such as the region 49, functions as the singulation openings 382 and 383. The etching process used to form openings 382, 383 through dielectric 326 is generally the same as the process used to form openings 328, 329 (see FIG. 12) through dielectrics 323, 326. is there. The openings 382 and 383 are typically formed such that the corresponding dielectric liner 380 on the sidewalls of the trench 379 is located below the openings 382 and 383, but the dielectric liner 380 is As long as the material 381 is exposed, it need not be exposed. Those skilled in the art will appreciate that the openings 382, 383 are typically two parts of a single opening that surrounds the die 35-37, but are shown as two openings for cross-sectional view. Will understand.

  After the openings 382, 383 are formed through the dielectrics 326, 323, the mask 387 is removed as indicated by the dashed line and the substrate 318 is thinned as indicated by the dashed line 386. Thinning removes most of the substrate 318 under the trench 379. The substrate 318 is generally the bottom of the trench 379 because the dielectric liner 380 dielectric material may damage or scratch the tool used to thin the wafer 30. It is not made thin until it reaches. Preferably, substrate 318 is thinned until approximately 2-5 microns from the bottom of trench 379 to substrate 318. In some embodiments, the substrate 318 may be thinned until the bottom of the trench 379 is exposed. Thereafter, the bottom surface of substrate 318 is metallized with metal layer 327 as described with respect to FIG. This metallization step is omitted in some embodiments. Subsequently, the wafer 30 is typically attached to a common carrier, such as a common carrier substrate or carrier tape 330.

  FIG. 22 shows the wafer 30 in a subsequent stage for an embodiment of a method for singulating dies 35-37 from the wafer 30. A second opening is formed through filler material 381 to form region 49 as an opening through substrate 318. Substrate 318 is preferably etched through singulation openings 382 and 383 using dielectric 326 as a mask. The etching process is typically performed using a chemical that selectively etches silicon at a much faster rate than the dielectric or metal, similar to the etching described with respect to FIG. An opening through material 381 is formed by the etching process. Typically, etching removes substantially all of the material 381, the singulation region 49 extends from the top surface of the substrate 318 through the fill material 381 of the trench 379, and the region from the wafer 30. 49 is removed. Since the etching step is selectively performed on silicon on the dielectric, the fill material 381 is removed without etching the dielectric liner 380 on the sidewalls of the trench 379. Accordingly, the dielectric liner 380 on the sidewalls of the trench 379 protects the silicon of the substrate 318 from isotropic etching. Isotropic etching has a much higher etching throughput than can be obtained using the Bosch method or using the Bosch method to a limited extent. The isotropic etch process etches any portion of the substrate 318 under the trench 379 through the fill material 381. Thus, an isotropic etch quickly etches any portion under the substrate 318 through the trench 379, thereby singulating the dies 35-37. Such rapid etching improves throughput and reduces manufacturing costs. Further, those skilled in the art will appreciate that the silicon-based material of filler material 381 reduces stress on the material on dielectric liner 380 and substrate 319.

  By singulating the dies 35-37 along the singulation region 49 through the trench 379, the singulation region occupies only a very small space of the semiconductor wafer. For example, the width of the trench 379 containing the fill material 381 is typically only about 3 microns. Thus, the width of the singulation region 49 is only about 3 microns, compared to 100 microns for other methods of singulating the die, such as scribing or wafer sawing. It will be apparent to those skilled in the art that the step of thinning wafer 30 may be omitted and that etching of material 381 may continue until openings 382 and 383 penetrate wafer 30.

  One skilled in the art will appreciate that layer 391 and AlN 393 may be used as a singulation mask, as described with respect to FIGS. 10-13.

  FIG. 23 shows an enlarged plan view of one embodiment of a die having a plurality of non-rectangular shapes, such as dies 233, 237, 241 which are identified by dashed line 230 in FIGS. It is formed on the part. The dies 233, 237, and 241 have corners that do not intersect at right angles. The die 233 has a corner 234 formed by oblique lines having straight lines running obliquely from the side 236 to the side 231. Therefore, the corner is not a right angle but a diagonal line. The diagonal portion of the corner 234 can be used as an alignment key for the die 233 to distinguish the corner 234 from the corner 235 that is perpendicular. This alignment key facilitates the orientation of die 233 when attaching die 233 to a substrate or package during manufacturing operations.

  The die 237 has a corner 238 that forms a right angle and a corner 239 that has a curved shape. The curved shape reduces stress on the corners, thereby improving the reliability of the die 237 throughout the die with right angle corners. Since corner 239 is different from corner 238, in some embodiments, corner 239 can be used as an alignment key. Although corner 239 is shown as a convexly curved shape, corner 239 may be any type of curved shape.

  The die 241 has a corner 242 in which all corners are formed in a curved shape. The curved shape reduces stress and improves the reliability of the die 241.

  One skilled in the art will appreciate that the dies 233, 237 are formed as dies having one corner of a different shape from the other corners of the die, such as corners 234, 239. The shapes of the corners 234, 239 are used to show examples of different corner shapes, and the corner shapes are not limited to diagonal and curved corners. However, any corner needs to be different from the other corners of the die in order to form an alignment key to identify one corner of the die. Further, other corners, such as corner 235, need not be square, but need to be of a different shape than an identifying corner, such as corner 234.

  In addition to the non-rectangular shape, the dies 237, 241 have a shape with at least one curved portion around the outer periphery of the singulated die.

  Those of ordinary skill in the art will recognize that the description contained herein is non-rectangular, multi-connected, and the like, such as one of the dies shown in FIGS. 2-10 and 23. A method of forming a semiconductor die, including a periphery of a top surface of the semiconductor die having one of a shape having an outwardly extending protrusion, an asymmetric shape, and a shape having at least one curved portion You will understand what you do.

  Further, those skilled in the art will appreciate that non-rectangular shapes include triangles, parallelograms, shapes with protrusions extending outwardly along the perimeter, shapes of multiple connections, and shapes that are curved around a portion of the perimeter. It will be appreciated that it includes one of the shapes.

  Furthermore, those skilled in the art will have a semiconductor die with one corner that is shaped differently than other corners, for example as shown by die 233, or the semiconductor die may be by die 237 or die 241, for example. It will be appreciated that it has at least one corner with a curved shape, as shown.

  In addition, those skilled in the art can form a semiconductor die by forming a plurality of semiconductor dies on an upper surface of a semiconductor wafer, wherein two or more of the plurality of semiconductor dies are non-rectangular. , Shapes with at least one protrusion along the periphery, shapes with multiple connections, shapes with at least one curved portion, asymmetric shapes, different values around the perimeter (eg dies 34-42, 151- 157) and a perimeter that is in the shape of one of an irregular shape (eg, indicated by dies 34-42, 51-56, 86-91, 71-74, 136-142) This irregular shape prevents the irregular shape from being singulated by using singulation lines extending axially across the semiconductor wafer Step; step of forming a singulation region as a region of the semiconductor wafer that is between the semiconductor die; and the step of using a dry-etching to singulate a plurality of semiconductor dies concurrently; will be understood to contain.

  Further, those skilled in the art will be able to form a semiconductor die by forming a plurality of semiconductor dies on an upper surface of a semiconductor wafer, wherein at least two of the plurality of semiconductor dies are a plurality of semiconductor dies. In order to prevent multiple semiconductor dies from being singulated by simply using axial singulation lines that extend axially across the portion of the semiconductor wafer on which the dies are formed, an irregular pattern (e.g. A pattern formed by dies 151-157,34-42,51-56,86-91,99-102,124-127,114-115,136-142), and a plurality of It will be appreciated that the method includes using dry etching to simultaneously singulate the semiconductor die.

  FIG. 24 is a plan view of one embodiment of a semiconductor device 500 that includes a semiconductor die 504.

  FIG. 25 is a cross-sectional view of device 500 taken along section line 25-25 in FIG. The following description refers to FIG. 24 and FIG. The die 504 is formed to have a receptacle 506 for receiving other components 510. Component 510 may be another active electrical component such as a semiconductor die, or an active electrical component not formed on a semiconductor substrate such as a gallium nitride light emitting diode, a capacitor, an inductor, or a component of die 504 There may be other types of components such as heat sinks, mold locks or alignment pins or alignment keys or other types of orientation elements to improve power loss. For example, the die 504 is adapted to a package or other device having alignment pins or orientation elements for orientation to match a device that only matches the die 504.

  In one example, component 510 is a semiconductor die and receptacle 506 is an opening through die 504. In this embodiment, component 510 together with die 504 is encapsulated within a semiconductor package 501, such as a package having a plastic package body. Package 501 includes a lead frame having a plurality of connection terminals and a plurality of leads 520-523. Some of the leads 520-523 (eg, leads 520, 522) are electrically connected to the die 504 and other leads (eg, leads 521, 523) are electrically connected to the semiconductor die of the component 510. Connected. In addition, the lead frame of package 501 includes a flag 527 to which die 504 is attached and another flag 518 to which the semiconductor die of component 510 is attached. In other embodiments, the die 504 and the semiconductor die of the component 510 may be attached to a single flag as shown by the dashed lines in FIG. Any type of connection known in the art, such as wire bonds, lead clips, ribbon bonds, etc., can be used for the electrical connections between the leads 520-523, the die 504, and the component 510. Component 510 typically includes a contact pad, such as pad 512, which facilitates the formation of an electrical connection to component 510.

  FIG. 26 shows a top view of one embodiment of a semiconductor device 550 in an alternative embodiment of the device 500 of FIG. In this illustrative example, die 504 has a component 546 within receptacle 506. Component 546 is similar to component 510. In this example, component 546 is a semiconductor die that includes contact pads 547 to facilitate electrical connection to component 546. Component 546 is electrically connected to die 504 instead of being electrically connected to leads 521, 523 as shown in FIG. In other embodiments, component 510 or 546 may have some connections to die 504 and other connections to some of leads 520-523. Component 546 is similar to component 510.

  The placement of the semiconductor die in the embodiment of component 510 or 546 in receptacle 506 facilitates the placement of two different types of semiconductor dies in a single package. The arrangement of components 546 facilitates the formation of short electrical connections between two semiconductor dies that cannot normally be formed on a single semiconductor substrate. For example, between a silicon semiconductor die and a gallium arsenide die, or between a power semiconductor die and a logic semiconductor die used to control the power semiconductor.

  Those skilled in the art will appreciate that although the die 504 is shown as a rectangular multi-connected die, the die 504 can be any of the dies described with respect to FIGS. 2-10 and FIG. Further, the receptacle 506 may be any protruding or curved shape around the die, similar to that described in FIGS. 2-6, or an opening in a multi-connected die.

  FIG. 27 shows a plan view of parts of another embodiment used in the apparatus 500,550. 27 includes dies 34, 35 (see FIG. 2), one of the dies 34, 35 having a receptacle for receiving the other one of the dies 34, 35, which is the die 504 (FIG. 24). -26). For example, die 34 corresponds to die 504 along with die 35, and die 35 has a protrusion that forms a receptacle for receiving die 34. The dies 34, 35 may be connected to each other by connection 495 as described with respect to FIG. 26, or may be connected to leads as described with respect to FIG. You may connect by combining a connection structure.

  FIG. 28 shows an enlarged plan view of a multiple connected die 534 having an opening 535 through the die 534. Opening 535 is located at a location to separate high frequency portion 536 of die 534 from the rest of die 534. The silicon removed from opening 535 ranges from conductive silicon, such as doped silicon, to a minimum dielectric constant of about 11.7 for true silicon. By removing silicon from opening 535, for example, the dielectric constant between portions of die 534 on the opposite side of opening 535 is dramatically reduced to approach 1.0, which is the dielectric constant of air or vacuum. A low dielectric material that separates portion 536 from the remainder of die 534 can be used to minimize capacitive or electromagnetic coupling between regions.

  In view of the foregoing description, one of ordinary skill in the art will provide a first semiconductor die (e.g., die 504) having a receptacle (e.g., receptacle 506) for receiving a second semiconductor die, as one example of a method for forming a semiconductor device. Disposing a second semiconductor die (eg, die 510) in the receptacle; connecting the first semiconductor die to a first connection terminal (eg, connection terminal 520) and connecting the second semiconductor die to a second connection terminal It will be understood that the method includes: connecting to (eg, connection terminal 521); and encapsulating the first and second semiconductor dies in a semiconductor package (eg, package 500).

  The illustrated method further forms the receptacle as one of an opening through the first semiconductor die, a protrusion along the periphery of the first semiconductor die, and a curved shape along the periphery of the first semiconductor die. The method further includes the step of:

  Further, those skilled in the art will now describe the example method of forming a semiconductor die, which includes a first semiconductor die (eg, die 504) having a receptacle (eg, receptacle 506) for receiving a second semiconductor die. Disposing a component (eg, component 510/546) within the receptacle; connecting a first semiconductor die to a first connection terminal (eg, terminal 520); and connecting the component to one of the first semiconductor die It will be understood that the method includes: connecting to one or a second connection terminal (eg, terminal 522); and sealing (eg, sealing in a ceramic body) the first semiconductor die and components. .

  One skilled in the art will recognize the receptacle as one of an opening through the first semiconductor die, a protrusion along the periphery of the first semiconductor die, and a curved shape along the periphery of the first semiconductor die. It will be understood that it further includes the step of forming.

  The method further includes disposing one of an alignment key, a heat sink, a gallium arsenide active device, a non-semiconductor active device, a gallium nitride active, and a passive electrical component within the receptacle.

  For those skilled in the art, from the description herein, a semiconductor device is a first semiconductor die (eg, die 504) having a receptacle (eg, receptacle 506) for receiving a component; and a component (eg, component) disposed within the receptacle. 546).

  In other embodiments, an opening through the die (eg, opening 535, or the opening described with respect to FIGS. 3-6) functions as a mold lock. With respect to mold locking, during the process of sealing the die with the mold mixture, some mold mixture spreads into the opening and assists in locking the mold mixture to the die through the opening. Those skilled in the art will understand that die openings (eg, opening 58 in FIG. 3, opening 104 in FIG. 5, openings 77 and 75 in FIG. 6, opening 535 in FIG. 28) are formed during die singulation. It will be appreciated that it may alternatively be formed prior to singulation. Also, those skilled in the art will recognize other known sealing techniques or devices in place of mold mixtures including the crop top mixture, ceramic bodies such as portions of ceramic semiconductor packages, or other known sealing devices. It will be appreciated that may be used.

  Die 504 is shown as having four connections or terminals, and dies 510 and 546 are shown as having two connections or terminals, but those skilled in the art will recognize that any die can have any number of connections. It will be understood that connections or terminals can be provided.

  In view of all of the above, a new shape die and a new method for forming a new shape die have been disclosed. Among other features, waste of wafers, especially by forming dies with various shapes, and maximizing the number of dies that can be formed on the wafer, including die placement. Includes minimizing the amount.

  Although the subject matter of the present invention has been described with particular preferred and different embodiments, the above-described drawings and related descriptions are merely exemplary embodiments of the subject matter of the present invention and, therefore, the present invention. It should be understood that the scope is not limited and many alternatives and variations will occur to those skilled in the art. Those of ordinary skill in the art will not need to remove all of the region 49 to singulate the die with respect to FIG. 2, but only the portion surrounding the outer perimeter need only be removed, for example, the section 67 may not be removed. You will understand that it is good. In addition, sections similar to sections 67 or 68 can be used for any die on wafer 30. To prevent any of the protective layers, such as the singulation mask described herein, or the selective etch layer, such as the dielectric layer or layer 324, from being etched during the simultaneous singulation of the semiconductor die. Can be used to protect the enhancement area. The typical shape of a die, such as die 35-37 in FIGS. 2-10 and 23, is a means for describing various methods for singulating the shape of the die, as described herein. Used as. However, those skilled in the art will appreciate that the method of singulating several dies, as described herein, is applicable to singulate any die. Further, the groups of dies shown in FIGS. 2-10 and 23 are not intended to limit the dies being formed with other specific die shapes, but use any combination of die shapes. Can do.

30: Semiconductor wafer 31: Singulation line 34-42, 51-56, 86-91, 99-102, 71-74, 124-127, 114-116, 136-142, 151-157: Die 49, 65, 80, 94, 109, 130, 119, 145, 160: Singulation region 318: Substrate 319: Bulk substrate 320: Epitaxial layer 321: Doped region 323, 326: Dielectric 324: Contact pad 391, 393: AlN layer 328, 329: opening 332, 387: mask 327: metal layer 330: transport (carrier) tape 401, 405, 409: polymer 335, 336: sidewall 379: trench 380: dielectric liner 500: semiconductor device 504: Die 510: Component 512 Pad 522: lead

Claims (5)

Providing a first semiconductor die having a receptacle for receiving a second semiconductor die;
Disposing the second semiconductor die in the receptacle;
Connecting the first semiconductor die to a first connection terminal and connecting the second semiconductor die to a second connection terminal;
Sealing the first semiconductor die and the second semiconductor die in a semiconductor package;
A method of forming a semiconductor device comprising:   Providing a first semiconductor die having the receptacle includes an opening through the first semiconductor die, a protrusion along the periphery of the first semiconductor die, and a curved shape along the periphery of the first semiconductor die. The method of claim 1 including providing the first semiconductor die with the receptacle being one of them.   The method of claim 1, wherein a dry etching method is used to singulate the first semiconductor die from a semiconductor wafer and simultaneously form the receptacle. Providing a first semiconductor die having a receptacle for receiving a second semiconductor die;
Placing a component in the receptacle;
Connecting the first semiconductor die to a first connection terminal;
Connecting the electrical component to one or a second connection terminal of the first semiconductor die;
Encapsulating the first semiconductor die and the component;
A method of forming a semiconductor die comprising: A first semiconductor die having a receptacle for receiving an electrical component;
A component disposed within the receptacle;
A semiconductor device comprising:

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