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JP5023614B2 - Semiconductor chip manufacturing method and semiconductor wafer processing method - Google Patents

Semiconductor chip manufacturing method and semiconductor wafer processing method Download PDF

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JP5023614B2
JP5023614B2 JP2006227647A JP2006227647A JP5023614B2 JP 5023614 B2 JP5023614 B2 JP 5023614B2 JP 2006227647 A JP2006227647 A JP 2006227647A JP 2006227647 A JP2006227647 A JP 2006227647A JP 5023614 B2 JP5023614 B2 JP 5023614B2
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resist film
semiconductor wafer
semiconductor
plasma
boundary groove
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JP2008053417A (en
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宏 土師
潔 有田
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Panasonic Corp
Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Priority to US12/373,813 priority patent/US7964449B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/36—Removing material
    • B23K26/40—Removing material taking account of the properties of the material involved
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B28—WORKING CEMENT, CLAY, OR STONE
    • B28D—WORKING STONE OR STONE-LIKE MATERIALS
    • B28D5/00—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2103/00—Materials to be soldered, welded or cut
    • B23K2103/50—Inorganic material, e.g. metals, not provided for in B23K2103/02 – B23K2103/26

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Optics & Photonics (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Dicing (AREA)
  • Drying Of Semiconductors (AREA)

Description

本発明は、複数の半導体素子が形成された半導体ウエハをプラズマエッチングにより切り分けて半導体チップを製造する半導体チップの製造方法及び半導体ウエハの処理方法に関するものである。   The present invention relates to a semiconductor chip manufacturing method for manufacturing a semiconductor chip by cutting a semiconductor wafer on which a plurality of semiconductor elements are formed by plasma etching, and a semiconductor wafer processing method.

半導体ウエハは厚さ数十μｍ程度にまで薄化してきており、加工や運搬工程においては曲げや反り、衝撃などの外力をなるべく与えないようにする取り扱いが必要である。半導体ウエハを個々の半導体チップに切り分けるダイシング工程では従来、円形刃等を用いた機械的な切断方法が一般的であったが、近年、機械的な切断によるウエハへのダメージを軽減し得るプラズマダイシングと呼ばれる方法が提案されている。プラズマダイシングは、半導体ウエハの一方の面に形成したレジスト膜にマスクを通してダイシングパターンを露光転写することによってレジスト膜に半導体素子同士を区分する境界溝を形成し、その境界溝に露出した半導体ウエハの表面をプラズマエッチングによって除去して半導体ウエハを境界溝に沿って個々の半導体チップに切り分けるというものである。   Semiconductor wafers have been thinned to a thickness of about several tens of μm, and it is necessary to handle them so that external forces such as bending, warping, and impact are not applied as much as possible in processing and transportation processes. Conventionally, a mechanical cutting method using a circular blade or the like is generally used in a dicing process for cutting a semiconductor wafer into individual semiconductor chips, but in recent years, plasma dicing can reduce damage to the wafer due to mechanical cutting. A method called as is proposed. In plasma dicing, a dicing pattern is exposed and transferred through a mask to a resist film formed on one surface of a semiconductor wafer to form a boundary groove for separating the semiconductor elements in the resist film, and the semiconductor wafer exposed in the boundary groove is formed. The surface is removed by plasma etching, and the semiconductor wafer is cut into individual semiconductor chips along the boundary grooves.

また、ダイシングパターンを露光転写によって形成させるのではなく、ダイシングパターンによって形成される境界溝に相当する部分にレーザ光を照射してその部分のレジスト膜を除去していく方法が提案されている（特許文献１）。この方法では高価な露光転写装置を用いる必要がないので、プラズマダイシングを低コストで行うことができる。
特開２００５−１９１０３９号公報 Also, a method is proposed in which a dicing pattern is not formed by exposure transfer, but a portion corresponding to a boundary groove formed by the dicing pattern is irradiated with laser light to remove the resist film in that portion ( Patent Document 1). In this method, since it is not necessary to use an expensive exposure transfer apparatus, plasma dicing can be performed at a low cost.
JP 2005-191039 A

しかしながら、レーザ光の照射によってレジスト膜に形成された境界溝の表面は滑らかではなく、鋭角に尖ったギザギザな凹凸形状となっている。このような境界溝の表面形状は、脈動のあるレーザ光によってレジスト膜を切断したためにそのレジスト膜の切断面に凹凸部ができたり、レジスト膜の切断時に周囲に飛散した残渣が境界溝の表面に付着したりしたことなどによって形成されたものである。このように境界溝の表面がギザギザな凹凸形状のままプラズマエッチングを行って個々の半導体チップに切り分けると、切り分けられた半導体チップの側面もギザギザな形状になってしまうが、半導体チップの側面の微小な凹凸部分、いわゆるチッピング部分には、外力が加わったときに応力集中が起き易く、その応力集中が起きた部分を基点に亀裂が生じて半導体チップが割れ易いという問題がある。   However, the surface of the boundary groove formed in the resist film by laser light irradiation is not smooth, but has a jagged uneven shape with sharp edges. The surface shape of such a boundary groove is that the resist film is cut by a pulsating laser beam, so that the cut surface of the resist film has irregularities, or residues scattered around when the resist film is cut are the surface of the boundary groove Or the like. If the surface of the boundary groove is cut into individual semiconductor chips by performing plasma etching while the surface of the boundary groove is jagged asperity, the side surface of the cut semiconductor chip also becomes jagged, but the side surface of the semiconductor chip is very small. Such an uneven portion, so-called chipping portion, has a problem that stress concentration is likely to occur when an external force is applied, and the semiconductor chip is likely to be cracked due to cracks originating from the portion where the stress concentration has occurred.

そこで本発明は、チッピングのない割れにくい半導体チップを製造することができる半導体チップの製造方法及び半導体ウエハの処理方法を提供することを目的とする。   Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor chip and a method for processing a semiconductor wafer, which can manufacture a semiconductor chip that is not easily cracked without chipping.

請求項１に記載の半導体チップの製造方法は、複数の半導体素子が形成された半導体ウエハの一方の面に有機物であるレジスト膜を形成するレジスト膜形成工程と、レジスト膜の半導体素子同士の境界部にレーザ光を照射してレジスト膜に半導体素子同士を区分する境界溝を形成し、その境界溝に半導体ウエハの表面を露出させるレーザ加工工程と、境界溝に露出した半導体ウエハの表面をフッ素系ガスのプラズマによりエッチングし、半導体ウエハを境界溝に沿って個々の半導体チップに切り分けるプラズマエッチング工程とを含み、前記レーザ加工工程と前記プラズマエッチング工程の間に、前記レーザ加工工程において凹凸形状となった境界溝の表面の凹凸部を酸素ガス若しくは酸素を主成分とする混合ガスのプラズマにより灰化して平滑化する境界溝表面平滑化工程を実行する。 The method of manufacturing a semiconductor chip according to claim 1 includes a resist film forming step of forming a resist film that is an organic substance on one surface of a semiconductor wafer on which a plurality of semiconductor elements are formed, and a boundary between the semiconductor elements of the resist film. A laser beam is formed on the resist film to form a boundary groove for separating the semiconductor elements, and the surface of the semiconductor wafer is exposed in the boundary groove, and the surface of the semiconductor wafer exposed in the boundary groove is fluorinated. A plasma etching step of etching with a plasma of a system gas and cutting a semiconductor wafer into individual semiconductor chips along a boundary groove, and an irregular shape in the laser processing step between the laser processing step and the plasma etching step. and an uneven portion of the surface of the turned boundary groove ashed by the plasma of a mixed gas mainly composed of oxygen gas or oxygen Executing a smoothed boundary groove surface smoothing step.

請求項２に記載の半導体チップの製造方法は、請求項１に記載の半導体チップの製造方法において、境界溝表面平滑化工程における境界溝の表面の平滑化は、境界溝の表面の凹凸部を酸素ガス若しくは酸素を主成分とする混合ガスのプラズマにより均して凹凸部の凹凸周期を大きくして行う。 The method for manufacturing a semiconductor chip according to claim 2 is the method for manufacturing a semiconductor chip according to claim 1, wherein the smoothing of the surface of the boundary groove in the boundary groove surface smoothing step is performed by using the uneven portion on the surface of the boundary groove. It is carried out by increasing the uneven period of the uneven part uniformly by plasma of oxygen gas or a mixed gas containing oxygen as a main component.

請求項３に記載の半導体チップの製造方法は、請求項１又は２に記載の半導体チップの製造方法において、プラズマエッチング工程の後、レジスト膜を酸素ガス若しくは酸素を主成分とする混合ガスのプラズマにより除去するレジスト膜除去工程を実行する。 The method for manufacturing a semiconductor chip according to claim 3 is the method for manufacturing a semiconductor chip according to claim 1 or 2, wherein after the plasma etching step, the resist film is plasma of oxygen gas or a mixed gas containing oxygen as a main component. A resist film removing step to be removed is executed.

請求項４に記載の半導体チップの製造方法は、請求項１乃至３のいずれかに記載の半導体チップの製造方法において、レジスト膜を半導体ウエハの半導体素子が形成された回路パターン形成面とは反対側の面に形成する。 The method for manufacturing a semiconductor chip according to claim 4 is the method for manufacturing a semiconductor chip according to any one of claims 1 to 3 , wherein the resist film is opposite to the circuit pattern forming surface on which the semiconductor element of the semiconductor wafer is formed. Form on the side surface.

請求項５に記載の半導体ウエハの処理方法は、複数の半導体素子が形成された半導体ウエハの一方の面に有機物であるレジスト膜を形成するレジスト膜形成工程と、レジスト膜の半導体素子同士の境界部にレーザ光を照射してレジスト膜に半導体素子同士を区分する境界溝を形成し、その境界溝に半導体ウエハの表面を露出させるレーザ加工工程と、レーザ加工工程が済んだ半導体ウエハをプラズマ処理装置の真空チャンバ内に搬入するウエハ搬入工程と、真空チャンバ内に発生させた酸素ガス若しくは酸素を主成分とする混合ガスのプラズマにより前記レーザ加工工程において凹凸形状となった境界溝の表面の凹凸部を灰化して平滑化する境界溝表面平滑化工程と、境界溝平滑化工程の後、境界溝に露出した半導体ウエハの表面をフッ素系ガスのプラズマによりエッチングし、半導体ウエハを境界溝に沿って個々の半導体チップに切り分けるプラズマエッチング工程と、プラズマエッチング工程が済んだ半導体ウエハを真空チャンバから搬出するウエハ搬出工程とを含む。 6. The method for processing a semiconductor wafer according to claim 5 , wherein a resist film forming step of forming a resist film which is an organic substance on one surface of the semiconductor wafer on which a plurality of semiconductor elements are formed, and a boundary between the semiconductor elements of the resist film A laser beam is irradiated onto the resist film to form a boundary groove that separates semiconductor elements from each other in the resist film, and a laser processing step that exposes the surface of the semiconductor wafer in the boundary groove, and a plasma processing of the semiconductor wafer that has undergone the laser processing step The wafer loading process for loading into the vacuum chamber of the apparatus, and the unevenness of the surface of the boundary groove that has become uneven in the laser processing process due to the plasma of oxygen gas generated in the vacuum chamber or a mixed gas containing oxygen as a main component and boundary groove surface smoothing step of smoothing by ashing the part after the boundary groove smoothing step, fluorine-based surface of a semiconductor wafer which is exposed to the boundary groove Etched by the scan of a plasma, comprising a plasma etching step cut into individual semiconductor chips along the semiconductor wafer in the boundary groove, the semiconductor wafer having undergone the plasma etching process and a wafer unloading step for unloading from the vacuum chamber.

請求項６に記載の半導体ウエハの処理方法は、請求項５に記載の半導体ウエハの処理方法において、前記プラズマエッチング工程と前記ウエハ搬出工程の間に、真空チャンバ内に発生させた酸素ガスもしくは酸素を主成分とする混合ガスのプラズマによりレジスト膜を除去するレジスト膜除去工程を実行する。 The semiconductor wafer processing method according to claim 6 is the semiconductor wafer processing method according to claim 5 , wherein oxygen gas or oxygen generated in a vacuum chamber between the plasma etching step and the wafer unloading step is provided. A resist film removing step is performed in which the resist film is removed by plasma of a mixed gas containing as a main component.

本発明では、有機物であるレジスト膜の半導体素子同士の境界部にレーザ光を照射してレジスト膜に半導体素子同士を区分する境界溝を形成し、その境界溝に半導体ウエハの表面を露出させた後、フッ素系ガスのプラズマによるエッチングを行って半導体ウエハを境界溝に沿って個々の半導体チップに切り分けるのであるが、そのフッ素系ガスのプラズマによるエッチングを行う前に、レーザ加工工程において凹凸形状となった境界溝の表面の凹凸部を酸素ガス若しくは酸素を主成分とする混合ガスのプラズマにより灰化して平滑化するようにしている。このため、プラズマエッチングによる半導体ウエハの切断面、すなわち切り分けられた半導体チップの側面を平坦なものとすることができ、チッピングのない割れにくい半導体チップが得られる。 In the present invention, a boundary groove for separating the semiconductor elements is formed in the resist film by irradiating the boundary between the semiconductor elements of the resist film, which is an organic substance, with a laser beam, and the surface of the semiconductor wafer is exposed in the boundary groove. After that, etching with a fluorine-based gas plasma is performed to divide the semiconductor wafer into individual semiconductor chips along the boundary grooves. The uneven portion on the surface of the boundary groove thus formed is ashed and smoothed by plasma of oxygen gas or a mixed gas containing oxygen as a main component. For this reason, the cut surface of the semiconductor wafer by plasma etching, that is, the side surface of the cut semiconductor chip can be flattened, and a semiconductor chip that is not easily chipped without chipping can be obtained.

以下、図面を参照して本発明の実施の形態を説明する。図１は本発明の一実施の形態における半導体チップの製造方法の実施に使用されるレーザ加工装置の斜視図、図２は本発明の一実施の形態における半導体チップの製造方法の実施に使用されるプラズマ処理装置の断面図、図３及び図４は本発明の一実施の形態における半導体チップの製造方法の工程説明図、図５は本発明の一実施の形態における半導体チップの製造方法の工程の流れを示すフローチャート、図６は本発明の一実施の形態における半導体チップの製造方法の境界溝表面平滑化工程の前後における境界溝の表面の変化の様子を（ａ），（ｂ）の順で示す図である。   Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a perspective view of a laser processing apparatus used to implement a semiconductor chip manufacturing method according to an embodiment of the present invention, and FIG. 2 is used to implement a semiconductor chip manufacturing method according to an embodiment of the present invention. FIG. 3 and FIG. 4 are process explanatory views of a method for manufacturing a semiconductor chip according to an embodiment of the present invention, and FIG. 5 is a process of the method for manufacturing a semiconductor chip according to an embodiment of the present invention. FIG. 6 is a flowchart showing the flow of the boundary groove surface before and after the boundary groove surface smoothing step of the semiconductor chip manufacturing method according to the embodiment of the present invention in the order of (a) and (b). It is a figure shown by.

先ず、図１及び図２を用いて本発明の一実施の形態における半導体チップの製造方法の実施に使用されるレーザ加工装置１０とプラズマ処理装置３０の構成について説明する。   First, the structure of the laser processing apparatus 10 and the plasma processing apparatus 30 used for implementation of the semiconductor chip manufacturing method according to one embodiment of the present invention will be described with reference to FIGS.

図１において、レーザ加工装置１０は加工対象となる半導体ウエハ１を水平姿勢に保持するウエハ保持部１１、ウエハ保持部１１の上方において移動自在に設けられた移動プレート１２、移動プレート１２に固定されたレーザ照射部１３及びカメラ１４のほか、移動プレート１２を移動させる移動機構１５、レーザ照射部１３にレーザ光を発生させるレーザ発生部１６、移動機構１５の駆動制御及びレーザ発生部１６におけるレーザ発生制御を行う制御部１７、カメラ１４の撮像画像から半導体ウエハ１の位置認識を行う認識部１８、制御部１７に操作信号・入力信号を与える操作・入力部１９等を有して成る。   In FIG. 1, a laser processing apparatus 10 is fixed to a wafer holding unit 11 that holds a semiconductor wafer 1 to be processed in a horizontal posture, a moving plate 12 that is movably provided above the wafer holding unit 11, and a moving plate 12. In addition to the laser irradiation unit 13 and the camera 14, the moving mechanism 15 that moves the moving plate 12, the laser generation unit 16 that generates laser light in the laser irradiation unit 13, the drive control of the movement mechanism 15, and the laser generation in the laser generation unit 16 A control unit 17 that performs control, a recognition unit 18 that recognizes the position of the semiconductor wafer 1 from an image captured by the camera 14, an operation / input unit 19 that supplies an operation signal / input signal to the control unit 17, and the like.

ウエハ保持部１１は上面に半導体ウエハ１を固定保持する真空チャック等の固定保持具を有しており、半導体ウエハ１はこの固定保持具によりレーザ加工が行われる面（後述するレジスト膜４が形成された面）を上に向けて固定保持される。移動プレート１２は移動機構１５を介して制御部１７によって移動制御がなされ、移動プレート１２に固定されたレーザ照射部１３及びカメラ１４は半導体ウエハ１の上方において三次元的に移動される。レーザ発生部１６は制御部１７より制御されてレーザ照射部１３にレーザを発生させ、レーザ照射部１３は発生したレーザを下方に照射する。カメラ１４は直下に位置する半導体ウエハ１を赤外光により撮像する。認識部１８はカメラ１４の撮像画像から半導体ウエハ１の位置認識を行い、その結果得られた半導体ウエハ１の位置情報を制御部１７へ送信する。制御部１７は、認識部１８から送信された半導体ウエハ１の位置情報に基づいて半導体ウエハ１とレーザ照射部１３との位置関係を把握し、レーザ照射部１３から照射されるレーザ光１３ａの照射位置を算出する。操作・入力部１９はオペレータの操作に応じ、移動機構１５の操作信号やレーザ発生部１６の作動に関する入力信号等を制御部１７に与える。   The wafer holder 11 has a fixing holder such as a vacuum chuck for fixing and holding the semiconductor wafer 1 on the upper surface, and the semiconductor wafer 1 is subjected to laser processing by this fixing holder (a resist film 4 described later is formed). The fixed surface is fixed and held upward. The moving plate 12 is controlled to move by the control unit 17 via the moving mechanism 15, and the laser irradiation unit 13 and the camera 14 fixed to the moving plate 12 are moved three-dimensionally above the semiconductor wafer 1. The laser generator 16 is controlled by the controller 17 to cause the laser irradiation unit 13 to generate a laser, and the laser irradiation unit 13 irradiates the generated laser downward. The camera 14 images the semiconductor wafer 1 located immediately below with infrared light. The recognition unit 18 recognizes the position of the semiconductor wafer 1 from the captured image of the camera 14 and transmits the position information of the semiconductor wafer 1 obtained as a result to the control unit 17. The control unit 17 grasps the positional relationship between the semiconductor wafer 1 and the laser irradiation unit 13 based on the position information of the semiconductor wafer 1 transmitted from the recognition unit 18, and irradiates the laser beam 13 a irradiated from the laser irradiation unit 13. Calculate the position. The operation / input unit 19 gives an operation signal of the moving mechanism 15, an input signal related to the operation of the laser generator 16, and the like to the control unit 17 in accordance with the operation of the operator.

図２において、プラズマ処理装置３０は真空チャンバ３１、真空チャンバ３１内に設けられた下部電極３２と上部電極３３、下部電極３２に高周波電圧を印加する高周波電源部３４、冷媒を下部電極３２内に循環させる冷却ユニット３５、上部電極３３内から真空チャンバ３１の外部に延び、真空チャンバ３１の外部において二股に分かれたガス供給路３６、二股に分かれたガス供給路３６の一方側の分岐路（第１分岐路３６ａとする）に接続された酸素ガス供給部３７、二股に分かれたガス供給路３６の他方側の分岐路（第２分岐路３６ｂとする）に接続されたフッ素系ガス供給部３８、第１分岐路３６ａ中に介装された第１開閉弁３９及び第１流量制御弁４０、第２分岐路３６ｂ中に介装された第２開閉弁４１及び第２流量制御弁４２から成っている。   In FIG. 2, the plasma processing apparatus 30 includes a vacuum chamber 31, a lower electrode 32 and an upper electrode 33 provided in the vacuum chamber 31, a high-frequency power supply unit 34 for applying a high-frequency voltage to the lower electrode 32, and a refrigerant in the lower electrode 32. The cooling unit 35 to be circulated, the inside of the upper electrode 33, extends to the outside of the vacuum chamber 31, and is divided into a bifurcated gas supply path 36 and a bifurcated gas supply path 36 on one side of the bifurcated gas supply path 36. An oxygen gas supply unit 37 connected to the first branch path 36a, and a fluorine-based gas supply section 38 connected to the other branch path (referred to as the second branch path 36b) of the bifurcated gas supply path 36. The first on-off valve 39 and the first flow control valve 40 interposed in the first branch path 36a, and the second on-off valve 41 and the second flow control valve 42 interposed in the second branch path 36b. It is made.

真空チャンバ３１の内部は半導体ウエハ１に対してプラズマ処理を行うための密閉空間
となっている。下部電極３２は真空チャンバ３１内において半導体ウエハ１の保持面を上にして設けられており、上部電極３３の下面は下部電極３２の上方において上部電極３２の上面と対向するように設けられている。 The inside of the vacuum chamber 31 is a sealed space for performing plasma processing on the semiconductor wafer 1. The lower electrode 32 is provided in the vacuum chamber 31 with the holding surface of the semiconductor wafer 1 facing upward, and the lower surface of the upper electrode 33 is provided above the lower electrode 32 so as to face the upper surface of the upper electrode 32. .

下部電極３２の上面には真空チャックや静電吸引機構等から成るウエハ保持機構（図示せず）と電気絶縁性材料から成るリング状のフレーム３２ａが設けられており、半導体ウエハ１はプラズマ処理が施される面を上に向け、フレーム３２ａによって周囲が囲まれるように支持されて、ウエハ保持機構によって下部電極３２の上面に固定される。   On the upper surface of the lower electrode 32, a wafer holding mechanism (not shown) including a vacuum chuck and an electrostatic suction mechanism and a ring-shaped frame 32a made of an electrically insulating material are provided. The semiconductor wafer 1 is subjected to plasma processing. The surface to be applied is faced up, supported by the frame 32a so as to be surrounded by the frame 32a, and fixed to the upper surface of the lower electrode 32 by the wafer holding mechanism.

酸素ガス供給部３７内には酸素ガス（酸素を主成分とする混合ガスであってもよい）が封入されており、その酸素ガスは、第１開閉弁３９が開弁されているとき（第２開閉弁４１は閉弁される）、第１分岐路３６ａ及びガス供給路３６を介して上部電極３３に供給される。酸素ガス供給部３７から上部電極３３に供給される酸素ガスの流量は、第１流量制御弁４０の開度調節によって行う。また、フッ素系ガス供給部３８内には例えば六弗化硫黄（ＳＦ６）等のフッ素系ガスが封入されており、そのフッ素系ガスは、第２開閉弁４１が開弁されているとき（第１開閉弁３９は閉弁される）、第２分岐路３６ｂ及びガス供給路３６を介して上部電極３３に供給される。フッ素系ガス供給部３８から上部電極３３に供給されるフッ素系ガスの流量は、第２流量制御弁４２の開度調節によって行う。 An oxygen gas (may be a mixed gas containing oxygen as a main component) is sealed in the oxygen gas supply unit 37, and the oxygen gas is supplied when the first on-off valve 39 is opened (first 2 on-off valve 41 is closed), and is supplied to upper electrode 33 via first branch path 36a and gas supply path 36. The flow rate of the oxygen gas supplied from the oxygen gas supply unit 37 to the upper electrode 33 is adjusted by adjusting the opening of the first flow control valve 40. Further, a fluorine-based gas such as sulfur hexafluoride (SF 6 ) is sealed in the fluorine-based gas supply unit 38, and the fluorine-based gas is used when the second on-off valve 41 is opened ( The first on-off valve 39 is closed), and is supplied to the upper electrode 33 via the second branch path 36b and the gas supply path 36. The flow rate of the fluorine-based gas supplied from the fluorine-based gas supply unit 38 to the upper electrode 33 is adjusted by adjusting the opening of the second flow rate control valve 42.

上部電極３３の下面には平板状の多孔質プレート３３ａが設けられており、ガス供給路３６を介して供給された酸素ガスやフッ素系ガスは、この多孔質プレート３３ａを介して下部電極３２の上面に均一に吹き付けられる。   A flat plate-like porous plate 33a is provided on the lower surface of the upper electrode 33, and oxygen gas and fluorine-based gas supplied through the gas supply path 36 are supplied to the lower electrode 32 through the porous plate 33a. The top surface is evenly sprayed.

次に、図３、図４及び図５を参照して半導体チップの製造方法を説明する。図３（ａ）において、半導体ウエハ１の回路パターン形成面１ａには複数の半導体素子２が形成されており、隣接する半導体素子２の間の境界部を切断すれば複数の半導体チップに切り分けられる状態となっている。   Next, a semiconductor chip manufacturing method will be described with reference to FIGS. In FIG. 3A, a plurality of semiconductor elements 2 are formed on a circuit pattern forming surface 1a of a semiconductor wafer 1, and if a boundary portion between adjacent semiconductor elements 2 is cut, it can be divided into a plurality of semiconductor chips. It is in a state.

この半導体ウエハ１から半導体チップを製造するには、先ず図３（ａ）に示すように、半導体ウエハ１の回路パターン形成面１ａに粘着質のシート状のＵＶテープ３を貼り付ける（図５に示すＵＶテープ貼付工程Ｓ１）。このＵＶテープ３は、最終的に半導体ウエハ１が半導体チップごとに切り出されたときに、半導体チップ同士がばらばらになってしまわないようにするために設けられるものである。   In order to manufacture a semiconductor chip from the semiconductor wafer 1, first, as shown in FIG. 3A, an adhesive sheet-like UV tape 3 is attached to the circuit pattern forming surface 1a of the semiconductor wafer 1 (see FIG. 5). UV tape application process S1) shown. The UV tape 3 is provided to prevent the semiconductor chips from being separated when the semiconductor wafer 1 is finally cut out for each semiconductor chip.

半導体ウエハ１の回路パターン形成面１ａにＵＶテープ３を貼付したら、図３（ｂ）に示すように、半導体ウエハ１の一方の面にレジスト膜４を形成する（図５に示すレジスト膜形成工程Ｓ２）。本実施の形態では、半導体ウエハ１の回路パターン形成面１ａとは反対側の面にレジスト膜４を形成する。このレジスト膜４はフッ素系ガスのプラズマに対して耐性を有する材質、例えばアルミニウムや樹脂等で形成される。アルミニウムを用いる場合には、蒸着処理による方法や、箔状のアルミ膜を貼り付ける方法などが用いられる。また、樹脂を用いる場合には、膜状に形成された樹脂を貼り付ける方法や、液状の樹脂をスピンコーティングにより塗布する方法等が用いられる。   When the UV tape 3 is attached to the circuit pattern forming surface 1a of the semiconductor wafer 1, a resist film 4 is formed on one surface of the semiconductor wafer 1 as shown in FIG. 3B (resist film forming step shown in FIG. 5). S2). In the present embodiment, the resist film 4 is formed on the surface of the semiconductor wafer 1 opposite to the circuit pattern formation surface 1a. The resist film 4 is formed of a material having resistance to fluorine-based gas plasma, such as aluminum or resin. In the case of using aluminum, a method by vapor deposition, a method of attaching a foil-like aluminum film, or the like is used. Moreover, when using resin, the method of sticking resin formed in the film form, the method of apply | coating liquid resin by spin coating, etc. are used.

半導体ウエハ１の一方の面にレジスト膜４を形成したら、半導体ウエハ１をレーザ加工装置１０のウエハ保持部１１に設置する。そして、図３（ｃ），（ｄ）に示すように、レジスト膜４の半導体素子２同士の境界部（隣接する半導体素子２の間の部分）にレーザ光１３ａを照射してその部分のレジスト膜４を除去し、レジスト膜４に半導体素子２同士を区分する境界溝５を形成する（図５に示すレーザ加工工程Ｓ３）。   After the resist film 4 is formed on one surface of the semiconductor wafer 1, the semiconductor wafer 1 is placed on the wafer holding unit 11 of the laser processing apparatus 10. Then, as shown in FIGS. 3C and 3D, the resist film 4 is irradiated with a laser beam 13a on the boundary portion between the semiconductor elements 2 of the resist film 4 (the portion between the adjacent semiconductor elements 2), and the resist in that portion. The film 4 is removed, and a boundary groove 5 for separating the semiconductor elements 2 from each other is formed in the resist film 4 (laser processing step S3 shown in FIG. 5).

このレーザ加工は、半導体ウエハ１に対してレーザ光１３ａを相対的に移動させながら
行う。レーザ加工装置１０のワークデータ記憶部２０には境界溝５の位置に関するデータが記憶されており、制御部１７はこのワークデータ記憶部２０に記憶されたデータに基づいてレーザ照射部１３を移動させる。具体的には、制御部１７は、カメラ１４及び認識部１８を介して得られたレーザ光１３ａの照射位置と、ワークデータ記憶部２０に記憶された境界溝５の位置のデータとを比較し、レーザ光１３ａの照射位置がワークデータ記憶部２０に記憶された境界溝５上を移動するように移動機構１５を駆動する。また、ワークデータ記憶部２０には境界溝５の幅のデータも記憶されており、制御部１７はレーザ照射部１３からレーザ光１３ａを照射させる際、レーザ照射部１３の出力を変化させてレーザ光１３ａのビーム径を調節し、実際に形成される境界溝５の幅がワークデータ記憶部２０に記憶された境界溝５の幅よりもやや狭くなるようにする。 This laser processing is performed while moving the laser beam 13 a relative to the semiconductor wafer 1. Data relating to the position of the boundary groove 5 is stored in the work data storage unit 20 of the laser processing apparatus 10, and the control unit 17 moves the laser irradiation unit 13 based on the data stored in the work data storage unit 20. . Specifically, the control unit 17 compares the irradiation position of the laser beam 13 a obtained through the camera 14 and the recognition unit 18 with the data on the position of the boundary groove 5 stored in the work data storage unit 20. The moving mechanism 15 is driven so that the irradiation position of the laser beam 13 a moves on the boundary groove 5 stored in the work data storage unit 20. Moreover, the width data of the boundary groove 5 is also stored in the work data storage unit 20, and when the control unit 17 irradiates the laser beam 13a from the laser irradiation unit 13, the output of the laser irradiation unit 13 is changed to change the laser. The beam diameter of the light 13a is adjusted so that the width of the boundary groove 5 actually formed is slightly narrower than the width of the boundary groove 5 stored in the work data storage unit 20.

レーザ加工工程Ｓ３が終了したら、半導体ウエハ１をレーザ加工装置１０のウエハ保持部１１から取り外し、プラズマ処理装置３０の真空チャンバ３１内に搬入して、半導体ウエハ１を下部電極３２の上面に固定する（図５に示すウエハ搬入工程Ｓ４）。このとき、半導体ウエハ１は、レジスト膜４が形成された面が上方に向くようにする。   When the laser processing step S3 is completed, the semiconductor wafer 1 is removed from the wafer holder 11 of the laser processing apparatus 10 and carried into the vacuum chamber 31 of the plasma processing apparatus 30 to fix the semiconductor wafer 1 to the upper surface of the lower electrode 32. (Wafer carrying-in process S4 shown in FIG. 5). At this time, the surface of the semiconductor wafer 1 on which the resist film 4 is formed is directed upward.

この段階において、レーザ加工された境界溝５の表面は、鋭角に尖ったギザギザな凹凸形状となっている。ここで「境界溝５の表面」とは、レーザ光１３ａでレジスト膜４を切り裂くことによって生じたレジスト膜４の対向する２つの切断面４ａと、これら２つの切断面４ａの間から境界溝５に露出した半導体ウエハ１の表面１ｂから成る面を指す（図３（ｄ）の部分拡大図参照）。境界溝５の表面がギザギザな凹凸形状となるのは、脈動のあるレーザ光１３ａによってレジスト膜４を切断したためにそのレジスト膜４の切断面４ａに凹凸部４ｂができたり、レジスト膜４の切断時に周囲に飛散した残渣４ｃが境界溝５の表面に付着したりすること等による（図６（ａ））。   At this stage, the laser-processed surface of the boundary groove 5 has a jagged uneven shape with sharp angles. Here, the “surface of the boundary groove 5” means two opposing cut surfaces 4a of the resist film 4 generated by cutting the resist film 4 with the laser beam 13a, and the boundary groove 5 between the two cut surfaces 4a. The surface which consists of the surface 1b of the semiconductor wafer 1 exposed to (refer the partial enlarged view of FIG.3 (d)). The surface of the boundary groove 5 has a jagged uneven shape because the resist film 4 is cut by the pulsating laser beam 13a, and thus the cut surface 4a of the resist film 4 has an uneven portion 4b or the resist film 4 is cut. This is because the residue 4c scattered around the surface sometimes adheres to the surface of the boundary groove 5 (FIG. 6A).

この状態で後述のプラズマエッチング工程Ｓ６（図５）を行うと、切り分けられた半導体チップの側面もギザギザな形状になってしまい、そこに応力集中が発生し易くなる。このため半導体ウエハ１を真空チャンバ３１内に搬入したら、プラズマエッチングを行う前に、真空チャンバ３１内に発生させた酸素ガスのプラズマによって、レーザ加工工程Ｓ３において凹凸形状となった境界溝５の表面の平滑化を行う（図５に示す境界溝表面平滑化工程Ｓ５）。   When a plasma etching step S6 (FIG. 5) described later is performed in this state, the side surface of the cut semiconductor chip also has a jagged shape, and stress concentration tends to occur there. For this reason, when the semiconductor wafer 1 is carried into the vacuum chamber 31, the surface of the boundary groove 5 that has become uneven in the laser processing step S <b> 3 by the plasma of oxygen gas generated in the vacuum chamber 31 before plasma etching is performed. Is smoothed (boundary groove surface smoothing step S5 shown in FIG. 5).

境界溝表面平滑化工程Ｓ５では、先ず、プラズマ処理装置３０の第２開閉弁４１を閉じた状態で第１開閉弁３９を開き、酸素ガス供給部３７から上部電極３３へ酸素ガスを供給させる。これにより上部電極３３から多孔質プレート３３ａを介して半導体ウエハ１の上面に酸素ガスが吹き付けられる。この状態で高周波電源部３４を駆動して下部電極３２に高周波電圧を印加すると、下部電極３２と上部電極３３の間に酸素ガスのプラズマＰｏが発生する（図４（ａ））。この酸素ガスのプラズマＰｏは有機物であるレジスト膜４を灰化するので、境界溝５の表面は平滑化される（図４（ｂ）、図６（ｂ））。   In the boundary groove surface smoothing step S <b> 5, first, the first on-off valve 39 is opened with the second on-off valve 41 of the plasma processing apparatus 30 closed, and oxygen gas is supplied from the oxygen gas supply unit 37 to the upper electrode 33. As a result, oxygen gas is blown from the upper electrode 33 onto the upper surface of the semiconductor wafer 1 through the porous plate 33a. When the high frequency power supply 34 is driven in this state and a high frequency voltage is applied to the lower electrode 32, a plasma Po of oxygen gas is generated between the lower electrode 32 and the upper electrode 33 (FIG. 4A). Since this oxygen gas plasma Po ashes the resist film 4 which is an organic substance, the surface of the boundary groove 5 is smoothed (FIGS. 4B and 6B).

この境界溝５の表面の平滑化は、具体的には、酸素ガス（若しくは酸素ガスを主成分とする混合ガス）のプラズマＰｏによって境界溝５の表面（レジスト膜４の対向する２つの切断面４ａ）の凹凸部４ｂを除去し、境界溝５の表面に付着したレジスト膜４の残渣４ｃを除去し、境界溝５の表面（レジスト膜４の対向する２つの切断面４ａ）の凹凸部４ｂを均してその凹凸部４ｂの凹凸周期を大きくすることによって行う（図６（ｂ）参照）。なお、酸素ガスのプラズマにより境界溝５の表面の平滑化を行っている間は、冷却ユニット３５を駆動して冷媒を下部電極３２内に循環させ、プラズマの熱によって半導体ウエハ１が昇温するのを防止するようにする。   Specifically, the surface of the boundary groove 5 is smoothed by the plasma Po of oxygen gas (or a mixed gas containing oxygen gas as a main component) and the surface of the boundary groove 5 (two cut surfaces facing the resist film 4). 4a) is removed, the residue 4c of the resist film 4 attached to the surface of the boundary groove 5 is removed, and the uneven portion 4b on the surface of the boundary groove 5 (the two cut surfaces 4a facing each other of the resist film 4). Is performed by increasing the uneven period of the uneven part 4b (see FIG. 6B). While the surface of the boundary groove 5 is being smoothed by the oxygen gas plasma, the cooling unit 35 is driven to circulate the refrigerant in the lower electrode 32, and the semiconductor wafer 1 is heated by the heat of the plasma. To prevent it.

酸素ガスのプラズマＰｏ中にレジスト膜４が曝露される時間が長ければ長いほどレジス
ト膜４の灰化は進行するが、この境界溝表面平滑化工程Ｓ５においてレジスト膜４を酸素ガスのプラズマＰｏ中に曝露する時間は、レジスト膜４の境界溝５の表面が平滑化されるのに必要な最小限度のものとする。目安として、曝露時間はレジスト膜４の表面が１〜３μｍ程度除去されるものであることが好ましい。 As the resist film 4 is exposed to the oxygen gas plasma Po for a longer time, the ashing of the resist film 4 proceeds. In this boundary groove surface smoothing step S5, the resist film 4 is moved into the oxygen gas plasma Po. The exposure time is the minimum necessary for smoothing the surface of the boundary groove 5 of the resist film 4. As a guide, the exposure time is preferably such that the surface of the resist film 4 is removed by about 1 to 3 μm.

境界溝５の表面の平滑化が終了したら、次いでフッ素系ガスのプラズマによって半導体ウエハ１を境界溝５に沿って個々の半導体チップに切り分けるプラズマエッチングを行う（図５に示すプラズマエッチング工程Ｓ６）。   When the smoothing of the surface of the boundary groove 5 is completed, plasma etching for cutting the semiconductor wafer 1 into individual semiconductor chips along the boundary groove 5 by plasma of fluorine-based gas is then performed (plasma etching step S6 shown in FIG. 5).

プラズマエッチング工程Ｓ６では、先ず、第１開閉弁３９を開から閉に切り換えた状態で第２開閉弁４１を開き、フッ素系ガス供給部３８から上部電極３３へフッ素系ガスを供給させる。これにより上部電極３３から多孔質プレート３３ａを介して半導体ウエハ１の上面にフッ素系ガスが吹き付けられる。この状態で高周波電源部３４を駆動して下部電極３２に高周波電圧を印加すると、下部電極３２と上部電極３３の間にフッ素系ガスのプラズマＰｆが発生する（図４（ｃ））。   In the plasma etching step S <b> 6, first, the second on-off valve 41 is opened with the first on-off valve 39 switched from open to closed, and the fluorine-based gas is supplied from the fluorine-based gas supply unit 38 to the upper electrode 33. As a result, the fluorine-based gas is sprayed from the upper electrode 33 onto the upper surface of the semiconductor wafer 1 through the porous plate 33a. When the high frequency power supply 34 is driven in this state and a high frequency voltage is applied to the lower electrode 32, a fluorine-based gas plasma Pf is generated between the lower electrode 32 and the upper electrode 33 (FIG. 4C).

発生したフッ素系ガスのプラズマＰｆは、境界溝５に露出しているシリコン製の半導体ウエハ１の表面１ｂをエッチングするので、半導体ウエハ１は境界溝５に沿って一括して切り分けられて複数の半導体チップ１′が生成される（図４（ｄ））。このとき境界溝５の表面はその前の工程（境界溝表面平滑化工程Ｓ５）において平滑化されているので、プラズマエッチングによって形成される半導体ウエハ１の切断面、すなわち半導体チップ１′の側面は平坦なものとなる。なお、フッ素系ガスのプラズマＰｆにより半導体ウエハ１の表面１ｂのエッチングを行っている間は、冷却ユニット３５を駆動して冷媒を下部電極３２内に循環させ、プラズマの熱によって半導体ウエハ１が昇温するのを防止するようにする。   Since the generated fluorine-based gas plasma Pf etches the surface 1b of the silicon semiconductor wafer 1 exposed in the boundary groove 5, the semiconductor wafer 1 is collectively cut along the boundary groove 5 to form a plurality of pieces. A semiconductor chip 1 ′ is generated (FIG. 4D). At this time, since the surface of the boundary groove 5 is smoothed in the previous step (boundary groove surface smoothing step S5), the cut surface of the semiconductor wafer 1 formed by plasma etching, that is, the side surface of the semiconductor chip 1 'is It will be flat. During the etching of the surface 1b of the semiconductor wafer 1 by the fluorine-based gas plasma Pf, the cooling unit 35 is driven to circulate the coolant in the lower electrode 32, and the semiconductor wafer 1 is raised by the heat of the plasma. Try to prevent warming.

上記プラズマエッチング工程Ｓ６が終了したら、境界表面平滑化工程Ｓ５の場合と同様の手順により、真空チャンバ３１内に酸素ガスのプラズマＰｏを発生させて（図４（ｅ））、半導体ウエハ１（切り分けられた各半導体チップ１′がＵテープ３によって繋がった状態のもの）の上面に残っているレジスト膜４の灰化除去を行う（図４（ｆ）、図５に示すレジスト膜除去工程Ｓ７）。   When the plasma etching step S6 is completed, a plasma Po of oxygen gas is generated in the vacuum chamber 31 by the same procedure as that in the boundary surface smoothing step S5 (FIG. 4 (e)), and the semiconductor wafer 1 (slicing is performed). The resist film 4 remaining on the upper surface of the semiconductor chips 1 'connected with the U tape 3) is removed by ashing (FIG. 4 (f), resist film removing step S7 shown in FIG. 5). .

このレジスト膜除去工程Ｓ７では、表面に残ったレジスト膜４が完全に灰化除去されるまで半導体ウエハ１を酸素ガスのプラズマＰｏ中へ曝露させる必要があるため、酸素ガスのプラズマＰｏ中に半導体ウエハ１を曝露する時間は、境界溝表面平滑化工程Ｓ５において酸素ガスのプラズマＰｏ中に半導体ウエハ１を曝露した時間よりも長いものとなる（境界溝表面平滑化工程Ｓ５における曝露時間のおよそ１０倍程度）。なお、このレジスト膜除去工程Ｓ７において、酸素ガスのプラズマＰｏによりレジスト膜４の灰化除去を行っている間は、冷却ユニット３５を駆動して冷媒を下部電極３２内に循環させ、プラズマの熱によって半導体ウエハ１が昇温するのを防止するようにする。   In this resist film removing step S7, it is necessary to expose the semiconductor wafer 1 to the oxygen gas plasma Po until the resist film 4 remaining on the surface is completely ashed and removed, so that the semiconductor is contained in the oxygen gas plasma Po. The exposure time of the wafer 1 is longer than the exposure time of the semiconductor wafer 1 in the plasma Po of oxygen gas in the boundary groove surface smoothing step S5 (approximately 10 times the exposure time in the boundary groove surface smoothing step S5). About twice). In this resist film removal step S7, while the resist film 4 is incinerated and removed by the oxygen gas plasma Po, the cooling unit 35 is driven to circulate the refrigerant in the lower electrode 32, and the plasma heat is removed. This prevents the temperature of the semiconductor wafer 1 from rising.

レジスト膜４が完全に灰化除去されたら、真空チャンバ３１内から半導体ウエハ１（切り分けられた半導体チップ１′がＵＶテープ３によって繋がった状態のもの）を搬出する（図５に示すウエハ搬出工程Ｓ８）。半導体ウエハ１を真空チャンバ３１から搬出した後、半導体ウエハ１の回路パターン形成面１ａに貼り付けられたＵＶテープ３を引き伸ばすと、切り分けられた半導体チップ１′を互いに引き離した状態にすることができる。そして、その後ＵＶテープ３に紫外線を照射すると、ＵＶテープ３は光化学反応を起こして粘着力が失われ、半導体チップ１′をそれぞれ容易にＵＶテープ３から剥がすことができるようになる。   When the resist film 4 is completely ashed and removed, the semiconductor wafer 1 (with the cut semiconductor chips 1 'connected by the UV tape 3) is unloaded from the vacuum chamber 31 (wafer unloading step shown in FIG. 5). S8). After unloading the semiconductor wafer 1 from the vacuum chamber 31, when the UV tape 3 attached to the circuit pattern forming surface 1a of the semiconductor wafer 1 is stretched, the separated semiconductor chips 1 ′ can be separated from each other. . When the UV tape 3 is then irradiated with ultraviolet rays, the UV tape 3 undergoes a photochemical reaction and loses its adhesive force, and the semiconductor chip 1 ′ can be easily peeled off from the UV tape 3.

このように、本実施の形態における半導体チップの製造方法では、レジスト膜４の半導体素子２同士の境界部にレーザ光１３ａを照射してレジスト膜４に半導体素子２同士を区分する境界溝５を形成し、その境界溝５に半導体ウエハ１の表面１ｂを露出させた後、フッ素系ガスのプラズマによるエッチングを行って半導体ウエハ１を境界溝５に沿って個々の半導体チップ１′に切り分けるのであるが、そのフッ素系ガスのプラズマによるエッチングを行う前に、レーザ加工工程Ｓ３において凹凸形状となった境界溝５の表面を酸素ガス（若しくは酸素を主成分とする混合ガス）のプラズマにより平滑化するようにしている。このため、プラズマエッチングによる半導体ウエハ１の切断面、すなわち切り分けられた半導体チップ１′の側面を平坦なものとすることができ、チッピングのない割れにくい半導体チップ１′を製造することができる。   As described above, in the method of manufacturing a semiconductor chip in the present embodiment, the boundary groove 5 that divides the semiconductor elements 2 into the resist film 4 by irradiating the laser beam 13 a on the boundary between the semiconductor elements 2 of the resist film 4. After the formation, the surface 1b of the semiconductor wafer 1 is exposed in the boundary groove 5, and etching with a fluorine-based gas plasma is performed to cut the semiconductor wafer 1 into individual semiconductor chips 1 'along the boundary groove 5. However, before etching with the fluorine-based gas plasma, the surface of the boundary groove 5 that has been uneven in the laser processing step S3 is smoothed with a plasma of oxygen gas (or a mixed gas containing oxygen as a main component). I am doing so. For this reason, the cut surface of the semiconductor wafer 1 by plasma etching, that is, the side surface of the cut semiconductor chip 1 'can be flattened, and the semiconductor chip 1' that is not easily cracked without chipping can be manufactured.

また、この半導体チップの製造方法は、図５に示したように、レジスト膜形成工程Ｓ２、レーザ加工工程Ｓ３、ウエハ搬入工程Ｓ４、境界溝表面平滑化工程Ｓ５、プラズマエッチング工程Ｓ６及びウエハ搬出工程Ｓ８をこの順で行う半導体ウエハ１の処理方法、更にはプラズマエッチング工程Ｓ６とウエハ搬出工程Ｓ８の間にレジスト膜除去工程Ｓ７を行う半導体ウエハ１の処理方法として捉えることができ、このような半導体ウエハ１の処理方法によっても、上記チッピングのない割れにくい半導体チップ１′を製造することができる。   Further, as shown in FIG. 5, this semiconductor chip manufacturing method includes a resist film forming step S2, a laser processing step S3, a wafer carry-in step S4, a boundary groove surface smoothing step S5, a plasma etching step S6, and a wafer carry-out step. The semiconductor wafer 1 processing method in which S8 is performed in this order, and furthermore, the semiconductor wafer 1 processing method in which the resist film removal step S7 is performed between the plasma etching step S6 and the wafer unloading step S8 can be considered. Even with the processing method of the wafer 1, the above-described chipping-free semiconductor chip 1 'without chipping can be manufactured.

また、図５に示したように、レジスト膜形成工程Ｓ２、レーザ加工工程Ｓ３、ウエハ搬入工程Ｓ４、境界溝表面平滑化工程Ｓ５、プラズマエッチング工程Ｓ６及びウエハ搬出工程Ｓ８をこの順で行う半導体ウエハ１の処理方法、更にはプラズマエッチング工程Ｓ６とウエハ搬出工程Ｓ８の間にレジスト膜除去工程Ｓ７を行う半導体ウエハ１の処理方法によっても、上記チッピングのない割れにくい半導体チップ１′を製造することができる。   Further, as shown in FIG. 5, a semiconductor wafer in which a resist film forming step S2, a laser processing step S3, a wafer carry-in step S4, a boundary groove surface smoothing step S5, a plasma etching step S6 and a wafer carry-out step S8 are performed in this order. The semiconductor chip 1 ′ which is not easily chipped without chipping can also be manufactured by the processing method 1 and the processing method of the semiconductor wafer 1 in which the resist film removing step S7 is performed between the plasma etching step S6 and the wafer unloading step S8. it can.

これまで本発明の好ましい実施の形態について説明してきたが、本発明は上述の実施の形態に示したものに限定されない。例えば、上述の実施の形態では、レジスト膜４は半導体ウエハ１の回路パターン形成面１ａとは反対側の面に形成されたが、レジスト膜４は半導体ウエハ１の回路パターン形成面１ａに形成されてもよい。但し、レジスト膜４が半導体ウエハ１の回路パターン形成面１ａに形成された場合には、境界溝表面平滑化工程Ｓ５において、レジスト膜４を酸素若しくは酸素を主成分とする混合ガスのプラズマにより除去した際、半導体素子２の表面に設けられた有機物からなる保護膜を傷めるおそれがあるため、レジスト膜４は半導体ウエハ１の回路パターン形成面１ａではなく、上述の実施の形態に示したように、回路パターン形成面１ａとは反対側の面に形成されることが好ましい。   Although the preferred embodiments of the present invention have been described so far, the present invention is not limited to those shown in the above-described embodiments. For example, in the above-described embodiment, the resist film 4 is formed on the surface opposite to the circuit pattern formation surface 1 a of the semiconductor wafer 1, but the resist film 4 is formed on the circuit pattern formation surface 1 a of the semiconductor wafer 1. May be. However, when the resist film 4 is formed on the circuit pattern forming surface 1a of the semiconductor wafer 1, the resist film 4 is removed by plasma of oxygen or a mixed gas containing oxygen as a main component in the boundary groove surface smoothing step S5. In this case, the protective film made of an organic material provided on the surface of the semiconductor element 2 may be damaged. Therefore, the resist film 4 is not the circuit pattern forming surface 1a of the semiconductor wafer 1 but the above-described embodiment. It is preferably formed on the surface opposite to the circuit pattern forming surface 1a.

プラズマエッチングによる半導体ウエハの切断面、すなわち切り分けられた半導体チップの側面を平坦なものとすることができ、チッピングのない割れにくい半導体チップを製造することができる。   The cut surface of the semiconductor wafer by plasma etching, that is, the side surface of the cut semiconductor chip can be made flat, and a semiconductor chip that is not easily chipped without chipping can be manufactured.

図１は本発明の一実施の形態における半導体チップの製造方法の実施に使用されるレーザ加工装置の斜視図FIG. 1 is a perspective view of a laser processing apparatus used for carrying out a semiconductor chip manufacturing method according to an embodiment of the present invention. 本発明の一実施の形態における半導体チップの製造方法の実施に使用されるプラズマ処理装置の断面図Sectional drawing of the plasma processing apparatus used for implementation of the manufacturing method of the semiconductor chip in one embodiment of this invention 本発明の一実施の形態における半導体チップの製造方法の工程説明図Process explanatory drawing of the manufacturing method of the semiconductor chip in one embodiment of this invention 本発明の一実施の形態における半導体チップの製造方法の工程説明図Process explanatory drawing of the manufacturing method of the semiconductor chip in one embodiment of this invention 本発明の一実施の形態における半導体チップの製造方法の工程の流れを示すフローチャートThe flowchart which shows the flow of the process of the manufacturing method of the semiconductor chip in one embodiment of this invention 本発明の一実施の形態における半導体チップの製造方法の境界溝表面平滑化工程の前後における境界溝の表面の変化の様子を（ａ），（ｂ）の順で示す図The figure which shows the mode of the change of the surface of a boundary groove | channel before and behind the boundary groove | channel surface smoothing process of the manufacturing method of the semiconductor chip in one embodiment of this invention in order of (a), (b)

符号の説明Explanation of symbols

１ 半導体ウエハ
１′ 半導体チップ
１ａ 回路パターン形成面
１ｂ 露出した半導体ウエハの表面（境界溝の表面）
２ 半導体素子
４ レジスト膜
４ａ レジスト膜の切断面（境界溝の表面）
４ｂ 凹凸部
４ｃ 残渣
５ 境界溝
１０ レーザ加工装置
１３ａ レーザ光
３０ プラズマ処理装置
３１ 真空チャンバ DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 1 'Semiconductor chip 1a Circuit pattern formation surface 1b The surface of the exposed semiconductor wafer (surface of a boundary groove)
2 Semiconductor element 4 Resist film 4a Cut surface of resist film (surface of boundary groove)
4b Uneven portion 4c Residue 5 Boundary groove 10 Laser processing device 13a Laser light 30 Plasma processing device 31 Vacuum chamber

Claims (6)

複数の半導体素子が形成された半導体ウエハの一方の面に有機物であるレジスト膜を形成するレジスト膜形成工程と、レジスト膜の半導体素子同士の境界部にレーザ光を照射してレジスト膜に半導体素子同士を区分する境界溝を形成し、その境界溝に半導体ウエハの表面を露出させるレーザ加工工程と、境界溝に露出した半導体ウエハの表面をフッ素系ガスのプラズマによりエッチングし、半導体ウエハを境界溝に沿って個々の半導体チップに切り分けるプラズマエッチング工程とを含み、
前記レーザ加工工程と前記プラズマエッチング工程の間に、前記レーザ加工工程において凹凸形状となった境界溝の表面の凹凸部を酸素ガス若しくは酸素を主成分とする混合ガスのプラズマにより灰化して平滑化する境界溝表面平滑化工程を実行することを特徴とする半導体チップの製造方法。 A resist film forming step of forming a resist film, which is an organic substance, on one surface of a semiconductor wafer on which a plurality of semiconductor elements are formed, and a semiconductor element on the resist film by irradiating laser light to the boundary between the semiconductor elements of the resist film A boundary processing groove is formed, and a laser processing step is performed to expose the surface of the semiconductor wafer in the boundary groove, and the surface of the semiconductor wafer exposed to the boundary groove is etched with plasma of a fluorine-based gas, and the semiconductor wafer is then processed into the boundary groove. And a plasma etching step of cutting into individual semiconductor chips along
Between the laser processing step and the plasma etching step, the concavo-convex portion on the surface of the boundary groove that has been concavo-convex in the laser processing step is ashed and smoothed by oxygen gas or plasma of a mixed gas containing oxygen as a main component. A method of manufacturing a semiconductor chip, comprising performing a boundary groove surface smoothing step. 境界溝表面平滑化工程における境界溝の表面の平滑化は、境界溝の表面の凹凸部を酸素ガス若しくは酸素を主成分とする混合ガスのプラズマにより均して凹凸部の凹凸周期を大きくして行うことを特徴とする請求項１に記載の半導体チップの製造方法。   In the boundary groove surface smoothing step, the surface of the boundary groove is smoothed by increasing the uneven period of the uneven part by leveling the uneven part on the surface of the boundary groove with plasma of oxygen gas or a mixed gas containing oxygen as a main component. The method of manufacturing a semiconductor chip according to claim 1, wherein the method is performed. プラズマエッチング工程の後、レジスト膜を酸素ガス若しくは酸素を主成分とする混合ガスのプラズマにより除去するレジスト膜除去工程を実行することを特徴とする請求項１又は２に記載の半導体チップの製造方法。 3. The method of manufacturing a semiconductor chip according to claim 1, wherein after the plasma etching step, a resist film removing step is performed in which the resist film is removed by plasma of oxygen gas or a mixed gas containing oxygen as a main component. . レジスト膜を半導体ウエハの半導体素子が形成された回路パターン形成面とは反対側の面に形成することを特徴とする請求項１乃至３のいずれかに記載の半導体チップの製造方法。 A semiconductor chip manufacturing method according to any one of claims 1 to 3, characterized in that the resist film circuit pattern formation surface of the semiconductor element is formed of a semiconductor wafer formed on the opposite side. 複数の半導体素子が形成された半導体ウエハの一方の面に有機物であるレジスト膜を形成するレジスト膜形成工程と、レジスト膜の半導体素子同士の境界部にレーザ光を照射してレジスト膜に半導体素子同士を区分する境界溝を形成し、その境界溝に半導体ウエハの表面を露出させるレーザ加工工程と、レーザ加工工程が済んだ半導体ウエハをプラズマ処理装置の真空チャンバ内に搬入するウエハ搬入工程と、真空チャンバ内に発生させた酸素ガス若しくは酸素を主成分とする混合ガスのプラズマにより前記レーザ加工工程において凹凸形状となった境界溝の表面の凹凸部を灰化して平滑化する境界溝表面平滑化工程と、境界溝平滑化工程の後、境界溝に露出した半導体ウエハの表面をフッ素系ガスのプラズマによりエッチングし、半導体ウエハを境界溝に沿って個々の半導体チップに切り分けるプラズマエッチング工程と、プラズマエッチング工程が済んだ半導体ウエハを真空チャンバから搬出するウエハ搬出工程とを含むことを特徴とする半導体ウエハの処理方法。 A resist film forming step of forming a resist film, which is an organic substance, on one surface of a semiconductor wafer on which a plurality of semiconductor elements are formed, and a semiconductor element on the resist film by irradiating laser light to the boundary between the semiconductor elements of the resist film Forming a boundary groove that separates each other and exposing the surface of the semiconductor wafer in the boundary groove; and a wafer carrying-in step of carrying the semiconductor wafer that has undergone the laser processing step into the vacuum chamber of the plasma processing apparatus; Boundary groove surface smoothing is performed by ashing and smoothing the uneven portions on the surface of the boundary grooves that have become uneven in the laser processing step by plasma of oxygen gas generated in a vacuum chamber or a mixed gas containing oxygen as a main component. After the process and the boundary groove smoothing process, the surface of the semiconductor wafer exposed in the boundary groove is etched with a fluorine-based gas plasma, and the semiconductor wafer is etched. A plasma etching step cut into individual semiconductor chips along the c the boundary groove processing method of a semiconductor wafer which comprises a wafer unloading step of the semiconductor wafer having undergone the plasma etching process is unloaded from the vacuum chamber. 前記プラズマエッチング工程と前記ウエハ搬出工程の間に、真空チャンバ内に発生させた酸素ガスもしくは酸素を主成分とする混合ガスのプラズマによりレジスト膜を除去するレジスト膜除去工程を実行することを特徴とする請求項５に記載の半導体ウエハの処理方法。 A resist film removing step is performed between the plasma etching step and the wafer unloading step, wherein the resist film is removed by plasma of oxygen gas generated in a vacuum chamber or a mixed gas containing oxygen as a main component. A method for processing a semiconductor wafer according to claim 5 .
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