JP2011140429A - Epitaxial wafer and semiconductor element - Google Patents

Abstract

Provided are a silicon carbide epitaxial wafer and a silicon carbide semiconductor device which can improve the crystal quality of an epitaxially grown layer and have a low device resistance without causing a decrease in carrier mobility even when a thick epitaxially grown layer is formed. To do.
A silicon carbide semiconductor device includes an n-type silicon carbide substrate doped with a dopant whose lattice constant increases by doping, such as arsenic, at a concentration of C1, and a silicon carbide substrate containing the same dopant as the silicon carbide substrate. The n-type silicon carbide drift layer 3 doped with a lower concentration C2 and the n-type buffer layer doped with the dopant between the silicon carbide substrate 1 and the silicon carbide drift layer 3 are provided. Buffer layer 2 was configured such that the doping concentration decreased linearly from C1 to C2 from the interface with silicon carbide substrate 1 toward the interface with silicon carbide drift layer 3.
[Selection] Figure 1

Description

  The present invention relates to an epitaxial wafer made of silicon carbide and a semiconductor element formed using the epitaxial wafer.

In a semiconductor element using a silicon carbide semiconductor, an epitaxial growth layer grown on a low resistance substrate is often used as an operation layer as an element structure. In a power semiconductor element, the epitaxial growth layer functions as a breakdown voltage layer. However, the epitaxial growth layer is usually formed as a single layer (see, for example, Patent Document 1), and the epitaxial growth layer has a thickness of 3 to 100 μm or more depending on the operating voltage. In addition, the doping concentration is at most 10 ¹⁶ cm ^{−3, and} more often 10 ¹⁵ cm ⁻³ . On the other hand, the low-resistance crystal serving as the substrate is often doped with a dopant of about 10 ¹⁹ cm ⁻³ . Therefore, since the doping concentration differs greatly between the epitaxial growth layer (pressure-resistant layer) and the substrate, the lattice constants of the two are different. When the epitaxial growth layer is thick, the lattice constant difference, that is, the crystal defect due to lattice mismatch As a result, the crystal quality of the epitaxially grown layer is deteriorated. As a result, the carrier mobility is lowered and the device resistance is increased.

Therefore, in order to mitigate the influence on the crystal quality caused by the lattice constant difference, a buffer layer having a doping concentration of 2 × 10 ^{15 to} 3 × 10 ¹⁹ cm ⁻³ and a layer thickness of 0.3 to ¹⁵ μm is formed between the substrate and the epitaxial growth layer. Is provided for a (11-20) -plane silicon carbide crystal, and a single-layer film, a graded graded structure, or a continuously graded structure within the above-described doping concentration and layer thickness ranges can be provided. (For example, refer to Patent Document 2).

  In addition, as a buffer layer provided between the substrate and the epitaxial growth layer, for the purpose of suppressing introduction of basal plane dislocations into the epitaxial growth layer, 1/10 to 1/2 of the doping concentration of the underlying substrate. It has been shown for silicon carbide crystals on the (0001) plane and the (000-1) plane that a plurality of layers having a doping concentration of a certain degree are stacked and a graded graded film whose doping concentration changes stepwise is shown (for example, And Patent Document 3).

JP-A-6-268202 JP 2000-319099 A JP 2008-74661 A

  In the above-described conventional epitaxial wafers and semiconductor elements made of silicon carbide semiconductors, the single layer film and the doping concentration change stepwise or continuously between the substrate and the epitaxially grown layer that becomes the breakdown voltage layer. However, it has been disclosed that a buffer layer having a graded structure or a continuously graded structure is provided, but an appropriate configuration according to the type and concentration of the dopant in the substrate and the epitaxial growth layer has not been shown. In particular, for a buffer layer having a graded structure and a buffer layer having a continuously graded structure, the structure of the buffer layer considering the direction of lattice mismatch caused by the added dopant is not shown. In the device, the crystal quality of the epitaxial growth layer is deteriorated, and the carrier mobility may be lowered.

  The present invention has been made to solve the above-described problems, and can improve the crystal quality of the epitaxially grown layer as compared with the prior art, and the carrier mobility is lowered even when a thick epitaxially grown layer is formed. An epitaxial wafer and a semiconductor element that do not occur and have low element resistance are realized.

  An epitaxial wafer and a semiconductor device according to the present invention include a first conductivity type silicon carbide substrate doped with a dopant whose lattice constant increases by doping, and a first conductivity type provided on the silicon carbide substrate and doped with the dopant. Type buffer layer and a first conductivity type silicon carbide epitaxial growth layer provided on the buffer layer and doped with the dopant at a concentration lower than that of the silicon carbide substrate, and the doping concentration of the buffer layer is , Linearly decreasing from the doping concentration of the silicon carbide substrate to the doping concentration of the silicon carbide epitaxial growth layer from the interface with the silicon carbide substrate toward the interface with the silicon carbide epitaxial growth layer. .

  In addition, an epitaxial wafer and a semiconductor device according to the present invention are provided on a silicon carbide substrate of a first conductivity type doped with a dopant whose lattice constant increases by doping, and any one of Ge, Sn, or Pb provided on the silicon carbide substrate. And a lattice constant of the silicon carbide substrate and the silicon carbide epitaxial growth layer substantially coincide with each other at a growth temperature of the epitaxial growth layer.

  According to the present invention, since the lattice mismatch between the silicon carbide substrate and the epitaxial growth layer can be effectively reduced, crystal defects caused by the lattice constant difference between the silicon carbide substrate and the epitaxial growth layer are introduced into the epitaxial growth layer. This can be suppressed. As a result, deterioration of the crystal quality of the epitaxial growth layer can be prevented, and even if a thick epitaxial growth layer is formed, the carrier mobility does not decrease, and an epitaxial wafer and a semiconductor device with low device resistance can be obtained.

It is sectional drawing which shows the structure of the semiconductor element in Embodiment 1 of this invention. It is sectional drawing which shows the structure of the epitaxial wafer in Embodiment 1 of this invention. It is sectional drawing which shows the structure of the semiconductor element in Embodiment 2 of this invention. It is sectional drawing which shows the structure of the semiconductor element in Embodiment 3 of this invention. It is sectional drawing which shows the structure of the epitaxial wafer in Embodiment 3 of this invention. It is sectional drawing which shows the structure of the semiconductor element in Embodiment 4 of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, in the Miller index notation indicating the crystal plane, a negative sign representing a negative index is generally added above the index, but in this specification, the negative sign is indicated before the index.

Embodiment 1 FIG.
FIG. 1 is a cross-sectional view showing a configuration of a semiconductor element according to Embodiment 1 of the present invention. FIG. 2 is a cross-sectional view showing the structure of the epitaxial wafer in the first embodiment of the present invention.

  In FIG. 2, epitaxial wafer 100 includes an n-type low-resistance silicon carbide substrate 1 that is a first conductivity type having an off-angle from the (0001) plane, and an n-type buffer layer 2 formed on silicon carbide substrate 1. And an epitaxial growth layer 3 formed by epitaxial growth on the buffer layer 2. The configuration of the buffer layer 2 will be described in detail separately.

Then, using this epitaxial wafer 100, silicon carbide Schottky barrier diode 101 which is a semiconductor element shown in FIG. 1 is formed. In the Schottky barrier diode 102, the epitaxial growth layer 3 of the epitaxial wafer 100 becomes an n-type drift layer for maintaining a breakdown voltage. Drift layer 3 has a thickness of about 3 to 150 μm and a doping concentration of about 0.5 to 20 × 10 ¹⁵ cm ⁻³ and is formed at a doping concentration lower than that of silicon carbide substrate 1. Further, a p-type region 4 of the second conductivity type is formed as a termination structure in the periphery of the element of the Schottky barrier diode 102. The p-type region 4 is selectively formed in the drift layer 3 in the epitaxial wafer 100 by ion implantation and an activation heat treatment step, and has a layer thickness of about 0.5 to 2 μm and a doping concentration of 1 to 100 × 10 ¹⁷ cm ^−. It is formed with about ³ . The anode electrode 5 is formed on the drift layer 3 so as to be in contact with the p-type region 4. Further, the cathode electrode 6 is formed on the back surface of the n-type low resistance silicon carbide substrate 1.

The anode electrode 5 has a Schottky contact with the drift layer 3 and may have a Schottky contact or an ohmic contact with the p-type region 4. In order for the anode electrode 5 to function as an ohmic electrode with respect to the p-type region 4, if the contact resistance value is 10 ⁻³ Ωcm ² or less, the influence of the contact portion when the current flows through the p-type region 4. The rise in on-voltage due to can be reduced. More desirably, if the contact resistance value is 10 ⁻⁴ Ωcm ² or less, the voltage increase due to the influence of the contact portion can be almost ignored.

Silicon carbide substrate 1 desirably has a low resistivity as much as possible so as not to increase device resistance, and is doped with a group V element at a high concentration. However, if the doping concentration is too high, crystal defects are likely to be introduced. In general, doping is performed so that the concentration is about 10 ¹⁹ cm ⁻³ . In the present embodiment, an element such as arsenic (As) that increases the lattice constant of the silicon carbide crystal as the doping concentration is increased is used as a dopant for silicon carbide substrate 1.

  The buffer layer 2 is doped with the same dopant as that of the silicon carbide substrate 1, and the doping concentration is equal to the doping concentration C1 of the silicon carbide substrate 1 at the interface with the silicon carbide substrate 1, as shown in FIG. At the interface with the drift layer 3, it is equal to the doping concentration C2 of the drift layer 3. Inside the buffer layer 2, a continuous gradient composition is formed such that the doping concentration decreases linearly from C2 to C1 from the interface with the silicon carbide substrate 1 toward the interface with the drift layer 3. ing.

  In this way, by doping the silicon carbide substrate 1 and the buffer layer 2 with an element that increases the lattice constant of the silicon carbide crystal as the doping concentration is increased as a dopant, the lattice constant of the drift layer 3 that is an epitaxial growth layer is silicon carbide. It becomes smaller than the substrate 1. Therefore, the buffer layer 2 is subjected to tensile stress in the horizontal direction and compressive stress in the growth direction of the epitaxial growth layer, that is, in the thickness direction. In the growth direction, the shrinkage at the time of cooling to the room temperature after the epitaxial growth and the compressive stress are synergistic, so that cracking is likely to occur. In this way, the impurity concentration of the buffer layer 2 is stepwise and the lattice constant is linearly scaled. By making the structure changed with substantially the same amount of change, it is possible to suppress the growth of crystal defects in the growth direction, and even if a crystal defect is generated, each layer constituting the buffer layer 2 or the silicon carbide substrate 1 Since it extends in a direction parallel to any interface with the drift layer 3, it can be prevented from being formed in the epitaxial growth layer, the carrier mobility is not lowered, and the device resistance is low. A device can be realized.

  Further, by setting the thickness of each layer constituting the buffer layer 2 to 100 nm or less and a value extremely smaller than the thickness of the drift layer 3, an increase in element resistance caused by introducing the buffer layer 2 can be suppressed.

Embodiment 2. FIG.
FIG. 3 is a cross-sectional view showing the configuration of the semiconductor element according to the second embodiment of the present invention.

  In FIG. 3, silicon carbide MOSFET 102 which is a semiconductor element includes an n-type low resistance silicon carbide substrate 1 having an off angle from the (0001) plane and a buffer formed on silicon carbide substrate 1, as in the first embodiment. It is formed using an epitaxial wafer 100 having layer 2 and an n-type silicon carbide drift layer (epitaxial growth layer) 3 formed on this buffer layer 2 by epitaxial growth for maintaining a withstand voltage. The configuration of the buffer layer 2 is the same as that in the first embodiment.

P-type silicon carbide body region 14 and n-type silicon carbide source region 15 are selectively formed in n-type drift layer 3 by ion implantation and an activation heat treatment process. The body region 14 has a layer thickness of about 0.5 to 2 μm and a doping concentration of about 3 to 20 × 10 ¹⁷ cm ⁻³ , so that a channel is formed or is close to the channel. On the surface, the doping concentration can be lowered. By reducing the doping concentration on the outermost surface, scattering due to impurities can be reduced, carrier mobility in the channel can be increased, and device resistance can be lowered. Only the outermost surface region of the contact region 24 in the body region 14 may be selectively selectively implanted so as to have a higher concentration of doping than other portions of about 5 to 50 × 10 ¹⁸ cm ⁻³ . The source region 15 has a layer thickness of about 0.3 to 1 μm and a doping concentration of about 5 to 50 × 10 ¹⁸ cm ⁻³ .

  A gate insulating film 17 and a gate electrode 18 are formed on this layer structure to produce a gate portion. The MOSFET 102 shown in FIG. 3 is not provided with a channel layer, but a channel layer may be provided separately. When the channel layer is provided, the conductivity type may be n-type or p-type, and in order to improve the surface roughness caused by the activation heat treatment of the ion-implanted species, for example, formation by epitaxial growth is desirable, but the surface produced by the activation heat treatment If the roughness is small, a channel layer may be formed by selective ion implantation.

  The activation heat treatment of the ion implantation species may be performed at once, or the activation heat treatment may be performed for each implantation step.

  The gate insulating film 17 is a region that becomes a channel in the body region by forming a silicon oxide film or a silicon oxynitride film by thermal oxidation or nitridation of a silicon carbide semiconductor, or depositing an insulating film, or a combination thereof. In a portion facing 34, the film is formed to a thickness of about 10 to 100 nm.

The gate electrode 18 is formed by forming a polycrystalline silicon film or a metal film. The channel layer 16, the gate insulating film 17, and the gate electrode 18 are removed from the region other than the gate portion. For the channel layer 16, regions other than the gate portion may be removed before the gate insulating film 17 is formed.
After forming the interlayer insulating film 19, the source electrode 20 is formed after removing the interlayer insulating film in the region that becomes the contact portion of the source electrode 20. Further, the drain electrode 21 is formed on the back surface of the n-type substrate 1, and the wiring 22 is formed on the source electrode 20 and the interlayer insulating film 19. Although not shown, the wiring 22 on the interlayer insulating film is removed in a partial region of the outer periphery of the element where the gate electrode pad is formed.

  The buffer layer 2 has the same configuration as that of the first embodiment as shown in FIG. 1, and the doping concentration of the buffer layer 2 is silicon carbide from the interface with the silicon carbide substrate 1 toward the silicon carbide epitaxial growth layer 3 side. Since it is formed so as to decrease linearly from the concentration C1 of the substrate 1 to the concentration C2 of the silicon carbide epitaxial layer, the lattice mismatch between the silicon carbide substrate 1 and the epitaxial growth layer 3 can be effectively reduced. Crystal defects can be prevented from being introduced into the drift layer 3, which is a layer, the carrier mobility is not lowered, and an increase in device resistance can be suppressed.

  Further, by setting the thickness of each layer constituting the buffer layer 2 to 100 nm or less and a value extremely smaller than the thickness of the drift layer 3, an increase in element resistance caused by introducing the buffer layer 2 can be suppressed.

  In the first and second embodiments described above, the plane orientation of silicon carbide substrate 1 is the plane having an off angle from the (0001) plane, but the (0001) plane and (000-1) plane having no off angle. In any crystal plane orientation such as (11-20) plane, (03-38) plane, etc., the buffer layer having the configuration shown in FIG. 1 can prevent the introduction of crystal defects into the epitaxial growth layer, An increase in element resistance can be suppressed.

  In Embodiments 1 and 2, an example of arsenic is shown as a dopant. However, even if it is other than arsenic, a buffer layer is shown in FIG. 1 as long as the dopant increases the lattice constant of the silicon carbide crystal by doping. By adopting such a configuration, it is possible to prevent the introduction of crystal defects into the epitaxial growth layer and to suppress the increase in element resistance.

Embodiment 3 FIG.
FIG. 4 is a cross-sectional view showing the configuration of the semiconductor element according to the third embodiment of the present invention. FIG. 5 is a cross-sectional view showing the structure of the epitaxial wafer in the third embodiment of the present invention.

  In FIG. 4, an epitaxial wafer 200 is formed on an n-type low-resistance silicon carbide substrate 51, which is the first conductivity type having an off angle from the (0001) plane, and Ge, Sn as dopants. Or an epitaxial growth layer 53 doped with either Pb.

Then, using this epitaxial wafer 200, silicon carbide Schottky barrier diode 201 which is a semiconductor element shown in FIG. 4 is formed. In the Schottky barrier diode 201, the epitaxial growth layer 53 of the epitaxial wafer 200 becomes an n-type drift layer for maintaining a breakdown voltage. The drift layer 53 has a thickness of about ³ to 150 μm and a doping concentration of about 0.5 to 20 × 10 ¹⁵ cm ⁻³ .

Further, a p-type region 54 of the second conductivity type is formed as a termination structure in the peripheral portion of the Schottky barrier diode 201. The p-type region 4 is formed in the epitaxial growth layer 53 of the epitaxial wafer 200 by ion implantation and an activation heat treatment step, and is formed with a layer thickness of about 0.5 to 2 μm and a doping concentration of about 1 to 100 × 10 ¹⁷ cm ^−3. Is done. The anode electrode 55 is formed on the drift layer 53 so as to be in contact with the p-type region 54. Further, the cathode electrode 56 is formed on the back surface of the silicon carbide substrate 51.

The anode electrode 55 is in a Schottky contact with the drift layer 53, and may be either a Schottky contact or an ohmic electrode with respect to the p-type region 54. In order for the anode electrode 55 to function as an ohmic electrode, if the contact resistance value is 10 ⁻³ Ωcm ² or less, the increase in the on-voltage due to the influence of the contact portion when the current flows through the p-type region 54 is reduced. More preferably, if it is 10 ⁻⁴ Ωcm ² or less, the voltage increase due to the influence of the contact portion can be almost ignored.

Silicon carbide substrate 51 desirably has a low resistivity as much as possible so as not to increase device resistance, and is doped with a group V element at a high concentration. However, if the doping concentration is too high, crystal defects are introduced. Usually, doping is performed so as to have a concentration of about 10 ¹⁹ cm ⁻³ . In the present embodiment, an element, such as arsenic (As), whose lattice constant increases with increasing doping concentration is used as a dopant for silicon carbide substrate 51.

  As described above, when arsenic is used as the dopant, the lattice constant increases as the doping concentration increases, so that the lattice constant of the epitaxial growth layer having a low doping concentration is smaller than that of the substrate having a high doping concentration. Therefore, the epitaxial growth layer 53 is doped with any one of Ge, Sn, or Pb, which is the same group IV as the elements constituting silicon carbide, C and Si, and has a large number of atoms, thereby carbonizing the lattice constant of the epitaxial growth layer 53. An epitaxial growth layer having substantially the same lattice constant as that of the silicon substrate 51 can be formed. Silicon carbide and silicon carbide doped with any of Ge, Sn, or Pb may have different thermal expansion coefficients, but Ge, Sn, and the like so that the lattice constants substantially coincide with each other at the growth temperature of the epitaxial growth layer 53. Alternatively, the doping amount of either Pb is adjusted. By adopting such a configuration, it is possible to prevent the occurrence of crystal defects introduced into the epitaxial growth layer 53 due to the difference in lattice constant, and the carrier mobility does not decrease even in the thick breakdown voltage layer, and the device resistance is low. A semiconductor element can be realized.

  It should be noted that the lattice constant of silicon carbide substrate 51 and the lattice constant of epitaxial growth 53 are “substantially identical” as long as the effects of the present invention are achieved, the lattice constants of both may not be completely identical. Means.

Embodiment 4 FIG.
FIG. 6 is a cross-sectional view showing the configuration of the semiconductor element according to the fourth embodiment of the present invention.

  In FIG. 6, silicon carbide MOSFET 202, which is a semiconductor element, is formed on n-type low-resistance silicon carbide substrate 51 having an off-angle from the (0001) plane, and formed on this silicon carbide substrate 51, as in the third embodiment. , And an epitaxial growth layer 53 doped with either Sn or Pb. In addition, the epitaxial growth layer 53 functions as an n-type carbonized drift layer for maintaining a breakdown voltage as in the third embodiment.

P-type silicon carbide body region 64 and n-type silicon carbide source region 65 are selectively formed in n-type drift layer 53 by ion implantation and an activation heat treatment process. The body region 64 has a layer thickness of about 0.5 to 2 μm, a doping concentration of about 3 to 20 × 10 ¹⁷ cm ⁻³ , and a channel is formed or is the outermost surface that is close to the channel In the structure, the doping concentration can be lowered. By reducing the doping concentration on the outermost surface, scattering due to impurities can be reduced, the mobility of carriers in the channel can be increased, and the device resistance can be lowered. Only the outermost surface region of the contact region 74 out of the body region 64 may be selectively ion-implanted separately so as to have a higher concentration of doping than other portions of about 5 to 50 × 10 ¹⁸ cm ⁻³ . The source region 55 has a layer thickness of about 0.3 to 1 μm and a doping concentration of about 5 to 50 × 10 ¹⁸ cm ⁻³ .

  A gate insulating film 67 and a gate electrode 68 are formed on this layer structure to produce a gate portion. The MOSFET 202 shown in FIG. 6 is not provided with a channel layer, but a channel layer may be provided separately. When the channel layer is provided, the conductivity type may be n-type or p-type, and in order to improve the surface roughness caused by the activation heat treatment of the ion-implanted species, for example, formation by epitaxial growth is desirable, but the surface produced by the activation heat treatment If the roughness is small, a channel layer may be formed by selective ion implantation.

  The activation heat treatment of the ion implantation species may be performed at once, or the activation heat treatment may be performed for each implantation step.

  The gate insulating film 67 is formed by forming a silicon oxide film, a silicon oxynitride film, or the like by thermal oxidation or nitridation of a silicon carbide semiconductor, depositing an insulating film, or a combination thereof. Is formed to a thickness of about 10 to 100 nm at a portion facing the surface.

  The gate electrode 68 is formed by forming a polycrystalline silicon film or a metal film. In regions other than the gate portion, the channel layer (not shown), the gate insulating film 67, and the gate electrode 68 are removed. For the channel layer (not shown), a region other than the gate portion may be removed before the gate insulating film 67 is formed.

  After the interlayer insulating film 69 is formed, the source electrode 70 is formed after removing the interlayer insulating film in the region to be a contact portion of the source electrode 70. Further, the drain electrode 71 is formed on the back surface of the silicon carbide substrate 51, and the wiring 72 is formed on the source electrode 70 and the interlayer insulating film 69. Although not shown, the wiring 72 on the interlayer insulating film is removed in a partial region of the outer periphery of the element where the gate electrode pad is formed.

  When the dopant of the silicon carbide substrate 51 is arsenic, the lattice constant increases as the doping concentration increases. Therefore, the lattice constant of the epitaxial growth layer with a low doping concentration is smaller than that of the substrate with a high doping concentration, but constitutes silicon carbide. An epitaxial growth layer having the same lattice constant as that of the substrate can be formed by doping the epitaxial growth layer 53 with any one of Ge, Sn, and Pb having the same group IV as the elements C and Si and a large number of atoms. Silicon carbide and silicon carbide doped with either Ge, Sn, or Pb may have different thermal expansion coefficients, but either Ge, Sn, or Pb may be used so that the lattice constants coincide at the epitaxial growth temperature. Adjust the amount of doping. By adopting such a configuration, it is possible to prevent the occurrence of crystal defects introduced into the epitaxial growth layer due to the difference in lattice constant, and the carrier mobility does not decrease even in the thick breakdown voltage layer, and the semiconductor having low element resistance An element can be realized.

  In Embodiments 3 and 4 described above, the plane orientation of silicon carbide substrate 51 is a plane having an off angle from the (0001) plane, but the (0001) plane and the (000-1) plane having no off angle. In any crystal plane orientation such as the (11-20) plane and the (03-38) plane, the introduction of crystal defects into the epitaxial growth layer can be prevented and the increase in device resistance can be suppressed.

  In the third and fourth embodiments, arsenic is shown as the dopant. However, if the dopant increases the lattice constant of the silicon carbide crystal by doping, C is an element constituting silicon carbide in the epitaxial growth layer. Further, by doping any of Ge, Sn, or Pb, which is the same group IV as Si and Si with a large number of atoms, the lattice constants of the silicon carbide substrate and the epitaxial growth layer can be made to substantially match, and the epitaxial growth of crystal defects can be achieved. Introduction into the layer can be prevented, and an increase in element resistance can be suppressed.

  1,51 Silicon carbide substrate, 2 buffer layer, 3,53 drift layer (silicon carbide epitaxial layer), 100,200 epitaxial wafer, 101,201 Schottky barrier diode, 102,202 MOSFET.

Claims (8)

A silicon carbide substrate of the first conductivity type doped with a dopant whose lattice constant increases by doping;
A buffer layer of a first conductivity type provided on the silicon carbide substrate and doped with the dopant;
A silicon carbide epitaxial growth layer of a first conductivity type provided on the buffer layer and doped with the dopant at a concentration lower than that of the silicon carbide substrate;
The doping concentration of the buffer layer decreases linearly from the doping concentration of the silicon carbide substrate to the doping concentration of the silicon carbide epitaxial growth layer from the interface with the silicon carbide substrate toward the interface with the silicon carbide epitaxial growth layer. An epitaxial wafer characterized by A silicon carbide substrate of the first conductivity type doped with a dopant whose lattice constant increases by doping;
A silicon carbide epitaxial growth layer provided on the silicon carbide substrate and doped with any of Ge, Sn, or Pb;
An epitaxial wafer characterized in that lattice constants of the silicon carbide substrate and the silicon carbide epitaxial growth layer substantially coincide with each other at a growth temperature of the silicon carbide epitaxial growth layer.   The epitaxial wafer according to claim 1, wherein the dopant is arsenic.   The epitaxial wafer according to claim 1, wherein the buffer layer has a layer thickness of 100 nm or less. A silicon carbide substrate of the first conductivity type doped with a dopant whose lattice constant increases by doping;
A buffer layer of a first conductivity type provided on the silicon carbide substrate and doped with the dopant;
A silicon carbide epitaxial growth layer of a first conductivity type provided on the buffer layer and doped with the dopant at a concentration lower than that of the silicon carbide substrate;
The doping concentration of the buffer layer decreases linearly from the doping concentration of the silicon carbide substrate to the doping concentration of the silicon carbide epitaxial growth layer from the interface with the silicon carbide substrate toward the interface with the silicon carbide epitaxial growth layer. ,
The semiconductor element, wherein the silicon carbide epitaxial growth layer is a drift layer. A silicon carbide substrate of the first conductivity type doped with a dopant whose lattice constant increases by doping;
A silicon carbide epitaxial growth layer provided on the silicon carbide substrate and doped with any of Ge, Sn, or Pb;
The lattice constants of the silicon carbide substrate and the silicon carbide epitaxial growth layer substantially coincide with each other at the growth temperature of the silicon carbide epitaxial growth layer, and
The semiconductor element, wherein the silicon carbide epitaxial growth layer is a drift layer.   The semiconductor element according to claim 5, wherein the dopant is arsenic.   The semiconductor element according to claim 5, wherein the buffer layer has a layer thickness of 100 nm or less.

Images