JP2011077123A - METHOD OF FORMING GATE ELECTRODE, METHOD OF MANUFACTURING ALGaN/GaN-HEMT, AND ALGaN/GaN-HEMT - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of forming a gate electrode having gate length not more than a lithography limit, to provide a method of manufacturing AlGaN/GaN-HEMT having good high-frequency characteristics, and to provide AlGaN/GaN-HEMT. <P>SOLUTION: The method of forming a gate electrode includes a process of film-forming a first SiN surface protective layer 2 on the surface of a substrate 1, a process of forming a resist opening 3a of a lithography limit in resist 3 on the surface of the first SiN surface protective layer, and opening the first SiN surface protective layer by etching, a process of film-forming a second SiN surface protective layer 4 on the surface of an opening 2a of the first SiN surface protective layer and the first SiN surface protective layer, a process of forming an opening 4a of the second SiN surface protective layer and a sidewall 4b of the second SiN surface protective layer by forming a resist opening 5a of a lithography limit in resist 5 on the surface of the second SiN surface protective layer and etching the second SiN surface protective layer by anisotropic RIE, and a process of forming a gate electrode 6 for covering a substrate surface inside the sidewall, the sidewall, and the opening of the second SiN surface protective layer. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for forming a gate electrode, a method for manufacturing an AlGaN / GaN-HEMT, and an AlGaN / GaN-HEMT. Technology.

  Conventionally, in AlGaN / GaN-HEMT, the short gate technology has been disclosed in Non-Patent Document 1, for example, as a technology for improving the high-frequency characteristics of a transistor.

  AlGaN / GaN-HEMT is grown on substrates such as SiC, Si, and sapphire by metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). It is produced using an epitaxial substrate having an epitaxial layer having a multilayer structure.

  For example, AlGaN / GaN-HEMT is a buffer layer, an unintentionally doped (UID) -GaN electron transit layer (hereinafter referred to as a UID-GaN layer), a UID-AlGaN electron supply layer, which are sequentially grown from the substrate side. Device fabrication is performed using an epitaxial substrate configured to include (hereinafter referred to as a UID-AlGaN layer).

  In the HEMT, electrons traveling in a two-dimensional electron gas (2DEG (hereinafter referred to as 2DEG) layer) generated on the UID-GaN layer side of the interface between the UID-AlGaN layer and the UID-GaN layer. It operates by being controlled by the source electrode, the gate electrode, and the drain electrode.

In the device fabrication process, first, an SiN surface protective film is formed on a plasma-enhanced chemical vapor deposition (PE-CVD) (hereinafter referred to as PE-CVD) on the epitaxial substrate on which the epitaxial layers are stacked. )) Method, and element isolation for specifying a device region by ion implantation is performed to form a source electrode and a drain electrode.

  Next, a gate opening pattern by resist is formed by photolithography, and using this resist pattern as a mask, inductive coupled plasma reactive ion etching (ICP-RIE (hereinafter referred to as ICP-RIE)). The AlGaN / GaN-HEMT is fabricated by opening the SiN surface protective film at the gate electrode formation position by dry etching such as the method, and forming the gate electrode in the opening by vacuum deposition.

Nishihara et al., IEICE Technical Report ED2007-211, pp.29-31.

  However, the gate electrode forming method according to the background art has a problem in that a gate length less than that size cannot be obtained because the short gate length is limited by the gate opening pattern size by photolithography. It was.

  The present invention has been made to solve the above-described problems, and provides a method for forming a gate electrode having a gate length less than the lithography limit, a method for manufacturing an AlGaN / GaN-HEMT, and an AlGaN / GaN-HEMT. For the purpose.

  In order to achieve the above object, a method for forming a gate electrode according to the present invention includes a first step of forming a first SiN surface protective layer on a substrate surface, and a resist applied to the surface of the first SiN surface protective layer. A second step of forming a resist opening having a lithography limit and etching and opening the first SiN surface protective layer using the resist as a mask; an opening of the first SiN surface protective layer having the etching opening; and the first SiN surface protection A third step of forming a second SiN surface protective layer on the surface of the layer; and a resist applied to the surface of the second SiN surface protective layer on the opening of the first SiN surface protective layer, the resist of the lithography limit An opening is formed, and the second SiN surface protective layer is etched by anisotropic RIE using the resist as a mask. A fourth step of forming an opening of the protective layer and a sidewall of the second SiN surface protective layer on an opening side wall of the first SiN surface protective layer; and the substrate surface and the sidewall inside the sidewall; And a fifth step of forming a gate electrode covering the opening of the second SiN surface protective layer.

  According to this gate electrode formation method, not only the lithography limit, that is, not only the light exposure technique using ultraviolet, far ultraviolet, and extreme ultraviolet (EUV), but also an electron beam (EB) is used. It is possible to form a gate electrode having a fine gate length equal to or less than the lithography limit value by the EB exposure technique. In addition, since the sidewall is formed using the SiN surface protective layer having a two-layer structure, the thickness and step coverage are uniform and controllable, so that the shape of the gate electrode can be easily controlled. . In particular, the gate length of the gate electrode to be formed can be determined by controlling the thickness of the second SiN surface protective layer.

  In order to achieve the above object, the AlGaN / GaN-HEMT manufacturing method of the present invention provides an epitaxial substrate by sequentially laminating a buffer layer, a UID-GaN electron transit layer, and a UID-AlGaN electron supply layer on the substrate surface. A first step, a second step of forming a first SiN surface protective layer, a source electrode and a drain electrode on the surface of the UID-AlGaN electron supply layer of the epitaxial substrate, and a gap between the source electrode and the drain electrode. Forming a lithography-limited resist opening in the resist applied to the surface of the first SiN surface protective layer, etching the first SiN surface protective layer using the resist as a mask, and the source electrode and The surface of the drain electrode, the opening of the first SiN surface protective layer opened by etching, and the first a fourth step of forming a second SiN surface protective layer on the surface of the iN surface protective layer, and the lithography limit on the resist applied to the surface of the second SiN surface protective layer over the opening of the first SiN surface protective layer. And opening the second SiN surface protective layer and the first SiN surface protective layer by etching the second SiN surface protective layer by anisotropic RIE using the resist as a mask. A fifth step of forming a sidewall of the second SiN surface protective layer on the sidewall; a surface of the UID-AlGaN electron supply layer inside the sidewall; an opening of the sidewall and the second SiN surface protective layer; And a sixth step of forming a gate electrode that covers the substrate.

  According to the AlGaN / GaN-HEMT manufacturing method according to the first to sixth steps, a desired gate length size is combined with a lithography-limited opening size and the thicknesses of the first and second SiN surface protective layers. Can be designed and formed. Then, the shape and thickness of the gate electrode to be formed, in particular, the gate length size that is the gate contact portion, and a desired gate electrode sidewall shape reaching the gate electrode surface can be obtained.

  Further, in the AlGaN / GaN-HEMT manufacturing method according to the first to sixth steps, in the second step, gate insulation is provided between the UID-AlGaN electron supply layer and the first SiN surface protective layer. In the third step, only the first SiN surface protective layer on the gate insulating film is etched open, and in the fifth step, the anisotropic RIE is performed on the gate insulating film. Only the second SiN surface protective layer is etched, and in the sixth step, the surface of the gate insulating film inside the sidewall, the sidewall, and the opening of the second SiN surface protective layer are covered. According to the manufacturing method of forming the gate electrode, the manufacturing method of the AlGaN / GaN-HEMT having the MIS type gate structure may be used. Kill.

  In order to achieve the above object, the AlGaN / GaN-HEMT of the present invention includes an epitaxial substrate in which a buffer layer, a UID-GaN electron transit layer, and a UID-AlGaN electron supply layer are sequentially laminated on the substrate surface, and the epitaxial substrate. A first SiN surface protective layer formed on the surface of the UID-AlGaN electron supply layer, a source electrode and a drain electrode, and a resist coated on the surface of the first SiN surface protective layer between the source electrode and the drain electrode. Lithographic limit resist opening formed, the first SiN surface protective layer etched using the resist as a mask, the surface of the source and drain electrodes, the opening of the first SiN surface protective layer opened by etching, and A second SiN surface protective film formed on the surface of the first SiN surface protective layer. A resist opening of the lithography limit is formed in the resist applied to the surface of the second SiN surface protection layer on the layer and the opening of the first SiN surface protection layer, and anisotropic RIE is performed using the resist as a mask. An opening of the second SiN surface protective layer formed by etching the second SiN surface protective layer, and a side wall of the second SiN surface protective layer formed on the side wall of the opening of the first SiN surface protective layer; And a gate electrode formed so as to cover the surface of the UID-AlGaN electron supply layer inside the sidewall, the sidewall, and the opening of the second SiN surface protective layer.

The AlGaN / GaN-HEMT having such a configuration can be designed by combining a desired gate length size with a lithography-limited opening size and the thicknesses of the first and second SiN surface protective layers. The gate electrode has a shape and thickness, particularly a gate length size that is a gate contact portion, and a desired gate electrode sidewall shape reaching the gate electrode surface, the gate capacitance is reduced, and the cutoff frequency ( An AlGaN / GaN-HEMT having improved high-frequency characteristics such as f _T ) and maximum oscillation frequency (f _max ) can be obtained.

  In the AlGaN / GaN-HEMT having the above-described configuration, a gate insulating film is formed between the UID-AlGaN electron supply layer and the first SiN surface protective layer, and the gate electrode is formed on the inner side of the sidewall. It has a MIS type gate structure in which the gate leakage current is suppressed and the breakdown voltage is increased by covering the surface of the gate insulating film, the sidewall, and the opening of the second SiN surface protective layer. AlGaN / GaN-HEMT can be obtained.

  ADVANTAGE OF THE INVENTION According to this invention, the formation method of the gate electrode which has the gate length below a lithography limit, the manufacturing method of AlGaN / GaN-HEMT with good high frequency characteristics, and AlGaN / GaN-HEMT can be provided.

FIG. 6 is a process cross-sectional view (No. 1) for describing the gate electrode formation method according to the first embodiment of the present invention; FIG. 5 is a process cross-sectional view (No. 2) for describing the gate electrode formation method of the first embodiment following FIG. 1; It is process sectional drawing for demonstrating the manufacturing method of the AlGaN / GaN-HEMT of the 2nd Embodiment of this invention (the 1). FIG. 4 is a process cross-sectional view (No. 2) for explaining the manufacturing method of the AlGaN / GaN-HEMT according to the second embodiment following FIG. 3; FIG. 6 is a process cross-sectional view (No. 3) for explaining the manufacturing method of the AlGaN / GaN-HEMT according to the second embodiment following FIG. 4; It is a schematic flowchart which shows the manufacturing process of the manufacturing method of AlGaN / GaN-HEMT of 2nd Embodiment. It is sectional drawing for demonstrating the manufacturing method of the MIS type AlGaN / GaN-HEMT of the 3rd Embodiment of this invention.

  An embodiment of the present invention will be described with reference to FIGS. Each drawing is described so as to clarify the features of the present invention, and the dimensional relationship and the like are not necessarily drawn to the actual ones, and thus does not limit the present invention. In addition, the same code | symbol is attached | subjected to the same component in each figure. Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
A method for forming a gate electrode according to the first embodiment of the present invention will be described with reference to FIGS. 1 (a) to 1 (d) and FIG.
The method for forming a gate electrode according to this embodiment is a method of forming a gate electrode 6 on a simplified substrate 1 with respect to a method for forming a gate electrode having a fine gate length equal to or smaller than a lithography limit value, which is one of the requirements of the present invention. The process will be described mainly.

  First, as shown in FIG. 1A, the manufacturer forms the first SiN surface protective layer 2 on the surface of the substrate 1 by PE-CVD. The thickness of the first SiN surface protective layer 2 determines the height of the side wall described later. The reason for using SiN is considering the adhesion to the substrate 1, the ease of the film forming process and the step coverage effect, and the workability by plasma etching.

Next, as shown in FIG. 1B, the manufacturer applies a resist 3 on the first SiN surface protective layer 2 to form a resist opening 3a at the limit of the lithography process. Then, using this resist pattern as a mask, the first SiN surface protective layer 2 is dry-etched in SF ₆ gas by ICP-RIE to form the opening 2a. According to the dry etching in SF ₆ gas, for example, when the substrate 1 is a substrate such as Si, SiC, sapphire, GaAs, GaN, AlGaN, or AlN, the surface of the substrate 1 is not etched. Only the desired first SiN surface protective layer can be etched.

  Next, as shown in FIG. 1C, the second SiN surface protective layer 4 is formed on the opening 2 a of the first SiN surface protective layer having been etched and the surface of the first SiN surface protective layer 2. The second SiN surface protective layer 4 becomes a ridge-shaped side wall 4b (FIG. 1D) to be described later. The thickness of the second SiN surface protective layer 4 determines the gate length of the gate electrode 6. Therefore, the second SiN surface protective layer 4 made of SiN is used in the same manner as the reason for adopting the first SiN surface protective layer 2 described above.

Next, as shown in FIG. 1 (d), a resist 5 is applied to the surface of the second SiN surface protective layer 4 on the opening 2a of the first SiN surface protective layer to form a resist opening 5a at the limit of the lithography process, Using the resist 5 as a mask, the second SiN surface protective layer 4 is anisotropically etched by anisotropic RIE by ICP-RIE. This anisotropic ICP-RIE is a condition for forming the sidewall 4b. For example, in the SF ₆ gas, the ICP output is 50 W, the RIE output is 10 W, and the pressure is 7.5 mTorr. In this way, the opening 4a of the second SiN surface protection layer 4 and the sidewall 4b of the second SiN surface protection layer 4 are formed on the side walls of the opening 2a of the first SiN surface protection layer 2.

Finally, as shown in FIG. 2, the gate electrode 6 covering the surface of the substrate 1 inside the sidewall 4b, the sidewall 4b, and the opening 4a of the second SiN surface protective layer 4 is formed to be short. A gate electrode having a gate length is formed. That is, the electrode width of the upper gate length (L _g2 ) determined by the opening 4a having the opening width that is the limit of the lithography process and the width of the sidewalls 4b on both sides from the lithography limit value that is in contact with the substrate 1 (to be a gate contact) A gate electrode 6 having a shortened short gate length (L _g1 ) can be formed. As shown in FIG. 2, the gate length (L _g3 ) of the outermost surface of the gate electrode 6 can be made a normal lithography size by a photolithography process.

  According to the method for forming a gate electrode of the present embodiment, not only the lithography limit, that is, not only a light exposure technique using ultraviolet, far ultraviolet, and extreme ultraviolet (EUV), but also an electron beam (EB). A gate electrode having a fine gate length equal to or less than a lithography limit value can be formed by an EB exposure technique using a). In addition, since the sidewall is formed using the SiN surface protective layer having a two-layer structure, the thickness and step coverage are uniform and controllable, so that the shape of the gate electrode can be easily controlled. . In particular, the gate length of the gate electrode to be formed can be determined by controlling the thickness of the second SiN surface protective layer.

(Second Embodiment)
A method of manufacturing the AlGaN / GaN-HEMT according to the second embodiment of the present invention will be described with reference to FIGS. In the AlGaN / GaN-HEMT manufacturing method of this embodiment, the above-described gate electrode forming method is applied to AlGaN / GaN-HEMT device fabrication.

  First, as illustrated in FIG. 3A, the manufacturer sequentially forms a buffer layer 11, a UID-GaN layer 12, and a UID-AlGaN layer 13 on the surface of the substrate 10 to obtain an epitaxial substrate 100. In the present embodiment, the substrate 10 can be a substrate such as SiC, Si, or sapphire. Then, the manufacturer sequentially grows the buffer layer 11, the UID-GaN layer 12, and the UID-AlGaN layer 13 by MOCVD, thereby forming the epitaxial substrate 100 having a stacked layer.

  Next, as shown in FIG. 3B, the manufacturer forms a first SiN surface protective layer 15 on the surface of the UID-AlGaN layer 13 of the epitaxial substrate 100 by PE-CVD. Next, Ar ions and the like are ion-implanted using an ion implantation method to form an isolation region 16 for device isolation that limits the HEMT device region. Further, the first SiN surface protective layer 15 is opened, and the source electrode 17-1 and the drain electrode 17-2 that are ohmic electrodes 17 are formed. The requirements of the first SiN surface protective layer 15 are the same as those of the first SiN surface protective layer 2 of the first embodiment.

Next, as shown in FIG. 3C, a resist opening 18a at the lithography limit is formed in the resist 18 on the surface of the first SiN surface protective layer 15 between the source electrode 17-1 and the drain electrode 17-2, and the manufacturing is performed. The person forms an opening 15a by etching opening the first SiN surface protection layer 15 using the resist 18 as a mask. The method for opening the first SiN surface protective layer 15 by etching is the ICP-RIE method in SF ₆ gas, similar to the method for opening the first SiN surface protective layer 2 of the first embodiment.

  Next, as shown in FIG. 4A, the manufacturer makes the surface of the source electrode 17-1 and the drain electrode 17-2, the opening portion 15 a of the first SiN surface protective layer opened by etching, and the first SiN surface protective layer 15. A second SiN surface protective layer 19 is formed on the surface. The requirements for the second SiN surface protective layer 19 are the same as those of the second SiN surface protective layer 4 of the first embodiment.

  Then, as shown in FIG. 4B, the manufacturer forms a resist opening 19a at the lithography limit in the resist 20 on the surface of the second SiN surface protective layer 19 on the opening 15a of the first SiN surface protective layer 15. The second SiN surface protective layer 19 is anisotropically etched by anisotropic RIE using the resist 19 as a mask, so that the opening 19a of the second SiN surface protective layer 19 and the side wall of the opening 15a of the first SiN surface protective layer 15 are etched. A sidewall 19b of the second SiN surface protective layer 19 is formed.

In this anisotropic ICP-RIE, for example, in SF ₆ gas, an ICP output of 50 W, an RIE output of 10 W, and a pressure of 7.5 mTorr are set as conditions for forming the sidewall 19b. In this way, the opening 19a of the second SiN surface protective layer 19 and the side wall 19b of the second SiN surface protective layer 19 are formed on the side walls of the opening 15a of the first SiN surface protective layer 15.

  And finally, as shown in FIG. 5, the gate electrode 21 which covers the surface of the UID-AlGaN 13 inside the sidewall 19b, the sidewall 19b, and the opening 19a of the second SiN surface protective layer 19 is formed. An AlGaN / GaN-HEMT having a short gate length is produced.

  Here, the flowchart which shows the main manufacturing process of the AlGaN / GaN-HEMT of this embodiment is demonstrated with reference to FIG. The main steps are to produce an epitaxial substrate including a UID-GaN layer and a UID-AlGaN layer on the substrate (step S1), form a first SIN surface protective layer, and form an isolation region and an ohmic electrode (step) S2), a resist opening having a gate length of a lithography limit value is formed in a gate formation scheduled portion, an opening is formed in the first SiN surface protective layer by etching (step S3), a second SiN surface protective layer is formed, and step S3 and A similar resist opening is performed, and the second SiN surface protection layer is etched by anisotropic RIE to form a sidewall and a gate opening (step S4), and a gate electrode is formed (step S5). .

  As described above, according to the AlGaN / GaN-HEMT manufacturing method of the present embodiment, in addition to the effects of the gate electrode forming method of the first embodiment, a desired shortening is achieved in the AlGaN / GaN-HEMT. The gate length size can be formed by a process design combining the lithography-limited opening size and the thicknesses of the first and second SiN surface protective layers. Then, the shape and thickness of the gate electrode to be formed, in particular, the gate length size that is the gate contact portion, and a desired gate electrode sidewall shape reaching the gate electrode surface can be obtained.

In addition, the AlGaN / GaN-HEMT according to the present embodiment can be designed by combining a desired shortened gate length size with a lithography limit opening size and the thicknesses of the first and second SiN surface protective layers. The gate electrode has a shape and thickness, in particular, a gate length size which is a gate contact portion, and a desired gate electrode sidewall shape reaching the gate electrode surface, the gate capacitance is reduced, and f _T and An AlGaN / GaN-HEMT with improved high frequency characteristics such as f _max can be obtained.

(Third embodiment)
A MIS type AlGaN / GaN-HEMT according to a third embodiment of the present invention will be described with reference to FIG. The manufacturing method of the MIS type AlGaN / GaN-HEMT according to the present embodiment is an application of the second embodiment described above to the fabrication of a MIS type AlGaN / GaN-HEMT.

  The difference between the MIS-type AlGaN / GaN-HEMT of this embodiment and the AlGaN / GaN-HEMT of the second embodiment is that, as shown in FIG. 7, the gate electrode (M) 21 as a metal (Metal) and the semiconductor As an insulator having an etching rate value smaller than the etching rate values of the first SiN surface protective layer 15 and the second SiN surface protective layer 19 between the UID-AlGaN layer (S) 13 as (Semiconductor) In other words, the gate insulating film (I) 30 is provided.

In the present embodiment, as the gate insulating film 30, an SiO ₂ film formed by PE-CVD or AlN is used. The etching rate of these insulating films by IPC-RIE in SF ₆ gas is 6 nm / min for the SiO ₂ film, and is not etched by the AlN film, and the etching rate is substantially zero. Incidentally, the etching rate by IPC-RIE in SF ₆ gas of the SiN surface protective layer of the first embodiment and the second embodiment is 40 nm / min to 50 nm / min. Therefore, these gate insulating films have a sufficient etching selectivity with the SiN surface protective layer.

  Therefore, by using the gate insulating film of the present embodiment, in the manufacturing method in the MIS type AlGaN / GaN-HEMT of the present embodiment shown in FIG. 7, the manufacturer has the UID-AlGaN 13 and the first SiN surface protective layer 15. Further, a gate insulating film 30 is further formed between them, and only the first SiN surface protective layer 15 on the gate insulating film 30 is etched open, and only the second SiN surface protective layer 19 on the gate insulating film 30 is formed by anisotropic RIE. The gate electrode 21 that covers the surface of the gate insulating film 30 inside the sidewall 19b, the sidewall 19b, and the opening 19a of the second SiN surface protective layer 19 can be formed by etching.

  Then, the gate insulating film 30 is formed between the UID-AlGaN 13 and the first SiN surface protective layer 15, and the gate electrode 30 is formed on the surface of the gate insulating film 30 inside the side wall 19b, the side wall 19b, and the second SiN surface. By covering the opening 19a of the protective layer 19, it is possible to obtain an AlGaN / GaN-HEMT having a MIS type gate structure in which the gate leakage current is suppressed and the breakdown voltage is increased.

  As described above, according to the present embodiment, a method for forming a gate electrode having a gate length less than the lithography limit, a method for manufacturing an AlGaN / GaN-HEMT with good high frequency characteristics, and an AlGaN / GaN-HEMT are provided. Can do.

(Modification 1)
In the embodiment of the present invention, ICP-RIE is used in the opening etching process of the SiN surface protection layer in the ohmic electrode and gate electrode formation locations, but wet etching using HF or the like and other dry etching methods may be used. Is possible.

(Modification 2)
In this embodiment, the PE-CVD method is used as the method for forming the SiN surface protective film, but the present invention is not limited to this, and a thermal CVD method or other growth methods can also be used.

(Modification 3)
Furthermore, this embodiment can also be used as a method for forming a short gate electrode using another semiconductor such as GaAs.

DESCRIPTION OF SYMBOLS 1 Substrate 2 1st SiN surface protection layer 2a, 3a, 4a, 5a Opening 3, 5 Resist 4 2nd SiN surface protection layer 4b Side wall 6 Gate electrode 10 Substrate 11 Buffer layer 12 UID-GaN layer 13 UID-AlGaN layer 14 2DEG Layer (two-dimensional electron gas layer)
15 First SiN surface protective layer 15a, 18a, 19a, 20a Opening 16 Isolation region 17 Ohmic electrode 17-1 Source electrode 17-2 Drain electrode 18, 20 Resist 19 Second SiN surface protective layer 19b Side wall 21 Gate electrode 30 Gate Insulating film 100 Epitaxial substrate 150, 200 AlGaN / GaN-HEMT

Claims (7)

A first step of forming a first SiN surface protective layer on the substrate surface;
A second step of forming a lithography-limited resist opening in a resist applied to the surface of the first SiN surface protective layer, and etching opening the first SiN surface protective layer using the resist as a mask;
A third step of forming a second SiN surface protective layer on the surface of the opening of the first SiN surface protective layer that is opened by etching and the surface of the first SiN surface protective layer;
The resist opening of the lithography limit is formed in the resist applied to the surface of the second SiN surface protective layer on the opening of the first SiN surface protective layer, and the first resist is masked by anisotropic RIE using the resist as a mask. A fourth step of forming an opening of the second SiN surface protective layer and a sidewall of the second SiN surface protective layer on the side wall of the opening of the first SiN surface protective layer by etching the 2SiN surface protective layer;
A gate electrode forming method comprising: a fifth step of forming a gate electrode that covers the substrate surface inside the sidewall, the sidewall, and the opening of the second SiN surface protective layer. . A first step of sequentially stacking a buffer layer, a UID-GaN electron transit layer, and a UID-AlGaN electron supply layer on the substrate surface to form an epitaxial substrate;
A second step of forming a first SiN surface protective layer, a source electrode and a drain electrode on the surface of the UID-AlGaN electron supply layer of the epitaxial substrate;
A resist opening having a lithography limit is formed in the resist applied on the surface of the first SiN surface protective layer between the source electrode and the drain electrode, and the first SiN surface protective layer is opened by etching using the resist as a mask. 3 steps,
A fourth step of forming a second SiN surface protective layer on the surface of the source electrode and the drain electrode, the opening of the first SiN surface protective layer that has been opened by etching, and the surface of the first SiN surface protective layer;
The resist opening of the lithography limit is formed in the resist applied to the surface of the second SiN surface protective layer on the opening of the first SiN surface protective layer, and the first resist is masked by anisotropic RIE using the resist as a mask. A second step of forming an opening of the second SiN surface protective layer and a sidewall of the second SiN surface protective layer on the side wall of the opening of the first SiN surface protective layer by etching the 2SiN surface protective layer;
And at least a sixth step of forming a gate electrode that covers the surface of the UID-AlGaN electron supply layer inside the sidewall, the sidewall, and the opening of the second SiN surface protective layer. Manufacturing method of AlGaN / GaN-HEMT. The second step further includes forming a gate insulating film between the UID-AlGaN electron supply layer and the first SiN surface protective layer,
In the third step, only the first SiN surface protective layer on the gate insulating film is etched open,
In the fifth step, only the second SiN surface protective layer on the gate insulating film is etched by the anisotropic RIE,
3. The sixth step is to form a gate electrode that covers the surface of the gate insulating film inside the sidewall, the sidewall, and the opening of the second SiN surface protective layer. A method for producing the AlGaN / GaN-HEMT described in 1. The gate insulating film formed in the second step is an insulating film having an etching rate value smaller than an etching rate value of the first SiN surface protective layer and the second SiN surface protective layer. 3. The method for producing an AlGaN / GaN-HEMT described in 3. The gate insulating film, a manufacturing method of the AlGaN / GaN-HEMT according to claim 4, characterized in that one of the insulating film selected from AlN and SiO _2. An epitaxial substrate in which a buffer layer, a UID-GaN electron transit layer, and a UID-AlGaN electron supply layer are sequentially laminated on the substrate surface;
A first SiN surface protective layer formed on the surface of the UID-AlGaN electron supply layer of the epitaxial substrate, a source electrode and a drain electrode;
A lithography-limited resist opening formed in a resist coated on the surface of the first SiN surface protective layer between the source electrode and the drain electrode, and the first SiN surface protective layer opened by etching using the resist as a mask; ,
A surface of the source and drain electrodes, an opening of the first SiN surface protective layer having the etching opening, and a second SiN surface protective layer formed on the surface of the first SiN surface protective layer;
The resist opening of the lithography limit is formed in the resist applied to the surface of the second SiN surface protective layer on the opening of the first SiN surface protective layer, and the first resist is masked by anisotropic RIE using the resist as a mask. An opening of the second SiN surface protection layer formed by etching the 2SiN surface protection layer, and a sidewall of the second SiN surface protection layer formed on the opening side wall of the first SiN surface protection layer;
The gate electrode formed at least by covering the surface of the UID-AlGaN electron supply layer inside the sidewall, the sidewall, and the opening of the second SiN surface protective layer. GaN-HEMT. A gate insulating film is formed between the UID-AlGaN electron supply layer and the first SiN surface protective layer;
The AlGaN / GaN- according to claim 6, wherein the gate electrode covers the surface of the gate insulating film inside the sidewall, the sidewall, and the opening of the second SiN surface protective layer. HEMT.

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