JP2011071193A - Lamination soi wafer and manufacturing method of the same - Google Patents
Lamination soi wafer and manufacturing method of the same Download PDFInfo
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- 238000003475 lamination Methods 0.000 title abstract description 7
- 235000012431 wafers Nutrition 0.000 claims abstract description 271
- 238000010438 heat treatment Methods 0.000 claims abstract description 28
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- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
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Abstract
Description
本発明は、埋込み酸化膜層厚さが大きい高耐圧デバイスに適した貼合せSOI(Silicon On Insulater)ウェーハ及びその製造方法に関するものである。 The present invention relates to a bonded SOI (Silicon On Insulater) wafer suitable for a high breakdown voltage device having a large buried oxide film layer thickness and a method for manufacturing the same.
SOIウェーハは、シリコン単結晶を支持基板とし、埋込み酸化膜(Buried Oxide;以下、BOXという。)層を介して活性層となる単結晶シリコン層(以下、SOI層という。)が形成された構造を有する。そして、BOX層の誘電体分離によって素子間が電気的に分離されることを活かして高耐圧デバイスへの応用がなされている。特に、自動車エレクトロニクスやフラットパネルディスプレイ、モーター制御や電源など多くの分野において、より高耐圧なデバイスに対応したSOIウェーハへの需要がある。 The SOI wafer has a structure in which a single crystal silicon layer (hereinafter referred to as an SOI layer) serving as an active layer is formed through a buried oxide film (hereinafter referred to as BOX) layer using a silicon single crystal as a supporting substrate. Have Application to high withstand voltage devices has been made by taking advantage of the fact that elements are electrically isolated by dielectric separation of the BOX layer. In particular, in many fields such as automotive electronics, flat panel displays, motor control and power supplies, there is a demand for SOI wafers corresponding to higher voltage devices.
一般的に、より高耐圧なデバイスへ適応するためには素子間の電気抵抗を大きくすればよい。即ち、素子間の電気分離に用いられているBOX層を厚くすることによって高耐圧に対応したSOIウェーハがこれまで作製されてきた。 In general, in order to adapt to a device having a higher breakdown voltage, the electrical resistance between elements may be increased. That is, an SOI wafer corresponding to a high breakdown voltage has been manufactured so far by increasing the thickness of a BOX layer used for electrical isolation between elements.
SOIウェーハの製造方法としては、薄膜化される活性層用ウェーハと、支持用ウェーハを貼合せて形成する貼合せ法や、ウェーハ表面より酸素イオンを注入してウェーハ表面から所定の深さの領域にBOX層を形成するSIMOX(Separation by Implanted Oxygen)法などがある。 As an SOI wafer manufacturing method, an active layer wafer to be thinned and a supporting wafer are bonded to each other, or a region having a predetermined depth from the wafer surface by injecting oxygen ions from the wafer surface. There is a SIMOX (Separation by Implanted Oxygen) method for forming a BOX layer.
このうち、貼合せ法によるSOIウェーハの製造方法は、図7に示すように、先ず、活性層用ウェーハ1と支持用ウェーハ2を用意し、いずれか一方或いは双方のウェーハに熱酸化による酸化膜1a,2aを形成する。図7では、双方のウェーハに酸化膜を形成している。次に、2枚のウェーハ1,2を重ね合せて加圧することによって2枚のウェーハ1,2を酸化膜1a,2aを介して接着する。重ね合せウェーハ3は水素結合によって接着されているに過ぎず、接着強度が弱いため、酸化雰囲気中、1100〜1250℃の温度で貼合せ熱処理を施して、接着強度を高める。これにより重ね合せたウェーハの間に介在する酸化膜1a,2aをBOX層5とする。更に、熱処理後の重ね合せウェーハ4の活性層用ウェーハを研削、研磨によって所望する厚さになるように減肉化処理を施してSOI層6とし、更にテラス研磨を施すことにより貼合せSOIウェーハ7が製造される。 Among these, as shown in FIG. 7, in the manufacturing method of the SOI wafer by the bonding method, first, an active layer wafer 1 and a supporting wafer 2 are prepared, and either one or both wafers are oxidized by thermal oxidation. 1a and 2a are formed. In FIG. 7, oxide films are formed on both wafers. Next, the two wafers 1 and 2 are bonded to each other through the oxide films 1a and 2a by applying pressure by superimposing the two wafers 1 and 2 on each other. Since the laminated wafer 3 is only bonded by hydrogen bonding and has a low bonding strength, a bonding heat treatment is performed at a temperature of 1100 to 1250 ° C. in an oxidizing atmosphere to increase the bonding strength. Thus, the oxide films 1a and 2a interposed between the stacked wafers are used as the BOX layer 5. Furthermore, the active layer wafer of the superposed wafer 4 after the heat treatment is subjected to a thinning process so as to have a desired thickness by grinding and polishing to form an SOI layer 6, and further subjected to terrace polishing to obtain a bonded SOI wafer. 7 is manufactured.
前述した高耐圧デバイス向けSOIウェーハを製造する際には、上記の熱酸化時間を長くしてBOX層を厚く形成することによって対応してきたが、BOX厚さが2μm以上と、BOX層が厚いSOIウェーハ(以下、厚BOX−SOIウェーハという。)を製造する際に、活性層用ウェーハに形成する酸化膜厚さと支持用ウェーハに形成する酸化膜厚さの厚み差が大きくなると、貼合せ熱処理の際に、重ね合せた2枚のウェーハの断面の周端領域にスリップと呼ばれる結晶欠陥が生じていた(例えば、特許文献1参照。)。このため、厚BOX−SOIウェーハの製造では、活性層用ウェーハに形成する酸化膜の厚さと支持用ウェーハに形成する酸化膜の厚さの厚み差を小さくする、具体的には2μm以下にする必要があった。 When manufacturing the above-described SOI wafer for a high voltage device, the above-described thermal oxidation time has been increased to form a thick BOX layer. However, an SOI having a thick BOX layer with a BOX thickness of 2 μm or more. When manufacturing a wafer (hereinafter referred to as a thick BOX-SOI wafer), if the difference in thickness between the oxide film thickness formed on the active layer wafer and the oxide film thickness formed on the support wafer increases, At this time, crystal defects called slips were generated in the peripheral edge regions of the cross-sections of the two wafers that were superposed (see, for example, Patent Document 1). For this reason, in manufacturing a thick BOX-SOI wafer, the thickness difference between the thickness of the oxide film formed on the active layer wafer and the thickness of the oxide film formed on the support wafer is reduced, specifically, 2 μm or less. There was a need.
また、この貼合せ熱処理時に生じるスリップの発生を大幅に抑えるために、2枚のウェーハを重ね合せ、活性層用ウェーハを所望のSOI層厚さにまで薄膜化した後、貼合せ熱処理することが提案されている(例えば、特許文献2参照。)。 In addition, in order to greatly suppress the occurrence of slip that occurs during the bonding heat treatment, two wafers may be overlapped, and the active layer wafer may be thinned to a desired SOI layer thickness, followed by bonding heat treatment. It has been proposed (see, for example, Patent Document 2).
しかしながら、上記特許文献1に記載の方法で厚BOX−SOIウェーハを作製した場合、必然的にBOX層厚さと支持用ウェーハ裏面の酸化膜厚さに厚み差が生じるため、結果として、得られるSOIウェーハには、この厚み差に起因して反りが増大していた。この反りが100μm以上になると、半導体製造工程における露光不良や吸着不良の原因となる。 However, when a thick BOX-SOI wafer is produced by the method described in Patent Document 1, a difference in thickness is inevitably generated between the BOX layer thickness and the oxide film thickness on the back surface of the supporting wafer. The warpage of the wafer increased due to this thickness difference. When this warp is 100 μm or more, it causes exposure failure and adsorption failure in the semiconductor manufacturing process.
また、上記特許文献2に記載の方法では、所望のSOI層厚さになるまで薄膜化した後に貼合せ熱処理すると、薄膜化によって活性層用ウェーハ自体の強度が弱くなっているため、活性層用ウェーハが熱応力により割れてしまうおそれがあった。更に、2枚のウェーハを単に重ね合せただけの接着強度が弱い状態で面取り加工や、研削加工及び研磨加工によって所望のSOI層厚さになるまで薄膜化が行われるため、加工処理中に、重ね合せた2枚のウェーハが接着面で剥がれてしまい、加工そのものができないことが予想される。 Further, in the method described in Patent Document 2, if the bonding heat treatment is performed after thinning to a desired SOI layer thickness, the strength of the active layer wafer itself is weakened due to the thinning. There was a possibility that the wafer was cracked by thermal stress. Furthermore, since the thinning is performed until the desired SOI layer thickness is obtained by chamfering processing, grinding processing, and polishing processing in a state where the adhesive strength simply by overlapping the two wafers is weak, during processing, It is expected that the two stacked wafers will be peeled off at the bonding surface, and the processing itself cannot be performed.
本発明の目的は、貼合せ熱処理の際に生じていた貼合せ界面の結晶欠陥を低減するとともに、ウェーハに生じる反りを低減し得る、貼合せSOIウェーハ及びその製造方法を提供することにある。 An object of the present invention is to provide a bonded SOI wafer and a method for manufacturing the same, which can reduce crystal defects at the bonding interface that have occurred during the bonding heat treatment, and can reduce warpage generated in the wafer.
本発明の第1の観点は、支持用ウェーハの上にBOX層を介してSOI層が形成された貼合せSOIウェーハにおいて、支持用ウェーハの裏面に形成された酸化膜の厚さが0.45〜6μmの範囲内にあって、BOX層の厚さと支持用ウェーハ裏面酸化膜の厚さとの厚み差が1μm以下であり、かつSOI層にスリップ転位が存在しないことを特徴とする。 A first aspect of the present invention is a bonded SOI wafer in which an SOI layer is formed on a supporting wafer via a BOX layer, and the thickness of the oxide film formed on the back surface of the supporting wafer is 0.45. In the range of ˜6 μm, the thickness difference between the thickness of the BOX layer and the thickness of the support wafer back surface oxide film is 1 μm or less, and no slip dislocation exists in the SOI layer.
本発明の第2の観点は、図1に示すように、活性層用ウェーハ11の全面に酸化膜11bを形成し、このウェーハ11を支持するための支持用ウェーハ12の全面に酸化膜12aを形成し、活性層用ウェーハ11を支持用ウェーハ12に酸化膜11b,12aを介して重ね合せ、2枚の重ね合せウェーハ13を熱処理して貼合せ、これにより2枚の重ね合せたウェーハ14の間に介在する酸化膜11b,12aをBOX層15にし、その後、活性層用ウェーハ11に減肉化処理を施すことにより、支持用ウェーハ12の上にBOX層15を介してSOI層16を形成した貼合せSOIウェーハ17を製造する方法であって、貼合せ熱処理前において、活性層用ウェーハ11の厚さが支持用ウェーハ12の厚さより小さく、かつ活性層用ウェーハ11の全面に形成する酸化膜11bの厚さが支持用ウェーハ12の全面に形成する酸化膜12aの厚さより小さいことを特徴とする。 As shown in FIG. 1, the second aspect of the present invention is that an oxide film 11b is formed on the entire surface of the active layer wafer 11, and an oxide film 12a is formed on the entire surface of the supporting wafer 12 for supporting the wafer 11. Then, the active layer wafer 11 is laminated on the supporting wafer 12 via the oxide films 11b and 12a, and the two laminated wafers 13 are heat-treated and bonded together. The intervening oxide films 11b and 12a are formed into a BOX layer 15, and thereafter, an SOI layer 16 is formed on the supporting wafer 12 through the BOX layer 15 by subjecting the active layer wafer 11 to a thinning process. In which the thickness of the active layer wafer 11 is smaller than the thickness of the supporting wafer 12 before the bonding heat treatment, and the active layer wafer is manufactured. Entirely in the thickness of the oxide film 11b to form the 11 being less than the thickness of the oxide film 12a is formed on the entire surface of the supporting wafer 12.
本発明の第3の観点は、第2の観点に基づく発明であって、更に支持用ウェーハの裏面に形成された酸化膜の厚さが0.45〜6μmの範囲内にあって、BOX層の厚さと支持用ウェーハ裏面酸化膜の厚さとの厚み差が1μm以下であることを特徴とする。 A third aspect of the present invention is the invention based on the second aspect, wherein the thickness of the oxide film formed on the back surface of the supporting wafer is in the range of 0.45 to 6 μm, and the BOX layer And the thickness of the supporting wafer back surface oxide film is 1 μm or less.
本発明の第4の観点は、第2又は第3の観点に基づく発明であって、更に支持用ウェーハの厚さが325〜725μmの範囲内にあるとき、活性層用ウェーハの厚さが支持用ウェーハの厚さより小さい300〜700μmの範囲内であることを特徴とする。 A fourth aspect of the present invention is the invention based on the second or third aspect, wherein the thickness of the active layer wafer is supported when the thickness of the supporting wafer is in the range of 325 to 725 μm. It is characterized by being in the range of 300 to 700 μm, which is smaller than the thickness of the wafer for use.
本発明の第5の観点は、第2の観点に基づく発明であって、更にBOX層の厚さが0.5〜7μmであることを特徴とする。 A fifth aspect of the present invention is the invention based on the second aspect, and is characterized in that the BOX layer has a thickness of 0.5 to 7 μm.
本発明の第6の観点は、第1の観点に基づく発明であって、更にBOX層の厚さが0.5〜7μmμmであり、かつウェーハに生じる反りが100μm以下であることを特徴とする。 A sixth aspect of the present invention is the invention based on the first aspect, wherein the thickness of the BOX layer is 0.5 to 7 μm μm, and the warp generated in the wafer is 100 μm or less. .
本発明の貼合せSOIウェーハの製造方法では、活性層用ウェーハの厚さを支持用ウェーハの厚さより小さくなるように厚み調整することで、貼合せ熱処理の際に重ね合せウェーハの厚み方向の温度差が少なくなり、熱応力が低下するため、貼合せ熱処理の際に生じていた貼合せ界面の結晶欠陥を低減することができ、活性層用ウェーハに形成する酸化膜の厚さを支持用ウェーハに形成する酸化膜の厚さより小さくすることで、BOX層と支持側ウェーハの裏面酸化膜との体積膨張差が小さくなるため、得られるSOIウェーハに生じる反りを、100μm以下にまで低減することができる。 In the method for manufacturing a bonded SOI wafer according to the present invention, the thickness of the active layer wafer is adjusted so that the thickness of the active layer wafer is smaller than the thickness of the supporting wafer. Since the difference is reduced and the thermal stress is reduced, the crystal defects at the bonding interface that occurred during the bonding heat treatment can be reduced, and the thickness of the oxide film formed on the active layer wafer can be reduced to the supporting wafer. Since the volume expansion difference between the BOX layer and the back surface oxide film of the support side wafer is reduced by making the thickness smaller than the thickness of the oxide film formed on the substrate, the warpage occurring in the obtained SOI wafer can be reduced to 100 μm or less. it can.
また、本発明の貼合せSOIウェーハは、貼合せ界面の結晶欠陥が低減されているため、耐圧特性の低下を解決することができ、また、反りが低減されているため、半導体製造工程における露光不良や吸着不良を低減できる。 Moreover, since the bonded SOI wafer of the present invention has reduced crystal defects at the bonded interface, it can solve the deterioration of the pressure resistance characteristics, and since the warpage is reduced, exposure in the semiconductor manufacturing process. Defects and adsorption defects can be reduced.
次に本発明を実施するための形態を図面に基づいて説明する。 Next, an embodiment for carrying out the present invention will be described based on the drawings.
本発明の貼合せSOIウェーハの製造方法では、先ず、図1に示すように、活性層用ウェーハ11及びこのウェーハを支持するための支持用ウェーハ12を用意する。活性層用ウェーハ11及び支持用ウェーハ12は、ともに直径が200mmの鏡面加工されたウェーハが好ましい。支持用ウェーハ12の厚さは325〜725μmの範囲内が好適である。また、貼合せ熱処理時におけるウェーハの厚み方向の温度差を小さくするために、貼合せ熱処理時前の活性層用ウェーハ11の厚さは支持用ウェーハ12の厚みよりも小さくすることが有効となる。このため、活性層用ウェーハ11を製造する段階において、事前に支持用ウェーハの厚みよりも厚みを小さく製造した厚み調整ウェーハ11aを活性層用ウェーハ11として用いてもよいし、活性層用ウェーハ11として支持用ウェーハ12と同程度の厚さのものを用いる場合には、図2〜図4に示すように、この活性層用ウェーハ11に対し、支持用ウェーハ12の厚さより小さくなるように予備的な減肉化処理を施せばよい。この予備的な減肉化処理は、所望の減肉化量のうちの大部分を砥石などを用いた研削加工によって行い、残部を、研磨布などを用いた鏡面仕上げ加工によって行うことが好ましい。また、図2に示すように、予備的減肉化処理した後に酸化膜形成、2枚のウェーハを重ね合せ、貼合せ熱処理の順としてもよいし、図3や図4に示すように、2枚のウェーハを重ね合せる前又は重ね合せた状態で、この予備的減肉化処理を行ってもよい。 In the method for manufacturing a bonded SOI wafer of the present invention, first, as shown in FIG. 1, an active layer wafer 11 and a supporting wafer 12 for supporting the wafer are prepared. Both the active layer wafer 11 and the supporting wafer 12 are preferably mirror-finished wafers having a diameter of 200 mm. The thickness of the supporting wafer 12 is preferably in the range of 325 to 725 μm. Further, in order to reduce the temperature difference in the thickness direction of the wafer during the bonding heat treatment, it is effective to make the thickness of the active layer wafer 11 before the bonding heat treatment smaller than the thickness of the supporting wafer 12. . Therefore, in the stage of manufacturing the active layer wafer 11, the thickness adjusting wafer 11 a manufactured in advance to be smaller than the thickness of the supporting wafer may be used as the active layer wafer 11, or the active layer wafer 11 may be used. As shown in FIG. 2 to FIG. 4, the active layer wafer 11 is spared so as to be smaller than the thickness of the support wafer 12. A thinning process may be applied. This preliminary thinning treatment is preferably carried out by grinding using a grindstone or the like for the majority of the desired thinning amount and by mirror finishing using a polishing cloth or the like. Further, as shown in FIG. 2, after the preliminary thinning process, the oxide film is formed, the two wafers may be overlapped, and the bonding heat treatment may be performed in order, or as shown in FIG. 3 and FIG. This preliminary thinning process may be performed before or after the wafers are stacked.
なお、0.3〜250μmといった所望のSOI層となるまで厚みを薄くしたものを活性層用ウェーハ11に使用した場合には、その後に行う貼合せ熱処理時に活性層用ウェーハ11が割れてしまうおそれがあることから、活性層用ウェーハ11aの厚さを支持用ウェーハ12の厚さより小さい300〜700μmの範囲内にすることが望ましい。従来生じていたスリップ欠陥は、2枚のウェーハを重ね合せた後に施す貼合せ熱処理の際に、ウェーハの厚み方向の温度差が大きく、熱応力が増大することによるものと考えられる。一方、貼合せ熱処理時前の活性層用ウェーハ11の厚さを支持用ウェーハ12の厚さより小さくなるように加工することで、貼合せ熱処理の際に重ね合せウェーハの厚み方向の温度差が少なくなり、熱応力が低下するため、後に続く貼合せ熱処理の際に生じていた貼合せ界面の結晶欠陥を低減することができる。 In addition, when what thinned until it became desired SOI layers, such as 0.3-250 micrometers, is used for the wafer 11 for active layers, there exists a possibility that the wafer 11 for active layers may crack at the time of the bonding heat processing performed after that. Therefore, it is desirable that the thickness of the active layer wafer 11 a be in the range of 300 to 700 μm, which is smaller than the thickness of the support wafer 12. A slip defect that has conventionally occurred is considered to be due to a large temperature difference in the thickness direction of the wafer and an increase in thermal stress during the bonding heat treatment performed after the two wafers are overlaid. On the other hand, by processing the thickness of the active layer wafer 11 before the bonding heat treatment to be smaller than the thickness of the supporting wafer 12, the temperature difference in the thickness direction of the laminated wafer is small during the bonding heat treatment. Since the thermal stress is reduced, crystal defects at the bonding interface that have occurred during the subsequent bonding heat treatment can be reduced.
続いて、厚み調整した活性層用ウェーハ11aと支持用ウェーハ12をSC−1洗浄、純水リンス及びフッ酸有機酸洗浄をこの順に行い、各ウェーハ表面を清浄化させる。 Subsequently, the thickness of the active layer wafer 11a and the supporting wafer 12 are subjected to SC-1 cleaning, pure water rinsing, and hydrofluoric acid organic acid cleaning in this order to clean the surface of each wafer.
次に、厚み調整した活性層用ウェーハ11aの全面に酸化膜11bを形成し、支持用ウェーハ12の全面に酸化膜12aを形成する。ここで厚み調整した活性層用ウェーハ11aの全面に形成された酸化膜11bの厚さを、支持用ウェーハ12の全面に形成された酸化膜12aの厚さより小さくすることで、SOIウェーハのBOX層と支持側ウェーハの裏面酸化膜との体積膨張差が小さくなるため、得られるSOIウェーハに生じる反りを、100μm以下にまで低減することができる。また、2枚のウェーハ11a,12に形成する酸化膜11b,12aは、最終的に得られるSOIウェーハのBOX層の厚さが0.5〜7μmとなるようにそれぞれの厚さが調整される。また、支持用ウェーハ12の裏面に形成された酸化膜12aの厚さが0.45〜6μmの範囲内にあって、BOX層の厚さと支持用ウェーハ裏面酸化膜12aの厚さとの厚み差が1μm以下となるように、2枚のウェーハ11a,12に形成する酸化膜11b,12aの厚さをそれぞれ調整することが好ましい。各ウェーハへの酸化膜形成は、水素及び酸素混合ガス雰囲気下で熱処理を行うことが好適である。なお、いずれか一方のウェーハのみに酸化膜を形成し、他方のウェーハには酸化膜を形成しない場合、スリップの発生を低減することができず、また、貼合せ界面にある汚染が活性層に拡散していく不具合を生じる。 Next, an oxide film 11 b is formed on the entire surface of the active layer wafer 11 a whose thickness has been adjusted, and an oxide film 12 a is formed on the entire surface of the support wafer 12. The BOX layer of the SOI wafer is formed by making the thickness of the oxide film 11b formed on the entire surface of the active layer wafer 11a whose thickness is adjusted smaller than the thickness of the oxide film 12a formed on the entire surface of the support wafer 12. And the back surface oxide film of the support side wafer become small, so that the warpage generated in the obtained SOI wafer can be reduced to 100 μm or less. The thicknesses of the oxide films 11b and 12a formed on the two wafers 11a and 12 are adjusted so that the thickness of the BOX layer of the finally obtained SOI wafer becomes 0.5 to 7 μm. . Further, the thickness of the oxide film 12a formed on the back surface of the supporting wafer 12 is in the range of 0.45 to 6 μm, and there is a difference in thickness between the thickness of the BOX layer and the thickness of the supporting wafer back surface oxide film 12a. It is preferable to adjust the thicknesses of the oxide films 11b and 12a formed on the two wafers 11a and 12 so that the thickness is 1 μm or less. For forming an oxide film on each wafer, it is preferable to perform a heat treatment in a hydrogen and oxygen mixed gas atmosphere. In addition, when an oxide film is formed only on one of the wafers and an oxide film is not formed on the other wafer, the occurrence of slip cannot be reduced, and contamination at the bonding interface may occur in the active layer. This causes a problem of spreading.
続いて、全面に酸化膜を形成した2枚のウェーハ11a,12をSC−1洗浄、純水リンス及びフッ酸有機酸洗浄をこの順に行い、各ウェーハ表面を水素終端させる。その後に、表面を水素終端させた2枚のウェーハ11a,12を重ねて重石を乗せて加圧することによって2枚のウェーハ11a,12を酸化膜11b,12aを介して接着する。 Subsequently, SC-1 cleaning, pure water rinsing, and hydrofluoric acid organic acid cleaning are performed in this order on the two wafers 11a and 12 having an oxide film formed on the entire surface, and the surface of each wafer is terminated with hydrogen. After that, the two wafers 11a and 12 whose surfaces are hydrogen-terminated are stacked and a heavy stone is placed on the two wafers 11a and 12 to apply pressure, thereby bonding the two wafers 11a and 12 through the oxide films 11b and 12a.
次に、貼合せ熱処理することにより、水素結合によって接着されていた重ね合せウェーハ13の接着強度を高める。貼合せ熱処理は、水素及び酸素混合ガス雰囲気中、1200℃の温度で60〜180分間保持することにより行われる。なお、重ね合せた2枚のウェーハ11a,12の間に介在する酸化膜11b,12aはBOX層15になる。 Next, the bonding heat treatment increases the bonding strength of the laminated wafer 13 bonded by hydrogen bonding. The bonding heat treatment is performed by holding at a temperature of 1200 ° C. for 60 to 180 minutes in a hydrogen and oxygen mixed gas atmosphere. Note that the oxide films 11b and 12a interposed between the two wafers 11a and 12 that are overlapped become the BOX layer 15.
次に、貼合せ熱処理を施した重ね合せウェーハ14の活性層用ウェーハ側をその厚さが0.3〜250μmのSOI層とになるように減肉化処理を施す。減肉化処理は平面研削、鏡面研磨により行われる。これにより、支持用ウェーハ12の上にBOX層15を介してSOI層16が形成される。 Next, a thinning process is performed so that the active layer wafer side of the laminated wafer 14 subjected to the bonding heat treatment becomes an SOI layer having a thickness of 0.3 to 250 μm. The thinning process is performed by surface grinding or mirror polishing. As a result, the SOI layer 16 is formed on the supporting wafer 12 via the BOX layer 15.
更に、BOX層15及びSOI層16の周端にテラス研磨を施すことにより、裏面に酸化膜12aが形成された支持用ウェーハ12の上にBOX層15を介してSOI層16が形成された貼合せSOIウェーハ17が得られる。 Further, the peripheral edge of the BOX layer 15 and the SOI layer 16 is subjected to terrace polishing so that the SOI layer 16 is formed on the supporting wafer 12 having the oxide film 12a formed on the back surface via the BOX layer 15. A combined SOI wafer 17 is obtained.
本発明の貼合せSOIウェーハは、支持用ウェーハ12の裏面に形成された酸化膜12aの厚さが0.45〜6μmの範囲内にあって、BOX層15の厚さと支持用ウェーハ12の裏面に形成された酸化膜12aの厚さとの厚み差が1μm以下であり、SOI層にスリップ転位が存在しないことを特徴とする。また、BOX層15の厚さが0.5〜7μmであり、かつウェーハに生じる反りが100μm以下である。貼合せ界面の結晶欠陥が低減されているため、耐圧特性の低下を解決することができ、また、反りが100μm以下にまで低減されているため、半導体製造工程における露光不良や吸着不良を低減できる。 In the bonded SOI wafer of the present invention, the thickness of the oxide film 12a formed on the back surface of the support wafer 12 is in the range of 0.45 to 6 μm, and the thickness of the BOX layer 15 and the back surface of the support wafer 12 are The difference in thickness with respect to the thickness of the oxide film 12a formed in 1 is 1 μm or less, and no slip dislocation exists in the SOI layer. Further, the thickness of the BOX layer 15 is 0.5 to 7 μm, and the warp generated in the wafer is 100 μm or less. Since the crystal defects at the bonding interface are reduced, it is possible to solve the deterioration of the pressure resistance characteristics, and since the warpage is reduced to 100 μm or less, it is possible to reduce exposure defects and adsorption defects in the semiconductor manufacturing process. .
なお、ウェーハの厚みは静電容量測定により測定し、BOX層、酸化膜の厚さは反射率分光法により測定し、スリップ転位は貼合せ界面にレーザー光を照射しその散乱光の解析により測定し、また、ウェーハに生じる反りは非接触式の静電容量測定により測定する。 The thickness of the wafer is measured by capacitance measurement, the thickness of the BOX layer and oxide film is measured by reflectance spectroscopy, and the slip dislocation is measured by irradiating the bonding interface with laser light and analyzing the scattered light. Further, the warpage generated in the wafer is measured by non-contact type capacitance measurement.
次に本発明の実施例を比較例とともに詳しく説明する。 Next, examples of the present invention will be described in detail together with comparative examples.
<実施例1>
先ず、活性層用ウェーハ及び支持用ウェーハとして、ともに厚さが725μm、直径が200mmの鏡面加工されたウェーハを用意した。次いで、予備的減肉化処理として、活性層用ウェーハに対し、砥石を用いて研削加工を行い、ウェーハ厚さを650μmになるまで薄くし、続いて、研削加工後のウェーハに対し、研摩布を用いて鏡面仕上げ加工を行い、ウェーハ厚さを640μmにまで厚さ調整した。そして、薄く加工した活性層用ウェーハと支持用ウェーハをSC−1洗浄、純水リンス及びフッ酸有機酸洗浄をこの順に行い、ウェーハ表面を清浄化させた。次に、2枚のウェーハを水素及び酸素混合ガス雰囲気下で熱処理を行い、活性層用ウェーハには厚さ1μmの酸化膜を、支持用ウェーハには厚さ5μmの酸化膜をそれぞれ形成した。そして、2枚のウェーハをSC−1洗浄、純水リンス及びフッ酸有機酸洗浄をこの順に行い、表面を水素終端させた後に、2枚のウェーハを重ね合せて接着した。次に、水素及び酸素混合ガス雰囲気中、1200℃の温度で重ね合せウェーハに貼合せ熱処理を施した。貼合せ熱処理を施した重ね合せウェーハの活性層用ウェーハ側を平面研削によって活性層用ウェーハの厚さが15μmのSOI層となるように減肉化処理を施し、更に、テラス研磨を施し、貼合せSOIウェーハを得た。
<Example 1>
First, a mirror-finished wafer having a thickness of 725 μm and a diameter of 200 mm was prepared as an active layer wafer and a supporting wafer. Next, as a pre-thinning process, the active layer wafer is ground using a grindstone to reduce the wafer thickness to 650 μm, and then the ground wafer is ground. Mirror finish processing was performed using, and the wafer thickness was adjusted to 640 μm. The thinly processed active layer wafer and supporting wafer were subjected to SC-1 cleaning, pure water rinsing, and hydrofluoric acid organic acid cleaning in this order to clean the wafer surface. Next, the two wafers were heat-treated in a hydrogen and oxygen mixed gas atmosphere to form an oxide film having a thickness of 1 μm on the active layer wafer and an oxide film having a thickness of 5 μm on the supporting wafer. Then, the two wafers were subjected to SC-1 cleaning, pure water rinsing, and hydrofluoric acid organic acid cleaning in this order, and the surfaces were hydrogen-terminated, and then the two wafers were stacked and bonded. Next, a bonding heat treatment was performed on the laminated wafer at a temperature of 1200 ° C. in a hydrogen and oxygen mixed gas atmosphere. The active layer wafer side of the laminated wafer subjected to the bonding heat treatment is subjected to surface grinding by surface grinding so that the thickness of the active layer wafer becomes an SOI layer of 15 μm, and further subjected to terrace polishing and pasting. A combined SOI wafer was obtained.
<実施例2>
予備的減肉化処理で厚さ調整して活性層用ウェーハ厚さを700μmとした以外は実施例1と同様にして貼合せSOIウェーハを得た。
<Example 2>
A bonded SOI wafer was obtained in the same manner as in Example 1 except that the thickness of the active layer was adjusted to 700 μm by adjusting the thickness by preliminary thinning treatment.
<実施例3>
活性層用ウェーハ及び支持用ウェーハとして、ともに厚さが325μm、直径が200mmの鏡面加工されたウェーハを用意し、予備的減肉化処理で厚さ調整して活性層用ウェーハ厚さを300μmとし、支持用ウェーハに厚さ4μmの酸化膜を形成した以外は実施例1と同様にして貼合せSOIウェーハを得た。
<Example 3>
Prepare both active layer wafer and support wafer as mirror-finished wafers with a thickness of 325μm and a diameter of 200mm, and adjust the thickness by pre-thinning to make the active layer wafer thickness 300μm. A bonded SOI wafer was obtained in the same manner as in Example 1 except that a 4 μm thick oxide film was formed on the supporting wafer.
<比較例1>
活性層用ウェーハに予備的減肉化処理を施さない以外は実施例1と同様にして貼合せSOIウェーハを得た。
<Comparative Example 1>
A bonded SOI wafer was obtained in the same manner as in Example 1 except that the active layer wafer was not subjected to preliminary thinning treatment.
<比較例2>
活性層用ウェーハに予備的減肉化処理を施さず、活性層用ウェーハ及び支持用ウェーハにそれぞれ厚さ3μmの酸化膜を形成した以外は実施例1と同様にして貼合せSOIウェーハを得た。
<Comparative Example 2>
A bonded SOI wafer was obtained in the same manner as in Example 1 except that the active layer wafer was not subjected to preliminary thinning treatment and an oxide film having a thickness of 3 μm was formed on each of the active layer wafer and the supporting wafer. .
<比較例3>
活性層用ウェーハに予備的減肉化処理を施さず、活性層用ウェーハに厚さ2μmの酸化膜を、支持用ウェーハに厚さ4μmの酸化膜を形成した以外は実施例1と同様にして貼合せSOIウェーハを得た。
<Comparative Example 3>
The same as in Example 1 except that the active layer wafer was not subjected to preliminary thinning treatment, an oxide film having a thickness of 2 μm was formed on the wafer for active layer, and an oxide film having a thickness of 4 μm was formed on the supporting wafer. A bonded SOI wafer was obtained.
<比較例4>
活性層用ウェーハ及び支持用ウェーハにそれぞれ厚さ3μmの酸化膜を形成した以外は実施例1と同様にして貼合せSOIウェーハを得た。
<Comparative example 4>
A bonded SOI wafer was obtained in the same manner as in Example 1 except that an oxide film having a thickness of 3 μm was formed on each of the active layer wafer and the supporting wafer.
<比較例5>
支持用ウェーハとして、厚さが640μm、直径が200mmの鏡面加工されたウェーハを用意し、活性層用ウェーハに予備的減肉化処理を施さず、活性層用ウェーハ及び支持用ウェーハにそれぞれ厚さ3μmの酸化膜を形成した以外は実施例1と同様にして貼合せSOIウェーハを得た。
<Comparative Example 5>
As a support wafer, a mirror-finished wafer having a thickness of 640 μm and a diameter of 200 mm is prepared, and the active layer wafer is not subjected to preliminary thinning treatment, and the active layer wafer and the support wafer are respectively thick. A bonded SOI wafer was obtained in the same manner as in Example 1 except that a 3 μm oxide film was formed.
<比較例6>
支持用ウェーハのみに厚さ6μmの酸化膜を形成した以外は実施例1と同様にして貼合せSOIウェーハを得た。
<Comparative Example 6>
A bonded SOI wafer was obtained in the same manner as in Example 1 except that an oxide film having a thickness of 6 μm was formed only on the supporting wafer.
<比較例7>
活性層用ウェーハのみに厚さ3μmの酸化膜を形成した以外は実施例1と同様にして貼合せSOIウェーハを得た。
<Comparative Example 7>
A bonded SOI wafer was obtained in the same manner as in Example 1 except that an oxide film having a thickness of 3 μm was formed only on the active layer wafer.
<比較例8>
活性層用ウェーハに厚さ2μmの酸化膜を、支持用ウェーハに厚さ1μmの酸化膜を形成した以外は実施例1と同様にして貼合せSOIウェーハを得た。
<Comparative Example 8>
A bonded SOI wafer was obtained in the same manner as in Example 1 except that an oxide film having a thickness of 2 μm was formed on the active layer wafer and an oxide film having a thickness of 1 μm was formed on the supporting wafer.
<比較例9>
支持用ウェーハとして、厚さが640μm、直径が200mmの鏡面加工されたウェーハを用意し、予備的減肉化処理で厚さ調整して活性層用ウェーハ厚さを700μmとし、活性層用ウェーハに厚さ2μmの酸化膜を、支持用ウェーハに厚さ4μmの酸化膜を形成した以外は実施例1と同様にして貼合せSOIウェーハを得た。
<Comparative Example 9>
As a supporting wafer, a mirror-finished wafer having a thickness of 640 μm and a diameter of 200 mm is prepared, and the thickness of the active layer is adjusted to 700 μm by a preliminary thinning process. A bonded SOI wafer was obtained in the same manner as in Example 1 except that an oxide film having a thickness of 2 μm was formed on a supporting wafer and an oxide film having a thickness of 4 μm was formed.
<比較試験及び評価1>
実施例1〜3及び比較例1〜9で貼合せ熱処理を終えた後の重ね合せウェーハを用意し、この重ね合せウェーハをBOX層のところで剥離し、フッ酸洗浄で酸化膜を除去した活性層用ウェーハの貼合せ界面を表面検査装置(SP1)にてスリップ観察した。スリップ発生の有無を次の表1に示した。なお、スリップが発生したものについては、そのスリップ発生長さの合計長さの値を表内に示した。
<Comparison test and evaluation 1>
An active layer in which a laminated wafer after finishing the bonding heat treatment in Examples 1 to 3 and Comparative Examples 1 to 9 was prepared, the laminated wafer was peeled off at the BOX layer, and the oxide film was removed by cleaning with hydrofluoric acid. Slip observation was performed on the bonding interface of the wafers using a surface inspection apparatus (SP1). The presence or absence of slip occurrence is shown in Table 1 below. In addition, about the thing which slip generate | occur | produced, the value of the total length of the slip generation length was shown in the table | surface.
また、図5に比較例1の予備的減肉化処理を施していない活性層用ウェーハの貼合せ界面におけるSP1画像を、図6に実施例1の予備的減肉化処理を施して厚さ640μmにまで加工した活性層用ウェーハの貼合せ界面におけるSP1画像をそれぞれ示す。 5 shows the SP1 image at the bonding interface of the wafer for active layer not subjected to the preliminary thinning process of Comparative Example 1, and FIG. 6 shows the thickness after the preliminary thinning process of Example 1 is applied. SP1 images at the bonding interface of the wafer for active layer processed to 640 μm are shown.
<比較試験及び評価2>
実施例1〜3及び比較例1〜9でそれぞれ得られた貼合せSOIウェーハについて、平坦度測定装置(ADE9500)にて反りを示すwarpを測定した。その結果を次の表1にそれぞれ示す。
<Comparison test and evaluation 2>
For the bonded SOI wafers obtained in Examples 1 to 3 and Comparative Examples 1 to 9, warp indicating warpage was measured by a flatness measuring device (ADE9500). The results are shown in Table 1 below.
また、表1より明らかなように、BOX層厚さと支持用ウェーハ裏面酸化膜厚さとの厚み差が大きくなる比較例2〜5及び7〜9では得られるSOIウェーハに生じる反りが増大していた。更に、一方のウェーハにしか酸化膜が形成されていない比較例6及び7でも貼合せ界面にスリップが発生していた。一方、実施例1〜3では、貼合せ界面にスリップがなく、得られるSOIウェーハに生じる反りも100μm以下と低減されていた。 Further, as apparent from Table 1, in Comparative Examples 2 to 5 and 7 to 9 in which the thickness difference between the BOX layer thickness and the supporting wafer backside oxide film thickness is large, the warpage generated in the obtained SOI wafer was increased. . Furthermore, even in Comparative Examples 6 and 7 in which an oxide film was formed only on one wafer, slip occurred at the bonding interface. On the other hand, in Examples 1 to 3, there was no slip at the bonding interface, and the warpage generated in the obtained SOI wafer was reduced to 100 μm or less.
なお、各実施例及び各比較例とも、貼合せ熱処理後の活性層用ウェーハ側を減肉化処理(平面研削)して所定厚みのSOI層を形成した後に、テラス研磨を施した例を例示したが、貼合せ熱処理後の活性層用ウェーハにテラス研磨を施した後に、活性層用ウェーハ側を減肉化処理(平面研削)して所定厚みのSOI層を形成するようにしてもよい。 In each example and each comparative example, the active layer wafer side after the bonding heat treatment is thinned (surface grinding) to form an SOI layer having a predetermined thickness, and then terrace polishing is performed. However, after the active layer wafer subjected to the bonding heat treatment is subjected to terrace polishing, the active layer wafer side may be subjected to thinning treatment (surface grinding) to form an SOI layer having a predetermined thickness.
11 活性層用ウェーハ
11a 厚み調整した活性層用ウェーハ
11b 酸化膜
12 支持用ウェーハ
12a 酸化膜
13 重ね合せウェーハ
14 熱処理後の重ね合せウェーハ
15 埋込み酸化膜層
16 SOI層
17 SOIウェーハ
DESCRIPTION OF SYMBOLS 11 Active layer wafer 11a Thickness-adjusted active layer wafer 11b Oxide film 12 Support wafer 12a Oxide film 13 Overlapping wafer 14 Overlapped wafer after heat treatment 15 Embedded oxide film layer 16 SOI layer 17 SOI wafer
Claims (6)
前記支持用ウェーハの裏面に形成された酸化膜の厚さが0.45〜6μmの範囲内にあって、前記埋込み酸化膜層の厚さと前記支持用ウェーハ裏面酸化膜の厚さとの厚み差が1μm以下であり、前記SOI層にスリップ転位が存在しない貼合せSOIウェーハ。 In a bonded SOI wafer in which an SOI layer is formed on a supporting wafer via a buried oxide film layer,
The thickness of the oxide film formed on the back surface of the supporting wafer is in the range of 0.45 to 6 μm, and the thickness difference between the thickness of the buried oxide layer and the thickness of the back surface oxide film of the supporting wafer is A bonded SOI wafer having a thickness of 1 μm or less and having no slip dislocation in the SOI layer.
前記貼合せ熱処理前において、前記活性層用ウェーハの厚さが前記支持用ウェーハの厚さより小さく、かつ前記活性層用ウェーハの全面に形成する酸化膜の厚さが前記支持用ウェーハの全面に形成する酸化膜の厚さより小さい
ことを特徴とする貼合せSOIウェーハの製造方法。 An oxide film is formed on the entire surface of the active layer wafer, an oxide film is formed on the entire surface of the support wafer for supporting the wafer, and the active layer wafer is stacked on the support wafer via the oxide film. Then, the two laminated wafers are heat-treated and bonded to each other so that an oxide film interposed between the two laminated wafers is embedded to form an oxide film layer, and then the active layer wafer is thinned. A method of manufacturing a bonded SOI wafer in which an SOI layer is formed on the supporting wafer via the buried oxide film layer by performing a treatment,
Before the bonding heat treatment, the thickness of the active layer wafer is smaller than the thickness of the supporting wafer, and the thickness of the oxide film formed on the entire surface of the active layer wafer is formed on the entire surface of the supporting wafer. A method for producing a bonded SOI wafer, wherein the thickness is smaller than a thickness of an oxide film to be bonded.
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2013175705A1 (en) * | 2012-05-24 | 2013-11-28 | 信越半導体株式会社 | Method for manufacturing soi wafer |
WO2014034019A1 (en) * | 2012-09-03 | 2014-03-06 | 信越半導体株式会社 | Soi wafer manufacturing method |
JP2015050210A (en) * | 2013-08-30 | 2015-03-16 | 株式会社Sumco | Manufacturing method of soi wafer |
FR3024280A1 (en) * | 2014-07-25 | 2016-01-29 | Soitec Silicon On Insulator | METHOD FOR DETACHING A USEFUL LAYER |
FR3076393A1 (en) * | 2017-12-28 | 2019-07-05 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | METHOD OF TRANSFERRING A USEFUL LAYER |
CN115799273A (en) * | 2022-12-21 | 2023-03-14 | 中环领先半导体材料有限公司 | Silicon wafer on insulator, preparation method and semiconductor device |
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05109678A (en) * | 1991-10-18 | 1993-04-30 | Sony Corp | Manufacture of soi substrate |
JPH098124A (en) * | 1995-06-15 | 1997-01-10 | Nippondenso Co Ltd | Insulation separation substrate and its manufacture |
JP2001094079A (en) * | 1999-09-20 | 2001-04-06 | Komatsu Electronic Metals Co Ltd | Method for manufacturing bonding soi wafer |
JP2001093788A (en) * | 1999-09-21 | 2001-04-06 | Komatsu Electronic Metals Co Ltd | Method for manufacturing bonded soi wafer |
JP2008244019A (en) * | 2007-03-26 | 2008-10-09 | Shin Etsu Handotai Co Ltd | Manufacturing method of SOI wafer |
-
2009
- 2009-09-24 JP JP2009219039A patent/JP2011071193A/en active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05109678A (en) * | 1991-10-18 | 1993-04-30 | Sony Corp | Manufacture of soi substrate |
JPH098124A (en) * | 1995-06-15 | 1997-01-10 | Nippondenso Co Ltd | Insulation separation substrate and its manufacture |
JP2001094079A (en) * | 1999-09-20 | 2001-04-06 | Komatsu Electronic Metals Co Ltd | Method for manufacturing bonding soi wafer |
JP2001093788A (en) * | 1999-09-21 | 2001-04-06 | Komatsu Electronic Metals Co Ltd | Method for manufacturing bonded soi wafer |
JP2008244019A (en) * | 2007-03-26 | 2008-10-09 | Shin Etsu Handotai Co Ltd | Manufacturing method of SOI wafer |
Cited By (16)
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---|---|---|---|---|
US9029240B2 (en) | 2012-05-24 | 2015-05-12 | Shin-Etsu Handotai Co., Ltd. | Method for manufacturing SOI wafer |
JP2013247204A (en) * | 2012-05-24 | 2013-12-09 | Shin Etsu Handotai Co Ltd | Soi wafer manufacturing method |
KR101914755B1 (en) | 2012-05-24 | 2018-11-05 | 신에쯔 한도타이 가부시키가이샤 | Method for manufacturing soi wafer |
WO2013175705A1 (en) * | 2012-05-24 | 2013-11-28 | 信越半導体株式会社 | Method for manufacturing soi wafer |
CN104364880A (en) * | 2012-05-24 | 2015-02-18 | 信越半导体股份有限公司 | Method for manufacturing SOI wafer |
US9673085B2 (en) | 2012-09-03 | 2017-06-06 | Shin-Etsu Handotai Co., Ltd. | Method for manufacturing SOI wafer |
JP2014049699A (en) * | 2012-09-03 | 2014-03-17 | Shin Etsu Handotai Co Ltd | Soi wafer manufacturing method |
WO2014034019A1 (en) * | 2012-09-03 | 2014-03-06 | 信越半導体株式会社 | Soi wafer manufacturing method |
JP2015050210A (en) * | 2013-08-30 | 2015-03-16 | 株式会社Sumco | Manufacturing method of soi wafer |
FR3024280A1 (en) * | 2014-07-25 | 2016-01-29 | Soitec Silicon On Insulator | METHOD FOR DETACHING A USEFUL LAYER |
FR3076393A1 (en) * | 2017-12-28 | 2019-07-05 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | METHOD OF TRANSFERRING A USEFUL LAYER |
US11738993B2 (en) | 2019-01-16 | 2023-08-29 | Murata Manufacturing Co., Ltd. | Silicon substrate having cavity and cavity SOI substrate including the silicon substrate |
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CN115799273B (en) * | 2022-12-21 | 2024-02-09 | 中环领先半导体科技股份有限公司 | Silicon-on-insulator wafer, preparation method and semiconductor device |
JP2025504365A (en) * | 2022-12-21 | 2025-02-12 | 中▲環▼▲領▼先半▲導▼体科技股▲分▼有限公司 | Silicon-on-insulator wafer and its manufacturing method, and semiconductor device |
JP7678942B2 (en) | 2022-12-21 | 2025-05-16 | 中▲環▼▲領▼先半▲導▼体科技股▲分▼有限公司 | Silicon-on-insulator wafer and its manufacturing method, and semiconductor device |
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