JP2011061520A - Mos type image sensor, method of driving the same, and imaging apparatus - Google Patents

Abstract

Reset noise can be accurately removed even with an incomplete transfer type image sensor.
An image sensor 100 includes a storage diode SD formed in a semiconductor substrate 1, a transistor RSTr for resetting the potential of SD, and gate electrodes WCG and WCG electrically connected to SD. The pixel portion 21 includes a transistor WT including a floating gate FG for storing charge injected from the substrate 1 and a transistor RT whose threshold voltage changes according to the charge stored in the FG, and resets the SD potential. After the reset, the electric charge corresponding to the SD potential is injected into the FG, and then the first signal corresponding to the RT threshold voltage is read and held, and then the exposure started after the reset is completed. A charge corresponding to the SD potential is injected into the FG, and then the drive control circuit 4 for reading out the second signal corresponding to the RT threshold voltage, and the first signal When and a differential circuit 8 for outputting a difference of the second signal.
[Selection] Figure 3

Description

  The present invention relates to a MOS image sensor, a method for driving a MOS image sensor, and an imaging apparatus.

  A three-transistor CMOS image sensor and a laminated image sensor in which an inorganic or organic photoelectric conversion layer is stacked on a substrate, and charges generated in the photoelectric conversion layer are stored in a storage diode provided in the substrate Then, at the start of exposure, it is necessary to reset unnecessary charges stored in the photodiode or storage diode to a reset voltage using a switch of a MOS transistor. When the charge accumulated in the capacitor is reset by the switch of the MOS transistor, the thermal noise of the switch is held in the capacitor as it is when the switch is turned off. Noise generated and held by this reset is referred to as reset noise or kTC noise.

  As a method of removing this reset noise, after resetting the floating diffusion, the reset noise corresponding to the potential of the floating diffusion is read, and after the exposure is completed, the charge is completely transferred from the fully depleted embedded photodiode to the floating diffusion, A CDS (double correlation sampling) method is known in which a signal corresponding to the potential of the floating diffusion after the transfer is read and reset noise is subtracted from this signal (see Non-Patent Document 1).

  However, when the photodiode is not a buried type, the reset noise cannot be completely transferred from the photodiode to the floating diffusion, and a transfer residue occurs, so that the reset noise cannot be removed completely. In particular, in a stacked image sensor, it is necessary to electrically connect a storage diode provided in a substrate and one of a pair of electrodes sandwiching a photoelectric conversion layer with a conductor, and the storage diode is completely embedded in a silicon substrate. Cannot be depleted. For this reason, the laminated image sensor becomes an incomplete transfer type image sensor.

  As described above, the incomplete transfer type image sensor cannot remove the reset noise (kTC noise) even if the CDS processing is performed, and is inferior in noise performance as compared with the complete transfer type image sensor using the embedded photodiode. It was.

Kazuya Yonemoto, “Basics and Applications of CCD / CMOS Image Sensors”, CQ Publisher, 186p-191p, 250p-253p (Removal of KTC noise)

  The present invention has been made in view of the above circumstances, and an object thereof is to make it possible to accurately remove reset noise even in an incomplete transfer type image sensor.

  The MOS type image sensor of the present invention is a MOS type image sensor having a plurality of pixel units, and the pixel unit is formed in a semiconductor substrate and stores a charge generated according to incident light; and A reset transistor for resetting a potential of the charge storage unit; a gate electrode electrically connected to the charge storage unit; and a floating gate for storing charge injected from the semiconductor substrate in accordance with the potential of the gate electrode A write transistor; and a read transistor having a floating gate electrically connected to the floating gate and having a threshold voltage that changes according to the charge accumulated in the floating gate, and turning on the reset transistor to turn the charge on The potential of the storage unit is reset, and the charge storage unit after the reset is completed. The charge corresponding to the position is injected into the floating gate of the write transistor, and then the first signal corresponding to the threshold voltage of the read transistor is read and held, and then the exposure started after the reset is completed. A control unit that injects a charge corresponding to the potential of the charge storage unit after being injected into the floating gate of the write transistor, and then reads a second signal corresponding to a threshold voltage of the read transistor; And a signal output unit that outputs a difference between the signal and the second signal as an imaging signal.

  The MOS image sensor driving method according to the present invention is a MOS image sensor driving method having a plurality of pixel portions, and the pixel portions are formed in a semiconductor substrate and accumulate charges generated according to incident light. A charge storage unit that performs electrical storage, a gate electrode that is electrically connected to the charge storage unit, a write transistor that includes a floating gate that stores charges injected from the semiconductor substrate in accordance with a potential of the gate electrode, and the floating gate And a readout transistor that has a floating gate electrically connected to the threshold voltage and changes in accordance with the charge accumulated in the floating gate, resets the potential of the charge accumulation portion, and Charge corresponding to the potential of the charge storage portion is injected into the floating gate of the write transistor. Thereafter, the first signal corresponding to the threshold voltage of the readout transistor is read out and held, and then the electric charge corresponding to the electric potential of the electric charge storage unit after the exposure started after the end of the reset is completed. Injecting into the floating gate of the writing transistor and then reading out a second signal corresponding to the threshold voltage of the reading transistor; and outputting a difference between the first signal and the second signal as an imaging signal With.

  The imaging device of the present invention includes the MOS image sensor.

  According to the present invention, reset noise can be accurately removed even with an incomplete transfer type image sensor.

The figure which shows schematic structure of the MOS type image sensor for describing one Embodiment of this invention The figure which shows schematic structure of the pixel array in the MOS type image sensor shown in FIG. The figure which shows schematic structure of the signal part in the pixel part in the pixel array shown in FIG. 2, and the MOS type image sensor shown in FIG. The figure which shows the cross-section of the pixel part in the pixel array shown in FIG. The flowchart for demonstrating the operation | movement at the time of imaging of the MOS type image sensor shown in FIG.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram showing a schematic configuration of a MOS type image sensor for explaining an embodiment of the present invention. The MOS image sensor 100 is used for an imaging device such as a digital camera and a digital video camera, an imaging module mounted on an electronic endoscope, a mobile phone with a camera, and the like.

  A MOS image sensor 100 shown in FIG. 1 includes a pixel array 2, a vertical drive scanning circuit 3, a drive control circuit 4, a column signal processing circuit 5, a signal line 6, a horizontal drive scanning circuit 7 formed on a semiconductor substrate 1, and A difference circuit 8 is provided.

  Although described in detail later, the pixel array 2 includes a plurality of pixel portions arranged in a two-dimensional manner. In the example to be described later, the plurality of pixel units are arranged by arranging a plurality of pixel unit rows composed of a plurality of pixel units arranged in the row direction in the vertical direction orthogonal to the row direction, or a plurality of pixel units arranged in the column direction. A plurality of pixel portion columns are arranged in the row direction.

  The vertical drive scanning circuit 3 drives a plurality of pixel units included in the pixel array 2, and can select and drive a plurality of pixel unit rows one by one.

  The drive control circuit 4 comprehensively controls the vertical drive scanning circuit 3, the column signal processing circuit 5, the horizontal drive scanning circuit 7, and the difference circuit 8.

  The column signal processing circuit 5 includes a readout circuit provided corresponding to each of the plurality of pixel unit columns. Details of the column signal processing circuit 5 will be described later.

  The horizontal drive scanning circuit 7 includes a switch connected to each of a plurality of readout circuits included in the column signal processing circuit 5 and a control circuit that controls on / off of the switch. When this switch is turned on, a signal read by the reading circuit is output to the signal line 6.

  The difference circuit 8 calculates a difference between two signals input via the signal line 6 and outputs the difference as an imaging signal to the outside of the MOS image sensor 100.

  FIG. 2 is a schematic plan view showing a schematic configuration of the pixel array shown in FIG. As shown in FIG. 2, the pixel array 2 includes a plurality of pixel portions 21 (denoted as pixels in the drawing), a capacitor 22, a read control line RL, a write control line WL, a reset control line RST, and a reset power source. A line Vrst and a signal line BL are included. As described above, the plurality of pixel portions 21 are arranged two-dimensionally (in the example of FIG. 2 in the form of a square lattice) in the row direction X and the column direction Y on the semiconductor substrate 1. The capacitor 22 is provided corresponding to each pixel unit column.

  The pixel unit 21 receives light and generates a charge corresponding to the amount of light received, and outputs a signal corresponding to the generated charge.

  One read control line RL, one write control line WL, one reset control line RST, and one reset power supply line Vrst are provided for one pixel portion row. The read control line RL, the write control line WL, and the reset control line RST are respectively connected to each pixel unit 21 and the vertical drive scanning circuit 3 in the corresponding pixel unit row. The reset power line Vrst is connected to each pixel unit 21 in the corresponding pixel unit row and a power source (not shown).

  One signal line BL is provided for one pixel portion column. The signal line BL is connected to each pixel unit 21 of the corresponding pixel unit column, a capacitor 22 corresponding to the pixel unit column, and a readout circuit in the column signal processing circuit 5 corresponding to the pixel unit column. Yes.

  FIG. 3 is a diagram showing an internal configuration of the pixel unit 21 shown in FIG. 2, the column signal processing circuit 5 and the vertical drive scanning circuit 3 shown in FIG. The pixel unit 21 includes a storage diode SD, a pixel electrode 221, a photoelectric conversion layer 222, a counter electrode 223, a reset transistor RSTr, a write transistor WT, and a read transistor RT.

  The pixel electrode 221 is an electrode provided above the semiconductor substrate 1 and is separated for each pixel portion 21. The photoelectric conversion layer 222 is formed on the pixel electrode 221 and includes at least a layer including an organic or inorganic photoelectric conversion material that generates charges in response to received light. The photoelectric conversion layer 222 has a single configuration common to all the pixel units 21. The counter electrode 223 is a transparent electrode formed on the photoelectric conversion layer 222. The counter electrode 223 has a single configuration common to all the pixel portions 21. The photoelectric conversion layer 222 and the counter electrode 223 may be separated for each pixel portion 21.

  The storage diode SD stores charges (electrons or holes) generated in the photoelectric conversion layer 222, and is composed of an n-type impurity layer or a p-type impurity layer formed in the semiconductor substrate 1, and the pixel electrode 221. And are electrically connected. A bias voltage can be applied to the counter electrode 223, and an electric field can be applied between the pixel electrode 221 and the counter electrode 223 by the bias voltage. By this electric field, one of the charge pairs generated in the photoelectric conversion layer 222 moves to the pixel electrode 221 and the other moves to the counter electrode 223.

  Note that the counter electrode 223 may be electrically connected to the storage diode SD instead of the pixel electrode 221. In this case, the counter electrode 223 may be separated for each pixel portion 21 so that a bias voltage can be applied to the pixel electrode 221.

  The reset transistor RSTr discharges the charge accumulated in the storage diode SD and resets the potential of the storage diode SD to a predetermined potential. A reset control line RST is connected to the gate electrode RG of the reset transistor RSTr. A reset power supply line Vrst is connected to the drain region of the reset transistor RSTr. When holes are accumulated in the storage diode SD, the voltage of the reset control line RST when the reset transistor RSTr is on becomes low level (ground 0 V), and the potential of the storage diode SD rises after the reset is completed. When electrons are stored in the storage diode SD, the voltage of the reset control line RST when the reset transistor RSTr is turned on is at a high level (plus several volts), and the potential of the storage diode SD drops after the reset ends.

  The write transistor WT includes a write control gate WCG that is a gate electrode electrically connected to the storage diode SD, and a floating gate FG that accumulates charges injected from the semiconductor substrate 1 in accordance with the potential of the write control gate WCG. It is a MOS transistor having. A write control line WL is connected to the drain region of the write control gate WCG.

  The read transistor RT is a MOS transistor having a floating gate FG electrically connected to the floating gate FG of the write transistor WT and a read control gate RCG that is a gate electrode connected to the read control line RL. The source region of the read transistor RT is shared with the source region of the write transistor WT. The floating gate FG of the read transistor RT may be integrated with the floating gate FG of the write transistor WT, or two floating gates may be connected by wiring separately from the floating gate FG of the write transistor WT. May be. The drain region of the read transistor RT is connected to the signal line BL.

  The column signal processing circuit 5 includes a readout circuit 50, a readout control unit 51, a DA converter 52, a counter 53, and a precharge circuit 54 provided for each pixel unit column.

  The read circuit 50 includes transistors 55 and 56, a sense amplifier 57, and latch circuits 58a and 58b.

  The transistor 55 is provided between the signal line BL and the sense amplifier 57 and controls connection between the signal line BL and the sense amplifier 57. The transistor 56 is provided between the signal line BL and the precharge circuit 54, and controls supply of the voltage supplied from the precharge circuit 54 to the signal line BL.

  The sense amplifier 57 monitors the voltage of the signal line BL and outputs a detection signal to the latch circuit 58a or the latch circuit 58b when the voltage changes. For example, the sense amplifier output is inverted by detecting that the voltage of the signal line BL has dropped.

  The latch circuits 58a and 58b hold the count value of the counter 53 when the detection signal is input.

  The counter 53 is an N-bit counter (for example, N = 8 to 12), and resets the count value to the initial value according to an instruction from the drive control circuit 4 to start counting. The DA converter 52 converts the count value of the counter 53 (a combination of N 1s and 0s) into an analog signal, and supplies a ramp waveform voltage that gradually increases or decreases to the readout control line RL of each pixel unit row by using the switch 3a. Supply through.

  The read control unit 51 controls on / off of the transistors 55 and 56. The readout control unit 51 also performs on / off control of the switch 3a, and performs control to supply a ramp waveform voltage to the readout control line RL of an arbitrary pixel unit row.

  The precharge circuit 54 supplies a predetermined voltage to the signal line BL and precharges the capacitor 22 connected to the signal line BL.

  When the voltage of the read control gate RCG exceeds the threshold voltage of the read transistor RT while the capacitor 22 is precharged, the read transistor RT becomes conductive, and at this time, the potential of the precharged signal line BL drops. This is detected by the sense amplifier 57 and an inverted signal is output. The latch circuit 58a or the latch circuit 58b holds (latches) a count value corresponding to the value of the ramp waveform voltage when the inverted signal is received. Accordingly, a signal corresponding to the threshold voltage of the read transistor RT can be read and held as a digital value (combination of 1 and 0).

  FIG. 4 is a schematic cross-sectional view showing an example of a cross-sectional structure of the pixel unit 21 shown in FIG. In FIG. 4, the semiconductor substrate 1 is a p-type silicon substrate, and the storage diode SD is composed of an n-type impurity layer. The reset transistor RSTr, the write transistor WT, and the read transistor RT are each an n-channel transistor.

  On the p-type silicon substrate 1, n-type impurity layers 211, 212, 213, and 214, a storage diode SD, and an element isolation layer 215 are formed.

  The storage diode SD is formed of an n-type impurity layer formed in the p-type silicon substrate 1. The n-type impurity layer 211 is formed slightly to the left of the storage diode SD and functions as the drain of the reset transistor RSTr. The n-type impurity layer 212 is formed on the right side of the storage diode SD with the element isolation region 215 interposed therebetween, and functions as the drain of the write transistor WT. The n-type impurity layer 213 is provided to the right of the n-type impurity layer 212 and functions as the source of the write transistor WT and the read transistor RT. The n-type impurity layer 214 is provided to the right of the n-type impurity layer 213 and functions as the drain of the read transistor RT.

  On the p-type silicon substrate 1 between the n-type impurity layer 211 and the storage diode SD, a gate electrode RG of the reset transistor RSTr is formed via an insulating film 219. A floating gate FG is formed on the p-type silicon substrate 1 between the n-type impurity layer 212 and the n-type impurity layer 214 via an insulating film 219.

  On the floating gate FG located between the n-type impurity layer 212 and the n-type impurity layer 213, the write control gate WCG of the write transistor WT is formed via the insulating film 220. On the floating gate FG located between the n-type impurity layer 213 and the n-type impurity layer 214, the read control gate RCG of the read transistor RT is formed via the insulating film 220.

  Above the p-type silicon substrate 1, a pixel electrode 221, a photoelectric conversion layer 222, and a counter electrode 223 are stacked in this order, and the storage diode SD and the pixel electrode 221 are electrically connected.

  In the structure example shown in FIG. 4, a method of storing electrons in the storage diode SD and injecting electrons into the floating gate FG from the n-type impurity layer 212 which is a drain region according to the potential of the storage diode SD, and the storage diode SD Any of a method in which holes are accumulated in the semiconductor layer and electrons are injected into the floating gate FG from the n-type impurity layer 212 which is a drain region in accordance with the potential of the storage diode SD can be employed.

  In the structure example shown in FIG. 4, the p-type silicon substrate 1 is an n-type silicon substrate, and the n-type impurity layers 211, 212, 213, and 214 and the storage diode SD are respectively p-type impurity layers. Also good. In this configuration, electrons are stored in the storage diode SD, holes are injected into the floating gate FG from the p-type impurity layer 212 as the drain region according to the potential of the storage diode SD, and holes are stored in the storage diode SD. And a method of injecting holes from the p-type impurity layer 212 which is a drain region into the floating gate FG in accordance with the potential of the storage diode SD can be employed.

  Note that the write transistor WT includes hot electrons generated by FN tunneling electron injection, channel hot electron injection, or band-to-band tunneling as disclosed in Japanese Patent Laid-Open No. 9-8153 and US Pat. No. 5,687,118. The voltage supplied to each of the drain region 212, the source region 213, and the p-type silicon substrate 1 may be determined so that can be injected into the floating gate FG.

  Next, an operation of injecting electrons into the floating gate FG in the structural example shown in FIG. 4, a read operation of a signal corresponding to the electrons injected into the floating gate FG (a signal corresponding to the threshold voltage of the read transistor RT), A specific example of the electron erasing operation of the floating gate FG will be described.

1) Write to FG Electrons are injected from the drain region 212 into the floating gate FG according to the potential of the write control gate WCG connected to the storage diode SD, and the threshold voltage of the write transistor WT is set according to the amount of injected electrons. In order to change the voltage, the voltage of the write control line WL connected to the drain region 212 of the write transistor WT is set to H (plus several volts). However, the signal line BL connected to the drain region 214 of the read transistor RT is 0 volts.

2) Reading from FG A positive ramp signal whose voltage gradually increases is input to the read control line RL connected to the read control gate RCG as the threshold voltage of the read transistor RT changed by the electrons injected into the floating gate FG. This is detected by the voltage value of the read control gate RCG when the drain signal starts to flow from the signal line BL connected to the drain region 214 of the read transistor RT.

3) Charge erase in FG By setting the voltage of the write control line WL and the voltage of the read control line RL to −H (minus several volts), the electrons in the floating gate FG are swept out to the p-type silicon substrate 1.

  The following table summarizes the above operations. In the case where the silicon substrate 1 is n-type, the reset transistor RSTr, the write transistor WT, and the read transistor RT are p-channel transistors and the storage diode SD is a p-type impurity layer to store electrons, The polarity of each voltage may be reversed.

  Next, the operation of the MOS image sensor 100 configured as described above will be described. In the following, the operation when the pixel portion 21 of the MOS image sensor 100 has the structure shown in FIG. 4 and the method of storing holes in the storage diode SD and injecting electrons into the floating gate FG is adopted. explain.

  The following description is an operation when the MOS image sensor 100 is driven by a so-called rolling shutter system in which exposure and signal readout are sequentially performed in units of pixel units. Focusing on the nth pixel portion row, the imaging operation will be described with reference to FIG. FIG. 5 is a timing chart for explaining the operation of the MOS type image sensor shown in FIG. 1 in the rolling shutter mode.

  When the reading of the exposure signal of the previous frame is completed in the nth pixel portion row, the vertical drive scanning circuit 3 sets the voltage of the write control line WL and the voltage of the read control line RL in the nth pixel portion row. From the middle level (floating state) to the low level (minus several volts). Thereby, the electrons accumulated in the floating gate FG are swept out to the semiconductor substrate 1, and the electrons in the floating gate FG are erased.

  Next, the vertical drive scanning circuit 3 changes the voltage of the reset control line RST in the nth pixel portion row from a low level to a high level. As a result, the reset transistor RSTr is turned on, and the potential of the storage diode SD is reset to a predetermined reset voltage. This reset voltage is, for example, ground (0 V).

  Next, the vertical drive scanning circuit 3 returns the voltage of the reset control line RST in the nth pixel portion row from the high level to the low level, and turns off the reset transistor RSTr. When the reset transistor RSTr is turned off, exposure of each pixel unit 21 in the nth pixel unit row is started.

  Immediately after turning off the reset transistor RSTr, the vertical drive scanning circuit 3 changes the voltage of the write control line WL in the nth pixel portion row from the middle level to the high level (plus several volts). Thereby, electrons are injected from the drain region 212 to the floating gate FG according to the potential of the storage diode SD immediately after the reset transistor RSTr is turned off. At this time, electrons corresponding to the reset noise (kTC noise) generated by the reset operation of the reset transistor RSTr are superimposed on the electrons injected into the floating gate FG.

  Next, the read control circuit 51 turns on the switch 3a in the n-th pixel portion row, turns on the transistors 55 and 56, and makes the signal line BL and the sense amplifier 57 conductive, and the potential of the signal line BL. Is precharged (plus a few volts). At the same time as the switch 3a is turned on, the drive control circuit 4 resets the count value of the counter 53 and starts counting. As a result, the supply of the ramp waveform voltage to the read control gate RCG of each pixel portion 21 in the nth pixel portion row is started.

  As soon as the ramp waveform voltage exceeds a certain value, the drain signal of the read transistor RT flows, the charge accumulated in the capacitor 22 of the signal line BL is discharged, and the potential of the signal line BL returns to a low level (approximately zero volts). The digital count value at that time is latched (held) in the latch circuit 58a. The latch value at this time becomes a signal (hereinafter referred to as reset noise signal) proportional to the holes (hereinafter also referred to as reset noise charge) present in the storage diode SD immediately after the reset transistor RSTr is reset. When the reset noise signal is read out from each pixel unit 21 in the nth pixel unit row and latched in the latch circuit 58a, the readout control circuit 51 switches the transistors 55 and 56 and the switch in the nth pixel unit row. Turn off 3a.

  Next, the vertical drive scanning circuit 3 changes the voltage of the write control line WL in the nth pixel portion row from the middle level to the high level. Thereby, electrons are injected from the drain region 212 to the floating gate FG according to the potential of the storage diode SD due to the holes stored in the storage diode SD during the exposure period. Note that since light is incident on the photoelectric conversion layer 222 even during the period in which the voltage of the write control line WL is at a high level, the charge generated in the photoelectric conversion layer 222 during this period is also accumulated in the storage diode SD. The potential of the storage diode SD changes slightly.

  Next, the vertical drive scanning circuit 3 returns the voltage of the write control line WL to the low level. As a result, the exposure period of the nth pixel portion row ends. When the voltage of the write control line WL is returned to the low level, the floating gate FG is injected with an amount of electrons corresponding to the amount of holes accumulated in the storage diode SD during the exposure period.

  Next, the read control circuit 51 turns on the switch 3a in the n-th pixel portion row, turns on the transistors 55 and 56, and makes the signal line BL and the sense amplifier 57 conductive, and the potential of the signal line BL. Is precharged. At the same time as the switch 3a is turned on, the drive control circuit 4 resets the count value of the counter 53 and starts counting. As a result, the supply of the ramp waveform voltage to the read control gate RCG of each pixel portion 21 in the nth pixel portion row is started.

  As soon as the ramp waveform voltage exceeds a certain value, the drain signal of the read transistor RT flows, the charge accumulated in the capacitor 22 of the signal line BL is discharged, and the potential of the signal line BL returns to the low level. The digital count value at that time is latched (held) in the latch circuit 58b. The latch value at this time becomes a signal (hereinafter referred to as an exposure signal) proportional to the holes (hereinafter also referred to as exposure charge) accumulated in the storage diode SD during the exposure period.

  When an exposure signal is read out from each pixel unit 21 in the nth pixel unit row and latched in the latch circuit 58b, the readout control circuit 51 includes the transistors 55 and 56 and the switch 3a in the nth pixel unit row. Turn off.

  Next, when the latch circuits 58a and 58b corresponding to one pixel unit column are selected by the control of the horizontal drive scanning circuit 7, the reset noise signal and the exposure signal are read to the signal line 6 from the latch circuits 58a and 58b. Are respectively input to the difference circuit 8. The difference circuit 8 subtracts the reset noise signal from the input exposure signal and outputs an imaging signal without reset noise.

  As described above, according to the MOS image sensor 100, the reset noise signal corresponding to the amount of the reset noise charge is read and held without physically transferring the reset noise charge existing in the storage diode SD after the reset. can do. Further, an exposure signal corresponding to the amount of the exposure charge can be read without physically transferring the exposure charge existing in the storage diode SD after the exposure is completed. Since the exposure signal includes a reset noise signal, an imaging signal from which the reset noise is completely removed can be obtained by obtaining a difference between the exposure signal and the reset noise signal. According to this configuration, it is not necessary to transfer the charge stored in the storage diode SD to another location, so that reset noise can be accurately removed even with an incomplete transfer type image sensor.

  Since the MOS image sensor 100 needs to electrically connect the pixel electrode 221 and the storage diode SD in the semiconductor substrate 1, a structure in which the storage diode SD is embedded in the semiconductor substrate 1 cannot be employed. For this reason, the charge cannot be completely transferred from the storage diode SD to another location, and the reset noise cannot be removed by the conventional method. According to the MOS type image sensor 100, since the signal can be read without transferring the charge of the storage diode SD to another location, the reset noise can be completely removed even if the storage diode SD is not embedded. it can. As described above, it is particularly effective in the stacked image sensor to connect the storage diode SD and the write control gate WCG and adopt a method of writing charges to the floating gate FG according to the potential of the storage diode SD.

  Further, according to the MOS type image sensor 100, since the charge corresponding to the reset noise charge and the charge corresponding to the exposure charge are accumulated in the same floating gate FG, there is a manufacturing variation in the threshold voltage of the read transistor RT. Even in this case, the effect of this variation can be eliminated.

  In addition, since the floating gate FG does not change the stored information due to the difference in the information holding period and the temperature change, when imaging is performed with a constant light amount, the pixel unit row read out first and the pixel read out later A level difference does not occur in the image pickup signal between the pixel portion rows, and it is possible to prevent deterioration of the captured image such as shading.

  In addition, when the method of storing electrons in the storage diode SD and injecting electrons into the floating gate FG according to the potential of the storage diode SD is adopted, the potential of the storage diode SD is the highest after reset, After that, the direction changes. In this case, since a large amount of electrons are injected into the floating gate FG when the charge corresponding to the reset noise charge is written in the floating gate FG, the electrons in the floating gate FG are not erased after that. The charge corresponding to the exposure charge cannot be written to the floating gate FG. Therefore, in the timing chart shown in FIG. 5, it is necessary to drive to erase the charge in the floating gate FG between the time when the reset noise signal is read and the time when the charge corresponding to the exposure charge is written.

  On the other hand, in a case where holes are accumulated in the storage diode SD and electrons are injected into the floating gate FG according to the potential of the storage diode SD, the potential of the storage diode SD is lowest after reset. Then, change in the direction of rising. Therefore, it is possible to continuously write the charge corresponding to the reset noise charge and the charge corresponding to the exposure charge to the floating gate FG without erasing the charge in the floating gate FG. As a result, it is possible to reduce the power and time required for erasing the floating gate FG. Such an effect can be obtained in the same manner even when a method of storing electrons in the storage diode SD and injecting holes into the floating gate FG according to the potential of the storage diode SD is adopted.

  Heretofore, the case where the MOS type image sensor 100 is a laminated type has been described as an example, but the MOS type image sensor 100 may not be a laminated type. For example, in the pixel section cross-sectional structure shown in FIG. 4, the pixel electrode 221, the photoelectric conversion layer 222, and the counter electrode 223 are deleted, the storage diode SD is a PN junction photodiode, and this PN junction photodiode is used as the write control gate WCG. And may be configured to be electrically connected to each other. In this case as well, an incomplete transfer type image sensor is obtained, but the reset noise can be accurately removed because the charge of the photodiode is not transferred to another location.

  As described above, the following items are disclosed in this specification.

  The disclosed MOS type image sensor is a MOS type image sensor having a plurality of pixel units, and the pixel units are formed in a semiconductor substrate and store a charge generated according to incident light; and A reset transistor for resetting a potential of the charge storage unit; a gate electrode electrically connected to the charge storage unit; and a floating gate for storing charge injected from the semiconductor substrate in accordance with the potential of the gate electrode A write transistor; and a read transistor having a floating gate electrically connected to the floating gate and having a threshold voltage that changes according to the charge accumulated in the floating gate, and turning on the reset transistor to turn the charge on Reset the potential of the storage unit, and the charge storage unit after the reset Charge corresponding to the potential is injected into the floating gate of the write transistor, and then the first signal corresponding to the threshold voltage of the read transistor is read and held, and then the exposure started after the reset is completed. A control unit that injects a charge corresponding to the potential of the charge storage unit after being injected into the floating gate of the write transistor, and then reads a second signal corresponding to a threshold voltage of the read transistor; And a signal output unit that outputs a difference between the signal and the second signal as an imaging signal.

  With this configuration, it is possible to read and hold the first signal corresponding to the amount of the reset noise charge without physically transferring the reset noise charge present in the charge storage unit after reset. Further, the second signal corresponding to the amount of the charge can be read out without physically transferring the charge existing in the charge storage portion after the exposure is completed. Since the second signal also includes the first signal corresponding to the reset noise charge, the reset noise can be completely removed by obtaining the difference between the first signal and the second signal. it can. According to this configuration, it is not necessary to transfer the charge accumulated in the charge accumulation unit to another location, and therefore reset noise can be accurately removed even with an incomplete transfer type image sensor.

  In the disclosed MOS image sensor, the charge storage unit is a photodiode formed in the semiconductor substrate.

  In the disclosed MOS type image sensor, the pixel portion is disposed between a pair of electrodes provided above the semiconductor substrate, and a photoelectric conversion layer that generates charges in response to incident light, and is disposed between the pair of electrodes. And the charge storage portion formed in the semiconductor substrate and electrically connected to one of the pair of electrodes.

  In the disclosed MOS type image sensor, the charge storage unit stores holes, and the writing transistor and the reading transistor are n-channel transistors.

  In the disclosed MOS type image sensor, the charge storage unit stores electrons, and the write transistor and the read transistor are p-channel transistors.

  The disclosed MOS image sensor driving method is a MOS image sensor driving method having a plurality of pixel portions, and the pixel portions are formed in a semiconductor substrate and accumulate charges generated according to incident light. A charge storage unit that performs electrical storage, a gate electrode that is electrically connected to the charge storage unit, a write transistor that includes a floating gate that stores charges injected from the semiconductor substrate in accordance with a potential of the gate electrode, and the floating gate And a readout transistor that has a floating gate electrically connected to the threshold voltage and changes in accordance with the charge accumulated in the floating gate, resets the potential of the charge accumulation portion, and Charge corresponding to the potential of the charge storage portion is applied to the floating gate of the write transistor. Then, a first signal corresponding to the threshold voltage of the readout transistor is read out and held, and subsequently, a charge corresponding to the potential of the charge storage unit after the exposure started after the end of the reset is completed. Injecting into the floating gate of the write transistor and then reading out a second signal corresponding to the threshold voltage of the read transistor, and outputting the difference between the first signal and the second signal as an imaging signal Steps.

  In the disclosed MOS image sensor driving method, the charge storage unit is a photodiode formed in the semiconductor substrate.

  In the disclosed MOS type image sensor driving method, the pixel portion is arranged between a pair of electrodes provided above the semiconductor substrate and the pair of electrodes, and generates a charge in response to incident light. A conversion layer; and the charge storage portion formed in the semiconductor substrate and electrically connected to one of the pair of electrodes.

  According to the disclosed MOS image sensor driving method, the writing transistor and the reading transistor are n-channel transistors, and holes are accumulated in the charge accumulation unit, and the floating gate is applied to the floating gate in accordance with the potential of the charge accumulation unit. Inject electrons.

  In the disclosed MOS image sensor driving method, the writing transistor and the reading transistor are p-channel transistors, electrons are stored in the charge storage unit, and the floating gate is positively connected according to the potential of the charge storage unit. Inject holes.

  The disclosed imaging device includes the MOS image sensor.

100 MOS type image sensor 4 Drive control circuit 8 Difference circuit 21 Pixel part SD Storage diode RSTr Reset transistor WT Write transistor WT
RT Read transistor RT
WCG Write control gate RCG Read control gate

Claims (11)

A MOS type image sensor having a plurality of pixel portions,
The pixel unit is electrically connected to the charge storage unit that is formed in the semiconductor substrate and stores a charge generated according to incident light, a reset transistor that resets the potential of the charge storage unit, and the charge storage unit. A write transistor including a gate electrode and a floating gate for accumulating charges injected from the semiconductor substrate in accordance with a potential of the gate electrode, and a floating gate electrically connected to the floating gate. A read transistor whose threshold voltage changes according to the accumulated charge,
The reset transistor is turned on to reset the potential of the charge storage unit, and a charge corresponding to the potential of the charge storage unit after completion of the reset is injected into the floating gate of the write transistor. A first signal corresponding to the threshold voltage is read out and held, and then a charge corresponding to the potential of the charge storage unit after the exposure started after the reset is finished is injected into the floating gate of the write transistor. And then, a control unit that reads a second signal corresponding to the threshold voltage of the read transistor;
A MOS type image sensor comprising: a signal output unit that outputs a difference between the first signal and the second signal as an imaging signal. The MOS image sensor according to claim 1,
A MOS type image sensor in which the charge storage portion is a photodiode formed in the semiconductor substrate. The MOS image sensor according to claim 1,
The pixel portion is formed between the pair of electrodes provided above the semiconductor substrate, the photoelectric conversion layer disposed between the pair of electrodes and generating charges in response to incident light, and the semiconductor portion formed in the semiconductor substrate. A MOS type image sensor including the charge storage unit electrically connected to one of a pair of electrodes. The MOS type image sensor according to claim 1,
The charge storage section stores holes;
A MOS type image sensor in which the writing transistor and the reading transistor are n-channel transistors. The MOS type image sensor according to claim 1,
The charge storage unit stores electrons;
A MOS type image sensor in which the writing transistor and the reading transistor are p-channel transistors. A method of driving a MOS image sensor having a plurality of pixel portions,
The pixel unit includes a charge storage unit that is formed in a semiconductor substrate and stores a charge generated according to incident light, a gate electrode electrically connected to the charge storage unit, and a potential of the gate electrode. A read transistor having a floating gate for storing a charge injected from a semiconductor substrate, and a floating gate electrically connected to the floating gate, wherein a threshold voltage changes in accordance with the charge stored in the floating gate Including a transistor,
The potential of the charge storage unit is reset, and a charge corresponding to the potential of the charge storage unit after completion of the reset is injected into the floating gate of the write transistor, and then the first corresponding to the threshold voltage of the read transistor Is then injected into the floating gate of the write transistor after the exposure started after the reset is completed, and then the read transistor is injected. Reading a second signal corresponding to the threshold voltage of
A method for driving a MOS image sensor, comprising: outputting a difference between the first signal and the second signal as an imaging signal. A MOS image sensor driving method according to claim 6,
A method for driving a MOS type image sensor, wherein the charge storage unit is a photodiode formed in the semiconductor substrate. A MOS image sensor driving method according to claim 6,
The pixel portion is formed between the pair of electrodes provided above the semiconductor substrate, the photoelectric conversion layer disposed between the pair of electrodes and generating charges in response to incident light, and the semiconductor portion formed in the semiconductor substrate. A method for driving a MOS image sensor, comprising: the charge storage portion electrically connected to one of a pair of electrodes. A method for driving a MOS type image sensor according to any one of claims 6 to 8,
The write transistor and the read transistor are n-channel transistors;
Accumulating holes in the charge storage part,
A method for driving a MOS image sensor in which electrons are injected into the floating gate. A method for driving a MOS type image sensor according to any one of claims 6 to 8,
The write transistor and the read transistor are p-channel transistors;
Accumulate electrons in the charge accumulation part,
A method for driving a MOS type image sensor in which holes are injected into the floating gate.   An imaging device comprising the MOS image sensor according to any one of claims 1 to 5.

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