JP2011049306A - Method for predicting connection resistance value - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a prediction method for easily and accurately predicting a connection resistance value of a contact part between laminated bases when the bases each of which is composed of a wafer or a chip are mutually laminated. <P>SOLUTION: The prediction method for predicting a connection resistance value includes a process for calculating a contact area (contacted area S<SB>1</SB>) between a first connection part and a second connection part in a surface contact part, a process for calculating a contact area (reference contact area S<SB>0</SB>) between a first reference connection part and a second reference connection part in a reference surface contact part formed by laminating a reference value setting first base including a first reference connection part having the same resistivity as that of the first connection part and a reference value setting second base including a second reference connection part having the same resistivity as that of the second connection part and allowing the first reference connection part and the second reference connection part to make surface contact with each other, a process for obtaining a connection resistance value (reference connection resistance value R<SB>0</SB>) of the reference surface contact part, and a process for calculating a connection resistance value R of the surface contact part by using R=R<SB>0</SB>ä1/(S<SB>1</SB>/S<SB>0</SB>)} (formula 1). <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a method for predicting a connection resistance value, and in particular, a connection resistance of a contact portion between a laminated substrate and a substrate formed in a semiconductor device or the like in which a plurality of substrates including wafers or chips are bonded together. The present invention relates to a method for predicting a connection resistance value that can easily and accurately predict a value.

  2. Description of the Related Art Conventionally, a three-dimensional semiconductor integrated circuit device having a configuration in which two or more wafers are stacked and electrically connected by embedded wiring is known (see, for example, Patent Document 1). In the semiconductor device described in Patent Document 1, an embedded wiring is formed on one of the wafers to be laminated, and a back surface bump is formed at the position of the embedded wiring on the back surface of the wafer by connecting to the embedded wiring. The stacked wafers are electrically connected to each other by bringing the bumps in contact with the bumps on the surface formed on the surface of the other wafer to be stacked.

When electrical connection is made between the wafers stacked in this way, the bump surface is not completely flat, so contact between the bumps formed on one wafer and the bumps formed on the other wafer Is a point contact. When the wafers are electrically connected by point contact, the connection resistance value at the contact portion between the wafers becomes high, and the resistance value and reliability in electrical connection between the wafers may not be sufficiently obtained.
As a method for solving this problem, a method is adopted in which a load is applied between stacked wafers, and one or both of the bumps are deformed to bring the bumps into contact with the bumps. However, in this method, the load applied between the laminated wafers adversely affects the wafers and the elements constituting the circuit formed on the wafers, so that there is a case where a high manufacturing yield cannot be obtained. .

In addition, when the bumps formed on one wafer and the bumps formed on the other wafer are brought into contact with each other to electrically connect the stacked wafers, the contact area of the contact portion between the wafers varies. Since the connection resistance value is increased, it is difficult to control the connection resistance value, and there is a problem in that the connection resistance value varies greatly.
As a technique for solving this problem, a through electrode protruding from one substrate through one wafer is brought into contact with a bump formed on the other wafer to electrically connect the stacked wafers. (For example, refer patent document 2). In the semiconductor device described in Patent Document 2, the through wiring portion exposed from the back surface of the upper substrate and the bumps on the main surface of the lower substrate are joined in contact with each other, thereby being electrically connected to each other. Yes.

  In addition, when a substrate made of a wafer or a chip is laminated, the connection resistance value of the contact portion between the laminated substrate and the substrate affects the performance of the circuit formed on the substrate. is there. As a method of measuring the connection resistance value of the contact portion between the laminated base and the base, for example, a method of configuring a double bridge circuit using a resistance material to be measured and measuring with a probe through a pad, for example, The Kelvin method is known.

JP 11-261000 A JP 2007-59769 A

  However, in the conventional technique, when the bases made of wafers or chips are stacked, the connection resistance value of the contact portion between the stacked bases must be measured after the bases are stacked. I couldn't know. For this reason, in the conventional technology, when designing a semiconductor device in which a plurality of bases made of wafers or chips are stacked, an optimum design corresponding to the connection characteristics of the contact portion between the bases is performed. In some cases, it has been desired to provide a method capable of grasping the connection resistance value of the contact portion between the substrates at the design stage of the semiconductor device.

  The present invention has been made in view of such circumstances, and when a substrate made of a wafer or a chip is laminated, the connection resistance value of a contact portion between the laminated substrate and the substrate can be easily obtained. An object of the present invention is to provide a method for predicting a connection resistance value that can be accurately predicted.

  In order to achieve the above-mentioned object, the present inventor has conducted earnest research by paying attention to the contact area of the contact portion between the substrates. As a result, a reference surface contact portion made of a conductive material having the same resistivity as the contact portion between the base bodies to be predicted is formed, its connection resistance is measured to obtain a reference connection resistance value, and the reference connection resistance value and its contact area The present inventors have found that the connection resistance value of the contact portion between the substrates can be easily and accurately predicted using the contact area of the contact portion between the substrates to be predicted, and have arrived at the connection resistance value prediction method of the present invention.

  A method for predicting a connection resistance value according to the present invention includes a first base made of a wafer or a chip having a first connection portion (for example, the first connection portion 32 in the embodiment) (for example, the first wafer 13 in the embodiment), and A second base made of a wafer or a chip (for example, the second wafer 14 in the embodiment) having a second connection portion (for example, the bump portion 42a in the embodiment) is stacked, and the first connection portion and the second connection are stacked. A method of predicting a connection resistance value of a surface contact portion (for example, the surface contact portion 12 in the embodiment) that is conductively connected by surface contact with a portion, wherein the first connection portion and the second connection in the surface contact portion A step of calculating a contact area that is a contact area with the connection portion, and a first reference connection portion (for example, the first reference connection portion 31 in the embodiment) made of a conductive material having the same resistivity as the first connection portion. A reference value setting first substrate (for example, the reference value setting first wafer 3 in the embodiment) made of a wafer or chip having a second reference connection made of a conductive material having the same resistivity as the second connection portion. A reference value setting second substrate (for example, the reference value setting second wafer 4 in the embodiment) made of a wafer or a chip having a portion (for example, the bump portion 41a in the embodiment), and the first reference connection. The first reference connection portion and the second reference in a reference surface contact portion (for example, the reference surface contact portion 2 in the embodiment) formed by bringing the portion and the second reference connection portion into surface contact and conducting conductive connection A step of calculating a reference contact area which is a contact area with the connection portion, a step of obtaining a reference connection resistance value from a result of measuring the connection resistance value of the reference surface contact portion, and the following (Equation 1) are used. Characterized in that it comprises a step of calculating the connection resistance value of the surface contact portion Te.

R = R ₀ {1 / (S ₁ / S ₀ )} (Formula 1)
In (Formula 1), R represents the connection resistance value of the surface contact portion, S ₀ represents the reference contact area, R ₀ represents the reference connection resistance value, and S ₁ represents the contacted area.

  In the method for predicting a connection resistance value of the present invention, the first connection portion includes a columnar portion (for example, the columnar portion 32a in the embodiment) protruding in a columnar shape from the back surface of the first base. 2 connecting portions are formed on the surface of the second base, and have a bump portion (for example, a bump portion 42a in the embodiment) having a shape surrounding the columnar portion of the first connecting portion in a plan view, The surface contact portion is formed by embedding at least a part of the columnar portion of the first connection portion in the bump portion of the second connection portion, and the first reference connection portion is the reference portion. It has a columnar part (for example, columnar part 31a in the embodiment) that protrudes in a columnar shape from the back surface of the first base for value setting, and the second reference connection part is formed on the surface of the second base for reference value setting. Formed And a bump portion having a shape surrounding the columnar portion of the first reference connection portion in a plan view (for example, the bump portion 41a in the embodiment), and at least one of the columnar portions of the first reference connection portion. The reference surface contact portion is formed by embedding a portion in the bump portion of the second reference connection portion.

  In the method for predicting a connection resistance value of the present invention, various metal materials are targeted, but the first connection portion and the first reference connection portion are made of a hard metal material such as tungsten or copper. The second connecting portion and the second reference connecting portion may be made of a soft metal material such as indium or tin.

  In the method for predicting a connection resistance value according to the present invention, the step of obtaining the reference connection resistance value includes the first base for setting a reference value having a plurality of first reference connection portions and a plurality of second reference connection portions. The reference value setting second base is laminated, and the plurality of first reference connection portions and the plurality of second reference connection portions are brought into surface contact with each other to form a plurality of reference surface contact portions. It can be set as the method characterized by being the process of calculating the average value of the connection resistance value of a contact part.

According to the connection resistance value prediction method of the present invention, R = R ₀ {1 / (S ₁ / S ₀ )} (formula 1) ((1) using the contacted area, the reference contact area, and the reference connection resistance value. In Equation 1), R represents the connection resistance value of the surface contact portion, S ₀ represents the reference contact area, R ₀ represents the reference connection resistance value, and S ₁ represents the contact area). Since the connection resistance value of the portion is calculated, the connection resistance value of the surface contact portion between the first base and the second base can be accurately predicted.
By using the method for predicting a connection resistance value according to the present invention, the connection resistance value of the surface contact portion is easily known as compared with the case where the connection resistance value of the surface contact portion between the first base and the second base is measured. be able to.
In addition, according to the method for predicting the connection resistance value of the present invention, the connection resistance value of the surface contact portion between the first base and the second base is calculated using the contacted area, the reference contact area, and the reference connection resistance value. Therefore, the connection resistance value can be easily and accurately predicted regardless of the shape of the surface contact portion.

Further, according to the method for predicting the connection resistance value of the present invention, even if the first base and the second base are not actually stacked and conductively connected, the surface contact between the stacked first base and the second base is achieved. Therefore, the connection resistance value of the surface contact portion between the first base and the second base can be grasped at the design stage.
For this reason, for example, the design suitable for the connection characteristic of the contact portion between the first base and the second base is reflected by reflecting the predicted result of the connection resistance value of the surface contact portion between the first base and the second base. It can be carried out. In particular, depending on the connection characteristics of the contact portion between the first base and the second base, such as when the structure formed by laminating the first base and the second base has a digital circuit and / or an analog circuit. When the influence on the circuit performance is great, the prediction result of the connection resistance value of the surface contact portion between the first substrate and the second substrate is reflected in the connection characteristic of the contact portion between the first substrate and the second substrate. A corresponding optimum design can be made and is preferred.

FIG. 1 is a plan view for explaining a semiconductor device after stacking provided with an example of a reference surface contact portion used in the connection resistance value prediction method of the present embodiment. FIG. 2 is a longitudinal sectional view showing a part of the semiconductor device shown in FIG. 1. FIG. 2 is a diagram for explaining reference plane contact portions provided in each region 1b divided in a lattice shape in FIG. It is a cross-sectional schematic diagram. 3A is an enlarged longitudinal sectional view showing only the vicinity of the reference surface contact portion shown in FIG. 2, and FIG. 3B is a cross section corresponding to the line AA in FIG. 3A. FIG. FIG. 4 is a plan view for explaining a semiconductor device including an example of another surface contact portion whose connection resistance value is predicted using the connection resistance value prediction method of the present embodiment. FIG. 5 is a longitudinal sectional view showing a part of the semiconductor device shown in FIG. 4. FIG. 5 is a schematic cross-sectional view for explaining the surface contact portions provided in each region divided in a lattice shape in FIG. It is. 6 is an enlarged longitudinal sectional view showing only the vicinity of the surface contact portion shown in FIG. FIG. 7 is a graph showing variations in the connection resistance value of the reference surface contact portion in the embodiment of FIG. FIG. 8 is a graph showing the variation in the predicted connection resistance value of the surface contact portion. FIG. 9 shows the relationship between the contacted area (S ₁ ) and the predicted value (8.45Ω) of the connection resistance value of the surface contact portion and the connection resistance value (8.37Ω) of the surface contact portion calculated from the actual measurement value. And a graph showing the relationship between the reference contact area (S ₀ ) and the reference connection resistance value (R ₀ ).

Next, the present invention will be described in detail with reference to the drawings.
The method for predicting a connection resistance value according to the present embodiment includes stacking a first wafer (first substrate) having a first connection portion and a second wafer (second substrate) having a second connection portion, and first connection. This is a method for predicting the connection resistance value of the surface contact portion in which the portion and the second connection portion are brought into surface contact and conductively connected.

First, the reference plane contact portion used in the connection resistance value prediction method of this embodiment will be described with reference to the drawings.
FIG. 1 is a plan view for explaining a semiconductor device including an example of a reference surface contact portion used in the connection resistance value prediction method of the present embodiment. FIG. 2 is a longitudinal sectional view showing a part of the semiconductor device shown in FIG. 1. FIG. 2 is a diagram for explaining reference plane contact portions provided in each region 1b divided in a lattice shape in FIG. It is a cross-sectional schematic diagram. 3A is an enlarged longitudinal sectional view showing only the vicinity of the reference surface contact portion shown in FIG. 2, and FIG. 3B is a cross section corresponding to the line AA in FIG. 3A. FIG.

  A semiconductor device 1 shown in FIG. 1 includes a reference value setting first wafer 3 (reference value setting first substrate) and a reference value setting second wafer 4 (reference value setting first substrate, as shown in FIG. Are laminated and bonded together. Each of the reference value setting first wafer 3 and the reference value setting second wafer 4 includes multilayer wiring layers 3a and 4a provided on substrates 3b and 4b made of silicon or the like. In the multilayer wiring layers 3a and 4a, a plurality of elements 6 such as a plurality of MOS-FETs (Metal Oxide Semiconductor Field Effect Transistors) constituting the semiconductor circuit of the semiconductor device 1 and a plurality of connections electrically connected to the element 6 are provided. Wiring 7 is formed.

  In FIG. 1, a reference surface contact portion 2 shown in FIG. 2 is formed in each region 1b divided into a lattice shape. Each reference surface contact portion 2 includes two first reference connection portions 31 provided on the reference value setting first wafer 3 and a bump portion (second reference connection portion provided on the reference value setting second wafer 4). ) 41a is brought into surface contact and conductively connected. The first reference connecting portion 31 is made of, for example, tungsten, and the bump portion 41a is made of, for example, indium.

As shown in FIG. 2, each first reference connection portion 31 is electrically connected to the connection wiring 7 provided in the multilayer wiring layer 3 a of the first reference value setting wafer 3. A substrate 3b constituting one wafer 3 is provided so as to penetrate in the thickness direction. Each first reference connecting portion 31 has a columnar portion 31a that protrudes in a columnar shape from the back surface of the reference value setting first wafer 3, as shown in FIG. The cross-sectional shape of the columnar part 31a is a rectangle as shown in FIG. However, the cross-sectional shape of the columnar part 31a is not limited to a rectangle.
Each bump portion 41 a is formed on the surface of the reference value setting second wafer 4 and has a shape surrounding the columnar portion 31 a of the first reference connection portion 31 in plan view. The bump part 41a is electrically connected to the connection wiring 7 provided on the multilayer wiring layer 4a of the reference value setting second wafer 4 of FIG. 2 via the metal part 41b shown in FIG.

  In the present embodiment, as shown in FIGS. 2, 3A, and 3B, a part of the columnar portion 31a of the first reference connecting portion 31 is embedded in the bump portion 41a, whereby each reference A surface contact portion 2 is formed.

  2, 3 </ b> A, and 3 </ b> B, reference numeral 5 denotes a substrate 3 b made of an insulating film that penetrates the substrate 3 b that constitutes the reference value setting first wafer 3, and the first reference connection portion. It is a penetration separation part which separates. As shown in FIG. 3A, the through separation portion 5 is provided so as to protrude from the back surface of the reference value setting first wafer 3. The penetrating separation part 5 has a shape surrounding the first reference connection part 31, and a part thereof is embedded in the bump part 41a.

Next, the surface contact part estimated in this embodiment is demonstrated using drawing.
FIG. 4 is a plan view for explaining a semiconductor device including an example of a surface contact portion whose connection resistance value is predicted using the method for predicting the connection resistance value of the surface contact portion according to the present embodiment. FIG. 5 is a longitudinal sectional view showing a part of the semiconductor device shown in FIG. 4. FIG. 5 is a schematic cross-sectional view for explaining the surface contact portions provided in each region 10b divided in a lattice shape in FIG. FIG. 6 is an enlarged longitudinal sectional view showing only the vicinity of the surface contact portion shown in FIG.

  As shown in FIG. 5, the semiconductor device 10 shown in FIG. 4 is formed by laminating a first wafer 13 and a second wafer 14 together. Each of the first wafer 13 and the second wafer 14 includes multilayer wiring layers 13a and 14a provided on substrates 3b and 4b made of silicon or the like. In the multilayer wiring layers 13a and 14a, a plurality of elements 6 such as MOS / FETs and a plurality of connection wirings 7 that are electrically connected to the elements 6 are formed. .

  Further, in FIG. 4, the surface contact portion 12 shown in FIG. 5 is formed in each of the regions 10 b divided in a lattice shape. Each surface contact portion 12 conducts conductive connection by bringing the first connection portion 32 provided on the first wafer 13 into surface contact with the bump portion (second connection portion) 42a provided on the second wafer 14. It will be. The first connection part 32 is made of tungsten like the first reference connection part 31 shown in FIG. 2, and the bump part 42a is made of indium like the bump part 41a shown in FIG.

As shown in FIG. 5, each first connection portion 32 is electrically connected to the connection wiring 7 provided on the multilayer wiring layer 13 a of the first wafer 13, and the substrate 3 b constituting the first wafer 13 is connected to the first connection portion 32. It is provided penetrating in the direction of the back surface. Each first connection portion 32 has a columnar portion 32a that protrudes in a columnar shape from the back surface of the first wafer 13, as shown in FIG. The case where the cross-sectional shape of the columnar part 32a is circular is assumed.
Each bump portion 42a is formed on the surface of the second wafer 14, and has a shape surrounding the columnar portion 32a of the first connection portion 32 in plan view. The bump part 42a is electrically connected to the connection wiring 7 provided on the multilayer wiring layer 14a of the second wafer 14 through the metal part 42b shown in FIG.

  In this embodiment, as shown in FIGS. 5 and 6, each surface contact portion 12 is formed by embedding a part of the columnar portion 32 a of the first connection portion 32 in the bump portion 42 a.

  In FIG. 5 and FIG. 6, reference numeral 15 denotes a through separation portion that separates the first connection portion 32 from the substrate 3 b made of an insulating film that penetrates through the substrate 3 b constituting the first wafer 13. The penetrating separation part 15 is provided in contact with the periphery of the first connection part 32 embedded in the first wafer 13, and a part thereof protrudes from the back surface of the first wafer 13. Further, the through separation portion 15 is not provided in a portion embedded in the bump portion 42a in the columnar portion 32a of the first connection portion 32, and as shown in FIG. 6, a columnar shape embedded in the bump portion 42a. The entire surface of the portion 32a is in contact with the bump portion 42a.

In the present embodiment, in order to predict the connection resistance value of the surface contact portion 12 of the semiconductor device 10 shown in FIGS. 4 to 6 using the reference surface contact portion 2 of the semiconductor device 1 shown in FIGS. The contact area (S ₁ ), the reference contact area (S ₀ ), and the reference connection resistance value (R ₀ ) are used.

As the contacted area (S ₁ ), the contact area between the columnar part 32a and the bump part 42a in the surface contact part 12 shown in FIG. 6 (contact area between the first connection part and the second connection part) is calculated.
In the present embodiment, the columnar portion 32a has a columnar shape and is embedded in the bump portion 42a. Therefore, the columnar portion 32a embedded in the circumferential length of the columnar portion 32a and the bump portion 42a is formed in the transverse area of the columnar portion 32a. It is the area which added the product with the length of.

As the reference contact area (S ₀ ), as shown in FIG. 3, the reference value setting first wafer 3 and the reference value setting second wafer 4 are stacked, and the columnar portion 31a of the first reference connection portion 31 The contact area between the two columnar portions 31a and the bump portion 41a in the reference surface contact portion 2 formed by conducting conductive connection by bringing the bump portion 41a into surface contact is calculated.
In the present embodiment, the columnar portion 31a has a columnar shape, and there are two columnar portions 31a as shown in FIG. 3, which are embedded in the bump portion 41a. Therefore, in the cross-sectional area of the columnar portion 31a, the circumference of the columnar portion 31a is The area is twice the area obtained by adding the product of the length and the length of the columnar part 31a embedded in the bump part 41a.

Based on the ratio (S ₁ / S ₀ ) of the contacted area (S ₁ ) and the reference contact area (S ₀ ), the connection resistance value of the surface contact portion 12 of the stacked semiconductor device 10 can be predicted with high accuracy.

The reference connection resistance value (R ₀ ) is obtained from the result of measuring the connection resistance value of the reference surface contact portion 2. The method for measuring the connection resistance value of the reference surface contact portion 2 is not particularly limited. For example, a double bridge circuit is configured using a resistance material to be measured, and the measurement is performed by a probe via a pad. A Kelvin method or the like can be used.

The reference connection resistance value (R ₀ ) is obtained by measuring the connection resistance values of a plurality of reference surface contact portions 2 formed in each region 1b divided in a lattice shape in FIG. Therefore, it is possible to predict the connection resistance value of the surface contact portion 12 of the stacked semiconductor device 10 with higher accuracy.

In the present embodiment, the contact area (S ₁ ), the reference contact area (S ₀ ), and the reference connection resistance value (R ₀ ) thus obtained are substituted into (Equation 1) shown below. The connection resistance value is calculated.
R = R ₀ {1 / (S ₁ / S ₀ )} (Formula 1)
In (Expression 1), R represents the connection resistance value of the surface contact portion, S ₀ represents the reference contact area, R ₀ represents the reference connection resistance value, and S ₁ represents the contacted area.

According to the present embodiment, the contact area (S ₁ ), the reference contact area (S ₀ ), and the reference connection resistance value (R ₀ ) are obtained, and the connection resistance value of the surface contact portion is obtained using the above (Equation 1). Since R is calculated, the connection resistance value of the surface contact portion 12 between the first wafer 13 and the second wafer 14 can be accurately predicted, and the connection resistance value of the surface contact portion 12 between the first wafer 13 and the second wafer 14 is estimated. As compared with the case of actually measuring, it is possible to easily know the connection resistance value of the surface contact portion 12.

In addition, according to the method for predicting the connection resistance value of the present invention, the reference contact area (S ₀ ) and the reference connection resistance value (R ₀ ) using the same material as the contacted area (S ₁ ) are used. Since the connection resistance value of the surface contact portion 12 between the first wafer 13 and the second wafer 14 is calculated, the connection resistance value can be easily and accurately predicted regardless of the shape of the surface contact portion 12.
In addition, according to the method for predicting a connection resistance value of the present invention, the first wafer 13 and the second wafer 14 that are stacked without actually conducting the conductive connection by stacking the first wafer 13 and the second wafer 14. Therefore, the connection resistance value of the surface contact portion 12 between the first wafer 13 and the second wafer 14 can be grasped at the design stage.

  In the present embodiment, the case where the first substrate and the second substrate are wafers having connection portions has been described as an example. However, the first substrate and / or the second substrate is a chip having connection portions. May be. Therefore, the structure in which the first base and the second base are stacked may be a stack of a wafer and a wafer as in the present embodiment, or a stack of a wafer and a chip, It may be a laminate of chips. Examples of the chip include a chip having one or more of the first connection portion 32 or the bump portion 42a described above.

  In the present embodiment, the case where the reference value setting first substrate and the reference value setting second substrate are wafers having reference connection portions has been described as an example. However, the reference value setting first substrate and the reference value setting first substrate / Or the chip | tip which has a connection part may be sufficient as the 2nd base | substrate for reference value setting. Therefore, the structure in which the reference value setting first base and the reference value setting second base are stacked may be a structure in which a wafer and a wafer are stacked as in this embodiment, or a wafer and a chip. May be laminated, or a chip and a chip may be laminated. Examples of the chip include a chip having one or more of the first reference connection portion 31 or the bump portion 41a described above.

In the above-described embodiment, the first connecting portion 32 and the first reference connecting portion 31 are made of tungsten, and the bump portion 41a and the bump portion 42a are made of indium. As described above, the first connecting portion and the first reference connecting portion are conductive materials having the same resistivity, and the second connecting portion and the second reference connecting portion may be conductive materials having the same resistivity. The materials are not limited to the above.
For example, as another conductive material that can be used for the first connection portion and / or the first reference connection portion, copper or the like can be given. Other conductive materials that can be used for the second connection part and / or the second reference connection part include composites of gold on the surface of indium (In / Au) and tin (Sn). Can be mentioned.

In the above-described embodiment, the reference surface contact portion 2 is a contact area between the two first reference connection portions 31 and the bump portions 41a having a rectangular cross section, and the surface contact portion 12 has a cross section. The case where the shape is the contact area between the first connecting portion 32 and the bump portion 42a having a circular shape has been described as an example, but the cross-sectional shape and number of the surface contact portion 12 and the reference surface contact portion 2 are It is not limited to the embodiment described above.
Specifically, the number of the first connection portions 32 and the first reference connection portions 31 may be any number, and the cross-sectional shapes of the first connection portions 32 and the first reference connection portions 31 are circular, rectangular, and many. Any shape such as a square may be used.

Moreover, in embodiment mentioned above, the connection resistance value of the surface contact part 12 of the semiconductor device 10 shown in FIGS. 4-6 is estimated using the reference plane contact part 2 of the semiconductor device 1 shown in FIGS. As described above, the surface contact portion 12 is formed by stacking the first wafer having the first connection portion and the second wafer having the second connection portion, and the first connection portion and the second connection. The reference surface contact portion 2 has a first reference connection portion made of a conductive material having the same resistivity as that of the first connection portion. A wafer and a reference value setting second wafer having a second reference connection portion made of a conductive material having the same resistivity as that of the second connection portion are stacked, and the first reference connection portion and the second reference connection portion are faced to each other. Any semiconductor device may be used as long as it is formed by contact and conductive connection. Structure is not limited to the embodiments described above.
Specifically, the reference value setting first wafer 3 and the reference value setting second wafer 4, the first wafer 13 and the second wafer 14, the substrates 3b and 4b, and the multilayer wiring layers 13a and 14a are also described above. It is not limited to the embodiment.

"Experimental example"
The first wafer 13 having the first connection portion 32 made of tungsten and the second wafer 14 having the bump portion 42a made of indium are laminated to manufacture the semiconductor device 10 shown in FIG. By making surface contact with the bump part 42a, the surface contact part 12 shown in FIG. 5 that is conductively connected to each region 10b divided in a lattice shape in FIG. 4 is formed. The connection resistance value was predicted.

  As the substrates 3b and 4b constituting the semiconductor device 10 shown in FIG. 4, a substrate made of silicon having a diameter of 200 mm (8 inches) was used. In addition, each surface contact portion 12 is formed by surface contact between the columnar portion 32a of the first connecting portion 32 and the bump portion 42a, and each columnar portion 32a has a circular shape with a diameter of 1 μm. The length of each columnar portion 32a protruding from the back surface of the first wafer 13 was 5 μm, and the length of the columnar portion 32a embedded in the bump portion 42a was 3 μm.

  First, a reference value setting first wafer 3 having a first reference connection portion 31 made of tungsten and a reference value setting second wafer 4 having a bump portion 41a made of indium are stacked, and the semiconductor device shown in FIG. 1 and the first reference connection portion 31 and the bump portion 41a are brought into surface contact with each other, and the reference surface shown in FIG. 2 is conductively connected to each region 1b divided in a lattice shape in FIG. A contact portion 2 was formed.

  Note that six sets of the semiconductor device 1 shown in FIG. 1 were manufactured. Further, as the substrates 3b and 4b constituting the semiconductor device 1 shown in FIG. 1, as in the substrates 3b and 4b constituting the semiconductor device 10 shown in FIG. 4, a substrate made of silicon having a diameter of 200 mm (8 inches) is used. It was. Each reference surface contact portion 2 is formed by surface contact between the columnar portions 31a of the two first reference connection portions 31 and the bump portions 41a. The cross-sectional shape of each columnar portion 31a is 5. It is a rectangle of 6 μm and a width of 1.5 μm, the length of each columnar portion 31 a protruding from the back surface of the reference value setting first wafer 3 is 10 μm, and the length of each columnar portion 31 a embedded in the bump portion 41 a is 7 μm. Met.

Next, the contact area between one columnar part 32a and the bump part 42a in the surface contact part 12 shown in FIG. 5 was calculated as the contacted area (S ₁ ).
That is, the product of the circumferential length of the columnar portion 32a and the length of the columnar portion 32a embedded in the bump portion 42a in the cross-sectional area of the columnar portion 32a (0.5 μm × 0.5 μm × 3.14 = 0.785 μm ² ). ((1 μm × 3.14) × 3 μm = 9.42 μm 2) was added to the area (0.785 μm ² +9.42 μm ² = 10.205 μm ² ).

As the reference contact area (S ₀ ), the contact area between the two columnar parts 31a and the bump part 41a in the reference surface contact part 2 shown in FIG. 2 was calculated.
That is, the product of the circumferential length of the columnar portion 31a and the length of the columnar portion 31a embedded in the bump portion 41a ((5.5 μm × 1.5 μm = 8.4 μm ² ) in the cross-sectional area of the columnar portion 31a (5.6 μm × 1.5 μm = 8.4 μm ² ). 6μm × 1.5μm × 2) × 7 = 2 times the 99.4μm ²⁾ the area was added ^{(8.4μm 2 + 99.4μm 2 = 107.8μm} 2) (107.8μm 2 × 2 = 215.6μm 2 ).

The ratio (S ₁ / S ₀ ) between the contacted area (S ₁ ) and the reference contact area (S ₀ ) calculated in this way was 1 / 21.1.

Further, the reference connection resistance value (R ₀ ) was obtained by measuring the connection resistance value of the reference surface contact portion 2. As a method for measuring the connection resistance value of the reference surface contact portion 2, a double bridge circuit was configured using a resistance material to be measured, and the measurement was performed by a method using a probe via a pad, that is, the Kelvin method.

The reference connection resistance value (R ₀ ) is a measurement of the connection resistance values of 58 reference plane contact portions 2 arranged in each region 1b divided in a lattice form in FIG. 1 for each of six sets of semiconductor devices 1. And it obtained by calculating the average value of the result of the connection resistance value of the reference plane contact part 2 of a total of 310 places obtained. The calculated reference connection resistance value (R ₀ ) was 0.4Ω.

  The result of measuring the connection resistance value of the reference surface contact portion 2 is shown in FIG. FIG. 7 is a graph showing variations in the connection resistance value of the reference surface contact portion 2. As shown in FIG. 7, the frequency distribution of the connection resistance value of the reference surface contact portion 2 was steep and the variation was very small. Further, the standard deviation of the connection resistance value of the reference surface contact portion 2 was obtained. As a result, the standard deviation was ± 0.025.

The contact area (S ₁ ), the reference contact area (S ₀ ), and the reference connection resistance value (R ₀ ) thus obtained are substituted into the following (formula 1) to connect the surface contact portion. The resistance value was calculated.
R = R ₀ {1 / (S ₁ / S ₀ )} (Formula 1)
In (Expression 1), R represents the connection resistance value of the surface contact portion, S ₀ represents the reference contact area, R ₀ represents the reference connection resistance value, and S ₁ represents the contacted area.
That is, from the reciprocal 21.1 of the ratio 1 / 21.1 of the contacted area (S ₁ ) and the reference contact area (S ₀ ) and the reference connection resistance value (R ₀ ) 0.4, 0.4 × 21. 1 = 8.44 (Ω) is obtained,
This value was a predicted value of the connection resistance value of the surface contact portion.

  Further, three sets of the semiconductor device 10 shown in FIG. 4 are manufactured, and for each of the three sets of semiconductor devices 10, connection of 31 surface contact portions 12 arranged in each region 10b divided in a lattice shape in FIG. The resistance value was measured in the same manner as the reference surface contact portion 2, and the average value of the connection resistance values of the obtained 91 surface contact portions 12 in total was calculated. The connection resistance value of the surface contact portion 12 calculated from the actually measured value was 8.37Ω.

  The result of measuring the connection resistance value of the surface contact portion 12 is shown in FIG. FIG. 8 is a graph showing variations in the connection resistance value of the surface contact portion 12. As shown in FIG. 8, the frequency distribution of the connection resistance value of the surface contact portion 12 was steep and the variation was small. Further, the standard deviation of the connection resistance value of the surface contact portion 12 was obtained. As a result, the standard deviation was ± 0.05.

  Thus, the predicted value (8.44Ω) of the connection resistance value of the surface contact portion 12 and the connection resistance value (8.37Ω) of the surface contact portion 12 calculated from the actual measurement values are approximate, and the above prediction is made. It was confirmed that the connection resistance value of the surface contact portion 12 between the first wafer 13 and the second wafer 14 can be accurately predicted by the method.

Further, the relationship between the contacted area (S ₁ ) and the predicted value (8.44Ω) of the connection resistance value of the surface contact portion 12 and the connection resistance value (8.37Ω) of the surface contact portion 12 calculated from the actual measurement value. FIG. 9 shows the relationship between the reference contact area (S ₀ ) and the reference connection resistance value (R ₀ ). In FIG. 9, a white circle indicates the reference connection resistance value (R ₀ ), a black circle indicates the connection resistance value of the surface contact portion 12 calculated from the actual measurement value, and an asterisk indicates a predicted value of the connection resistance value of the surface contact portion 12. Is shown.
From FIG. 9, the reference contact area (S ₀ ) having a larger area compared to the contacted area (S ₁ ) and the connection resistance value of the surface contact portion 12 are compared, and the reference connection resistance value (R) having a low resistance value is compared. ₀ )), it can be seen that the surface contact portion 12 can be predicted over a wide area range and resistance value range.

  DESCRIPTION OF SYMBOLS 1,10 ... Semiconductor device, 1b, 10b ... area | region, 2 ... Reference surface contact part, 3 ... 1st wafer for reference value setting (1st base | substrate for reference value setting), 3a, 4a, 13a, 14a ... Multilayer wiring layer 3b, 4b ... substrate, 4 ... second wafer for reference value setting (second base for reference value setting), 4c ... insulating layer, 5, 15 ... penetrating separation part, 6 ... element, 7 ... connection wiring, 12 ... Surface contact portion, 13 ... first wafer (first substrate), 14 ... second wafer (second substrate), 31 ... first reference connection portion, 31a, 32a ... columnar portion, 32 ... first connection portion, 41a ... Bump part (second reference connection part), 41b, 42b ... metal part, 42a ... bump part (second connection part).

Claims (4)

A first substrate made of a wafer or a chip having a first connection portion and a second substrate made of a wafer or a chip having a second connection portion are stacked, and the first connection portion and the second connection portion are in surface contact. A method for predicting a connection resistance value of a surface contact portion conductively connected,
Calculating a contact area that is a contact area between the first connection portion and the second connection portion in the surface contact portion;
A reference value setting first base body made of a wafer or chip having a first reference connection portion made of a conductive material having the same resistivity as that of the first connection portion; and a conductive material having the same resistivity as that of the second connection portion. And a reference value setting second substrate made of a wafer or a chip having a second reference connection portion and a conductive connection in which the first reference connection portion and the second reference connection portion are in surface contact with each other. Calculating a reference contact area that is a contact area between the first reference connection part and the second reference connection part in the reference surface contact part that has been performed;
Obtaining a reference connection resistance value from the result of measuring the connection resistance value of the reference surface contact portion;
The method of calculating the connection resistance value of the said surface contact part using the (Formula 1) shown below is provided.
R = R ₀ {1 / (S ₁ / S ₀ )} (Formula 1)
In (Expression 1), R represents the connection resistance value of the surface contact portion, S ₀ represents the reference contact area, R ₀ represents the reference connection resistance value, and S ₁ represents the contacted area. The first connection part has a columnar part protruding in a columnar shape from the back surface of the first base, the second connection part is formed on a surface of the second base, and the first connection part has the columnar part. It has a bump part which has the shape which surrounds a columnar part in plane view, and the surface contact is carried out by at least a part of the columnar part of the first connection part being embedded in the bump part of the second connection part. Part is formed,
The first reference connection part has a columnar part protruding in a columnar shape from the back surface of the reference value setting first base, and the second reference connection part is formed on the surface of the reference value setting second base. A bump portion formed and surrounding the columnar portion of the first reference connection portion in plan view, wherein at least a part of the columnar portion of the first reference connection portion is the second reference connection portion; The method for predicting a connection resistance value according to claim 1, wherein the reference surface contact portion is formed by being embedded in the bump portion. The first connection portion and the first reference connection portion are made of tungsten or copper,
The method for predicting a connection resistance value according to claim 1, wherein the second connection portion and the second reference connection portion are made of indium or tin.   The step of obtaining the reference connection resistance value includes stacking the reference value setting first base having a plurality of first reference connections and the reference value setting second base having a plurality of second reference connections. The plurality of first reference connection portions and the plurality of second reference connection portions are respectively brought into surface contact to form a plurality of reference surface contact portions, and the connection resistance values of the plurality of reference surface contact portions are measured, The method for predicting a connection resistance value according to claim 1, wherein the method is a step of calculating an average value of connection resistance values of the reference surface contact portion.

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