JP2010225766A - Semiconductor device and manufacturing method thereof, electro-optical device and manufacturing method thereof, circuit board and manufacturing method thereof, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device which can connect between conductive layers without using the photolithography method and the etching method. <P>SOLUTION: The method for manufacturing the semiconductor device has: the conductive layer step of successively stacking and forming a first conductive layer, an interlayer insulating film, and a second conductive layer on a substrate; and the contact hole forming step of performing physical processing from a surface of the second conductive layer to then form a recess part which penetrates the second conductive layer and the interlayer insulating film and reaches the first conductive layer. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, an electro-optical device and a manufacturing method thereof, a circuit board and a manufacturing method thereof, and an electronic apparatus.

  Development of a semiconductor device including an organic transistor using an organic semiconductor material, an organic insulating material, an organic conductive material, or the like is in progress (see, for example, Patent Document 1). Even in the manufacturing process of this type of semiconductor device, when a plurality of conductive layers are stacked on a substrate, a contact hole is formed in the organic insulating film formed as an interlayer insulating film in order to perform wiring connection between the conductive layers. It was necessary to form. Conventionally, as a method for forming a contact hole, a photolithography method and an etching method have been used.

JP 2003-218361 A

  However, if the photolithography method and the etching method are used for forming the contact hole, the photoresist used for the etching mask is an organic material (polymer), so that the photoresist cannot be peeled off from the lower organic insulating material in the mask removing process. There was a case. In addition, the organic semiconductor material may undergo a photoreaction and deteriorate due to the exposure process in the photolithography process.

  The present invention has been made in view of the above-described problems of the prior art, and is a method for manufacturing a semiconductor device and a method for manufacturing an electro-optical device that can connect conductive layers without using a photolithography method and an etching method. Another object is to provide a circuit board manufacturing method.

  The method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having a semiconductor layer on a substrate, wherein the first conductive layer, the interlayer insulating film, and the second conductive layer are sequentially stacked on the substrate. A contact hole forming step of forming a recess reaching the first conductive layer through the second conductive layer and the interlayer insulating film by performing physical processing from the surface of the second conductive layer; It is characterized by having.

  According to this manufacturing method, a contact hole for conductive connection can be formed without using a photolithography method and an etching method. Therefore, it is possible to avoid a problem in peeling of the resist mask used for etching and deterioration of elements on the substrate due to exposure in the photolithography process.

In the contact hole forming step, a pressing member is pushed into the surface of the second conductive layer to penetrate the interlayer insulating film, so that the pressed portion of the second conductive layer reaches at least the first conductive layer. Is preferred.
By setting it as such a manufacturing method, the site | part isolate | separated by the press of a 2nd conductive layer can be utilized for at least one part of the conductive connection of a 1st conductive layer and a 2nd conductive layer.

It is also preferable that the pressed portion of the second conductive layer penetrates the first conductive layer.
By setting it as such a manufacturing method, conduction | electrical_connection with the said site | part and a 1st conductive layer can be made more reliable, and the connection reliability of a 1st conductive layer and a 2nd conductive layer can be improved. .

  In the contact hole forming step, it is also preferable to form the recess by processing using a light beam or a charged particle beam. That is, as the physical processing, a processing method in which the second conductive layer and the interlayer insulating film are partially removed with a light beam or a charged particle beam can be employed.

It is preferable to have a connection part formation process which arrange | positions a electrically-conductive material in the said recessed part after the said contact hole formation process.
According to this manufacturing method, the first conductive layer and the second conductive layer can be connected by the connection portion made of the conductive material. Moreover, when the one part site | part of a 2nd conductive layer is arrange | positioned in a recessed part, it can be set as the structure which connects a 1st conductive layer and a 2nd conductive layer with the said site | part.

In the contact hole forming step, a through hole penetrating the first and second conductive layers and the interlayer insulating film and the substrate is formed, and in the connecting portion forming step, the conductive material is placed in the through hole. It is also preferable to arrange them.
According to this manufacturing method, the through hole penetrating the semiconductor device is formed as a contact hole. The first conductive layer and the second conductive layer are connected via a connection portion made of a conductive material arranged in the through hole.

  Next, in the method of manufacturing the electro-optical device according to the aspect of the invention, an organic transistor and an interlayer insulating film that covers at least a part of the element electrode of the organic transistor are formed on a substrate, and a pixel electrode is formed on the interlayer insulating film. And forming a recess that penetrates at least the pixel electrode and the interlayer insulating film and reaches the element electrode by performing physical processing from the surface of the pixel electrode. Features.

  According to this manufacturing method, since the concave portion penetrating the pixel electrode and the interlayer insulating film is formed as a contact hole by physical processing, a contact hole for conductive connection can be formed without using a photolithography method and an etching method. Can do. Therefore, it is possible to avoid a problem in peeling of the resist mask used for etching and deterioration of elements on the substrate due to exposure in the photolithography process.

  In the method of manufacturing an electro-optical device according to the aspect of the invention, an organic transistor and an interlayer insulating film that covers at least a part of the organic transistor are formed on a substrate, and a pixel electrode is formed on the interlayer insulating film. And a step of forming a recess penetrating the interlayer insulating film by pressing a pressing member on the surface of the pixel electrode, and causing at least the pressed portion of the pixel electrode to reach the element electrode. Features.

According to this manufacturing method, a contact hole is formed by pushing a part of the pixel electrode to the element electrode side. Therefore, a contact hole for conductive connection can be formed without using a photolithography method and an etching method. Can do. Therefore, it is possible to avoid a problem in peeling of the resist mask used for etching and deterioration of elements on the substrate due to exposure in the photolithography process.
In addition, since the pressed portion of the pixel electrode reaches the element electrode and is disposed in the contact hole, this portion can be used as at least a part of the connection structure between the pixel electrode and the element electrode.

It is also preferable to have a step of arranging a conductive material in the recess.
According to this manufacturing method, the conduction between the pixel electrode and the element electrode can be further ensured by the conductive material disposed in the recess.

  Next, the circuit board manufacturing method according to the present invention includes a conductive layer process in which a first conductive layer, an interlayer insulating film, and a second conductive layer are sequentially formed on the substrate, and a physical process from the surface of the second conductive layer. And a contact hole forming step of forming a contact hole that reaches the first conductive layer by passing through the second conductive layer and the interlayer insulating film by performing a general process.

  According to this manufacturing method, since the contact hole is formed by physical processing, the contact hole for conductive connection can be formed without using a photolithography method and an etching method. Therefore, it is possible to avoid a problem in peeling of the resist mask used for etching and deterioration of elements on the substrate due to exposure in the photolithography process.

  The method of manufacturing a circuit board according to the present invention includes a conductive layer forming step of sequentially stacking a first conductive layer, an interlayer insulating film, and a second conductive layer on a substrate, and physical processing from the surface of the second conductive layer. And a contact hole forming step of forming a recess that penetrates the second conductive layer and the interlayer insulating film and reaches the first conductive layer.

  According to this manufacturing method, a concave portion penetrating the second conductive layer and the substrate is formed as a contact hole by performing physical processing. Therefore, a contact hole for conductive connection without using a photolithography method and an etching method. Can be formed. Therefore, it is possible to avoid a problem in peeling of the resist mask used for etching and deterioration of elements on the substrate due to exposure in the photolithography process.

  Next, a semiconductor device of the present invention is a semiconductor device having a semiconductor layer, a first conductive layer, an interlayer insulating film, and a second conductive layer that are sequentially stacked on a substrate, and at least the second conductive layer. A recess that penetrates the layer and the interlayer insulating film and reaches the first conductive layer, and a connection portion that is disposed in the recess and connected to the first conductive layer and the second conductive layer. It is characterized by that.

  The semiconductor device having such a configuration is a semiconductor device that can be manufactured by the method for manufacturing a semiconductor device described above. This semiconductor device includes a recess opening in the surface of the second conductive layer, and the recess can be easily formed by physical processing. Therefore, a contact hole for connecting the first conductive layer and the second conductive layer can be formed without using a photolithography method and an etching method. Therefore, it is a semiconductor device with excellent manufacturability that can avoid problems caused by the photolithography process and the etching process.

  Next, the electro-optical device of the present invention includes an organic transistor, an interlayer insulating film that covers at least a part of the element electrode of the organic transistor, and a pixel electrode formed on the interlayer insulating film on a substrate. An electro-optical device, a recess that penetrates at least the pixel electrode and the interlayer insulating film and reaches the element electrode, and a connection portion that is disposed in the recess and is connected to the element electrode and the pixel electrode It is characterized by having.

  The electro-optical device having such a configuration can be manufactured by the above-described method for manufacturing an electro-optical device. This electro-optical device includes a recess opening on the surface of the pixel electrode, and the recess can be easily formed by physical processing. Therefore, a contact hole for connecting the element electrode and the pixel electrode can be formed without using a photolithography method and an etching method. Therefore, the electro-optical device is excellent in manufacturability and can avoid defects caused by the photolithography process and the etching process.

  The electro-optical device of the present invention includes an organic transistor, an interlayer insulating film that covers at least a part of the element electrode of the organic transistor, and a pixel electrode formed on the interlayer insulating film on a substrate. In this case, a part of the pixel electrode is pushed into the substrate side, penetrates the interlayer insulating film, and is in contact with the element electrode.

  The electro-optical device having such a configuration can also be manufactured by the electro-optical device manufacturing method described above. In this electro-optical device, a part of the pixel electrode is pushed into the element electrode side, and such a configuration can be easily formed by physical processing. Therefore, a contact hole for connecting the element electrode and the pixel electrode can be formed without using a photolithography method and an etching method. Therefore, the electro-optical device is excellent in manufacturability and can avoid defects caused by the photolithography process and the etching process.

It is preferable that the pixel electrode and the element electrode are connected by a part of the pixel electrode that is pushed in.
According to this configuration, the pixel electrode and the element electrode can be connected by an extremely simple physical process of pushing a part of the pixel electrode.

  Next, the circuit board of the present invention is a circuit board having a first conductive layer formed on one surface of the substrate and a second conductive layer formed on the other surface, and at least the second conductive layer. A recess that penetrates the layer and the substrate and reaches the first conductive layer, and a connecting portion that is disposed in the recess and is connected to the first conductive layer and the second conductive layer. Features.

  The circuit board having such a configuration is a circuit board that can be manufactured by the method for manufacturing a circuit board described above. This circuit board is provided with a recess opening on the surface of the second conductive layer, and such a recess can be easily formed by physical processing. Therefore, a contact hole for connecting the first conductive layer and the second conductive layer can be formed without using a photolithography method and an etching method. Therefore, it is a circuit board excellent in manufacturability that can avoid problems caused by the photolithography process and the etching process.

  The circuit board of the present invention is a circuit board having a first conductive layer, an interlayer insulating film, and a second conductive layer, which are sequentially stacked on the substrate, wherein at least the second conductive layer and the interlayer insulating film are provided. It has a concave portion that penetrates and reaches the first conductive layer, and a connecting portion that is disposed in the concave portion and is connected to the first conductive layer and the second conductive layer.

  The circuit board having such a configuration is a semiconductor device that can be manufactured by the method for manufacturing a circuit board described above. As described above, even when the first conductive layer, the interlayer insulating film, and the second conductive layer are laminated on the one surface side of the substrate, the concave portion opened on the surface of the second conductive layer is formed by physical processing. It can be formed easily. Therefore, a contact hole for connecting the first conductive layer and the second conductive layer can be formed without using a photolithography method and an etching method. Therefore, it is a circuit board excellent in manufacturability that can avoid problems caused by the photolithography process and the etching process.

Next, an electronic apparatus according to the invention includes the semiconductor device, the electro-optical device, or the circuit board described above.
According to this configuration, it is possible to provide an electronic device that is excellent in manufacturability.

1 is a schematic configuration diagram of an active matrix substrate according to an embodiment. The top view of a pixel and sectional drawing of an electrophoretic display device. FIG. 6 is a manufacturing process diagram of the electrophoretic display device according to the embodiment. FIG. 6 is a manufacturing process diagram of the electrophoretic display device according to the embodiment. FIG. 6 is a manufacturing process diagram of the electrophoretic display device according to the embodiment. The perspective view which illustrates a micro punch. Sectional drawing which shows the electrophoretic display apparatus which concerns on a modification. The figure which shows the circuit board which concerns on embodiment. FIG. 14 illustrates an example of an electronic device.

Hereinafter, an electrophoretic display device according to an embodiment of the electro-optical device of the invention will be described with reference to the drawings.
The scope of the present invention is not limited to the following embodiment, and can be arbitrarily changed within the scope of the technical idea of the present invention. Moreover, in the following drawings, in order to make each configuration easy to understand, the actual structure is different from the scale and number of each structure.

FIG. 1 is a schematic configuration diagram of an active matrix substrate 30 provided in the electrophoretic display device 100 according to the present embodiment. FIG. 2A is a plan view showing a configuration example of the pixel 40 in the active matrix substrate 30, and FIG. 2B is an electrophoretic display at a position along the line AA ′ in FIG. 2 is a cross-sectional view of the device 100. FIG.
The electrophoretic display device of this embodiment is an active matrix electrophoretic display device including an active matrix substrate 30 which is a semiconductor device according to the present invention.

  As shown in FIG. 2B, the electrophoretic display device 100 according to the present embodiment includes a plurality of microarrays between an active matrix substrate 30 (first substrate) and a counter substrate (second substrate) 31. The electrophoretic element 32 formed by arranging the capsules 20 is sandwiched.

  As shown in FIG. 1, the active matrix substrate 30 includes a display unit 5 in which a plurality of pixels 40 are arranged in a matrix. Around the display unit 5, a scanning line driving circuit 61 and a data line driving circuit 62 are arranged. The display unit 5 is formed with a plurality of scanning lines 36 extending from the scanning line driving circuit 61 and a plurality of data lines 38 extending from the data line driving circuit 62, and the pixels 40 corresponding to the intersecting positions thereof. Is provided. The pixel 40 includes a selection transistor 41 connected to the scanning line 36 and the data line 38, and a pixel electrode 35 (second conductive layer) connected to the selection transistor 41.

The scanning line driving circuit 61 is connected to each pixel 40 via m scanning lines 36 (G1, G2,..., Gm), and sequentially scans the scanning lines 36 from the first row to the m-th row. A selection signal that defines the ON timing of the selection transistor 41 provided in the pixel 40 is supplied via the selected scanning line 36.
The data line driving circuit 62 is connected to each pixel 40 via n data lines 38 (S1, S2,..., Sn), and receives an image signal defining pixel data for each pixel 40. Supply.

  As shown in FIG. 2, in the pixel 40, the scanning line 36 and the data line 38 extend along the edge of the pixel electrode 35 having a rectangular shape in plan view. A selection transistor 41 is formed in the vicinity of the intersection between the scanning line 36 and the data line 38.

  The selection transistor 41 is formed by branching the organic semiconductor layer 41a, the source electrode 41b formed by branching the data line 38, the drain electrode 41c (element electrode, first conductive layer), and the scanning line 36. A gate electrode 41d. The organic semiconductor layer 41a is formed over the source electrode 41b and the drain electrode 41c, and the gate electrode 41d is formed on the organic semiconductor layer 41a in a region between the source electrode 41b and the drain electrode 41c. The drain electrode 41c is connected to the pixel electrode 35 via a connection portion 35a embedded in the contact hole 34a.

Looking at the cross-sectional structure shown in FIG. 2B, the active matrix substrate 30 includes a substrate body 30A as a base.
A source electrode 41b (data line 38) and a drain electrode 41c are formed on one surface (illustrated upper surface) of the substrate body 30A. Between the source electrode 41b and the drain electrode 41c, an organic semiconductor layer 41a is formed so as to partially run over these electrodes 41b and 41c. A gate insulating film 33 is formed to cover the source electrode 41b, the drain electrode 41c, and the organic semiconductor layer 41a. A gate electrode 41 d (scanning line 36) is formed on the gate insulating film 33 at a position facing the organic semiconductor layer 41 a. A planarizing film 34 is formed so as to cover the gate electrode 41 d (scanning line 36) and the gate insulating film 33.

  A pixel electrode 35 is formed on the planarizing film 34. A contact hole 34a (concave portion) that penetrates the planarizing film 34 and the gate insulating film 33 and reaches the drain electrode 41c is formed. In the contact hole 34a, a connection portion 35a formed by pushing a part of the pixel electrode 35 toward the substrate body 30A is disposed. The pixel electrode 35 and the drain electrode 41c are connected through the connection part 35a.

On the other hand, the counter substrate 31 includes a substrate body 31A as a base.
A common electrode 37 is formed on one surface (lower surface in the drawing) of the substrate body 31A. An electrophoretic element 32 is formed on the common electrode 37. The electrophoretic element 32 is bonded to the pixel electrode 35 and the planarizing film 34 of the active matrix substrate 30 via an adhesive layer 39.
In the present embodiment, the electrophoretic element 32 is formed as an electrophoretic sheet that is formed in advance on the counter substrate 31 side and includes an adhesive layer 39 for bonding to the active matrix substrate 30. Therefore, the adhesive layer 39 is provided only on the active matrix substrate 30 side of the electrophoretic element 32.

  The substrate body 30A of the active matrix substrate 30 is a substrate made of glass, plastic, or the like, and is not necessarily transparent because it is disposed on the side opposite to the image display surface. In particular, in the case of the present embodiment, since the selection transistor 41 is an organic transistor having the organic semiconductor layer 41a, a plastic substrate that is inexpensive, lightweight, and excellent in flexibility can be used.

The pixel electrode 35 is an electrode for applying a driving voltage to the electrophoretic element 32, and is obtained by stacking nickel plating and gold plating in this order on a Cu (copper) foil, Al, ITO (indium tin oxide), or the like. It is formed using. Further, Cr, Ta, Mo, Nb, Ag, Pt, Pd, In, Nd and their alloys, conductive oxides such as InO ₂ and SnO ₂ , conductive polymers such as polyaniline, polypyrrole, polythiophene, polyacetylene, Carbon black with conductive polymer added with acids such as hydrochloric acid, sulfuric acid, sulfonic acid, Lewis acids such as PF ₆ , AsF ₅ , FeCl ₃ , halogen atoms such as iodine, metal atoms such as sodium potassium, etc. Alternatively, a conductive composite material in which metal particles are dispersed may be used.
The scanning line 36 and the data line 38 can be formed using the same material as that of the pixel electrode 35 described above.

Examples of the organic semiconductor material constituting the organic semiconductor layer 41a include poly (3-alkylthiophene), poly (3-hexylthiophene) (P3HT), poly (3-octylthiophene), and poly (2,5-thienylene). Vinylene) (PTV), poly (para-phenylene vinylene) (PPV), poly (9,9-dioctylfluorene) (PFO), poly (9,9-dioctylfluorene-co-bis-N, N ′-(4 -Methoxyphenyl) -bis-N, N'-phenyl-1,4-phenylenediamine) (PFMO), poly (9,9-dioctylfluorene-co-benzothiadiazole) (BT), fluorene-triallylamine copolymer , Triallylamine-based polymer, poly (9,9-dioctylfluorene-co-dithiophene) (F8T2) Fluorene - bithiophene copolymer of polymeric organic semiconductor materials also C ₆₀ or metal phthalocyanine or a substituted derivative thereof, or, anthracene, tetracene, pentacene, acene molecule materials such as hexacene or, alpha-oligothiophenes, specifically One kind or a mixture of two or more kinds of low molecular organic semiconductors such as quarterthiophene (4T), sexithiophene (6T), and octathiophene can be used.

  The constituent materials of the gate insulating film 33 and the planarizing film 34 are not particularly limited as long as they are insulating materials. As such an insulating material, either an organic material or an inorganic material can be used. However, since an organic insulating film generally easily forms a good interface with an organic semiconductor layer, an organic insulating material is preferably used. Suitable organic insulating materials for the gate insulating film 33 and the planarizing film 34 include polyvinyl alcohol, polyethylene, polypropylene, polybutylene, polystyrene, polymethyl methacrylate (acrylic), polyimide, polyvinylphenol, polycarbonate, paraxylylene, and the like. Examples of the inorganic insulating material include silicon oxide and silicon nitride. Two or more of these may be used in combination.

  The substrate body 31A of the counter substrate 31 is a substrate made of glass, plastic, or the like, and is a transparent substrate because it is disposed on the image display side. The common electrode 37 is an electrode for applying a voltage to the electrophoretic element 32 together with the pixel electrode 35, and is formed of MgAg (magnesium silver), ITO (indium tin oxide), IZO (indium zinc oxide) or the like. It is a transparent electrode.

  The microcapsule 20 has a particle size of, for example, about 50 μm and encloses therein a dispersion medium 21, a plurality of white particles (electrophoretic particles) 27, and a plurality of black particles (electrophoretic particles) 26. It is a spherical body. As shown in FIG. 2B, the microcapsule 20 is sandwiched between the common electrode 37 and the pixel electrode 35, and one or a plurality of microcapsules 20 are arranged in one pixel 40.

The outer shell (wall film) of the microcapsule 20 is formed using a transparent polymer resin such as acrylic resin such as polymethyl methacrylate and polyethyl methacrylate, urea resin, and gum arabic.
The dispersion medium 21 is a liquid that disperses the white particles 27 and the black particles 26 in the microcapsules 20. Examples of the dispersion medium 21 include water, alcohol solvents (methanol, ethanol, isopropanol, butanol, octanol, methyl cellosolve, etc.), esters (ethyl acetate, butyl acetate, etc.), ketones (acetone, methyl ethyl ketone, methyl isobutyl ketone, etc.). ), Aliphatic hydrocarbons (pentane, hexane, octane, etc.), alicyclic hydrocarbons (cyclohexane, methylcyclohexane, etc.), aromatic hydrocarbons (benzene, toluene, benzenes having a long-chain alkyl group ( Xylene, hexylbenzene, hebutylbenzene, octylbenzene, nonylbenzene, decylbenzene, undecylbenzene, dodecylbenzene, tridecylbenzene, tetradecylbenzene)), halogenated hydrocarbons (methylene chloride, chloroform, tetrachloride) Element, and 1,2-dichloroethane), can be exemplified a carboxylate, it may be other oils. These substances can be used alone or as a mixture, and a surfactant or the like may be further blended.

The white particles 27 are particles (polymer or colloid) made of a white pigment such as titanium dioxide, zinc white, and antimony trioxide, and are used, for example, by being negatively charged. The black particles 26 are particles (polymer or colloid) made of a black pigment such as aniline black or carbon black, and are used by being charged positively, for example.
These pigments include electrolytes, surfactants, metal soaps, resins, rubbers, oils, varnishes, compound charge control agents, titanium-based coupling agents, aluminum-based coupling agents, silanes as necessary. A dispersant such as a system coupling agent, a lubricant, a stabilizer, and the like can be added.
Further, instead of the black particles 26 and the white particles 27, for example, pigments such as red, green, and blue may be used. According to such a configuration, red, green, blue, or the like can be displayed on the display unit 5.

(Production method)
Next, a method for manufacturing the electrophoretic display device 100 of the present embodiment will be described with reference to the drawings.
3 to 5 are cross-sectional views showing the manufacturing process of the electrophoretic display device 100 of the present embodiment. Note that the cross-sectional views shown in FIGS. 3 to 5 correspond to positions along the line AA ′ shown in FIG. 2.

First, as shown in FIG. 3A, a substrate body 30A is prepared. The material of the substrate body 30A is not particularly limited, but it is preferable to use a flexible substrate such as a plastic substrate in the manufacturing method of this embodiment.
Next, the source electrode 41b (data line 38) and the drain electrode 41c are pattern-formed on one surface (the front surface in the drawing) of the substrate body 30A. Specifically, after forming a metal film such as Al, Ti, Cr, or a laminated film of these metals using a film forming method such as a sputtering method or a CVD method, patterning is performed by a photolithography process and an etching process, The planar scanning line 36, source electrode 41b, and drain electrode 41c shown in FIG. 2A are formed. Alternatively, the wiring may be formed by applying an ink containing metal particles and carbon to a predetermined pattern using a printing method such as a droplet discharge method, and drying and solidifying the ink.

  Next, as shown in FIG. 3B, the organic semiconductor material 41a is formed by disposing the organic semiconductor material at a predetermined position on the substrate body 30A. Organic semiconductor material film formation methods include vacuum deposition, molecular beam epitaxial growth, CVD, sputtering, plasma polymerization, electrolytic polymerization, chemical polymerization, ion plating, spin coating, casting, and pulling Examples thereof include, but are not limited to, the Langmuir Blodget method, the spray method, the ink jet method, the roll coat method, the bar coat method, the dispense method, the silk screen method, and the dip coat method. Among these methods, a method of coating and forming a semiconductor layer from a liquid material using an ink jet method or a dispensing method is preferable because the film thickness can be controlled most easily. In addition, after apply | coating the liquid material containing organic-semiconductor material on 30 A of board | substrate bodies, it is set as a solid organic-semiconductor layer by heat processing.

  Next, as shown in FIG. 3C, a gate insulating film 33 covering the organic semiconductor layer 41a and the like is formed. As a method for forming the gate insulating film 33, the same method as that for forming the organic semiconductor material described above can be used. In the present embodiment, since the gate insulating film 33 is formed on the entire upper surface of the substrate body 30A in the drawing, it is preferable to form the gate insulating film 33 using a spin coating method or a vapor deposition method in terms of film forming efficiency.

  Next, as illustrated in FIG. 3D, the gate electrode 41 d (scanning line 36) is formed on the gate insulating film 33. The gate electrode 41d can be formed by a process similar to the process for forming the source electrode 41b and the drain electrode 41c described above. That is, a method of etching the conductive film of the constituent material of the gate electrode 41d (scanning line 36) described above, a method of depositing the conductive film through a metal through mask having a hole in a predetermined shape, or metal particles And an ink containing carbon can be selectively applied by an ink jet method or the like.

Next, as shown in FIG. 3E, a planarizing film 34 that covers the gate electrode 41d and the like is formed. As a method for forming the planarizing film 34, the same method as the method for forming the organic semiconductor material described above can be used. In the present embodiment, since the planarizing film 34 is formed on the entire upper surface of the substrate body 30A in the figure, it is preferable to form the planarizing film 34 by using a spin coat method or a vapor deposition method in terms of film formation efficiency.
The gate insulating film 33 and the planarizing film 34 formed in FIGS. 3C and 3E constitute an interlayer insulating film according to the present invention.

Next, as shown in FIG. 4A, the pixel electrode 35 is formed on the planarizing film 34. The pixel electrode 35 can be formed by a process similar to the process of forming the source electrode 41b and the drain electrode 41c described above. That is, a method of forming the conductive film of the constituent material of the pixel electrode 35 described above by etching, a method of depositing the conductive film through a metal through mask having a hole in a predetermined shape, or metal particles, ITO particles, carbon An ink containing the above can be selectively applied by an inkjet method or the like.
In the case of this embodiment, the pixel electrode 35 is formed to have a film thickness larger than the total thickness of the gate insulating film 33 and the planarizing film 34.

Next, as shown in FIG. 4B, processing by the micro punch 150 is performed from the surface of the pixel electrode 35. The micro punch 150 is a tool for fine processing having a processing needle 150a having a diameter of 5 to 10 μm at the tip of the base 150b, and is suitably used as a pressing member according to the present invention.
As the micro punch 150, one having only one processing needle 150a may be used, but as shown in FIG. 6, a micro punch 150 in which a plurality of processing needles 150a are arranged in an array on the base 150b is used. You can also. In the micro punch 150 shown in FIG. 6, the processing needle 150a is provided for each region 140 corresponding to the pixel 40 of the active matrix substrate 30, and the contact holes 34a of the plurality of pixels 40 can be formed at once. is there.

  The micro punch 150 is aligned with a region where the pixel electrode 35 and the drain electrode 41 c overlap in a plane, and the processing needle 150 a is pushed into the pixel electrode 35. Then, as shown in FIG. 4C, a part (35a) of the pixel electrode 35 pressed by the processing needle 150a is separated from the pixel electrode 35 and pushed into the planarizing film 34 side. When the micro punch 150 is further pushed in, the pushed portion (35a) penetrates the planarizing film 34 and the gate insulating film 33 and reaches the drain electrode 41c. As a result, a contact hole 34a (concave portion) that penetrates the pixel electrode 35, the planarization film 34, and the gate insulating film 33 and reaches the drain electrode 41c is formed by physical processing using micro punching.

  In the contact hole 34a, a connection portion 35a composed of a part of the pixel electrode 35 pushed by the micro punch 150 is disposed. In the case of the present embodiment, as described above, since the film thickness of the pixel electrode 35 is larger than the total film thickness of the planarization film 34 and the gate insulating film 33, the pushed-in connection part 35a is connected to the contact hole 34a. The pixel electrode 35 is in contact with the drain electrode 41c at the bottom of the contact hole 34a and at the opening end side of the contact hole 34a. That is, the pixel electrode 35 and the drain electrode 41c are connected via the connection portion 35a.

  The processing using the micro punch 150 may be performed at least until the connection portion 35a comes into contact with the drain electrode 41c. However, as shown in FIG. 4C ', the pressed connection portion 35a is formed on the drain electrode 41c. It may be penetrated.

  When the micro punch 150 is pushed in, the connecting portion 35a separated from the pixel electrode 35 enters the drain electrode 41c side while partially destroying the planarizing film 34 and the gate insulating film 33. At this time, a part of the planarization film 34 and the gate insulating film 33 crushed by the connection portion 35a may exist at the front end of the connection portion 35a in the traveling direction. For this reason, if the processing is stopped at a position where the connection portion 35a reaches the drain electrode 41c, there is a risk of poor conduction due to the insulating film sandwiched between the connection portion 35a and the drain electrode 41c.

  Therefore, as shown in FIG. 4C ′, by passing through the connecting portion 35a through the drain electrode 41c, the crushed planarization film 34 and a part of the gate insulating film 33 are more than the drain electrode 41c in the substrate body. The structure can be obtained in which the connection portion 35a and the drain electrode 41c are securely connected to each other.

  Through the above steps, the active matrix substrate 30 (semiconductor device) of the above embodiment can be manufactured.

  Next, as shown in FIG. 5A, a counter substrate 31 is prepared. A common electrode 37 made of a transparent conductive material such as ITO, an electrophoretic element 32, and an adhesive layer 39 are formed on one surface side (the lower surface side in the drawing) of the counter substrate 31. Then, the adhesive layer 39 of the counter substrate 31 and the pixel electrode 35 of the active matrix substrate 30 manufactured as described above are opposed to each other, and the counter substrate 31 and the active matrix substrate 30 are bonded to each other, so that FIG. As shown in FIG. 4, the electrophoretic display device 100 of this embodiment can be manufactured.

  As described above in detail, according to the manufacturing method of the active matrix substrate 30 (semiconductor device) and the electrophoretic display device 100 (electro-optical device) of the present embodiment, the pixel electrode 35 (second conductive layer) is formed. After that, a part of the pixel electrode 35 is separated by the micro punch 150 to form a connection portion 35a, and the connection portion 35a is pushed toward the drain electrode 41c (first conductive layer) side, whereby the pixel electrode 35 and the drain electrode 41c are connected. A conductively connected structure is obtained.

  Therefore, according to the present invention, the pixel electrode 35 and the drain electrode 41c can be connected by physical processing using the micro punch 150, and a contact hole for conductive connection is formed using a photolithography method and an etching method. There is no need to do. Therefore, it is possible to avoid a problem in peeling of a resist mask used for etching or deterioration of the organic semiconductor layer 41a during exposure in a photolithography process, and the active matrix substrate 30 and the electrophoretic display device 100 can be manufactured with high yield. Can be manufactured.

  Further, since no resist mask is used, the gate insulating film 33, the planarizing film 34, the drain electrode 41c, and the like do not come into contact with a chemical solution such as a resist stripping solution. Therefore, in the present invention, it is possible to employ a material having low chemical resistance that could not be used conventionally, and there are many options for improving performance and reducing cost.

(Modification)
Next, a modification of the present invention will be described with reference to FIG.
FIG. 7A to FIG. 7D are views showing active matrix substrates 30a to 30d according to modifications of the present invention.
This modification is obtained by changing the configuration of the connection structure portion between the pixel electrode 35 and the drain electrode 41c in the active matrix substrate 30 according to the previous embodiment. Therefore, in FIG. 7, the same reference numerals are given to the same components as those in FIGS. 1 to 5, and detailed description thereof will be omitted.

  First, the active matrix substrate 30a shown in FIG. 7A is disposed on the first connection portion 35a connected to the drain electrode 41c and the first connection portion 35a, and the first connection portion 35a and the pixel electrode are arranged. 35 and a second connecting portion 35b connected to the second connecting portion 35b. The drain electrode 41c and the pixel electrode 35 are connected by the first and second connection portions 35a and 35b.

  In the active matrix substrate 30a shown in FIG. 7A, the film thickness of the pixel electrode 35 is smaller than the total film thickness of the gate insulating film 33 and the planarizing film 34. Therefore, when a part of the pixel electrode 35 is pushed by the micro punch 150, the first connection portion 35a separated from the pixel electrode 35 is separated from the pixel electrode 35 and enters the contact hole 34a.

  Further, even when the difference between the film thickness of the pixel electrode 35 and the total film thickness of the gate insulating film 33 and the planarizing film 34 is small, the first connection part 35a is crushed or the first connection part 35a. Or the like through the drain electrode 41c, the connection between the first connection portion 35a and the pixel electrode 35 may be lost.

Therefore, in the present modification, the second connection portion 35b made of a conductive material is disposed on the first connection portion 35a, and the drain electrode 41c and the pixel electrode 35 are connected by the first and second connection portions 35a and 35b. Connected configuration.
With such a configuration, the pixel electrode 35 and the drain electrode 41c can be reliably connected, and a highly reliable semiconductor device and electro-optical device can be obtained. In addition, it is not necessary to form the pixel electrode 35 to be excessively thick, which is an advantageous configuration for reducing the manufacturing cost and improving the manufacturing yield.

As a method for forming the second connection portion 35b, either a liquid phase method or a gas phase method may be used. When the liquid phase method is used, it is preferable to use a method capable of selectively applying a liquid material such as an ink jet method or a dispensing method. As a liquid material used in the liquid phase method, a dispersion liquid in which ITO particles or metal particles are dispersed, or a metal complex solution can be used.
On the other hand, also in the case of using a vapor phase method, it is preferable to use a mask vapor deposition method or the like capable of forming a film selectively.

  In FIG. 7A, the case where the first connecting portion 35a is pushed by the micro punch 150 to a position away from the pixel electrode 35 has been described. However, as shown in FIG. Even when the film thickness is sufficiently large and the first connecting portion 35a and the pixel electrode 35 can be brought into contact with each other, it is effective to provide the second connecting portion 35b.

  In the active matrix substrate 30b shown in FIG. 7B, since the pixel electrode 35 has a large thickness, the pixel electrode 35 and the first connection portion 35a are not formed even if the first connection portion 35a penetrates the drain electrode 41c. It comes into contact. However, the first connection portion 35a is formed by separating a part of the pixel electrode 35 with the micro punch 150, and is connected to the pixel electrode 35 only by the peripheral wall thereof. Therefore, as shown in the drawing, the second connection portion 35b is disposed in the contact hole 34a, and the first connection portion 35a and the pixel electrode 35 are connected via the second connection portion 35b. The electrical connection between the drain electrode 41c and the pixel electrode 35 can be made more reliable.

Next, the active matrix substrate 30c shown in FIG. 7C has a contact hole 34a penetrating the active matrix substrate 30c in the thickness direction, and a connection portion 35b filled in the contact hole 34a.
In the present invention, since the contact hole 34a is formed by physical processing, the micro punch 150 may penetrate the active matrix substrate 30c when the contact hole is formed. Further, when laser processing or ion beam (charged particle beam) processing is used for forming the contact hole, the substrate can be penetrated relatively easily.

  When the contact hole 34a penetrating the active matrix substrate 30c is formed, the connection portion 35a consisting of a part of the pixel electrode 35 is lost. Therefore, in the modification shown in FIG. A connection portion 35b is formed by filling a conductive material in 34a, and the drain electrode 41c and the pixel electrode 35 are connected.

  Even in such a configuration, the contact hole 34a can be formed without using a photolithography process and an etching process, and the drain electrode 41c and the pixel electrode 35 are connected to each other by the connection portion 35b provided in the contact hole 34a. Can be securely connected. Note that the connection portion 35b shown in FIG. 7C can also be formed by using either the liquid phase method or the gas phase method described above.

Next, FIG. 7D shows a configuration in which the drain electrode 41c and the pixel electrode 35 are connected only by the connecting portion 35b when the contact hole 34a does not penetrate the active matrix substrate 30d.
When laser processing or ion beam processing is used for forming the contact hole, a portion irradiated with the laser or ion beam is melted and evaporated, and only a concave portion is formed. Also in this case, the drain electrode 41c and the pixel electrode 35 can be connected by forming the connection portion 35b in the contact hole 34a using the liquid phase method or the gas phase method.

(Circuit board)
Next, FIG. 8 is a diagram showing an embodiment of a circuit board according to the present invention. Fig.8 (a) is a top view which shows the flexible circuit board based on Embodiment, FIG.8 (b) is sectional drawing of the flexible circuit board in the position which follows the BB 'line | wire of Fig.8 (a). is there. FIG. 8C is a cross-sectional view showing the printed circuit board.

  First, a flexible circuit board 200 shown in FIGS. 8A and 8B includes a flexible substrate 210 made of a resin film or the like, and a wiring-like first circuit formed on one surface of the flexible substrate 210. One conductive layer 201 and a wiring-like second conductive layer 202 formed on the other surface of the flexible substrate. Each first conductive layer 201 is connected to a corresponding second conductive layer 202 and a connection portion 202 a disposed inside a via 210 a (concave portion or contact hole) formed through the flexible substrate 210. It is connected.

  That is, the flexible circuit board 200 is a double-sided board in which conductive layers are formed on both sides, and a connection structure between a first conductive layer 201 formed on one side and a second conductive layer 202 formed on the other side. In addition, the same structure as that of the active matrix substrate 30 of the previous embodiment is provided.

  The connection part 202a is configured to press the micro punch 150 (see FIGS. 4 and 6) from the surface of the second conductive layer 202 after forming the first conductive layer 201 and the second conductive layer 202 on the flexible substrate 210. Formed with. That is, the via part 210a is formed by pushing the connecting part 202a formed of a part of the second conductive layer 202 and penetrating the flexible substrate 210, and the first conductive layer is formed by the connecting part 202a disposed inside the via 210a. 201 and the second conductive layer 202 are connected.

  According to the flexible circuit board 200 having the above configuration, it is not necessary to use a photolithography process or an etching process to connect the first conductive layer 201 and the second conductive layer 202 formed on both surfaces. It is possible to avoid the occurrence of malfunctions. Moreover, since these processes are not used, it can be manufactured at low cost.

  Also in the flexible circuit board 200, a part of the connection portion 202a may be embedded in the first conductive layer 201, or the connection portion 202a may be penetrated through the first conductive layer 201. Alternatively, a conductive material may be disposed over the connection portion 202a to form the second connection portion, thereby reinforcing the conductivity. Furthermore, instead of the connection part 202a made of a part of the second conductive layer 202, a connection part made of a conductive material may be arranged in the via 210a. Furthermore, laser processing or ion beam processing may be used as a method of forming the via 210a.

Next, the printed circuit board 300 shown in FIG. 8C covers the printed board 310 made of glass epoxy resin, the first conductive layer 301 formed on the printed board 310, and the first conductive layer 301. An interlayer insulating film 303 formed and a second conductive layer 302 formed on the interlayer insulating film 303 are provided. The first conductive layer 301 and the second conductive layer 302 are connected via a connecting portion 302a disposed in a contact hole 303a formed through the second conductive layer 302 and the interlayer insulating film 303. .
The printed circuit board 300 of this example also has a connection structure between the first conductive layer 301 and the second conductive layer 302 having the same structure as the active matrix substrate 30 of the previous embodiment.

  The connection portion 303a is formed by laminating the first conductive layer 301, the interlayer insulating film 303, and the second conductive layer 302 on the printed circuit board 310, and then the micro punch 150 (see FIGS. 4 and 6) from the surface of the second conductive layer 302. ). That is, a contact hole 303a is formed by pushing a connection portion 302a formed of a part of the second conductive layer 302 and penetrating the interlayer insulating film 303, and the first conductive layer is formed by the connection portion 302a disposed inside the contact hole 303a. The layer 301 and the second conductive layer 302 are connected.

  According to the printed circuit board 300 having the above-described configuration, it is not necessary to use a photolithography process or an etching process to connect the first conductive layer 301 and the second conductive layer 302 stacked via the interlayer insulating film 303. It is possible to avoid problems caused by these processes. Moreover, since these processes are not used, it can be manufactured at low cost.

  Note that also in the printed circuit board 300, a part of the connection portion 302 a may be embedded in the first conductive layer 301, or the connection portion 302 a may penetrate the first conductive layer 301. Alternatively, a conductive material may be provided over the connection portion 302a to form the second connection portion, and the conductivity may be reinforced. Furthermore, instead of the connection portion 302a made of a part of the second conductive layer 302, a connection portion made of a conductive material may be arranged in the contact hole 303a. Furthermore, laser processing or ion beam processing may be used as a method for forming the contact hole 303a.

(Electronics)
Next, a case where the electrophoretic display device 100 of the above embodiment is applied to an electronic device will be described.
FIG. 9A is a perspective view illustrating a configuration of the electronic paper 1100. An electronic paper 1100 includes the electrophoretic display device 100 of the above embodiment in a display area 1101. The electronic paper 1100 is flexible and includes a main body 1102 made of a rewritable sheet having the same texture and flexibility as conventional paper.

  FIG. 9B is a perspective view showing the configuration of the electronic notebook 1200. An electronic notebook 1200 is obtained by bundling a plurality of the electronic papers 1100 and sandwiching them between covers 1201. The cover 1201 includes display data input means (not shown) for inputting display data sent from an external device, for example. Thereby, according to the display data, the display content can be changed or updated while the electronic paper is bundled.

According to the electronic paper 1100 and the electronic notebook 1200 described above, since the electrophoretic display device 100 according to the present invention is employed, the electronic device includes a display unit that is excellent in manufacturability and can be provided at low cost.
In addition, said electronic device illustrates the electronic device which concerns on this invention, Comprising: The technical scope of this invention is not limited. For example, the electrophoretic display device according to the present invention can be suitably used for a display portion of an electronic device such as a mobile phone or a portable audio device.

  30, 30a, 30b, 30c, 30d Active matrix substrate (semiconductor device), 100 electrophoretic display device (electro-optical device), 200 flexible circuit board (circuit board), 300 printed circuit board (circuit board), 32 electrophoretic element , 34a Contact hole (recessed portion), 35 pixel electrode (second conductive layer), 35a, 35b connection portion, 40 pixel, 41c drain electrode (element electrode, first conductive layer), 150 micro punch (pressing member)

Claims (18)

A method of manufacturing a semiconductor device having a semiconductor layer on a substrate,
A conductive layer forming step of sequentially forming a first conductive layer, an interlayer insulating film, and a second conductive layer on the substrate;
A contact hole forming step of forming a recess reaching the first conductive layer through the second conductive layer and the interlayer insulating film by performing physical processing from the surface of the second conductive layer;
A method for manufacturing a semiconductor device, comprising: In the contact hole forming step,
2. The pressing member is pushed into the surface of the second conductive layer to penetrate the interlayer insulating film, so that the pressed portion of the second conductive layer reaches at least the first conductive layer. The manufacturing method of the semiconductor device as described in any one of.   3. The method of manufacturing a semiconductor device according to claim 2, wherein the pressed portion of the second conductive layer is made to penetrate the first conductive layer.   2. The method of manufacturing a semiconductor device according to claim 1, wherein, in the contact hole forming step, the recess is formed by processing using a light beam or a charged particle beam.   5. The method of manufacturing a semiconductor device according to claim 1, further comprising a connecting portion forming step of disposing a conductive material in the concave portion after the contact hole forming step.   In the contact hole forming step, a through hole penetrating the first and second conductive layers and the interlayer insulating film and the substrate is formed, and in the connecting portion forming step, the conductive material is placed in the through hole. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the semiconductor device is disposed. Forming an organic transistor and an interlayer insulating film covering at least a part of the device electrode of the organic transistor on a substrate, and forming a pixel electrode on the interlayer insulating film;
Forming a recess that penetrates at least the pixel electrode and the interlayer insulating film and reaches the element electrode by performing physical processing from the surface of the pixel electrode;
A method for manufacturing an electro-optical device. Forming an organic transistor and an interlayer insulating film covering at least a part of the device electrode of the organic transistor on a substrate, and forming a pixel electrode on the interlayer insulating film;
Forming a recess by penetrating the interlayer insulating film by pressing a pressing member on the surface of the pixel electrode, and allowing the pressed portion of the pixel electrode to reach at least the element electrode;
A method for manufacturing an electro-optical device.   The method of manufacturing an electro-optical device according to claim 7, further comprising a step of disposing a conductive material in the recess. Forming a first conductive layer on one surface of the substrate and forming a second conductive layer on the other surface;
A contact hole forming step of forming a recess reaching the first conductive layer through the second conductive layer and the substrate by performing physical processing from the surface of the second conductive layer;
A method of manufacturing a circuit board, comprising: A conductive layer forming step of sequentially stacking a first conductive layer, an interlayer insulating film, and a second conductive layer on the substrate;
A contact hole forming step of forming a recess reaching the first conductive layer through the second conductive layer and the interlayer insulating film by performing physical processing from the surface of the second conductive layer;
A method of manufacturing a circuit board, comprising: A semiconductor device having a semiconductor layer, a first conductive layer, an interlayer insulating film, and a second conductive layer, which are sequentially stacked on a substrate,
A recess that penetrates at least the second conductive layer and the interlayer insulating film and reaches the first conductive layer, and a connection that is disposed in the recess and connected to the first conductive layer and the second conductive layer And a semiconductor device. An electro-optical device comprising an organic transistor, an interlayer insulating film covering at least a part of the device electrode of the organic transistor, and a pixel electrode formed on the interlayer insulating film on a substrate,
A recess that penetrates at least the pixel electrode and the interlayer insulating film and reaches the device electrode; and a connection portion that is disposed in the recess and is connected to the device electrode and the pixel electrode. An electro-optical device. An electro-optical device comprising an organic transistor, an interlayer insulating film covering at least a part of the device electrode of the organic transistor, and a pixel electrode formed on the interlayer insulating film on a substrate,
An electro-optical device, wherein a part of the pixel electrode is pushed into the substrate side, penetrates the interlayer insulating film, and is in contact with the element electrode.   The electro-optical device according to claim 14, wherein the pixel electrode and the element electrode are connected by a part of the pressed pixel electrode. A circuit board having a first conductive layer formed on one surface of a substrate and a second conductive layer formed on the other surface,
A recess penetrating at least the second conductive layer and the substrate and reaching the first conductive layer; and a connecting portion disposed in the recess and connected to the first conductive layer and the second conductive layer; The circuit board characterized by having. A circuit board having a first conductive layer, an interlayer insulating film, and a second conductive layer, which are sequentially stacked on the substrate,
A recess that penetrates at least the second conductive layer and the interlayer insulating film and reaches the first conductive layer, and a connection that is disposed in the recess and connected to the first conductive layer and the second conductive layer And a circuit board.   An electronic apparatus comprising the semiconductor device according to claim 12, the electro-optical device according to any one of claims 13 to 15, or the circuit board according to claim 16 or 17.

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