JP2011222796A - Manufacturing method for substrate, manufacturing method for semiconductor device, and electrooptical device - Google Patents

Abstract

A method for manufacturing a substrate capable of forming an opening inclined in an arbitrary direction, a method for manufacturing a semiconductor device, and an electro-optical device including the semiconductor device to which the method is applied.
A method of manufacturing an element substrate 101 according to this application example includes a second insulating film that covers a TFT 110 as a semiconductor device provided on the element substrate 101 and is provided with a hole 104a as a first opening. Using the interlayer insulating film 104 as a mask, dry etching is applied to the gate insulating film 103 as the first insulating film from one direction intersecting the surface normal line 101a of the element substrate 101 to communicate with the hole 104a and to the drain electrode of the TFT 110 A hole 103a is formed as a second opening that opens to 110d.
[Selection] Figure 6

Description

  The present invention relates to a substrate manufacturing method, a semiconductor device manufacturing method, and an electro-optical device.

  As a method for manufacturing the semiconductor device, an interlayer insulating film includes a lower electrode disposed on a glass substrate, and an upper electrode disposed on both sides of an interlayer insulating film and a planarizing film disposed on the lower electrode. Forming a first contact hole penetrating to the lower electrode, and forming a second contact hole penetrating to the lower electrode in the planarizing film, the lower electrode of the second contact hole A method of manufacturing a thin film semiconductor device in which a side opening is formed inside an opening of a first contact hole is known (Patent Document 1).

  According to the above method for manufacturing a thin film semiconductor device, there is no step at the interface between the interlayer insulating film and the planarizing film on the inner wall of the second contact hole, so the upper electrode is formed so as to fill the second contact hole. Even so, the upper electrode does not cause a so-called disconnection.

JP 2000-340652 A

On the other hand, in the above-described conventional method for manufacturing a thin film semiconductor device, the first contact hole and the second contact hole are formed using the photo-etching technique, so that at least two masks having different openings are required. To do. In other words, a photoetching process using at least two masks must be performed, and there is a problem that the manufacturing process such as mask positioning becomes complicated.
Further, when the second contact hole is formed, the position of the second contact hole must be aligned unless the second contact hole forming mask is accurately aligned with the previously formed first contact hole. In the case of deviation, there is a problem that a part of the first contact hole may be exposed in the opening to cause a step.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

  Application Example 1 A substrate manufacturing method according to this application example includes a first layer and a second layer stacked on a substrate, and an opening that penetrates the first layer and the second layer. A step of forming a first opening constituting the opening in the second layer, and using the second layer in which the first opening is formed as a mask, Dry etching is performed from one direction intersecting the surface normal of the substrate to form a second opening that is inclined in the first direction and communicates with the first opening in the first layer. And a step of performing.

  According to this method, since the second layer in which the first opening is formed is used as a mask and is left on the substrate, the opening formed by the first opening and the second opening is made the conventional method. It can be formed with a smaller number of masks. Further, dry etching has etching anisotropy, and if one direction intersecting the surface normal of the substrate, that is, an etching direction (angle) with respect to the substrate is set, the dry etching is inclined in the one direction. The second opening can be formed in communication with the first opening.

Application Example 2 In the method for manufacturing a substrate according to the application example described above, the etching rate of the first layer in the dry etching is faster than the etching rate of the second layer.
According to this method, since the first layer is etched earlier than the second layer used as the mask, the second opening inclined in one direction can be formed with high dimensional accuracy. In other words, even if the one direction in the dry etching is arbitrarily changed, the second opening inclined in the arbitrary direction can be stably formed.

Application Example 3 In the substrate manufacturing method according to the application example described above, the etching rate of the first layer in the dry etching may be slower or equal to the etching rate of the second layer.
According to this method, in the dry etching, the etching of the second layer proceeds together with the etching of the first layer. Therefore, the first opening formed in the second layer expands as the dry etching progresses. Accordingly, the range in which the first layer is dry-etched expands in a planar manner, so that a second opening having an inclined surface that is gentler than the one direction that is the etching direction is formed. In other words, this is effective when it is desired to obtain an inclined surface that is looser than one direction in the opening formed by the first opening and the second opening.

Application Example 4 In the substrate manufacturing method according to the application example described above, the etching rate in the direction orthogonal to the thickness direction is higher than the etching rate in the thickness direction of the first layer on the substrate in the dry etching. In the case where the etching rate is faster, the etching rate in the direction perpendicular to the thickness direction is equal to or slower than the etching rate in the thickness direction. It is desirable to increase the tilt angle.
When the etching rate in the direction orthogonal to the thickness direction is faster than the etching rate in the thickness direction on the substrate of the first layer, a step (over-level) is present at the interface between the first layer and the second layer. Hang) is easily formed. Then, when the conductive film is formed in the opening, the conductive film is easily cut by a step (overhang).
In this method, since the inclination angle in one direction, which is the etching direction in dry etching, is increased, it is difficult to cause the step.

  Application Example 5 A method for manufacturing a semiconductor device according to this application example includes a semiconductor layer provided on a substrate, a first insulating film and a second insulating film sequentially stacked so as to cover at least the semiconductor layer, and the first A method of manufacturing a semiconductor device comprising: an opening penetrating through one insulating film and the second insulating film and overlapping one of a source region and a drain region of the semiconductor layer in plan view, A step of forming a first opening constituting the opening in two insulating films, and a surface normal of the substrate intersecting with the second insulating film in which the first opening is formed as a mask. Forming a second opening that is inclined in the one direction in the first insulating film and communicates with the first opening. .

  According to this method, since the second insulating film in which the first opening is formed is used as a mask and is left on the substrate, the opening formed by the first opening and the second opening is made a conventional method. It can be formed with a smaller number of masks. Further, dry etching has etching anisotropy, and if one direction intersecting the surface normal of the substrate, that is, an etching direction (angle) with respect to the substrate is set, the dry etching is inclined in the one direction. A semiconductor device in which the second opening communicates with the first opening can be formed.

Application Example 6 In the method of manufacturing a semiconductor device according to the application example described above, an etching rate of the first insulating film in the dry etching is faster than an etching rate of the second insulating film.
According to this method, the etching proceeds earlier in the first insulating film than in the second insulating film used as the mask, so that the second opening portion inclined in one direction can be formed with high dimensional accuracy. . In other words, even if the one direction in the dry etching is arbitrarily changed, the second opening inclined in the arbitrary direction can be stably formed.

Application Example 7 In the method of manufacturing a semiconductor device according to the application example, an etching rate in a direction perpendicular to the thickness direction in the dry etching is higher than an etching rate in the thickness direction of the first insulating film on the substrate. When this is faster, it is desirable to increase the tilt angle in the one direction with respect to the surface normal of the substrate in the dry etching than when the etching rate in the direction orthogonal to the thickness direction is equal or slower. .
When the etching rate in the direction orthogonal to the thickness direction is faster than the etching rate in the thickness direction on the substrate of the first insulating film, a step (over-level) is present at the interface between the first insulating film and the second insulating film. Hang) is easily formed. Then, when the conductive film is formed in the opening, it is difficult to form the conductive film in the step (overhang) portion, and there is a possibility that conduction cannot be obtained.
In this method, since the inclination angle in one direction, which is the etching direction in dry etching, is increased, it is difficult to cause the step. That is, a semiconductor device capable of obtaining stable operation can be manufactured.

Application Example 8 In the method for manufacturing a semiconductor device according to the application example, the semiconductor layer is formed using an organic semiconductor material so as to straddle a source electrode and a drain electrode, and the first insulating film is a general-purpose organic polymer. The second insulating film is an inorganic / organic hybrid polymer, and the second opening is formed to open to at least one of the source electrode and the drain electrode.
According to this method, the etching rate of general-purpose polymers in dry etching is faster than the etching rate of inorganic / organic hybrid polymers, so even if one direction is arbitrarily set in dry etching, an inclined surface with an arbitrary inclination angle is used. It is possible to form an organic semiconductor device having a second opening having

Application Example 9 In the method of manufacturing a semiconductor device according to the application example described above, a conductive material connected to at least one of the source region and the drain region of the semiconductor layer through the first opening and the second opening. A step of forming a film is provided.
According to this method, since the inclined surface inclined in one direction is formed on at least a part of the inner wall of the opening formed by the first opening and the second opening, the inner wall of the opening is in a standing state. As compared with the case of the above, the conductive film is efficiently formed on at least a part of the inclined surface. That is, the conductive film connected to the source region and / or the drain region can be efficiently formed with reduced material waste.

Application Example 10 In the method for manufacturing a semiconductor device according to the application example, it is preferable that the conductive film is formed by a vapor phase process.
According to this method, the conductive film can be efficiently formed on at least a part of the inclined surface formed on the inner wall of the opening by using a vapor phase process.

Application Example 11 In the semiconductor device manufacturing method of the application example, the conductive film may be formed by a liquid phase process.
According to this method, the conductive film can be efficiently formed on at least a part of the inclined surface formed on the inner wall of the opening by using a liquid phase process.

Application Example 12 An electro-optical device according to this application example includes a semiconductor device manufactured using the method for manufacturing a semiconductor device according to the application example.
According to this configuration, since the semiconductor device capable of stable operation is provided, an electro-optical device having high reliability can be provided.

The equivalent circuit diagram which shows the electric constitution of an electrophoresis apparatus. FIG. 2 is a schematic cross-sectional view showing the structure of an electrophoresis apparatus. The principal part sectional view showing the pixel structure of an electrophoretic device. The flowchart which shows the manufacturing method of an element substrate. (A)-(f) is a schematic sectional drawing which shows the manufacturing method of an element substrate. (G)-(k) is a schematic sectional drawing which shows the manufacturing method of an element substrate. The top view which shows the planar shape of a contact hole. (A) And (b) is a schematic sectional drawing which shows the manufacturing method of the semiconductor device of the modification 1. As shown in FIG. (A)-(c) is a schematic sectional drawing which shows the manufacturing method of the semiconductor device of the modification 2. FIG. FIG. 7 is a schematic cross-sectional view illustrating a structure of a semiconductor device according to a modification.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, embodiments of the invention will be described with reference to the drawings. Note that the drawings to be used are appropriately enlarged or reduced so that the part to be described can be recognized.

  In addition, in the following forms, when “on XX” is described, when arranged so as to touch XX, or when arranged on XX via other components, Or it shall arrange | position so that a part may contact | connect on (circle), and shall represent the case where a part is arrange | positioned via another structure.

<Electro-optical device>
First, an electrophoretic device will be described as an example of an electro-optical device including a semiconductor device to which the semiconductor device manufacturing method of the present embodiment is applied. FIG. 1 is an equivalent circuit diagram showing an electrical configuration of the electrophoretic device, FIG. 2 is a schematic cross-sectional view showing the structure of the electrophoretic device, and FIG. 3 is a cross-sectional view of the main part showing the pixel structure of the electrophoretic device.

As shown in FIG. 1, an electrophoretic device 100 as an electro-optical device of the present embodiment includes a plurality of scanning lines 113a and a plurality of data lines 114a that are insulated from each other and intersect. Pixels 117 are formed corresponding to the intersections of the scanning lines 113a and the data lines 114a, and the scanning lines 113a and the data lines 114a are connected to the respective pixels 117. The pixels 117 are arranged in a matrix in the extending direction of the scanning lines 113a and the extending direction of the data lines 114a.
The pixel 117 includes a thin film transistor (TFT) 110 as a switching element, a storage capacitor 122, a pixel electrode 124 and a common electrode 125 as a pair of electrodes, and an electric as an electro-optical element sandwiched between the pair of electrodes. And an electrophoretic layer 126.

The TFT 110 has a semiconductor layer made of an organic semiconductor material described later. The TFT 110 has a gate end connected to the scanning line 113a, a source end connected to the data line 114a, and a drain end connected to one electrode of the storage capacitor 122 and the pixel electrode 124.
The storage capacitor 122 is formed on an element substrate, which will be described later, and includes a pair of electrodes that are arranged to face each other with a dielectric film interposed therebetween. One electrode of the storage capacitor 122 is connected to the TFT 110, and the other electrode is connected to the capacitor line 118 arranged in parallel with the scanning line 113a. The image signal written via the TFT 110 by the storage capacitor 122 can be maintained for a certain period.

  The scanning line 113a is connected to the scanning line driving circuit 113. Based on a timing signal supplied from a controller (not shown), the scanning line driving circuit 113 sequentially supplies a selection signal to each of the scanning lines 113a in a pulsed manner, and exclusively each scanning line 113a. Select sequentially. The selected state refers to a state in which the TFT 110 connected to the scanning line 113a is on.

  The data line 114a is connected to the data line driving circuit 114. The data line driving circuit 114 supplies an image signal to each of the data lines 114a based on a timing signal supplied from a controller (not shown). In the present embodiment, for ease of explanation, it is assumed that the image signal has a binary potential of a high level potential VH (for example, 15 V) or a low level potential VL (for example, 0 V). Note that the electrophoretic layer 126 can be displayed by switching between white display and black display according to the potential applied between the pixel electrode 124 and the common electrode 125, and is low with respect to the pixel 117 where white is to be displayed. A level image signal (potential VL) is supplied, and a high-level image signal (potential VH) is supplied to the pixel 117 that should display black.

The common electrode 125 is supplied with a common electrode potential Vcom from a common electrode driving circuit (not shown). The common electrode drive circuit includes, for example, a DAC (waveform generation circuit) and an operational amplifier (current amplification circuit). The DAC is a D / A converter that generates a potential waveform from an input setting signal Vset. The potential waveform output from the DAC is current-amplified by an operational amplifier and supplied to the common electrode 125. In the common electrode driving circuit, an arbitrary potential waveform can be generated by the DAC, so that the common electrode potential Vcom can be changed in accordance with the gradation written in the pixel 117.
In the present embodiment, the common electrode potential Vcom is a binary potential of a low level potential VL (for example, 0 V) or a high level potential VH (for example, 15 V).

The capacitor line 118 is supplied with a capacitor line potential Vss from a capacitor line driving circuit (not shown). The capacitor line drive circuit is configured as a switch circuit including two switching elements that operate exclusively, for example. One switching element switches a potential supplied from a high-level (VH) power supply to the output terminal. The other switching element switches the potential supplied from the low-level (VL) power supply to the output terminal. A selection signal and an inverted selection signal are respectively input to the control terminals of the two switching elements, and the two switching elements operate exclusively with each other.
In the present embodiment, the common electrode potential Vcom outputs a low level potential VL (for example, 0 V) or a high level potential VH (for example, 15 V) as the capacitor line potential Vss. By changing the potential, it is possible to output an arbitrary capacitance line potential Vss.

  As shown in FIG. 2, the electrophoretic device 100 has a configuration in which an electrophoretic layer 126 is sandwiched between an element substrate 101 and a counter substrate 102. In the present embodiment, description will be made on the assumption that an image is displayed on the counter substrate 102 side.

As the element substrate 101, for example, a substrate made of glass or plastic can be used. On the element substrate 101, a stacked structure in which the above-described TFT 110, storage capacitor 122, scanning line 113a, data line 114a, capacitor line 118, and the like are formed is formed. A plurality of pixel electrodes 124 are formed in a matrix on the upper layer side of the stacked structure.
As the counter substrate 102, a transparent substrate made of, for example, glass or plastic can be used. On the element substrate 101 side of the counter substrate 102, a common electrode 125 is formed so as to face the plurality of pixel electrodes 124 and to extend over at least the display region 119. The common electrode 125 is formed of a transparent conductive material such as magnesium silver (MgAg), indium tin oxide (ITO), or indium zinc oxide.

The electrophoretic layer 126 is composed of a plurality of microcapsules 150 each including electrophoretic particles. The plurality of microcapsules 150 are fixed between the element substrate 101 and the counter substrate 102 by a binder 130 and an adhesive layer 131 made of, for example, resin. An electrophoretic sheet in which the electrophoretic layer 126 is previously fixed to the counter substrate 102 side by a binder 130, and the element substrate 101 on which the electrophoretic sheet is separately manufactured and the pixel electrode 124 and the like are formed are, for example, It is manufactured by bonding with an adhesive layer 140 made of a thermosetting or ultraviolet curable epoxy adhesive.
One or a plurality of microcapsules 150 are sandwiched between the pixel electrode 124 and the common electrode 125, and are arranged in one pixel 117 (in other words, with respect to one pixel electrode 124).

The enlarged view shown in FIG. 2 is a cross-sectional view showing the internal structure of the microcapsule 150. The microcapsule 150 has a configuration in which a dispersion medium 152, a plurality of white particles 153, and a plurality of black particles 154 are enclosed inside a coating film 151. The microcapsule 150 is formed in a spherical shape having a particle size of about 30 μm, for example.
The coating 151 functions as an outer shell of the microcapsule 150, and is formed from a translucent polymer resin such as acrylic resin such as polymethyl methacrylate and polyethyl methacrylate, urea resin, gum arabic, and gelatin. .
The dispersion medium 152 is a medium in which white particles 153 and black particles 154 are dispersed in the microcapsules 150 (in other words, in the coating film 151). Examples of the dispersion medium 152 include water, alcohol solvents (methanol, ethanol, isopropanol, butanol, octanol, methyl cellosolve, etc.), esters (ethyl acetate, butyl acetate, etc.), ketones (acetone, methyl ethyl ketone, methyl isobutyl ketone, etc.). ), Aliphatic hydrocarbons (pentane, hexane, octane, etc.), alicyclic hydrocarbons (cyclohexane, methylcyclohexane, etc.), aromatic hydrocarbons (benzene, toluene, benzenes having a long-chain alkyl group ( Xylene, hexylbenzene, hebutylbenzene, octylbenzene, nonylbenzene, decylbenzene, undecylbenzene, dodecylbenzene, tridecylbenzene, tetradecylbenzene)), halogenated hydrocarbons (methylene chloride, chloroform, tetrasalt) Carbon, 1,2-dichloroethane), can be exemplified a carboxylate, it may be other oils. These substances can be used alone or as a mixture, and a surfactant or the like may be further blended.

The white particles 153 are particles (polymer or colloid) made of a white pigment such as titanium dioxide, zinc white, and antimony trioxide, and are used, for example, by being negatively charged. The black particles 154 are particles (polymer or colloid) made of a black pigment such as aniline black or carbon black, and are used, for example, by being positively charged.
These pigments include electrolytes, surfactants, metal soaps, resins, rubbers, oils, varnishes, compound charge control agents, titanium-based coupling agents, aluminum-based coupling agents, silanes as necessary. A dispersant such as a system coupling agent, a lubricant, a stabilizer, and the like can be added.

Since the white particles 153 and the black particles 154 move in the dispersion medium 152 due to an electric field (potential difference) generated between the pixel electrode 124 and the common electrode 125, the pixel 117 depends on the color tone of the particles collected on the common electrode 125 side. The display color of will be affected. That is, either white display or black display can be performed by the potential difference.
Furthermore, if the potential difference is maintained, a white or black display state can be maintained. That is, the electrophoretic device 100 is a power-saving display device as compared with a self-luminous type, for example, an organic EL (electroluminescence) device that always requires electric power for display.

  Further, instead of the white particles 153 or the black particles 154, for example, pigments such as red, green, and blue may be used. According to such a configuration, the pixel 117 can display red, green, blue, or the like. Furthermore, in order to improve the color reproducibility of each display color, a colored layer (so-called color filter layer) corresponding to red, green, and blue may be provided between the counter substrate 102 and the common electrode 125.

<Semiconductor device>
Next, the TFT 110 as the semiconductor device of this embodiment provided in the electrophoresis apparatus 100 will be described with reference to FIG.
As shown in FIG. 3, a TFT 110 and a pixel electrode 124 electrically connected to the TFT 110 are provided on an element substrate 101 as a substrate.

  The TFT 110 includes a source electrode 110 s and a drain electrode 110 d that are arranged to face each other at a predetermined interval in the surface of the element substrate 101, and a semiconductor layer 110 a provided across the source electrode 110 s and the drain electrode 110 d. The gate insulating film 103 as a first insulating film (first layer) provided so as to cover the source electrode 110s, the semiconductor layer 110a, and the drain electrode 110d, and between the source electrode 110s and the drain electrode 110d. And a gate electrode 110g provided on the gate insulating film 103. In this embodiment, a part of the scanning line 113a is used as the gate electrode 110g.

  An interlayer insulating film 104 as a second insulating film (second layer) is provided so as to cover the gate electrode 110 g and the gate insulating film 103 of the TFT 110, and a pixel electrode 124 is provided on the interlayer insulating film 104. ing.

The pixel electrode 124 is electrically connected to the drain electrode 110d through a contact hole CTH1 serving as an opening provided in a region overlapping the drain electrode 110d in plan view. The contact hole CTH1 includes a contact hole 104a as a first opening provided in the interlayer insulating film 104 and a contact hole 103a as a second opening provided in the gate insulating film 103 so as to communicate with the contact hole 104a. Become.
The contact hole 104a is opened in a direction substantially parallel to the surface normal of the element substrate 101, and the contact hole 103a communicating with the contact hole 104a is inclined with respect to the surface normal.
The two contact holes 103a and contact holes 104a constituting the contact hole CTH1 may be referred to as holes 103a and 104a, respectively, in the following description of the semiconductor device manufacturing method.

<Manufacturing Method of Semiconductor Device and Manufacturing Method of Element Substrate>
Next, details of a method for manufacturing the element substrate 101 including the TFT 110 as a semiconductor device will be described with reference to FIGS. FIG. 4 is a flowchart showing a method for manufacturing an element substrate, and FIGS. 5A to 5F and 6G to 6K are schematic cross-sectional views showing a method for manufacturing the element substrate. Note that a method for manufacturing the element substrate 101 described below includes a method for manufacturing the TFT 110 as a semiconductor device.

  As shown in FIG. 4, in the method for manufacturing the element substrate 101 according to the present embodiment, an electrode forming step (step S1) for forming the source electrode 110s and the drain electrode 110d on the element substrate 101, and the semiconductor layer 110a are formed. Forming a semiconductor layer (step S2), forming a gate insulating film 103 as a first insulating film (first layer) (step S3), and forming a gate electrode 110g A step (step S4), an interlayer insulating film forming step (step S5) for forming an interlayer insulating film 104 as a second insulating film (second layer), and a first opening for forming a first opening in the interlayer insulating film 104; 1 opening formation process (step S6), 2nd opening formation process (step S7) which forms a 2nd opening part in the gate insulating film 103, and the pixel electric current which forms the pixel electrode 124 Forming step and a (Step S8) and.

In the electrode forming process of step S1, as shown in FIG. 5A, a source electrode 110s and a drain electrode 110d are formed on the element substrate 101 at a predetermined interval. Examples of the constituent material of these electrodes include metal materials such as Pd, Pt, Au, W, Ta, Mo, Al, Cr, Ti, Cu or alloys containing these, carbon such as carbon black, carbon nanotubes, and fullerenes. Material, polyacetylene, polypyrrole, polythiophene such as poly (3,4-ethylenedioxythiophene) (PEDOT), polyaniline, poly (p-phenylene), poly (p-phenylenevinylene), polyfluorene, polycarbazole, polysilane or Examples thereof include conductive polymer materials such as these derivatives and mixtures containing these, and one or more of them can be used in combination.
As a forming method, the constituent material is formed into a film using a vapor phase process such as vapor deposition, and this is formed by patterning, or the constituent material is applied to a predetermined region of the element substrate 101 and dried and fired. A method of forming a pattern using a liquid phase process may be mentioned. The liquid phase process referred to here is a liquid by dissolving or dispersing a material to be formed, and using this liquid, a film is formed by a spin coating method, a dip method, or a droplet discharge method (inkjet method). It is a method to do.

  The thicknesses of the source electrode 110s and the drain electrode 110d are not particularly limited, but are preferably about 50 nm to 500 nm, respectively. Then, the process proceeds to step S2.

In the semiconductor layer forming step of step S2, as shown in FIGS. 5B and 5C, the semiconductor layer 110a is formed so as to be in contact with the source electrode 110s and the drain electrode 110d and to fill the gap therebetween. The semiconductor layer 110a of this embodiment is formed using an organic semiconductor material.
Examples of the organic semiconductor material include poly (3-alkylthiophene), poly (3-hexylthiophene) (P3HT), poly (3-octylthiophene), poly (2,5-thienylenevinylene) (PTV), poly (Para-phenylene vinylene) (PPV), poly (2-methoxy, 5- (2′-ethylhexoxy) -para-phenylene vinylene) (MEH-PPV), poly (9,9-dioctylfluorene) (PFO), poly (9,9-dioctylfluorene-co-bis-N, N ′-(4-methoxyphenyl) -bis-N, N′-phenyl-1,4-phenylenediamine) (PFMO), poly (9,9- Dioctylfluorene-co-benzothiadiazole) (BT), fluorene-triarylamine copolymer, triarylamine-based polymer, High-molecular organic semiconductor materials such as orene-bithiophene copolymer (F8T2), polyarylamine (PAA), fullerene, metal phthalocyanine or derivatives thereof, acene molecular materials such as anthracene, tetracene, pentacene, hexacene, quarterthiophene ( 4T), sexithiophene (6T), octithiophene (8T), dihexyl quarterthiophene (DH4T), dihexylsexithiophene (DH6T) and other low-molecular organic semiconductor materials such as α-oligothiophenes. These can be used alone or in combination of two or more.

Among these, low molecular weight organic semiconductor materials having a low molecular weight organic semiconductor material as a main component, for example, low molecular weight organic semiconductor materials having crystallinity such as pentacene are generally excellent in carrier transporting ability and are suitable for gas phase processes. Yes. A material mainly composed of a high molecular organic semiconductor material, for example, a material such as P3HT, is generally better in solubility in a solvent than a low molecular material such as pentacene, and is therefore suitable for a liquid phase process. You can say that.
Further, the semiconductor layer 110a composed mainly of a polymer organic semiconductor material is generally excellent in flexibility, and is applicable to a switching element constituting a pixel circuit of a flexible display or its peripheral circuit. Is preferred.
The thickness of the semiconductor layer 110a is not particularly limited, but is preferably about 1 nm to 200 nm, and more preferably about 10 nm to 100 nm from the viewpoint of applying a liquid phase process. In the present embodiment, the semiconductor layer 110a made of P3HT is formed using a liquid phase process.

  Note that the semiconductor layer 110a may have a structure that is selectively provided in a region (channel region) between the source electrode 110s and the drain electrode 110d, and almost the entire source electrode 110s and the drain electrode 110d. The thing of the structure provided so that it might cover may be used.

The distance between the source electrode 110s and the drain electrode 110d, that is, the channel length L shown in FIG. 5C is not particularly limited, but is preferably about 0.05 μm to 100 μm, and is about 0.5 μm to 50 μm. Is more preferable. By setting the value of the channel length L in such a range, the characteristics of the TFT 110 can be improved (particularly, the on-current value can be increased).
The length of the source electrode 110s and the drain electrode 110d, that is, the channel width W shown in FIG. 5C is not particularly limited, but is preferably about 0.01 mm to 50 mm, and preferably about 0.05 mm to 1 mm. It is more preferable that By setting the value of the channel width W in such a range, the parasitic capacitance can be reduced, and deterioration of the characteristics of the TFT 110 can be prevented. Then, the process proceeds to step S3.

In the gate insulating film forming step in step S3, as shown in FIG. 5D, the gate insulating film 103 is formed so as to cover the source electrode 110s, the semiconductor layer 110a, and the drain electrode 110d. Examples of the constituent material of the gate insulating film 103 include inorganic insulating materials such as SiO ₂ (silicon oxide), imide resins such as polyimide and polyamideimide, acrylic resins such as polymethyl methacrylate (PMMA), Fluorine resin (fluoropolymer) such as polytetrafluoroethylene (PTFE), parylene resin such as polyparaxylylene, polyvinyl alcohol resin such as polyvinyl alcohol, phenol resin such as polyvinylphenol or novolac resin, poly Silsesquioxane resins such as methylsilsesquioxane and polyphenylsilsesquioxane, and organic resins such as olefin resins such as polyethylene, polypropylene, polyisobutylene, polystyrene, polybutene, and tetratetracontane It can be used edge material (generic organic polymer). From the viewpoint that it is difficult to give extra stress such as heat to the semiconductor layer 110a made of an organic semiconductor material during film formation, an organic insulating material (organic compound) is preferable. In the present embodiment, Cytop (registered trademark) manufactured by Asahi Glass Co., Ltd., which is an amorphous fluoropolymer, is applied using a spin coating method so that the thickness is about 500 nm, and is heated at about 60 ° C. for about 10 minutes. Thus, a gate insulating film 103 was formed. Then, the process proceeds to step S4.

In the gate electrode formation step in step S4, as shown in FIG. 5E, the semiconductor is formed at a predetermined position on the gate insulating film 103, that is, a position corresponding to the region between the source electrode 110s and the drain electrode 110d. A gate electrode 110g for applying an electric field to the layer 110a is formed.
As a constituent material of the gate electrode 110g, for example, Pd, Pt, Au, W, Ta, Mo, Al, Cr, Ti, Cu, or a metal material such as an alloy containing these, carbon such as carbon black, carbon nanotube, or fullerene. Material, polyacetylene, polypyrrole, polythiophene such as poly (3,4-ethylenedioxythiophene) (PEDOT), polyaniline, poly (p-phenylene), poly (p-phenylenevinylene), polyfluorene, polycarbazole, polysilane or Examples thereof include conductive polymer materials such as these derivatives and mixtures containing these, and one or more of these can be used in combination. Examples of the mixed conductive polymer material include poly (3,4-ethylenedioxythiophene) (PEDOT) / poly (styrenesulfonic acid) (PSS).
The thickness of the gate electrode 110g is not particularly limited, but is preferably about 1 nm to 200 nm. Then, the process proceeds to step S5.

In the interlayer insulating film forming step in step S5, the interlayer insulating film 104 is formed so as to cover the gate electrode 110g and the gate insulating film 103, as shown in FIG. As a constituent material of the interlayer insulating film 104, for example, an inorganic insulating material such as SiO ₂ (silicon oxide) similar to the gate insulating film 103, an imide resin such as polyimide and polyamideimide, and polymethyl methacrylate (PMMA) Of acrylic resins such as polytetrafluoroethylene (PTFE), parylene resins such as polyparaxylylene, polyvinyl alcohol resins such as polyvinyl alcohol, polyvinylphenol or novolac resins. Such as phenolic resins, silsesquioxane resins such as polymethylsilsesquioxane, polyphenylsilsesquioxane, polyethylene, polypropylene, polyisobutylene, polystyrene, polybutene, tetratetracontane, etc. Organic insulating material such as down-based resin (general-purpose organic polymer), or may be an inorganic-organic hybrid polymer, such as siloxane polymer. In the present embodiment, the interlayer insulating film 104 is formed by applying a siloxane polymer using a spin coating method so as to have a thickness of about 5000 nm (5 μm) and prebaking at 100 ° C. for about 5 minutes. Then, the process proceeds to step S6.

  In the first opening forming step in step S6, a hole 104a as a first opening is formed in the interlayer insulating film 104 as shown in FIG. Specifically, a predetermined portion of the interlayer insulating film 104 is exposed using photolithography, post-baked at about 80 ° C. for about 1 minute, and then developed using a tetramethylammonium hydroxide (TMAH) 2 wt% solution. As a result, a hole 104a was formed. The hole 104a of this embodiment is a circle having a diameter of approximately 20 μm in plan view. Then, the process proceeds to step S7.

  In the second opening forming step in step S7, as shown in FIGS. 6H and 6I, dry etching is performed on the gate insulating film 103 using the interlayer insulating film 104 provided with the hole 104a as a mask, and the first opening is formed. A hole 103a is formed as two openings. Specifically, the element substrate 101 is inclined and disposed in a chamber of a dry etching apparatus (not shown) so that the surface normal line 101a of the element substrate 101 intersects one direction. One direction corresponds to the dry etching direction. An angle formed by the surface normal 101a and the dry etching direction at this time is represented as θ1, and is referred to as an inclination angle θ1 of the element substrate 101. The inclination angle θ1 in the present embodiment is set within a range of approximately 20 degrees to 30 degrees.

  The dry etching conditions of the gate insulating film 103 are, for example, that the degree of vacuum in the chamber is about 100 mTorr to 200 mTorr, the flow rate of Ar (argon) as a processing gas is 4500 sccm to 5000 sccm, and dry etching is performed at an output of about 400 W to 500 W. .

  The etching rate of the interlayer insulating film 104 as a mask in the dry etching of this embodiment is substantially 0 (zero). That is, under this dry etching condition, the siloxane polymer is hardly etched. In contrast, the etching rate in the thickness direction of the gate insulating film 103 using the fluoropolymer was approximately 50 nm / min to 70 nm / min. Therefore, a substantially cylindrical hole 103a inclined in the dry etching direction (one direction) can be formed by dry etching for about 10 minutes. In other words, since the interlayer insulating film 104 as a mask is hardly etched, the etching always proceeds from a certain direction with respect to the gate insulating film 103, so that the hole 103a inclined at a desired inclination angle θ1 can be formed.

  By performing dry etching, a hole 103a communicating with the hole 104a of the interlayer insulating film 104 is formed. As shown in the perspective view of FIG. 6 (j), the appearance is a slight step between the inner wall 104b of the hole 104a and the edge of the hole 103a at the boundary between the interlayer insulating film 104 and the gate insulating film 103. 103c is formed. Further, the hole 103a provided in the region overlapping the drain electrode 110d in plan view has an inclined surface 103b inclined in the dry etching direction. By step S7, the contact hole CTH1 including the hole 104a and the hole 103a is formed. Then, the process proceeds to step S8.

  In the pixel electrode formation step in step S8, the pixel electrode 124 is formed on the interlayer insulating film 104 as shown in FIG. At the same time, a conductive portion that can electrically connect the pixel electrode 124 to the drain electrode 110d is formed in the contact hole CTH1.

Specifically, the pixel electrode 124 is obtained by depositing a transparent conductive film material such as ITO (Indium Tin Oxide) or IZO (Indiumu Zinc Oxide) by an evaporation method. At this time, the transparent conductive film material evaporated from the evaporation source is deposited not only on the surface of the interlayer insulating film 104 but also on the inner wall of the hole 104a, the inner wall of the hole 103a, and the surface of the drain electrode 110d exposed inside the hole 103a. Is done. Since the hole 103a has an inclined surface 103b inclined in a certain direction and a stepped portion 103c continuous with the inclined surface 103b, compared to the case where the hole 103a is opened in the surface normal direction of the element substrate 101, It is easy to form a transparent conductive film in the hole 103a, and it is possible to realize electrical connection between the transparent conductive film formed on the inner wall of the hole 104a and the transparent conductive film formed on the inner wall of the hole 103a. Easy. In other words, by setting the inclination angle θ1 to a non-zero value as in this embodiment, the pixel electrode 124 and the drain electrode 110d can be electrically connected through the step portion 103c.
Note that the conductive material forming the pixel electrode 124 is not limited to the transparent conductive film, and a metal material such as Al (aluminum) or Ag (silver) having light reflectivity or an alloy of these metal materials is used. Also good.

  FIG. 7 is a plan view showing a planar shape of the contact hole. In this embodiment, as shown in FIG. 7A, a circular contact hole CTH1 (hole 104a) is formed in plan view. Not limited to this, it may be a quadrangle as shown in FIG. 7B or a polygon such as a hexagon as shown in FIG. 7C.

According to the embodiment described above, the following effects can be obtained.
(1) The contact hole CTH1 penetrating the gate insulating film 103 and the interlayer insulating film 104 provided on the element substrate 101 is dry-etched using the interlayer insulating film 104 having the hole 104a as a mask, The hole 103 a reaching the drain electrode 110 d is formed in the gate insulating film 103. Therefore, compared with the method of forming the second contact hole inside the opening of the first contact hole as in the prior art, the number of masks to be used can be reduced and the contact hole CTH1 can be formed.

  (2) When the gate insulating film 103 is dry-etched, the element substrate 101 is tilted so that the surface normal line 101a of the element substrate 101 intersects the dry etching direction. A hole 103a having an inclined surface 103b inclined in a direction intersecting with the line can be formed. Therefore, when the contact hole CTH1 is used, it is easy to electrically connect the conductive layer provided on the second insulating film and the conductive layer provided below the first insulating film.

  (3) Since the etching rate of the gate insulating film 103 in dry etching is faster than the etching rate of the interlayer insulating film 104, the etching proceeds in a certain direction to form a hole 103a having a desired inclination angle θ1. Can do. In other words, the hole 103a having an arbitrary inclination angle can be formed.

  (4) Furthermore, in the pixel electrode formation step (step S8), when a conductive material is formed by vapor deposition, it is possible to efficiently form a film on the inclined surface 103b and the stepped portion 103c of the hole 103a. A contact hole CTH1 that can connect the electrode 124 and the drain electrode 110d in an electrically stable state can be formed. Therefore, when the contact hole CTH1 is used, it is easy to electrically connect the conductive layer provided on the second insulating film and the conductive layer provided below the first insulating film.

  (5) In the electrophoretic device 100 having the element substrate 101 obtained by applying the method for manufacturing the element substrate 101, stable electrical connection between the TFT 110 as the semiconductor device and the pixel electrode 124 is achieved. Therefore, the electrophoretic device 100 having high reliability in electrical driving can be provided.

  Various modifications other than the above embodiment are conceivable. Hereinafter, a modification will be described.

  (Modification 1) In the above embodiment, the formation of the contact hole CTH1 (hole 104a, hole 103a) using dry etching has been described. However, the shape of the contact hole CTH1 after etching is that of the insulating film in which the hole is formed. Needless to say, the material structure, dry etching conditions, and the etching rate of the insulating film in dry etching are affected. 8A and 8B are schematic cross-sectional views showing a method for manufacturing the semiconductor device of Modification 1. FIG.

  As shown in FIG. 8A, when the interlayer insulating film 104 is etched by dry etching, for example, when the etching rate of the gate insulating film 103 is equal to or slower than the etching rate of the interlayer insulating film 104, Since the etching of the film 104 proceeds further and the hole 104a expands, the surface area of the gate insulating film 103 that is dry-etched through the hole 104a increases. Therefore, after the dry etching is finished, as shown in FIG. 8B, the hole 103a and the hole 104a having inclined surfaces inclined with respect to the dry etching direction can be formed. That is, it becomes easier to deposit the subsequent conductive material.

  (Modification 2) The shape of the hole 103 a in the gate insulating film 103 also depends on the etching anisotropy of the gate insulating film 103. 9A to 9C are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device of Modification 2.

  As shown in FIG. 9A, depending on the material forming the gate insulating film 103 and the material forming the interlayer insulating film 104, the etching rate E1 in the film thickness direction in dry etching is etched in the direction perpendicular to the film thickness direction. Compared with the rate E2, it can be made slower (etching rate E1 <etching rate E2). In this case, as shown in FIG. 9B, when the gate insulating film 103 is dry-etched while the element substrate 101 is inclined at the inclination angle θ1, the interface between the gate insulating film 103 and the interlayer insulating film 104 in the dry etching direction In the vicinity, the etching of the gate insulating film 103 proceeds in a direction orthogonal to the film thickness direction, and thus an overhang occurs at this interface. Therefore, as shown in FIG. 9C, by setting the inclination angle to θ2 larger than θ1, the etching start region of the gate insulating film 103 is kept away from the inner wall of the hole 104a, thereby preventing the occurrence of overhang. Can do. Specifically, the inclination angle θ2 is preferably 30 degrees or more and 40 degrees or less.

  (Modification 3) The configuration to which the semiconductor device manufacturing method of the above embodiment can be applied is not limited to the TFT 110 having the semiconductor layer 110a made of an organic semiconductor material. FIG. 10 is a schematic cross-sectional view showing the structure of a modified semiconductor device.

  For example, as shown in FIG. 10, a manufacturing method of a TFT 210 as a semiconductor device is formed by forming a polycrystalline silicon film on an element substrate 201 using a quartz substrate, and doping impurities such as phosphorus therein. A semiconductor layer 210a having a channel region having a low impurity concentration and a source region 210s and a drain region 210d having a high impurity concentration sandwiching the channel region is formed. Subsequently, a gate insulating film 203 made of, for example, silicon oxide is formed so as to cover the semiconductor layer 210a, and a gate electrode 210g is formed at a position corresponding to the channel region. Then, a first interlayer insulating film 204 made of, for example, silicon oxide is formed so as to cover them. Next, by applying the semiconductor device manufacturing method of the above embodiment, first the first opening 204a and the first opening 204b are formed at positions corresponding to the source region 210s and the drain region 210d of the first interlayer insulating film 204. To do. Further, the element substrate 201 is tilted using the first interlayer insulating film 204 as a mask, and the gate insulating film 203 is dry etched to form the second opening 203a and the second opening 203b inclined in the dry etching direction. For example, when a liquid material containing a conductive material is applied on the first interlayer insulating film 204 by a liquid phase process, the contact hole CTH22 that connects the data line 214 and the source region 210s can be formed. Further, a front stage of the contact hole CTH21 connected to the drain region 210d can be formed.

Next, a second interlayer insulating film 205 is formed so as to cover them. The second interlayer insulating film 205 may be an inorganic insulating material or an organic insulating material. A third opening 205a communicating with the first opening 204a is formed by using a photolithography method. If the pixel electrode 224 is formed on the second interlayer insulating film 205 by using a vapor phase process or a liquid phase process, the contact hole CTH21 that connects the pixel electrode 224 and the drain region 210d can be formed.
Note that the present invention is not limited to the formation of the two contact holes CTH21 and 22, and the semiconductor device manufacturing method of the above embodiment may be applied to one of the formation methods.

  That is, the present invention can be applied to a method for manufacturing a semiconductor device having a semiconductor layer made of an inorganic material, and stable connection with a conductive film such as a data line, a pixel electrode, or a capacitor electrode can be achieved. In addition, a stable connection can be realized regardless of a vapor phase process or a liquid phase process in the method for forming a conductive film.

  Furthermore, the configuration of the insulating film is not limited to two layers, and may be three layers as described above. In other words, the opening may be formed in the corresponding insulating film so as to connect to the conductive film on the substrate.

  (Modification 4) The electro-optical device to which the method for manufacturing a semiconductor device and the method for manufacturing an element substrate in the above embodiment can be applied is not limited to the electrophoresis device 100. For example, the present invention can be applied to a liquid crystal device including a TFT as a switching element, an organic EL (electroluminescence) device, an FED (Field Emission Display), an SED (Surface-conduction Electron-emitter Display), and the like.

  DESCRIPTION OF SYMBOLS 100 ... Electrophoresis apparatus as an electro-optical device, 101 ... Element board | substrate as a board | substrate, 101a ... Surface normal, 103 ... Gate insulating film as a 1st layer or a 1st insulating film, 103a ... As 2nd opening part Hole 104, interlayer insulating film as second layer or second insulating film, 104a ... hole as first opening, 110 ... TFT as semiconductor device, 110a ... semiconductor layer, 110d ... drain electrode, 110s ... source Electrode, 110g, gate electrode, 124, pixel electrode as conductive film, 201, element substrate, 203, gate insulating film, 203a, second opening, 204, first interlayer insulating film, 204a, first opening, 205 ... Second interlayer insulating film, 210 ... TFT as semiconductor device, 210a ... Semiconductor layer, 210d ... Drain region, 210s ... Source region, 210g ... Gate Pole, CTH1,21,22 ... contact hole as an opening, E1 ... thickness direction of the etching rate, E2 ... direction of the etching rate perpendicular to the thickness direction, θ1, θ2 ... elements inclination angle of the substrate.

Claims (12)

A method of manufacturing a substrate having a first layer and a second layer stacked on a substrate, and an opening that penetrates the first layer and the second layer,
Forming a first opening constituting the opening in the second layer;
Using the second layer in which the first opening is formed as a mask, dry etching is performed from one direction intersecting the surface normal of the substrate, and the first layer is moved in the one direction. Inclining and forming a second opening communicating with the first opening;
A method for manufacturing a substrate, comprising:   The method for manufacturing a substrate according to claim 1, wherein an etching rate of the first layer in the dry etching is faster than an etching rate of the second layer.   2. The method of manufacturing a substrate according to claim 1, wherein an etching rate of the first layer in the dry etching is slower than or equal to an etching rate of the second layer.   In the dry etching, if the etching rate in the direction perpendicular to the thickness direction is faster than the etching rate in the thickness direction of the first layer on the substrate, etching in the direction perpendicular to the thickness direction is performed. 4. The tilt angle in the one direction with respect to the surface normal of the substrate in the dry etching is increased as compared with a case where the rate is equal to or slower than the etching rate in the thickness direction. The manufacturing method of the board | substrate as described in any one of these. Penetrating through a semiconductor layer provided on the substrate, at least a first insulating film and a second insulating film stacked in order covering the semiconductor layer, the first insulating film and the second insulating film, A manufacturing method of a semiconductor device comprising: an opening overlapping in plan view with one of a source region and a drain region of a semiconductor layer,
Forming a first opening constituting the opening in the second insulating film;
Using the second insulating film in which the first opening is formed as a mask, dry etching is performed from one direction intersecting the surface normal of the substrate, and the first insulating film is moved in the one direction. Inclining and forming a second opening communicating with the first opening;
A method for manufacturing a semiconductor device, comprising:   6. The method of manufacturing a semiconductor device according to claim 5, wherein an etching rate of the first insulating film in the dry etching is faster than an etching rate of the second insulating film.   In the dry etching, if the etching rate in the direction perpendicular to the thickness direction is faster than the etching rate in the thickness direction of the first insulating film on the substrate, etching in the direction perpendicular to the thickness direction is performed. 7. The method of manufacturing a semiconductor device according to claim 5, wherein an inclination angle of the one direction with respect to a surface normal of the substrate in the dry etching is increased as compared with a case where the rate is equal or slower. The semiconductor layer is formed across the source electrode and the drain electrode using an organic semiconductor material,
The first insulating film is a general-purpose organic polymer;
The second insulating film is an inorganic / organic hybrid polymer,
The method for manufacturing a semiconductor device according to claim 5, wherein the second opening is formed so as to open to at least one of the source electrode and the drain electrode.   6. The method of forming a conductive film connected to at least one of the source region and the drain region of the semiconductor layer through the first opening and the second opening. The manufacturing method of the semiconductor device as described in any one of thru | or 8.   The method for manufacturing a semiconductor device according to claim 9, wherein the conductive film is formed by a vapor phase process.   The method for manufacturing a semiconductor device according to claim 9, wherein the conductive film is formed by a liquid phase process.   An electro-optical device comprising a semiconductor device manufactured using the method for manufacturing a semiconductor device according to claim 5.

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