JP2010181588A - Electrooptical panel, electrooptical display device, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem of increased power consumption in an elimination sequence when the retention capacity is increased for enhancing the display performance in a display sequence. <P>SOLUTION: The retention capacity is constituted by a field effect transistor, with one end connected to a pixel electrode and the other end to a shared electrode potential. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an electro-optical panel, an electro-optical display device including the electro-optical panel, and an electronic apparatus including the electro-optical display device.

  Display devices that use display elements with memory characteristics such as electrophoresis displays (hereinafter referred to as EPDs) continue to display images even after the power is turned off. The use of electronic posters and electronic leaflets has begun to spread. In these display devices, in order to improve display performance such as display contrast, it is effective to drive with an active matrix substrate device using active elements such as thin film transistors. On the other hand, application of a high voltage is necessary for exhibiting sufficient performance of the display element, but at this time, the voltage applied to the active element also increases, and thus problems such as dielectric breakdown and reduced reliability are likely to occur. Therefore, Patent Document 1 proposes a method of executing a display sequence after executing an erasing sequence in which the potential of the common electrode is inverted to make all pixels have a predetermined display color.

  Further, in the case of a display device using a display element having a slow response speed and an active matrix substrate device, a desired potential is written to the pixel electrode in the display sequence, and the active element is turned off (in a high impedance state) and then the display element In order to reduce the phenomenon that the potential of the pixel electrode is lowered due to the movement of electric charge, it is effective to provide a storage capacitor in parallel with the display element capacitor. However, when executing the erasing sequence, a storage capacitor is not necessary, and an extra charge / discharge of the storage capacitor is required, leading to an increase in power consumption and an increase in sequence execution time. Patent Document 2 proposes a configuration in which the storage capacitor is separated by a switching unit because the frequency of the pulse is limited by the storage capacitor when the AC pulse signal is used in the erase sequence.

Japanese Patent No. 3719172 JP 2008-139738 A

  If a storage capacitor is added to ensure display performance, problems such as increase in power consumption and erasing time in the erasing sequence, limitation of the pulse frequency, and the like will occur. In order to solve this, if a switching means is provided as in Patent Document 2, an extra control signal is required, the drive circuit becomes complicated, and a high-definition display device cannot be realized.

  The present invention includes a plurality of pixel electrodes and a storage capacitor element having one end connected to the pixel electrode, and an erasing sequence for simultaneously writing potentials to all of the plurality of pixel electrodes, and the plurality of pixel electrodes individually. An electro-optical panel having a display sequence for writing an electric potential, wherein a capacitance value of the storage capacitor element is changed by a potential difference applied to both ends, and a capacitance value of the storage capacitor element in the erasing sequence is changed in the display sequence. An electro-optical panel is proposed that is smaller than the capacitance value of the storage capacitor element.

  The electro-optical panel configured in this way has a high-quality display performance because the storage capacitance value is changed between the display sequence and the erase sequence, and the power consumption and erase time of the erase sequence are reduced. it can. Here, as a configuration of a capacitive element whose capacitance value changes depending on a potential difference applied to both ends, a MOS (Metal-Oxide-Semiconductor) diode in addition to a short-circuited source electrode and drain electrode of a field effect transistor described in the embodiment. Alternatively, an element called a MOS capacitor can be used.

  In the present invention, a common electrode opposed to the plurality of pixel electrodes is provided, and the potential of the common electrode is different between the erase sequence and the display sequence, and the other end of the storage capacitor element is connected to the common electrode. It is also proposed that the same potential be supplied.

  With this configuration, the capacitance value of the storage capacitor can be changed depending on the potential of the common electrode, so that an unnecessary control signal is unnecessary, and the manufacturing cost can be reduced by further increasing the definition and simplifying the drive circuit.

  In the present invention, it is also proposed that a plurality of pixel switching elements connected to the plurality of pixel electrodes are provided, and the storage capacitor element and the pixel switching element are composed of thin films having the same film thickness and film composition. To do.

  With this configuration, at least a part of the manufacturing process of the storage capacitor and the pixel switching element can be the same process, so that the number of manufacturing processes and cost can be increased.

  In addition, it is proposed that the storage capacitor element includes a capacitor in which a source electrode and a drain electrode of a transistor are short-circuited.

  With this configuration, an electro-optical panel having a storage capacitor element whose capacitance value changes can be easily realized.

  It is also proposed that the one end of the storage capacitor element is composed of the gate electrode of the transistor, and the other end is composed of the shorted source and drain of the transistor.

  If comprised in this way, the electro-optical panel which can perform a display sequence and an erasing sequence more effectively is realizable.

  It is also proposed that the storage capacitor element and the pixel switching element each include a thin film silicon, an insulating film, and a metal electrode.

  With this configuration, since the material constituting the storage capacitor element and the pixel switching element can be made the same, the number of manufacturing steps and cost can be increased.

  It is also proposed that an electrophoretic element is provided between the pixel electrode and the common electrode, and the electrophoretic element includes positively or negatively charged pigment particles as a dispersoid.

  If comprised in this way, the electro-optical panel provided with the electrophoretic element which can perform a display sequence and an erasing sequence effectively is realizable.

  The present invention also proposes an electro-optic display device using these electro-optic panels and an electronic apparatus using the display device.

  As a result, a high-definition, low power consumption and low-cost display device and an electronic device equipped with the display device can be realized.

The perspective view block diagram of a display apparatus. 1 is a configuration diagram of an active matrix substrate. The pixel circuit diagram of an active matrix substrate. 1 is a block diagram illustrating an embodiment of an electronic device. 4 is a timing chart for explaining an erase sequence. The timing chart for demonstrating a display sequence. The Cg-Vg characteristic chart of the storage capacitor 403-nm.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, embodiments of the invention will be described with reference to the drawings.

  FIG. 1 is a perspective configuration diagram of a display device 910 according to the present embodiment. The display device 910 is configured by attaching an electrophoretic element 921 on an active matrix substrate 101 serving as an active matrix device, and further a protective sheet 922 thereon.

  Here, the electrophoretic element 921 is one in which capsules made of a light-transmissive polymer resin having a particle size of about 50 μm are filled in a single layer without any gap. Inside the capsule, a dispersant composed of an organic solvent, water, and a surfactant, white pigment particles that are negatively charged as dispersoids, and black pigment particles that are positively charged are encapsulated.

  The protective sheet 922 is made of PET (Poly Ethylene Terephthalate) resin having a thickness of about 300 μm, and a common electrode (COM) (not shown) made of an ITO (Indium Tin Oxide) thin film is formed on the contact surface with the electrophoretic element 921. ing. The protective sheet 922 is one side longer than the electrophoretic element 921, and a conductive paste 931 is applied to a protruding portion where the electrophoretic element 921 does not exist, and the common electrode (COM) and the common electrode pad (on the active matrix substrate 101) The common electrode pad 330, which will be described later with reference to FIG.

  The active matrix substrate 101 has a larger area than the electrophoretic element 921 and the protective sheet 922, and a first FPC 951 as a flexible substrate and a second FPC 961 as a flexible substrate are mounted on the overhanging portion. Is done. A gate driver 952 is mounted on the first FPC 951, and a source driver 962 is mounted on the second FPC 961, respectively.

  In this embodiment, the first FPC 951, the gate driver 952, the second FPC 961, and the source driver 962 are each constituted by one, but a plurality of them may be provided, and the gate driver 952 and the source driver 962 may be provided. A one-chip driver integrated into one IC may be used. Alternatively, an active matrix substrate with a built-in driving circuit in which a gate driver or a source driver is formed on the active matrix substrate 101 may be used.

  FIG. 2 is a configuration diagram of the active matrix substrate 101. On the active matrix substrate 101, 480 scanning lines 201 (201-1 to 201-480) and 1920 data lines 202 (202-1 to 202-1920) are formed orthogonally, and 480 lines are formed. The capacitor lines 203 (203-1 to 203-480) are arranged in parallel and alternately with the scanning lines 201-1 to 201-480. The capacitor lines 203-1 to 203-480 are connected to the common potential wiring 335, and the common potential wiring 335 is also connected to the common electrode pad 330. A dotted line A is a region where the electrophoretic elements 921 shown in FIG. 1 overlap in a plan view when configured as a display device, and corresponds to a display region. Each of the scanning lines 201-1 to 201-480 is connected to the mounting terminals 301-1 to 301-480, and is connected to the gate driver 952 via the first FPC 951 and driven appropriately. Similarly, the data lines 202-1 to 202-1920 are connected to the mounting terminals 302-1 to 302-1920, respectively, connected to the source driver 962 via the second FPC 961, and appropriately driven. The common potential wiring 335 is connected to the mounting terminal 320 and similarly connected to the source driver 962 via the second FPC 961 and is appropriately driven.

  FIG. 3 is a circuit diagram near the intersection of the mth data line 202-m (m = 1 to 1920 integer) and the nth scan line 201-n (n = 1 to 480 integer). A pixel switching element 401 (401-nm) made of an n-channel field effect transistor is formed at each intersection of the scanning line 201-n and the data line 202-m, and its gate electrode is the scanning line 201-n. The source / drain electrodes are connected to the data line 202-m and the pixel electrode 402-nm, respectively. The pixel electrode 402-nm and the common electrode (COM) on the protective sheet 922 are opposed to each other through the electrophoretic element 921 to form a capacitor.

  A storage capacitor element 403 (403-nm) is a capacitor having a configuration in which a source electrode and a drain electrode of an n-channel field effect transistor are short-circuited to each other, and constitutes a pixel switching element 401-nm. In this configuration, a source electrode and a drain electrode of a transistor configured using the same thin film silicon, insulating film, and metal electrode are short-circuited. In this embodiment, a transistor in which a silicon thin film with a thickness of 50 nm, a silicon oxide thin film with a thickness of 100 nm, a molybdenum thin film with a thickness of 200 nm, a silicon oxide thin film with a thickness of 500 nm, and an aluminum thin film with a thickness of 500 nm are stacked while being appropriately patterned. Are used to form a storage capacitor element 403-nm and a pixel switching element 401-nm. The gate electrode of the transistor constituting the storage capacitor element 403-nm is connected to the pixel electrode 402-nm, and the source / drain electrodes are connected to the capacitor line 203-n.

  FIG. 4 is a block diagram showing a specific configuration of the electronic apparatus 1000 in the present embodiment. The display device 910 is the display device described in FIG. 1, and the external power supply circuit 784 and the video processing circuit 780 are respectively connected to the gate driver 952 through the first FPC 951 and to the source driver 962 through the second FPC 961. Connected to supply necessary power, drive signals, and video signals. The central processing circuit 781 acquires input data from the input / output device 783 via the external I / F circuit 782. Here, the input / output device 783 is, for example, a keyboard, a mouse, a trackball, a touch panel, an LED, a speaker, an antenna, or the like. The central processing circuit 781 performs various arithmetic processing based on data from the outside, and transfers the result to the video processing circuit 780 or the external I / F circuit 782 as a command. The video processing circuit 780 updates the video information based on the command from the central processing circuit 781 and changes the signal supplied to the source driver 962, whereby the display video of the display device 910 changes. Here, the electronic device 1000 specifically includes, for example, an electronic book, a portable document reader, an electronic poster, an electronic flyer, a monitor, a TV, a notebook computer, a PDA, a digital camera, a video camera, a mobile phone, a mobile photo viewer, and a mobile video. Players, portable DVD players, portable audio players, and the like.

  As described above, the electrophoretic element 921 encloses negatively charged white pigment particles and positively charged black pigment particles as a dispersoid. Therefore, if the potential of the common electrode (COM) is higher than the potential of the pixel electrode 402-nm, the white pigment particles move to the protective sheet 922 side, and the black pigment particles move to the active matrix substrate 101 side, and from the protective sheet 922 side. It turns white when viewed. If the potential of the common electrode (COM) is lower than the potential of the pixel electrode 402-nm, the particles move on the contrary, and when viewed from the protective sheet 922 side, the particle turns black. If the potential of the common electrode (COM) and the potential of the pixel electrode 402-nm are equal, the adjustment is made so that the particles do not move, so the previous display state is maintained.

  Therefore, for example, when the common electrode (COM) is maintained at 0 V and a positive potential is applied to each pixel electrode 402-nm, black display can be performed, and white display can be performed by applying a negative potential. However, in this embodiment, the withstand voltage of the pixel switching element 401-nm is 20V, and the potential applied to each pixel electrode 402-nm is equalized when the response speeds for black and white display are the same. : +10 V, white display: −10 V, and the potential difference between the pixel electrode and the common electrode is 10 V. The larger the potential difference, the faster the pigment particles move, so that the response speed of the display device can be increased. However, such a driving method cannot increase the response speed any further. Therefore, in the present embodiment, a driving method for increasing the response speed is performed by sequentially performing an erasing sequence and a display sequence as in Patent Document 1.

  In this embodiment, a monochrome display element is used. However, color display may be performed using a capsule in which a pigment of a different color is enclosed for each pixel.

  FIG. 5 is a timing chart of the erase sequence. In the erase sequence, all scanning lines 201-1 to 201-480 are simultaneously selected to + 20V by the gate driver 952, and 0V is written to the data lines 202-1 to 202-1920 from the source driver 962. The potential of the common electrode (COM) is set to + 20V.

  In this embodiment, the threshold voltage (Vth) of each pixel switching element 401-nm is + 5V, and the gate-source voltage (Vgs) of all the pixel switching elements 401-nm is + 20V during this sequence. Therefore, Vgs >> Vth, and all the pixel switching elements 401-nm are turned on with a relatively low impedance. Therefore, 0 V is written to all the pixel electrodes 402-nm, and the white pigment particles start moving toward the protective sheet 922 and the black pigment particles start moving toward the active matrix substrate 101 over the entire display area. In this embodiment, this state is maintained for 200 msec to drive the particles sufficiently. When such an erasing sequence is performed, the entire display area becomes white and erasing is completed.

  FIG. 6 is a timing chart of the display sequence. The display sequence is performed subsequent to the erase sequence. In the display sequence, the scanning lines 201-1 to 201-480 are sequentially selected by the gate driver 952. That is, the scanning line 201-1 becomes +20 V for 30 μsec with a period of 16.667 msec (selected), and then returns to 0 V. The scanning line 201-2 is selected at a timing delayed by 34.6 μsec with the same period and pulse width as the scanning line 201-1. Thereafter, all the scanning lines 201-n are sequentially selected with a phase shift of 34.6 μsec. The potential of the common electrode (COM) is set to 0V.

  When the scanning line 201-n is selected, the data lines 202-1 to 202-1920 are supplied with a potential corresponding to the video potential of the pixel electrode 402 (402-n-1 to 402-n-1920) by the source driver 962. Written. That is, when the pixel electrode 402-nm corresponds to white display, 0 V is written to the data line 202-m. Then, the potential of the pixel electrode 402-n-m is also written to 0V, and the potential of the common electrode (COM) = the potential of the pixel electrode 402-n-m = 0V, so that the previous state, that is, the white display state is maintained. . On the other hand, when the pixel electrode 402-nm corresponds to black display, + 15V is written to the data line 202-m. Then, the potential of the pixel electrode 402-nm is also written to + 15V, the potential of the common electrode (COM) <the potential of the pixel electrode 402-nm, and the movement of particles occurs and the state changes to the black display state. To do. In this way, the potential corresponding to the video state is written to each pixel electrode 402-nm after 16.67 ms.

  By sequentially performing the erase sequence and the display sequence in this way, even if the withstand voltage of the pixel switching element 401-nm is 20V, the potential difference between the pixel electrode and the common electrode is set to 15V to 20V at the time of display / erasure. The response speed can be improved dramatically. In the present embodiment, the display is limited to black and white binary display for the sake of simplification, but it is of course possible to perform gradation display by applying an intermediate potential or a PWM waveform in the display sequence. Further, an AC pulse wave may be applied to the common electrode or the pixel electrode as described in Patent Document 2 in order to surely erase.

  In the display sequence described with reference to FIG. 6, the period during which + 15V is written in order to display the pixel electrode 402-nm in black is 30 μs during which the scanning line 201-n is selected. In the case of the present embodiment, the particles in the electrophoretic element 921 hardly move in 30 μsec, and then move in the capsule over a period of about 100 m to 200 msec. At this time, the energy ΔE corresponding to the electric charge amount of the particle × the average moving amount of the particle × the electric field intensity in the capsule is lost, and if the capacity of the storage capacitor element 403-nm is the capacitance C1, only the square root of ΔE ÷ C1. The potential of the pixel electrode 402-nm decreases. When the potential of the pixel electrode 402-nm decreases, the moving speed of the particles also decreases. Therefore, in order to increase the moving speed of the particles (that is, increase the black display response speed in the display sequence), the storage capacitor element 403-nm It is effective to increase the capacitance C1.

  On the other hand, when the pixel electrode 402-nm is kept in white display in the display sequence, no particle movement occurs, so that no energy loss occurs, and the capacitance of the storage capacitor element 403-nm at this time C2 is not related to the response speed. In the erasing sequence described with reference to FIG. 5, the period for writing 0V to the pixel electrode 402-nm is 200 msec, and the particles in the electrophoretic element 921 can finish the movement almost completely. Since energy is supplied from the source driver 962 through the data line 202-m and the pixel switching element 401-nm, there is no need to hold the potential by the storage capacitor 403-nm as in the display sequence. The capacitance C3 of the storage capacitor element 403-nm at this time is not related to the response speed. On the other hand, as the capacitance C2 and the capacitance C3 increase, the amount of charge written from the data lines 202-1 to 202-1920 increases, so that power consumption increases. Further, as described in Patent Document 2, when an afterimage is erased by applying an AC pulse potential to the pixel electrode 402-nm during the erasing sequence, the frequency is limited by the capacitor C3. From the above, it is better that the capacitance C2 of the storage capacitor element 403-nm in white display in the display sequence and the capacitance C3 of the storage capacitor element 403-nm in the erase sequence are smaller.

  If a normal capacitor is used for the storage capacitor element 403-nm, the capacitance is constant regardless of the potential state, so that C1 = C2 = C3 and these requirements cannot be satisfied at the same time. On the other hand, when a switching element is provided as in Patent Document 2, the capacitance C3 can be substantially “0”. However, since it is necessary to increase the number of switching elements, there is a disadvantage that high definition cannot be achieved. Further, the capacity C2 cannot be made smaller than the capacity C1. In this embodiment, these problems are solved by using a field effect transistor for the storage capacitor element 403-nm.

  FIG. 7 is a Cgs-Vgs characteristic diagram at a frequency of about 10 KHz to 1 MHz corresponding to the writing time of the field effect transistor used for the storage capacitor element 403-nm. Vgs is the potential between the gate electrode and the source electrode of the field effect transistor that constitutes the storage capacitor element 403-nm, and the storage capacitor element 403-nm includes the pixel switching element 401-nm. Since the source electrode and the drain electrode of a transistor configured using the same thin film silicon, insulating film, and metal electrode are short-circuited, the threshold voltage (Vth) is the same as that of the pixel switching element 401-nm. + 5V. Therefore, if Vgs >> Vth, the silicon (channel portion) that overlaps with the gate electrode of the storage capacitor element 403-nm is inverted and carriers are excited to increase the capacitance, so that Vgs ≦ Vth. For example, the channel portion is depleted and acts as an insulator, so that the capacitance decreases.

  In this embodiment, the gate electrode of the storage capacitor element 403-nm is connected to the pixel electrode 402-nm, and the source electrode and the drain electrode of the storage capacitor element 403-nm are connected to the capacitor line 202-n. Is done. At the time of black writing in the display sequence, the pixel electrode 402-nm is written to + 15V, and the capacitor line 202-n has the same potential as the common electrode (COM) and is 0V. At this time, since Vgs = 15 V and Vgs >> Vth is satisfied, the channel portion is in an inverted state, and the capacitance C1 = 500 fF as shown in FIG. On the other hand, at the time of white writing in the display sequence, the pixel electrode 402-nm is written to 0V, and since the capacitor line 202-n is also 0V, Vgs = 0V and Vgs ≦ Vth. Capacitance C2 = 20 fF. In the erase sequence, the pixel electrode 402-n-m is 0V and the capacitor line 202-n is + 20V, so Vgs = −20V, and similarly, the capacitor C3 = 20fF. That is, C1> C2 = C3, and it is possible to solve both the problems of improving display quality and reducing power consumption.

  In this way, the storage capacitor element 403-n-m is a capacitor in which the source electrode and the drain electrode of the field effect transistor are short-circuited, one end thereof is set to the same potential as the common electrode (COM), and the other end is connected to the pixel electrode. By doing so, it is possible to simultaneously improve the response speed during black display and reduce the power consumption during white display / erasure. Further, since there is no addition of a switching element or the like, high definition can be achieved.

  Further, in this embodiment, the field effect transistor constituting the storage capacitor element is formed of the same thin film as the pixel switching element and can be manufactured in the same manufacturing process without any additional process, so that the manufacturing cost does not increase. In this embodiment, a thin film transistor in which a source electrode and a drain electrode are short-circuited is used as a capacitor element. However, a so-called MOS (Metal-Oxide-Semiconductor) capacitor or a source electrode / drain electrode that is not structurally separated is used. There is no problem even if an element having a structure called a MOS diode is used as a storage capacitor.

  The present invention is not limited to the above-described embodiment, and can be applied to all display devices using display elements having memory properties such as ferroelectric liquid crystal elements in addition to electrophoretic elements.

  DESCRIPTION OF SYMBOLS 101 ... Active matrix substrate, 201 ... Scan line, 202 ... Data line, 203 ... Capacitor line, 401 ... Pixel switching element, 402 ... Pixel electrode, 403 ... Holding capacitor element, 910 ... Display device, 921 ... Electrophoretic element, 922 ... Protective sheet, 952 ... Gate driver, 962 ... Source driver.

Claims (9)

A plurality of pixel electrodes and a storage capacitor element having one end connected to the pixel electrodes are provided, and an erasing sequence for simultaneously writing potentials to all of the plurality of pixel electrodes and individually writing potentials to the plurality of pixel electrodes. An electro-optic panel having a display sequence,
The capacitance value of the holding capacitor element changes depending on the potential difference applied to both ends,
2. The electro-optical panel according to claim 1, wherein a capacitance value of the storage capacitor element in the erase sequence is smaller than a capacitance value of the storage capacitor element in the display sequence. A common electrode facing the plurality of pixel electrodes;
The potential of the common electrode is different between the erase sequence and the display sequence,
The electro-optical panel according to claim 1, wherein the other end of the storage capacitor is supplied with the same potential as that of the common electrode. Comprising a plurality of pixel switching elements connected to the plurality of pixel electrodes;
3. The electro-optical panel according to claim 1, wherein the storage capacitor element and the pixel switching element are formed of thin films having the same film thickness and film composition.   The electro-optical panel according to claim 1, wherein the storage capacitor element includes a capacitor in which a source electrode and a drain electrode of a transistor are short-circuited.   5. The electro-optical panel according to claim 4, wherein the one end of the storage capacitor element includes a gate electrode of the transistor, and the other end includes the short-circuited source and drain of the transistor.   The electro-optical panel according to claim 3, wherein the storage capacitor element and the pixel switching element each include a thin film silicon, an insulating film, and a metal electrode.   7. An electrophoretic element is provided between the pixel electrode and the common electrode, and the electrophoretic element includes positively or negatively charged pigment particles as a dispersoid. The electro-optical panel according to Item.   An electro-optic display device comprising the electro-optic panel according to claim 1.   An electronic apparatus comprising the electro-optical device according to claim 8.

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