CN113363266A - Array substrate and pixel driving circuit - Google Patents
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- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
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- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0257—Reduction of after-image effects
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Abstract
本发明公开了一种阵列基板及像素驱动电路，阵列基板包括呈阵列分布的多个像素电路以及与各像素电路电连接的第一信号线。像素电路包括驱动晶体管，驱动晶体管包括有源层、源漏极层和栅极层，源漏极层包括相互绝缘的源极和漏极，第一信号线设于栅极层背离有源层一侧，源极与第一信号线间形成第一电容，通过增大源极与第一信号线之间的重合面积，增大第一电容的电容量，减小驱动晶体管的栅极与驱动晶体管的源极之间的电位差，避免驱动晶体管的栅极与驱动晶体管的源极之间长时间保持较大的电位差，从而避免在切换画面时上一个画面依然存在导致的残影，提高显示面板的显示效果。
The invention discloses an array substrate and a pixel driving circuit. The array substrate comprises a plurality of pixel circuits distributed in an array and a first signal line electrically connected with each pixel circuit. The pixel circuit includes a drive transistor, the drive transistor includes an active layer, a source/drain layer and a gate layer, the source/drain layer includes a source electrode and a drain electrode that are insulated from each other, and the first signal line is arranged on the gate layer away from the active layer. On the side, a first capacitor is formed between the source and the first signal line. By increasing the overlapping area between the source and the first signal line, the capacitance of the first capacitor is increased, and the gate of the driving transistor and the driving transistor are reduced. The potential difference between the source electrodes of the driving transistor can be avoided to keep a large potential difference between the gate of the driving transistor and the source of the driving transistor for a long time, so as to avoid the afterimage caused by the presence of the previous screen when the screen is switched, and improve the display. The display effect of the panel.
Description
Technical Field
The invention belongs to the technical field of electronic products, and particularly relates to an array substrate and a pixel driving circuit.
Background
With the development and innovation in the field of photoelectric display, digital display devices are widely used, wherein display panels are indispensable interpersonal communication interfaces in display devices, especially Organic Light Emitting Diode (OLED) display panels, which have the advantages of self-luminescence, energy saving, consumption reduction, flexibility, good flexibility, and the like, and are widely used in terminal products such as smart phones and computer displays. However, the current display panel often has a certain delay when displaying black and white dynamic images, i.e. the brightness of the image needs to be adjusted and then gradually stabilized, and the macro appearance thereof is that the black image is switched to the white image and the black and white image is scrolled to generate a smear phenomenon.
Therefore, a new array substrate and a new pixel driving circuit are needed.
Disclosure of Invention
The embodiment of the invention provides an array substrate and a pixel driving circuit, wherein the array substrate reduces jump voltage during black-and-white image switching, improves the smear of a display panel and improves the display effect.
In one aspect, the embodiment of the invention provides an array substrate, which includes a plurality of pixel circuits distributed in an array and a first signal line electrically connected to each of the pixel circuits; the pixel circuit comprises a driving transistor, the driving transistor comprises an active layer, a source drain layer and a grid layer, the source drain layer and the grid layer are arranged on the active layer in an insulating mode, the source drain layer comprises a source electrode and a drain electrode which are insulated from each other, a first signal line is arranged on one side, deviating from the active layer, of the grid layer, and the projection area of the source electrode on the first signal line is larger than that of the drain electrode on the first signal line.
According to an aspect of the present invention, in an extending direction along the first signal line, a maximum distance between an orthogonal projection of the source electrode on the active layer and an orthogonal projection of the gate electrode layer on the active layer is larger than a maximum distance between an orthogonal projection of the drain electrode on the active layer and an orthogonal projection of the gate electrode layer on the active layer.
According to an aspect of the present invention, a maximum distance between an orthogonal projection of the source electrode on the active layer and an orthogonal projection of the gate electrode layer on the active layer in an extending direction of the first signal line is 20 μm to 60 μm.
According to an aspect of the present invention, the first signal line includes a high-level power supply signal line or a low-level power supply signal line.
According to an aspect of the present invention, the liquid crystal display device further includes a first insulating layer provided between the active layer and the gate layer and a second insulating layer provided between the gate layer and the first signal line in a direction perpendicular to an extending direction of the first signal line and perpendicular to the active layer.
According to an aspect of the invention, an overlapping portion of an orthographic projection of the source electrode on the active layer and an orthographic projection of the first signal line on the active layer is at least one of rectangular and T-shaped.
According to an aspect of the present invention, in a direction perpendicular to an extending direction of the first signal line and parallel to the active layer, a length of an orthogonal projection of the source electrode on the first signal line is larger than a length of an orthogonal projection of the drain electrode on the first signal line; and/or the width of the orthographic projection of the source electrode on the first signal line is larger than that of the orthographic projection of the drain electrode on the first signal line.
According to an aspect of the present invention, the active layer includes a channel portion provided in a space between the source electrode and the drain electrode, and an orthogonal projection of the channel portion on the first signal line and an orthogonal projection of the gate layer on the first signal line at least partially overlap.
According to an aspect of the present invention, an extended locus of an orthogonal projection of the channel portion on the first signal line is one of a straight line and a broken line.
An embodiment of the present invention further provides a pixel driving circuit, including: a light emitting element; a driving module for supplying a driving current to the light emitting element; the storage module is connected with the driving module and used for maintaining the electric potential of the control end of the driving module; the data writing module is connected with the driving module and the storage module and used for writing data signals into the control end of the driving module; the light-emitting control module is connected with the light-emitting element, the driving module and a power supply voltage input end and is used for controlling the light-emitting element to emit light; the initialization module is connected with the driving module and the light-emitting element and is used for initializing the control end of the driving module and the light-emitting element; and the potential difference reduction module is connected with the driving module and the light-emitting control module and used for reducing the potential difference between the input end of the driving module and the control end of the driving module under the action of a power supply voltage signal at the power supply voltage input end. Compared with the prior art, the array substrate provided by the embodiment of the invention comprises a plurality of pixel circuits distributed in an array manner and first signal lines electrically connected with the pixel circuits. The pixel circuit comprises a driving transistor, the driving transistor comprises an active layer, a source drain layer and a grid layer, the source drain layer comprises a source electrode and a drain electrode which are insulated from each other, a first signal line is arranged on one side, away from the active layer, of the grid layer, a first capacitor is formed between the source electrode and the first signal line, the capacitance of the first capacitor is increased by increasing the overlapping area between the source electrode and the first signal line, the potential difference between the grid electrode of the driving transistor and the source electrode of the driving transistor is reduced, the situation that a larger potential difference is kept between the grid electrode of the driving transistor and the source electrode of the driving transistor for a long time is avoided, therefore, the situation that the residual image caused by the fact that the previous picture still exists when the picture is switched is avoided, and the display effect of the display panel is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments of the present invention will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
FIG. 2 is a cross-sectional view taken along A-A of FIG. 1;
fig. 3 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present invention;
fig. 7 is a circuit diagram of a pixel driving circuit according to an embodiment of the present invention;
fig. 8 is a timing diagram of a pixel driving circuit according to an embodiment of the invention.
Detailed Description
Features and exemplary embodiments of various aspects of the present invention will be described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the present invention.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
For better understanding of the present invention, the array substrate and the pixel driving circuit according to the embodiments of the present invention are described in detail below with reference to fig. 1 to 8.
Referring to fig. 1 and 2, an embodiment of the invention provides an array substrate, which includes a plurality of pixel circuits distributed in an array and a first signal line 1 electrically connected to each pixel circuit; the pixel circuit comprises a driving transistor, the driving transistor comprises an active layer 2, a source drain layer 3 and a grid layer 4, the source drain layer 3 and the grid layer 4 are arranged on the active layer 2 in an insulating mode, the source drain layer 3 comprises a source electrode 31 and a drain electrode 32 which are mutually insulated, the first signal line 1 is arranged on one side, away from the active layer 2, of the grid layer 4, and the projection area of the source electrode 31 on the first signal line 1 is larger than that of the drain electrode 32 on the first signal line 1.
It should be noted that the first signal line 1 is disposed on a side of the gate layer 4 away from the active layer 2, so that a first capacitor C1 is formed between the source 31 and the first signal line 1, when the display panel is switched between black and white images, the first capacitor C1 discharges to provide a voltage for the source 31 of the driving transistor, so as to reduce a potential difference between the gate of the driving transistor and the source 31 of the driving transistor, and avoid a large potential difference between the gate of the driving transistor and the source 31 of the driving transistor for a long time, thereby avoiding an afterimage still existing on a previous picture when the picture is switched, and improving a display effect of the display panel. By increasing the projected area between the source 31 and the first signal line 2 and increasing the capacitance of the first capacitor C1, the potential difference between the gate of the driving transistor and the source 31 of the driving transistor is further reduced, thereby improving the smear of the display panel and enhancing the display effect.
According to the calculation formula of the capacitance, the capacitance of the first capacitor C1 is in direct proportion to the dielectric constant of the medium between the plates and the area of the plates and in inverse proportion to the distance between the plates. Therefore, the capacitance of the first capacitor C1 can be increased by increasing the area of the source 31 and the first signal line 1 that overlap each other, while the dielectric constant of the interpolar dielectric and the distance between the plates are kept constant. That is, when the first capacitor C1 discharges after the capacitance of the first capacitor C1 is increased, the potential at the source 31 of the driving transistor can be further increased, and the potential difference between the gate of the driving transistor and the source 31 of the driving transistor can be reduced.
In order to increase the overlapping area of the source electrode 31 and the first signal line 2, referring to fig. 1, in the extending direction of the first signal line 2, the maximum distance between the orthographic projection of the source electrode 31 on the active layer 2 and the orthographic projection of the gate electrode layer 4 on the active layer 2 in the embodiment of the invention is greater than the maximum distance between the orthographic projection of the drain electrode 32 on the active layer 2 and the orthographic projection of the gate electrode layer 4 on the active layer 2. Therefore, when the relative distance between the source 31 and the drain 32 is constant in a single driving transistor, the gate 41 is adjusted to be positioned relative to the source 31 and the drain 32, that is, the gate 41 is disposed in a direction away from the source 31, so that an asymmetric driving transistor structure is formed, and thus the effect of increasing the relative area between the source 31 and the first signal line 2 can be achieved, and the capacitance of the first capacitor C1 can be increased.
Optionally, the maximum distance between the orthographic projection of the source electrode 31 on the active layer 2 and the orthographic projection of the gate electrode layer 4 on the active layer 2 is 20 μm to 60 μm. The specific size thereof may be adjusted according to the actual structure of the driving transistor, and is not particularly limited herein.
To further illustrate the specific structure of the array substrate, please refer to fig. 2, the driving transistor of the array substrate includes an active layer 2, a source drain layer 3 and a gate layer 4, the active layer 2 is a semiconductor layer where the driving transistor is located, the source drain layer 3 includes a source 31 and a drain 32 that are insulated from each other, the source drain layer 3 is a metal conductive layer where the source 31 and the drain 32 of the driving transistor are located, and the gate layer 4 is a metal conductive layer where the gate 41 of the driving transistor is located. The drive transistor further includes an interlayer insulating layer 5, the interlayer insulating layer 5 including a first insulating layer 51 and a second insulating layer 52, the first insulating layer 51 being provided between the active layer 2 and the gate layer 4, and the second insulating layer 52 being provided between the gate layer 4 and the first signal line 1 in a direction perpendicular to the extending direction of the first signal line 1 and perpendicular to the active layer 2. The gate 41 of the driving transistor is generally used for receiving a control signal to turn on or off the driving transistor 31 under the control of the control signal. The source 31 of the driving transistor is connected to the first signal line, the drain 32 is connected to the light emitting element, and when the gate 41 receives an on control signal, the gate 41 controls the active layer 2 to be on, and a path is formed between the source 31 and the drain 32, thereby realizing light emission of the light emitting element.
Referring to fig. 1 and 2, an orthographic projection of the source 31 on the active layer 2 and an orthographic projection of the first signal line 1 on the active layer 2 are partially overlapped, so that a first capacitor C1 is formed, wherein the source 31 and the first signal line 1 are upper and lower plates, and the interlayer insulating layer 5 is an interpolar medium. When the display panel is switched between black and white pictures, the first capacitor C1 can supply power to the source electrode 31, and reduce the potential difference between the gate electrode 41 and the source electrode 31. When the projection area of the source 31 on the first signal line 1 is increased, the capacitance of the first capacitor C1 is also increased, and the potential difference between the gate 41 and the source 31 is further decreased, thereby avoiding the phenomenon of poor image sticking of the display panel.
Alternatively, the active layer 2 may be a single crystal Silicon active layer or a polysilicon active layer, which may be Low Temperature Polysilicon (LTPS). The material of the source 31, drain 32 and gate 41 may include one or a combination of molybdenum, titanium, aluminum, copper, etc.
Wherein the first signal line includes a power signal line or a ground signal line. Specifically, when the driving transistor is a PMOS transistor, the source 31 is connected to a high-level power supply signal line, i.e., a VDD signal line, the drain 32 is connected to the light emitting element, and the first capacitor C1 is formed between the source 31 and the VDD signal line. When the driving transistor is an NMOS transistor, the source 31 is connected to the low-level power supply signal line, i.e., the VSS signal line, and the first capacitor C1 is formed between the low-level power supply signal line and the source 31.
In some alternative embodiments, the overlapping portion of the orthographic projection of the source electrode 31 on the active layer 2 and the orthographic projection of the first signal line 1 on the active layer 2 is at least one of rectangular and T-shaped. Referring to fig. 1 and 4, in fig. 1, the overlapping portion of the orthographic projection of the source 31 on the active layer 2 and the orthographic projection of the first signal line 1 on the active layer 2 is T-shaped, and in fig. 4, the overlapping portion of the orthographic projection of the source 31 on the active layer 2 and the orthographic projection of the first signal line 1 on the active layer 2 is rectangular.
It is understood that the capacitance of the first capacitor C1 can be increased by changing the projected area of the source 31 on the first signal line 1. The shape of the overlapping portion needs to be adjusted by comprehensively considering the manufacturing process and the specific structure of the array substrate, which can increase the capacitance of the first capacitor C1. Specifically, the line width of the first signal line 1 is 1.5 μm to 25 μm, the length of the first signal line 1 is 1.5 μm to 25 μm, and the projection area of the source electrode 31 on the first signal line 1 is 2.5 μm2～500μm2Compared with the prior art, the projection area of the source electrode 31 on the first signal line 1 can be effectively increased by more than 5 μm2Effectively increasing the capacitance of the first capacitor C1.
In some alternative embodiments, in a direction perpendicular to the extending direction of the first signal line 1 and parallel to the active layer 2, the length of the orthographic projection of the source electrode 31 on the first signal line 1 is greater than the length of the orthographic projection of the drain electrode 32 on the first signal line 1; and/or the width of the orthographic projection of the source electrode 31 on the first signal line 1 is larger than the width of the orthographic projection of the drain electrode 32 on the first signal line 1. Specifically, the projection area of the source electrode 31 on the first signal line 1 can be increased by adjusting at least one of the length and the width of the orthographic projection of the source electrode 31 on the first signal line 1.
In addition, in order to further facilitate the conduction of the source electrode 31 and the drain electrode 32 and improve the response speed of the light emitting device, referring to fig. 1, fig. 2, fig. 5 and fig. 6, in the embodiment of the present invention, the active layer 2 includes the channel portion 6, the channel portion 6 is disposed in the space between the source electrode 31 and the drain electrode 32, and the orthographic projection of the channel portion 6 on the first signal line 1 and the orthographic projection of the gate layer 4 on the first signal line 1 at least partially overlap. By providing the channel portion 6 in the active layer 2 facing the gate layer 4, conduction between the gate layer 4 and the active layer 2 can be facilitated, and the response speed of the light-emitting element can be improved.
Alternatively, the extended locus of the orthographic projection of the channel portion 6 on the first signal line 1 may be one of a straight line and a broken line. Similarly, the specific extending trace of the channel portion 6 may also be adjusted according to the preparation process and the specific structure of the array substrate, and the specific shape and size thereof are not limited in detail herein.
Referring to fig. 6 to 7, a pixel driving circuit according to an embodiment of the present invention includes a light emitting device D1, a driving module P11, a memory module P12, a data writing module P13, a light emitting control module P14, an initialization module P15, and a potential difference reduction module P16. The Light Emitting element D1 can be selected according to the type of the display panel, for example, the Light Emitting element D1 can be a Light Emitting Diode (LED) or an Organic Light Emitting Diode (OLED), but is not limited thereto. Specifically, the cathode of the light emitting element D1 is connected to a second power supply voltage input terminal VSS.
The driving module P11 may be used to provide a driving current to the light emitting element D1. Specifically, whether the driving current can flow to the light emitting element D1 through the driving module P11 can be controlled by controlling the driving module P11 to be turned on and off.
The storage module P12 is connected to the driving module P11 and has a function of storing electric energy. The memory module P12 is used to maintain the voltage level at the control terminal of the driving module P11. Specifically, the storage block P12 may be charged during a charging phase in the driving process of the pixel driving circuit to the pixel cell. In the read-write light-emitting phase during the driving process, the memory module P12 can use the voltage charged in the charging phase to maintain the voltage at the control terminal of the driving module P11.
The data write module P13 is connected to the drive module P11 and the memory module P12 for writing data signals to the control terminal of the drive module P11. Specifically, the data write block P13 is connected to the data signal terminal VDATA and the first scan signal terminal S1. The data signal terminal VDATA is for providing a data signal. The first scan signal terminal S1 is used for providing a first scan signal. In a charging phase during driving, the data write block P13 charges the memory block P12 through the driving block P11 by using a data signal under the control of a first scan signal. In the read-write light-emitting phase during the driving process, the memory module P12 uses the voltage charged in the charging phase to maintain the voltage potential of the control terminal of the driving module P11, which is equivalent to writing the data signal into the control terminal of the driving module P11.
The light emitting control module P14 is connected to the light emitting device D1, the driving module P11 and the power voltage input terminal, and is used for controlling the light emitting device D1 to emit light. Specifically, the light emission control module P14 is connected to the light emission control signal terminal EM and the first power voltage input terminal VDD. The emission control signal terminal EM is used to provide an emission control signal. The first power supply voltage input terminal VDD is used to provide a high level signal. In the read/write lighting phase of the driving process, the lighting control module P14 is turned on under the control of the lighting control signal, and can transmit the driving current generated by the high level signal to the light emitting device D1, so that the light emitting device D1 emits light.
The initialization module P15 is connected to the driving module P11 and the light emitting device D1, and respectively initializes the control terminal of the driving module P11 and the anode of the light emitting device D1. Specifically, the initialization block P15 is connected to the reference voltage signal terminal VREF and the second scan signal terminal S2. The reference voltage signal terminal VREF is used to provide a reference voltage signal, which is used as an initialization signal. In some examples, the voltage of the reference voltage signal is negative. The second scan signal terminal S2 is for providing a second scan signal. In an initialization stage during the driving process, the initialization block P15 is turned on under the control of the second scan signal, and initializes the control terminal of the driving block P11 with the reference voltage signal, and charges the voltage of the reference voltage signal to the anodes of the memory block P12 and the light emitting element D1 to initialize the anode of the light emitting element D1.
The potential difference reduction module P16 is connected to the driving module P11 and the power voltage input terminal, and configured to reduce a potential difference between the input terminal of the driving module P11 and the control terminal of the driving module P11 under the action of a high level signal output by the first power voltage input terminal VDD.
Specifically, referring to fig. 6 and 7, the driving module P11 includes a first transistor T1, and the first transistor T1 is a driving transistor in the pixel driving circuit; the memory module P12 includes a second capacitor C2; the data write module P13 includes a second transistor T2 and a third transistor T3; the light emission control module P14 includes a fourth transistor T4 and a fifth transistor T5; the initialization module P15 includes a sixth transistor T6 and a seventh transistor T7.
A control terminal of the first transistor T1 is connected to a first terminal of the second capacitor C2, a second terminal of the second transistor T2, and a second terminal of the sixth transistor T6. A first terminal of the first transistor T1 is connected to the second terminal of the third transistor T3, the second terminal of the fourth transistor T4, and the first terminal of the first capacitor C1. The second terminal of the first transistor T1 is connected to the first terminal of the second transistor T2 and the first terminal of the fifth transistor T5. The first terminal of the first transistor T1 is the input terminal of the driving module P11, and the second terminal of the first transistor T1 is the output terminal of the driving module P11.
A control terminal of the second transistor T2 is connected to the first scan signal terminal S1. A first terminal of the second transistor T2 is connected to a first terminal of the fifth transistor T5. A second terminal of the second transistor T2 is connected to a first terminal of the second capacitor C2 and a second terminal of the sixth transistor T6.
A control terminal of the third transistor T3 is connected to the first scan signal terminal S1. A first terminal of the third transistor T3 is connected to the data signal terminal VDATA. A second terminal of the third transistor T3 is connected to the first terminal of the first capacitor C1 and the second terminal of the fourth transistor T4.
A control terminal of the fourth transistor T4 is connected to the emission control signal terminal EM. A first terminal of the fourth transistor T4 is connected to the first power voltage input terminal VDD and a second terminal of the second capacitor C2. A second terminal of the fourth transistor T4 is connected to a first terminal of the first capacitor C1.
A control terminal of the fifth transistor T5 is connected to the emission control signal terminal EM. A second terminal of the fifth transistor T5 is connected to the anode of the light emitting element D1.
A control terminal of the sixth transistor T6 is connected to the second scan signal terminal S2. A first terminal of the sixth transistor T6 is connected to the reference voltage input terminal VREF and a first terminal of the seventh transistor T7. A second terminal of the sixth transistor T6 is connected to a first terminal of the second capacitor C2.
A control terminal of the seventh transistor T7 is connected to the second scan signal terminal S2. A first terminal of the seventh transistor T7 is connected to the reference voltage signal terminal VREF. A second terminal of the seventh transistor T7 is connected to the anode of the light emitting element D1. The second terminal of the seventh transistor T7 is the first output terminal of the initialization block P15. A second terminal of the first capacitor C1 is connected to a second terminal of the seventh transistor.
A second terminal of the second capacitor C2 is connected to the first supply voltage input terminal VDD.
The cathode of the light emitting element D1 is connected to a second power supply voltage input terminal VSS. The second power voltage input terminal VSS is used for providing a low level signal, and in some examples, the second power voltage input terminal may be a ground terminal, which is not limited herein.
Taking fig. 3 as an example, the driving timing of the pixel circuit between two frames includes three stages, an initialization stage, a data writing stage, and a light emitting stage.
In the initialization period T1, the second scan signal S2 is at a high level, and the emission control signal EM and the first scan signal S1 are at a low level. The emission control signal EM controls the fourth transistor T4 and the fifth transistor T5 to be turned off; the second scan signal S2 controls the second transistor T2 and the third transistor T3 to be turned off; the first scan signal S1 controls the sixth transistor T6 to be turned on, and the initial voltage VREF initializes the gate of the first transistor T1; the first scan signal S1 controls the seventh transistor T7 to be turned on, and the initial voltage VREF initializes the anode of the light emitting device D1. Meanwhile, the first capacitor C1 is used as a potential difference reduction module to reduce the potential difference between the input terminal of the driving module P11 and the control terminal of the driving module P11 under the action of the power voltage signal. Specifically, compared to the control terminal of the driving module P11 in the prior art that is higher than the input terminal of the driving module P11, in the present embodiment, under the action of the first capacitor C1, the potential of the input terminal, i.e., the source, of the first transistor T1 is greater than the potential of the control terminal, i.e., the gate, of the first transistor T1, so that the first transistor T1 is in a conducting state. For example, in the initialization period T1 between two frames of the black to white frames of the related art, the voltage of the source of the first transistor T1 is-4V, the voltage of the gate thereof is-3V, and the first transistor T1 is in the off state, whereas in the initialization period T1 between two frames of the white to white frames of the related art, the voltage of the source of the first transistor T1 is 0V, the voltage of the gate thereof is-3V, and the first transistor T1 is in the on state, and the states of the first transistor T1 between two frames of the black to white frames and between two frames of the white to white frames are different, so that the time required for completing the display is long, and the problem of smear is easily generated.
In the embodiment of the present invention, in the initialization period T1 between two frames from the black frame to the white frame, the voltage of the source of the first transistor T1 is 3V, the voltage of the gate thereof is-3V, the first transistor T1 is in the on state, and between two frames from the white frame to the white frame, the voltage of the source of the first transistor T1 is 3V, the voltage of the gate thereof is-3V, the first transistor T1 is in the on state, and the states of the first transistor T1 between two frames from the black frame to the white frame and between two frames from the white frame to the black frame are the same, so that the display uniformity is achieved, and the problem of smear is avoided.
In the data writing phase T2, a data signal VDATA corresponding to the light emission luminance of the light emitting device D1 is supplied. The emission control signal EM and the first scan signal S1 are at a high level, and the second scan signal S2 is at a low level. The emission control signal EM controls the fourth and fifth transistors T4 and T5 to be turned off; the first scan signal S1 controls the sixth transistor T6 and the seventh transistor T7 to be turned off; the second scan signal S2 controls the second transistor T2 and the third transistor T3 to turn on, so that the data signal VDATA is written into the gate of the first transistor T1 via the source and the drain of the first transistor T1. The gate voltage of the first transistor T1 gradually increases to VDATA + Vth, and the data writing phase is completed.
In the light emitting period T3, the first scan signal S1 and the second scan signal S2 are at a high level, and the light emission control signal EM is at a low level. The first scan signal S1 controls the sixth transistor T6 and the seventh transistor T7 to be turned off; the second scan signal S2 controls the second transistor T2 and the third transistor T3 to be turned off; the light emission control signal EM controls the fourth transistor T4 and the fifth transistor T5 to be turned on, the gate voltage of the first transistor T1 is VDATA + Vth, and the source voltage applies the first power source VDD, thereby generating a driving current, which flows into the anode of the light emitting device D1, and drives the light emitting device D1 to emit light.
As will be apparent to those skilled in the art, for convenience and brevity of description, the specific working processes of the systems, modules and units described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again. It should be understood that the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive various equivalent modifications or substitutions within the technical scope of the present invention, and these modifications or substitutions should be covered within the scope of the present invention.
It should also be noted that the exemplary embodiments mentioned in this patent describe some methods or systems based on a series of steps or devices. However, the present invention is not limited to the order of the above-described steps, that is, the steps may be performed in the order mentioned in the embodiments, may be performed in an order different from the order in the embodiments, or may be performed simultaneously.
Claims (10)
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105336295A (en) * | 2014-08-05 | 2016-02-17 | 三星显示有限公司 | Display apparatus |
| WO2021102905A1 (en) * | 2019-11-29 | 2021-06-03 | 京东方科技集团股份有限公司 | Display substrate and manufacturing method therefor, and display apparatus |
| WO2021104481A1 (en) * | 2019-11-29 | 2021-06-03 | 京东方科技集团股份有限公司 | Display substrate and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105336295A (en) * | 2014-08-05 | 2016-02-17 | 三星显示有限公司 | Display apparatus |
| WO2021102905A1 (en) * | 2019-11-29 | 2021-06-03 | 京东方科技集团股份有限公司 | Display substrate and manufacturing method therefor, and display apparatus |
| WO2021104481A1 (en) * | 2019-11-29 | 2021-06-03 | 京东方科技集团股份有限公司 | Display substrate and display device |
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| CN115101537A (en) * | 2022-06-22 | 2022-09-23 | 合肥维信诺科技有限公司 | Array substrate and display panel |
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