JP2010157855A - Limiter circuit - Google Patents

Abstract

A limiter circuit capable of accurately limiting an output voltage level is provided.
A limiter circuit includes a constant current source, a differential input circuit including a first transistor and a second transistor connected to the constant current source and constituting a differential pair, and a first control of the first transistor. An output voltage generation circuit that generates an output voltage corresponding to a difference in voltage applied to each of the electrode and the second control electrode of the second transistor, and the voltage levels of the first control electrode and the second control electrode are matched. A feedback circuit that applies a feedback voltage corresponding to the output voltage to the second control electrode, and a level of the output voltage changes according to a change in the input voltage applied to either the first control electrode or the second control electrode. As a result, the first current corresponding to the level of the output voltage is absorbed from one of the electrodes on the side not connected to the constant current source of the first transistor or the second transistor. And a non-sink current circuit.
[Selection] Figure 1

Description

  The present invention relates to a limiter circuit.

A limiter circuit may be used to generate an output voltage corresponding to a change in the input voltage and limit the amplitude level of the output voltage (see, for example, Patent Document 1). FIG. 5 is a diagram illustrating a configuration example of the limiter circuit. The limiter circuit 200 is a circuit that outputs an output voltage Vout obtained by amplifying the input voltage Vin and limits the amplitude level of the output voltage Vout. The limiter circuit 200 includes an amplifier circuit 300, a voltage source 301, and diodes 302 and 303. The amplifier circuit 300 amplifies the input voltage Vin and outputs it as an output voltage Vout. In the diode 302, the output voltage Vout is applied to the cathode, and the voltage Vm of the voltage source 301 is applied to the anode. On the other hand, in the diode 303, the output voltage Vout is applied to the anode, and the voltage Vm is applied to the cathode. For this reason, for example, when the level of the output voltage Vout becomes higher than the voltage Vm by the forward voltage Vf of the diode 303, the diode 303 is turned on. On the other hand, when the level of the output voltage Vout becomes lower than the voltage Vm by the forward voltage Vf of the diode 302, the diode 302 is turned on. Therefore, the level of the output voltage Vout is limited in the range from Vm−Vf to Vm + Vf.
Japanese Unexamined Patent Publication No. 7-74568

  As described above, the limiter circuit 200 uses the diodes 302 and 303 to limit the amplitude level of the output voltage Vout. In general, the forward voltage Vf of the diodes 302 and 303 varies depending on manufacturing variations and temperature. For this reason, there is a problem that it is difficult to accurately limit the level of the output voltage Vout.

  The present invention has been made in view of the above problems, and an object thereof is to provide a limiter circuit capable of accurately limiting the level of an output voltage.

  In order to achieve the above object, a limiter circuit according to one aspect of the present invention includes a constant current source, and a difference provided with a first transistor and a second transistor connected to the constant current source and constituting a differential pair. A dynamic input circuit, an output voltage generation circuit for generating an output voltage corresponding to a difference between voltages applied to the first control electrode of the first transistor and the second control electrode of the second transistor, and the first A feedback circuit for applying a feedback voltage corresponding to the output voltage to the second control electrode in order to match the voltage levels of the control electrode and the second control electrode; and the first control electrode or the second control electrode When the level of the output voltage changes according to the change in the input voltage applied to either one of the first transistor and the second transistor on the side not connected to the constant current source From one electrode through which any small current of poles, characterized in that it and a sink current circuit for drawing a first current corresponding to the level of the output voltage.

  It is possible to provide a limiter circuit capable of accurately limiting the output voltage level.

  At least the following matters will become apparent from the description of this specification and the accompanying drawings.

  FIG. 1 is a diagram showing a configuration of a limiter circuit 10 according to an embodiment of the present invention. The limiter circuit 10 is a circuit that changes the output voltage Vout according to the input voltage Vin and limits the amplitude of the output voltage Vout. The limiter circuit 10 according to the present embodiment is used, for example, when amplifying an audio signal input from a microphone (not shown) and limiting the amplitude level of the amplified audio signal. The limiter circuit 10 includes a buffer circuit 20, a limit voltage generation circuit 21, a bias current generation circuit 22, a sink current circuit 23, and a clip detection circuit 24.

  The buffer circuit 20 is a circuit that outputs an output voltage Vout that can drive, for example, a power amplifier (not shown) based on an input voltage Vin corresponding to a change in sound input from a microphone (not shown), for example. . Note that the input voltage Vin in the present embodiment is a voltage that changes sinusoidally around the voltage Vm.

  The limit voltage generation circuit 21 is a circuit that generates a voltage for limiting the level of the output voltage Vout together with the voltage source 11 and the resistors 12 and 13. The limit voltage generation circuit 21 includes resistors 30 and 31, a voltage source 32, and an operational amplifier 33. A node to which one end of the resistor 30 and one end of the resistor 31 are connected is connected to the inverting input terminal of the operational amplifier 33, and the other end of the resistor 31 is connected to the output terminal of the operational amplifier 33. Therefore, the resistors 30 and 31 and the operational amplifier 33 constitute an inverting amplifier circuit. A voltage VA (first voltage) obtained by dividing the voltage Vm of the voltage source 11 by the resistors 12 and 13 is applied to the other end of the resistor 30, and a non-inverting input terminal of the operational amplifier 33 is applied from the voltage source 32. A voltage Vm is applied. In the present embodiment, the resistance values of the resistors 30 and 31 are the same. For this reason, the operational amplifier 33 outputs a voltage VB (second voltage) generated when the difference between the voltage VA and the voltage Vm is inverted around the voltage Vm of the voltage source 32.

  The bias current generation circuit 22 is a circuit that generates a bias current Ib for operating the sink current circuit 23 and the clip detection circuit 24. The bias current generation circuit 22 according to the present embodiment generates the temperature-compensated bias current Ib based on, for example, a reference voltage output from a bandgap reference voltage circuit (not shown).

  The sink current circuit 23 compares the input voltages VA and VB with the output voltage Vout of the buffer circuit 20, and controls the buffer circuit 20 so that the level of the output voltage Vout is limited between the voltage VA and the voltage VB. Circuit. Specifically, when the output voltage Vout decreases, the sink current circuit 23 sucks the current Is1 (first current) from the buffer circuit 20 so that the output voltage Vout is limited by the level of the voltage VA. On the other hand, when the output voltage Vout rises, the sink current circuit 23 sucks the current Is2 (second current) from the buffer circuit 20 so that the output voltage Vout is limited by the level of the voltage VB.

  The clip detection circuit 24 indicates whether or not the output voltage Vout has been clipped based on the input voltages VA and VB and the output voltage Vout, that is, whether or not a predetermined distortion has occurred in the output voltage Vout. It is a circuit that outputs a signal Vc. In this embodiment, when the clip detection circuit 24 detects that the output voltage Vout has been clipped, it outputs a low level (hereinafter, L level) clip signal Vc and detects that the output voltage Vout has not been clipped. In this case, a high level (hereinafter, H level) clip signal Vc is output.

  FIG. 2 is a diagram illustrating an example of the configuration of the buffer circuit 20. The buffer circuit 20 includes an operational amplifier 60 including NPN transistors Q1 to Q3, PNP transistors Q4 and Q5, and current sources 50 and 51, and a signal line 61. The current source 50 corresponds to the constant current source of the present invention, the NPN transistors Q1 and Q2 correspond to the first transistor and the second transistor of the present invention, the NPN transistor Q3, the PNP transistors Q4 and Q5, and the current The source 51 corresponds to the output voltage generation circuit of the present invention, and the signal line 61 corresponds to the feedback circuit of the present invention.

  In the operational amplifier 60, the NPN transistors Q1 and Q2, the PNP transistors Q4 and Q5, and the current source 50 constitute a differential amplifier circuit. For this reason, when the base voltage of the NPN transistor Q1 becomes higher than the base voltage of the NPN transistor Q2, the collector voltage of the NPN transistor Q2 increases. The base of the NPN transistor Q3 is connected to the collector of the NPN transistor Q2, and the NPN transistor Q3 and the current source 51 constitute an emitter follower. Therefore, the emitter voltage of NPN transistor Q3 rises as the collector voltage of NPN transistor Q2 rises. On the other hand, when the base voltage of the NPN transistor Q1 becomes lower than the voltage of the NPN transistor Q2, the collector voltage of the NPN transistor Q2 decreases. As a result, the voltage at the emitter of the NPN transistor Q3 also decreases. That is, in the operational amplifier 60, the base of the NPN transistor Q1 corresponds to a non-inverting input terminal, and the base of the NPN transistor Q2 corresponds to an inverting input terminal. In this embodiment, the output voltage Vout output from the emitter of the NPN transistor Q3 and corresponding to the output of the operational amplifier 60 is applied to the base of the NPN transistor Q2 that is the non-inverting input terminal of the operational amplifier 60 via the signal line 61. Has been. Therefore, the operational amplifier 60 and the signal line 61 constitute a unity gain buffer. That is, in this embodiment, an output voltage Vout equal to the input voltage Vin applied to the base of the NPN transistor Q1 is output from the emitter of the NPN transistor Q3 that is the output of the operational amplifier 60. Although details will be described later in this embodiment, when the output voltage Vout decreases to a predetermined level, the current Is1 is sucked into the sink current circuit 23 from the collector of the NPN transistor Q1. On the other hand, when the output voltage Vout rises to a predetermined level, the current Is2 is sucked into the sink current circuit 23 from the collector of the NPN transistor Q2.

  FIG. 3 is a diagram illustrating an example of the configuration of the sink current circuit 23 and the clip detection circuit 24.

  The sink current circuit 23 includes an NPN transistor Q10, a first sink current generation circuit 70, and a second sink current generation circuit 71. The diode-connected NPN transistor Q10 generates a voltage corresponding to the bias current Ib from the bias current generation circuit 22.

  The first sink current generation circuit 70 includes NPN transistors Q11, Q30, and Q31, PNP transistors Q20 to Q23, and resistors 80 to 84. Since the NPN transistor Q11 forms a current mirror with the NPN transistor Q10, a current corresponding to the bias current Ib flows through the NPN transistor Q11. Further, since the PNP transistor Q20 and the resistor 80 and the PNP transistor Q21 and the resistor 81 constitute a current mirror, as a result, a current corresponding to the bias current Ib flows through the PNP transistor Q21. Each of resistors 80 and 81 corresponds to an emitter resistor for increasing the output resistance of PNP transistors Q20 and Q21. The PNP transistor Q22 to which the output voltage Vout is applied to the base and the PNP transistor Q23 to which the voltage VA is applied to the base via the resistor 82 form a differential pair. The base of the diode-connected NPN transistor Q30 is connected to the collector of the PNP transistor Q22. The NPN transistor Q30 and the resistor 83, and the NPN transistor Q31 and the resistor 84 constitute a current mirror. Therefore, in the present embodiment, the current Is1 generated in the NPN transistor Q31 changes according to the magnitude relationship between the output voltage Vout and the voltage VA. Specifically, for example, when the output voltage Vout is sufficiently higher than the voltage VA, the current Is1 becomes zero because the PNP transistor Q22 is turned off. When the output voltage Vout drops from a state sufficiently higher than the voltage VA, the PNP transistor Q22 is turned on. Therefore, the current Is1 increases as the output voltage Vout decreases. In the present embodiment, when the output voltage Vout decreases, for example, when the voltage VP is 0.1 V higher than the voltage VA, the current value of the current Is1 cannot be ignored with respect to the current value of the constant current source 50. It will be a large size. As described above, the collector of the NPN transistor Q31 is connected to the collector of the PNP transistor Q4 of the buffer circuit 20. For this reason, the NPN transistor Q31 sucks the current Is1 that increases as the output voltage Vout decreases from the PNP transistor Q4 of the buffer circuit 20. Note that the first sink current generation circuit 70 in the present embodiment is designed to suck Is1 having a current value equal to the current value of the current source 50 of the buffer circuit 20 when the output voltage Vout becomes the voltage VA. . The resistors 83 and 84 are emitter resistors similar to the resistors 80 and 81, respectively.

  The second sink current generation circuit 71 includes NPN transistors Q12 and Q40 to Q43, PNP transistors Q50 to Q52, and resistors 85 to 89. Since the NPN transistor Q12 forms a current mirror with the NPN transistor Q10, a current corresponding to the bias current Ib flows through the NPN transistor Q12. The NPN transistor Q40 to which the voltage VB is applied to the base via the resistor 85 and the NPN transistor Q41 to which the output voltage Vout is applied to the base form a differential pair. The diode-connected PNP transistor Q50, the diode-connected PNP transistor Q51, and the resistor 86 correspond to respective loads of the PNP transistors Q40 and 41 constituting the differential pair. The PNP transistor Q51 and the resistor 86, and the PNP transistor Q52 and the resistor 87 constitute a current mirror, and the diode-connected NPN transistor Q42 and the resistor 88, and the NPN transistor Q43 and the resistor 89 constitute a current mirror. Therefore, in the present embodiment, the current Is2 generated in the NPN transistor Q43 changes according to the magnitude relationship between the output voltage Vout and the voltage VB. Specifically, for example, when the output voltage Vout is sufficiently lower than the voltage VB, the NPN transistor Q41 is turned off, so that the current Is2 becomes zero. When the output voltage Vout rises from a state sufficiently lower than the voltage VB, the NPN transistor Q41 is turned on. Therefore, the current Is2 increases as the output voltage Vout increases. In the present embodiment, when the output voltage Vout increases and becomes, for example, the voltage VQ that is 0.1 V lower than the voltage VB, the current value of the current Is2 cannot be ignored with respect to the current value of the constant current source 50. It will be a large size.

  As described above, the collector of the NPN transistor Q43 is connected to the collector of the PNP transistor Q5 of the buffer circuit 20. For this reason, the NPN transistor Q43 sucks the current Is2 that increases as the output voltage Vout increases from the PNP transistor Q5 of the buffer circuit 20. Note that the second sink current generation circuit 71 in the present embodiment is designed so that the current Is2 having a current value equal to the current value of the current source 50 of the buffer circuit 20 can be sucked when the output voltage Vout becomes the voltage VB. Suppose that Each of the resistors 86 to 89 is an emitter resistor similar to the resistors 80 and 81.

  The clip detection circuit 24 includes a first current generation circuit 72, a second current generation circuit 73, and a clip signal generation circuit 74.

  The first current generation circuit 72 is a circuit that generates a current Ic1 (third current) that increases as the output voltage Vout decreases, and includes an NPN transistor Q11, PNP transistors Q20, Q21, Q23, and Q60, and resistors 80 to 82 is comprised. As described above, a current corresponding to the bias current Ib is output from the PNP transistor Q21. The PNP transistor Q60 to which the output voltage Vout is applied to the base and the PNP transistor Q23 to which the voltage VA is applied to the base via the resistor 82 constitute a differential pair. Therefore, the current Ic1 generated by the PNP transistor Q60 changes according to the difference between the output voltage Vout and the voltage VA. Specifically, when the output voltage Vout is sufficiently higher than the voltage VA, the PNP transistor Q60 is turned off, so that the current Ic1 becomes zero. In the present embodiment, when the output voltage Vout decreases from a state sufficiently higher than the voltage VA, the PNP transistor Q60 is turned on, so that the current Ic1 increases as the output voltage Vout decreases.

  The second current generation circuit 73 is a circuit that generates a current Ic2 (fourth current) that increases as the output voltage Vout increases, and includes NPN transistors Q12, Q40, and Q41, PNP transistors Q50, Q51, and Q61, and a resistor 85, 86, 90 are comprised. The PNP transistor Q51 and the resistor 86, and the PNP transistor Q61 and the resistor 90 constitute a current mirror. As described above, a current corresponding to the bias current Ib flows through the NPN transistor Q12, and the NPN transistor Q40 and the NPN transistor Q41 constitute a differential pair. Therefore, when the output voltage Vout is sufficiently lower than the voltage VB, the NPN transistor Q41 is turned off and the current Ic2 becomes zero. In the present embodiment, when the output voltage Vout increases from a state sufficiently lower than the voltage VB, the NPN transistor Q41 is turned on, so that the current Ic2 increases as the output voltage Vout increases.

  The clip signal generation circuit 74 (comparison circuit) is a circuit that generates a clip signal Vc indicating whether or not the output voltage Vout has been clipped based on the currents Ic1 and Ic2. The clip signal generation circuit 74 includes a MOS transistor M1 and resistors 91 and 92. Since one end of the resistor 91 is connected to the collectors of the PNP transistors Q60 and Q61, a voltage corresponding to the sum of the current Ic1 and the current Ic2 is generated at one end of the resistor 91. The MOS transistor M1 and the resistor 92 constitute an inverter, and the gate of the MOS transistor M1 is connected to one end of the resistor 91 described above. Therefore, when the voltage Vz at one end of the resistor 91 is lower than the threshold value of the inverter, that is, the threshold voltage (third voltage) of the MOS transistor M1, the output of the inverter is at the H level. On the other hand, when voltage Vz is higher than the threshold value of the inverter, the output of the inverter is at the L level. The clip detection circuit 24 of the present embodiment is configured so that the NMOS transistor M1 is turned on based on the current Ic1 when the output voltage Vout becomes the voltage VA or the current Ic2 when the output voltage Vout becomes the voltage VB. It is assumed that the size of the transistors Q60 and 61 and the resistance value of the resistor 91 are determined.

<< Operation of Limiter Circuit 10 >>
Here, the operation of the limiter circuit 10 in the present embodiment will be described with reference to FIG. Here, a case will be described in which the maximum voltage of the input voltage Vin input to the buffer circuit 20 is larger than the voltage VB and the minimum voltage of the input voltage Vin is smaller than the voltage VA.

  First, when the input voltage Vin is input to the buffer circuit 20 at time T1, the buffer circuit 20 operates as a unity gain buffer, so that the output voltage Vout increases as the input voltage Vin increases. When the output voltage Vout becomes the voltage VQ at time T2, the current value of the current Is2 generated by the second sink current generation circuit 71 becomes a magnitude that cannot be ignored with respect to the current value of the constant current source 50. Here, the operation of the buffer circuit 20 when the current Is2 cannot be ignored with respect to the constant current source 50 will be described while considering the influence of the negative feedback in the buffer circuit 20. At time T2, since the input voltage Vin increases, the current flowing through the NPN transistor Q1 increases. As a result, the current flowing through the PNP transistor Q4 also increases, and the base voltage of the PNP transistor Q4 decreases. On the other hand, since the output voltage Vout does not change similarly to the input voltage Vin without time delay, the base voltage of the NPN transistor Q1 is higher than the base voltage of the NPN transistor Q2. As a result, the current flowing through the NPN transistor Q2 decreases. For this reason, the current flowing through the NPN transistor Q2 is less than the current flowing through the NPN transistor Q1. Further, the base voltage of the PNP transistor Q5 decreases as the base voltage of the PNP transistor Q4 decreases, but the current flowing through the NPN transistor Q2 decreases as described above. Therefore, for example, when the current value of the current Is2 is small enough to be ignored, the collector voltage of the NPN transistor Q2 increases so that the current flowing through the PNP transistor Q5 matches the current flowing through the NPN transistor Q2. However, at time T2, the second sink current generation circuit 71 sucks a part of the current output from the PNP transistor Q5 as the current Is2. For this reason, even if the current absorbed by the NPN transistor Q2 at time T2 decreases, the increase in the collector voltage of the PNP transistor Q5 is suppressed. As described above, the NPN transistor Q3 and the current source 51 constitute an emitter follower. For this reason, the rise of the output voltage Vout is suppressed similarly to the collector voltage of the PNP transistor Q5. That is, in this embodiment, when the output voltage Vout becomes the voltage VQ, the buffer circuit 20 does not operate as a unity gain buffer, and the second sink current generation circuit 71 suppresses the change in the output voltage Vout.

  Further, the second sink current generation circuit 71 of the present embodiment further increases the current Is2 after the level of the output voltage Vout rises to the voltage VQ. Therefore, when the output voltage Vout increases in accordance with the increase in the input voltage Vin after time T2, the change in the output voltage Vout is further suppressed.

When the output voltage Vout becomes the voltage VB at time T3, the second sink current generation circuit 71 sucks the current Is2 that is equal to the current value of the current source 50 of the buffer circuit 20 as described above. As a result, all the current from the current source 50 flows through the NPN transistor Q1 and the PNP transistor Q4, and a current equal to the current from the current source 50 is output from the PNP transistor Q5 to the second sink current generation circuit 71. . That is, at time T3, the current flowing through the NPN transistor Q2 becomes zero, and as a result, the NPN transistor Q2 is turned off. In the present embodiment, the input voltage Vin at time T3 is the voltage Vx.

  From time T3 to time T4, the input voltage Vin applied to the base of the NPN transistor Q1 is higher than the voltage Vx. As described above, at time T3, the NPN transistor Q2 is turned off. Further, all the current from the current source 50 flows through the NPN transistor Q1. Therefore, even when the input voltage Vin applied to the base of the NPN transistor Q1 becomes higher than the voltage Vx, the current flowing through the NPN transistor Q1 does not change. For this reason, the current flowing through each of the PNP transistors Q4 and Q5 does not change similarly. As a result, between time T3 and time T4, the collector voltage of the PNP transistor Q5 and the output voltage Vout do not change, and the upper limit of the output voltage Vout is limited by the voltage VB. That is, from time T3 to time T4, only the NPN transistor Q1 is operating among the NPN transistors Q1 and Q2 corresponding to the differential pair of the operational amplifier 60.

  When the time T4 has elapsed, the output voltage Vout decreases as the input voltage Vin decreases, contrary to the operation during the period from the time T2 to the time T3 described above. When the output voltage Vout decreases, the current Is2 generated by the second sink current generation circuit 71 also decreases. After time T5, the output voltage Vout becomes lower than the voltage VQ. For this reason, the current Is2 generated by the second sink current generation circuit 71 is sufficiently smaller than the current value of the constant current source 50. As a result, from time T5 to time T6 described later, the buffer circuit 20 operates as a unity gain buffer.

  When the output voltage Vout becomes the voltage VP according to the decrease of the input voltage Vin at time T6, the first sink current generation circuit 70 generates a current Is1 having a current value that cannot be ignored with respect to the current value of the constant current source 50. To do. Here, the operations of the buffer circuit 20 and the first sink current generation circuit 70 will be described in detail at time T6. First, at time T6, since the input voltage Vin decreases, the current flowing through the NPN transistor Q1 becomes smaller than the current flowing through the NPN transistor Q2. Here, when the current Is1 of the first sink current generation circuit 70 is sufficiently small, the base voltage of the PNP transistor Q4 increases as the current flowing through the NPN transistor Q1 decreases. However, at time T6, the current value of the current Is1 becomes so large that it cannot be ignored as described above, and therefore, an increase in the base voltage of the PNP transistor Q4 is suppressed. For this reason, an increase in the base voltage of the PNP transistor Q5 is also suppressed. Therefore, for example, as compared with a case where the current Is1 is sufficiently small, a decrease in the collector voltage of the PNP transistor Q5 is also suppressed. As a result, a decrease in the output voltage Vout is also suppressed. In addition, since the input voltage Vin is decreased after time T6, the output voltage Vout is also decreased in accordance with the decrease of the input voltage Vin. As a result, the current Is1 of the first sink current generation circuit 70 increases, and the decrease in the output voltage Vout is further suppressed. At time T7, when the output voltage Vout becomes the voltage VA, the current value of the current Is1 becomes the current value of the current source 50 as described above. Therefore, at least the current Is1 flows through the PNP transistor Q4. At this time, the PNP transistor Q4, which forms a current mirror with the PNP transistor Q4, operates to supply at least the current Is1 to the NPN transistor Q2. As described above, the current value of the current Is1 at the time T7 is equal to the current value of the current source 50. As a result, the NPN transistor Q2 is turned on and the NPN transistor Q1 is turned off. Here, the input voltage Vin when the output voltage Vout becomes the voltage VA according to the decrease of the input voltage Vin is defined as the voltage Vy.

  From time T7 to time T8, the input voltage Vin applied to the base of the NPN transistor Q1 is lower than the voltage Vy. In this case, since the NPN transistor Q1 continues to be turned off, the current flowing through the NPN transistors Q1 and Q2 does not change as a result. For this reason, the current flowing through each of the PNP transistors Q4 and Q5 does not change similarly. As a result, the collector voltage and output voltage Vout of the NPN transistor Q2 do not change, and the lower limit of the output voltage Vout is limited by the voltage VA.

  Note that, from time T8 to time T9, the output voltage Vout rises as the input voltage Vin rises, contrary to the operation from time T6 to time T7 described above. Then, after time T9 when the output voltage Vout becomes higher than the voltage VP, the current value of the current Is1 is sufficiently smaller than the current value of the constant current source 50. Therefore, the buffer circuit 20 operates as a unity gain buffer.

  In the present embodiment, the output voltage Vout becomes the voltage VB from time T3 to time T4, and the output voltage Vout becomes the voltage VA from time T7 to time T8. Therefore, during the period from time T3 to time T4 and from time T7 to time T8, the clip detection circuit 24 outputs an L level clip signal Vc indicating that the output signal Vout has been clipped.

  The first sink current generation circuit 70 of the limiter circuit 10 of the present embodiment having the configuration described above generates a current Is1 corresponding to the level of the output voltage Vout. Since the first sink current generation circuit 70 sucks the current Is1 from the collector of the NPN transistor Q1, the change in the output voltage Vout of the buffer circuit 20 is suppressed. When the output voltage Vout becomes the voltage VP, the current value of the current Is1 becomes a current value that cannot be ignored with respect to the current value of the constant current source 50. For this reason, the change of the output voltage Vout is further suppressed as the output voltage Vout decreases from the voltage VP. Therefore, as a result, the lower limit of the output voltage Vout is limited to a predetermined level. In the present embodiment, when limiting the lower limit of the output voltage Vout, for example, the forward voltage of a diode or the like is not used. Therefore, for example, the output voltage Vout can be accurately limited even when the temperature changes.

  In the limiter circuit 10 of the present embodiment, a current Is1 that increases as the output voltage Vout decreases and a current Is2 that decreases as the output voltage Vout increases are generated. For this reason, each of the rise and fall of the output voltage Vout of the buffer circuit 20 is suppressed. Further, when the output voltage Vout becomes the voltage VQ, the current value of the current Is2 becomes a current value that cannot be ignored with respect to the current value of the constant current source 50. For this reason, the change in the output voltage Vout is further suppressed as the output voltage Vout rises from the voltage VQ. Therefore, as a result, the upper limit of the output voltage Vout is limited to a predetermined level. Thus, in this embodiment, it is possible to limit the upper limit and the lower limit of the output voltage Vout without using a diode.

  Further, the first sink current generation circuit 70 of the present embodiment sucks the current Is1 having a current value equal to the current value of the current source 50 when the output voltage Vout becomes the voltage VA. As a result, the NPN transistor Q1 in the operational amplifier 60 is turned off. For this reason, even when the input voltage Vin applied to the base of the NPN transistor Q1 further decreases, the current flowing through each of the transistors constituting the operational amplifier 60 does not change, so the lower limit of the output voltage Vout is the voltage VA. It will be limited. On the other hand, when the output voltage Vout becomes the voltage VB, the second sink current generation circuit 71 of the present embodiment sucks the current Is2 having a current value equal to the current value of the current source 50. For this reason, the NPN transistor Q2 is turned off. For this reason, even if the input voltage Vin applied to the base of the NPN transistor Q1 further increases, the current flowing through each of the transistors constituting the operational amplifier 60 does not change, so the upper limit of the output voltage Vout is the voltage VB. It will be limited. Thus, in the present embodiment, the upper limit and the lower limit of the output voltage Vout can be determined by the voltages VA and VB generated by the voltage source 11, the resistors 12 and 13, and the limit voltage generation circuit 21. For this reason, the limit voltage can be determined with higher accuracy than in the case where a diode is used. In the present embodiment, for example, the voltages VA and VB for limiting the output voltage Vout can be easily changed by changing the resistance values of the resistors 12 and 13.

  Further, the clip detection circuit 24 of the present embodiment changes the clip signal Vc from the H level to the L level when the output voltage Vout becomes the voltage VA or the voltage VB. For this reason, in this embodiment, it is possible to determine whether or not clipping has been performed based on a change in a logic level signal.

  In addition, the said Example is for making an understanding of this invention easy, and is not for limiting and interpreting this invention. The present invention can be changed and improved without departing from the gist thereof, and the present invention includes equivalents thereof.

  For example, in the present embodiment, the buffer circuit 20 is a unity gain buffer, but the present invention is not limited to this. For example, instead of the signal line 61, the output voltage Vout may be divided and applied to the base of the NPN transistor Q2.

  Further, although the input voltage Vin is applied to the base of the NPN transistor Q1 corresponding to the non-inverting input of the operational amplifier 60, the present invention is not limited to this. For example, in order to invert and amplify the input voltage Vin to obtain the output voltage Vout, a predetermined voltage is applied to the base of the NPN transistor Q1, and the input voltage Vin is applied to the base of the NPN transistor Q2 via a resistor. Also good. In this case, a resistor for determining the gain of inversion amplification is also required between the output voltage Vout and the base of the NPN transistor Q2.

It is a figure which shows the structure of the limiter circuit 10 which is one Embodiment of this invention. 2 is a diagram illustrating a configuration of a buffer circuit 20. FIG. FIG. 3 is a diagram showing the configuration of a sink current circuit 23 and a limit detection circuit 24. 6 is a diagram for explaining the operation of the limiter 10. FIG. It is a figure which shows an example of a limiter circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Limiter circuit 11,32 Voltage source 12, 13, 30, 31, 80-92 Resistance 20 Buffer circuit 21 Limit voltage generation circuit 22 Bias current generation circuit 23 Sink current circuit 24 Clip detection circuit 33, 60 Operational amplifier 50, 51 Current source 61 signal line 70 first sink current generation circuit 71 second sink current generation circuit 72 first current generation circuit 73 second current generation circuit 74 clip signal generation circuit Q1 to Q3, Q10 to Q12, Q30, Q31, Q40 to Q43 NPN Transistors Q4, Q5, Q20 to Q23, Q50 to Q52, Q60, Q61 PNP transistor M1 NMOS transistor

Claims (4)

A differential input circuit comprising: a constant current source; and a first transistor and a second transistor connected to the constant current source and constituting a differential pair;
An output voltage generation circuit for generating an output voltage corresponding to a difference between voltages applied to the first control electrode of the first transistor and the second control electrode of the second transistor;
A feedback circuit for applying a feedback voltage corresponding to the output voltage to the second control electrode in order to match the voltage levels of the first control electrode and the second control electrode;
When the level of the output voltage changes according to a change in the input voltage applied to either the first control electrode or the second control electrode, the constant current source of the first transistor or the second transistor Is a sink current circuit that draws in a first current corresponding to the level of the output voltage from one electrode through which any smaller current flows among the electrodes on the unconnected side;
A limiter circuit comprising: The limiter circuit according to claim 1,
The sink current circuit is
Among the electrodes on the side that is not connected to the constant current source of the first transistor or the second transistor, the first current that increases according to a decrease in the level of the output voltage is sucked from the one electrode. Sucking in a second current that increases as the level of the output voltage increases from the other electrode;
Limiter circuit characterized by The limiter circuit according to claim 2,
The sink current circuit is
When the level of the output voltage decreases to the first voltage, the first current having a current value equal to the current value of the constant current source is sucked.
When the level of the output voltage rises and becomes a second voltage higher than the first voltage, the second current having a current value equal to the current value of the constant current source is sucked.
Limiter circuit characterized by The limiter circuit according to claim 2 or 3, wherein
A first current generation circuit for generating a third current that increases in response to a decrease in the level of the output voltage;
A second current generating circuit for generating a fourth current that increases in response to an increase in the level of the output voltage;
A comparison circuit for outputting a comparison result between a voltage corresponding to the sum of the third current and the fourth current and a third voltage;
Further comprising,
Limiter circuit characterized by

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