JP2010141725A - Distortion compensation device - Google Patents

Abstract

An object of the present invention is to achieve both a convergence speed and a stable operation in a distortion compensation apparatus using a DPD.
A distortion compensator according to the present invention is a distortion compensator that compensates for nonlinear distortion of a PA11 using a DPD, together with a delay correction circuit 21 and a phase correction circuit 22 for a feedback signal from the PA11. An error determination circuit 23 that determines whether or not the error is within the normal range is provided. When the error determination circuit 23 determines that the error is within the normal range, the lookup table to be referenced is updated, and the error determination circuit is within the normal range. If not, the lookup table is not updated.
[Selection] Figure 1

Description

  The present invention relates to a distortion compensator used for a radio transmission apparatus, and more particularly, to a distortion compensator using a DPD (Digital PreDistortion) for compensating distortion generated in an amplifier circuit.

FIG. 3 is a schematic configuration diagram illustrating an example of a conventional distortion compensation apparatus. The feedback signal 107 from the PA 111 is fast Fourier transformed by an FFT (Fast Fourier Transform) 122 and then an adjacent channel leak ratio is calculated by an ACLR (Adjacent Channel Leakage Ratio) calculating unit 123 to obtain a pull-in state from the ACLR value. The optimum step size μ is selected by the μ adjustment unit 124.
Patent No. 3876408

  In a distortion compensator that operates adaptively by obtaining an inverse distortion characteristic using an error between a feedback signal and an input signal to the distortion compensator as a nonlinear distortion amount, there is a trade-off relationship between convergence speed and stable operation.

  Therefore, an object of the present invention is to achieve both a convergence speed and a stable operation in a distortion compensation apparatus using a DPD.

  The inventors have discovered that when the inverse characteristic of nonlinear distortion is calculated in a state where errors other than nonlinear distortion remain, the stable operation of the DPD convergence process is hindered.

  Therefore, in order to solve the above-described problem, a distortion compensation apparatus according to the present invention includes an error detection unit that detects errors other than nonlinear distortion and a predetermined error detection unit in a distortion compensation apparatus that uses a DPD. When an error larger than the threshold is detected, the reference table used in the DPD is not updated, or the distortion compensation itself is not performed.

  Specifically, the distortion compensator according to the present invention is a distortion compensator that compensates for nonlinear distortion of an amplifier circuit using a DPD, and includes a delay error together with a delay correction circuit and a phase correction circuit for a feedback signal from the amplifier circuit. Alternatively, an error determination circuit for determining whether or not the phase error is within the normal range is provided, and when the error determination circuit is determined to be within the normal range, the reference table is updated, and the error determination circuit is determined not to be within the normal range. The reference table is not updated.

  Since the reference table is not updated when the delay error and the phase error of the feedback signal are large, the stable operation of the distortion compensator can be maintained. Further, since the stable operation can be maintained even if the update coefficient of the reference table is increased, the update speed of the adaptive distortion compensation can be increased by increasing the update coefficient of the reference table. Therefore, both convergence speed and stable operation can be achieved.

The distortion compensation apparatus according to the present invention further includes an analog error correction circuit that detects and corrects an analog error generated in the analog signal processing unit, and the error determination circuit includes the analog error within a normal range. It is preferable to determine whether or not there is.
According to the present invention, when the analog system error is large, the reference table is not updated, so that the stable operation of the distortion compensator can be maintained. Since the distortion compensation value update circuit can accurately detect nonlinear distortion, the convergence speed of adaptive distortion compensation can be increased.

In the distortion compensation apparatus according to the present invention, the error determination circuit further determines whether or not the delay error or phase error and the analog system error are within an abnormal range. The update circuit preferably replaces the reference table with a predetermined spare table.
Here, it is preferable that the distortion compensation value update circuit stores the reference table in a state before being replaced with the update table as the spare table for a certain period. The preliminary table is preferably the reference table in an initial state that has not been replaced by the distortion compensation value update circuit. The preliminary table preferably defines a distortion compensation value for maintaining the input signal waveform.
According to the present invention, when an abnormal error is detected, it is possible to return to the reference table in which the distortion compensator was operating stably. Therefore, the distortion compensating apparatus can be stably operated.

  ADVANTAGE OF THE INVENTION According to this invention, in a distortion compensation apparatus using DPD, it is possible to achieve both convergence speed and stable operation.

  Embodiments of the present invention will be described with reference to the accompanying drawings. The embodiment described below is an example of the configuration of the present invention, and the present invention is not limited to the following embodiment.

  FIG. 1 is a schematic configuration diagram of a distortion compensation apparatus according to the present embodiment. The distortion compensation apparatus according to this embodiment includes a D / A 13, a Q-MOD 14, a HYB 16, an oscillator 15, and a PA 11 as an amplifier circuit, and orthogonally modulates an input signal. The D / A 13 functions as a DA conversion circuit that converts a digital signal from the distortion compensation circuit 12 into an analog signal. The Q-MOD 14, the HYB 16, and the oscillator 15 function as a modulation circuit that quadrature modulates the input signal from the DA conversion circuit.

  The distortion compensation apparatus according to this embodiment includes a HYB 16, an oscillator 15, a Q-DEM 17, and an A / D 18, and orthogonally demodulates a feedback signal from the PA 11. The Q-DEM 17, the HYB 16, and the oscillator 15 function as a demodulation circuit that performs quadrature demodulation of the feedback signal from the PA 11. The A / D 18 functions as an AD conversion circuit that converts an analog signal from the demodulation circuit into a digital signal.

  The D / A 13, Q-MOD 14, HYB 16, oscillator 15, PA 11, Q-DEM 17, and A / D 18 are included in the analog signal processing unit 102 among the digital signal processing unit 101 and the analog signal processing unit 102.

  The distortion compensation apparatus according to the present embodiment includes a distortion compensation circuit 12, a delay correction circuit 21, a phase correction circuit 22, and a distortion compensation value update circuit 24, and performs adaptive distortion compensation for nonlinear distortion of the PA 11. The distortion compensation circuit 12 is connected to the front stage of the PA 11 and performs distortion compensation based on a reference table in which distortion compensation values are defined according to input signal power. The delay correction circuit 21 detects a delay error with respect to the input signal of the feedback signal from the PA 11 and corrects the delay error. The phase correction circuit 22 detects a phase error of the signal from the delay correction circuit 21 with respect to the input signal, and corrects the phase error. The distortion compensation value update circuit 24 detects distortion of the feedback signal corrected by the phase correction circuit 22 with respect to the input signal, creates an update table with a distortion compensation value that reduces the distortion, and updates the reference table. Replace with a table.

  The distortion compensation apparatus according to the present embodiment preferably further includes an analog error correction circuit 25. The analog system error correction circuit 25 detects an analog system error generated in the analog signal processing unit 102 among errors included in the feedback signal from the PA 11, and corrects the analog system error. The analog error correction circuit 25 outputs the feedback signal after correcting the analog error to the delay correction circuit 21 and outputs the detected analog error to the error determination circuit 23. Further, by further including the analog system error correction circuit 25, the distortion compensation value update circuit 24 can extract the inverse characteristic of the nonlinear distortion from the input signal and the feedback signal and perform the distortion compensation.

  The analog system error correction circuit 25 detects, for example, a quadrature error, an IQ imbalance error, or a DC offset error as the analog system error. For example, the analog error correction circuit 25 includes an ADC 25a, an ALC 25b, and an AQC 25c. The ADC 25a detects and corrects a DC offset error caused by a DC (Direct Current) offset process in the AD conversion circuit or the DA conversion circuit. The ALC 25b is an IQ balance resulting from an imbalance between an I component (In-phase component) and a Q component (Quadrature phase component) that are orthogonally modulated by a modulation circuit, or an imbalance between an I component and a Q component that are orthogonally demodulated by a demodulation circuit. Detect and correct errors. The AQC 25c detects and corrects the quadrature error caused by the phase difference of the carrier wave subjected to quadrature modulation by the modulation circuit or the phase difference of the carrier wave subjected to quadrature demodulation by the demodulation circuit. The error detected by the analog error correction circuit 25 may be only one of a DC offset error, an IQ balance error, and an orthogonal error. However, in order to detect the nonlinear distortion of the PA 11 more accurately, the DC offset error is detected. It is preferable to detect and correct all IQ balance errors and orthogonal errors.

  The error determination circuit 23 determines whether the delay error detected by the delay correction circuit 21 or the phase error detected by the phase correction circuit 22 is within a predetermined normal range. Here, the normal range is preferably a range of a delay error or a phase error that can be detected in a process in which the nonlinear distortion of the PA 11 is decreasing. When the error determination circuit 23 determines that it is within the normal range, the distortion compensation value update circuit 24 replaces the reference table with the update table. On the other hand, when the error determination circuit 23 determines that it is not within the normal range, the distortion compensation value update circuit 24 does not replace the reference table with the update table. As described above, when the error is large, the DPD update is not performed, so that the stable operation of the distortion compensator can be maintained. Furthermore, stable operation is guaranteed even when the update coefficient is increased.

  The error determination circuit 23 preferably further determines whether or not the analog system error detected by the analog system error correction circuit 25 is within a predetermined normal range. For example, it is determined whether or not the delay error or phase error and the analog system error are within a predetermined normal range. Thereby, it is possible to determine whether or not the correction in the AQC 25c, the ALC 25b, and the ADC 25a is in an over-control state that is higher than the design compensation. As described above, by providing a circuit for detecting an error other than nonlinear distortion and not performing DPD update when the error is large, stable operation of the distortion compensation apparatus can be maintained.

  The error determination circuit 23 preferably determines whether or not the delay error from the delay correction circuit 21 or the phase error from the phase correction circuit 22 is within a predetermined abnormal range. Further, the error determination circuit 23 preferably determines whether or not the analog system error is within a predetermined abnormal range. Here, the abnormal range may be other than the normal range, or may be a range independent of the normal range. As a range independent of the normal range, there is a range of errors that are clearly considered abnormal. The detection of the abnormal range is preferably performed for all objects for which error correction is performed. For example, when correcting a delay error, a phase error, a quadrature error, an IQ imbalance error, and a DC offset error, it is possible to set an abnormal range for all of these and determine whether or not they are within the abnormal range. preferable.

  When the error determination circuit 23 determines that it is within the abnormal range, the distortion compensation value update circuit 24 preferably replaces the reference table with a predetermined spare table. By preparing in advance a preliminary table that is used when an abnormality occurs in DPD update, the stable operation of the distortion compensation apparatus can be maintained.

  The spare table is a reference table in a state before being replaced with an update table, for example. In this case, it is preferable that the distortion compensation value update circuit 24 stores the reference table in a state before being replaced with the update table as a spare table for a certain period. The predetermined period can be exemplified by a predetermined time.

  The spare table is preferably selectable according to a distortion compensation value or an error defined in the reference table. For example, it is preferable that a reference table in an initial state not replaced by the distortion compensation value update circuit 24 can be selected. The initial state is a state at the time of shipment of the distortion compensation device, for example. Further, it is preferable that a reference table in which a distortion compensation value for maintaining the input signal waveform is defined can be selected. In this case, the distortion compensation value is, for example, 1 + j0.

  FIG. 2 is a pickup diagram illustrating an example of a phase correction circuit. The phase correction circuit shown in FIG. 2 includes an addition circuit 31, an averaging circuit 32, an equalization circuit 33, and a multiplication circuit 34. Portions other than the averaging circuit 32 constitute an LMS algorithm circuit. The adder circuit 31 adds the input signal ref (n) and the phase-corrected signal −y (n), and outputs a signal ε (n). The averaging circuit 32 averages the signal ε (n) and outputs it as a residual error to the error determination circuit (reference numeral 23 shown in FIG. 1). The equalization circuit 33 calculates a coefficient w (n) of the signal ε (n) for correcting the phase of the signal x (n) from the delay correction circuit (reference numeral 21 shown in FIG. 1). The multiplier circuit 34 multiplies the signal x (n) by the coefficient w (n) and corrects the signal y (n) obtained by correcting the phase of the signal x (n) (distortion compensation circuit 24 shown in FIG. 1). Output to.

  The present invention can be used in a distortion compensation device used in a wireless transmission device.

1 is a schematic configuration diagram of a distortion compensation apparatus according to an embodiment. It is a pick-up figure which shows an example of a phase correction circuit. It is a schematic block diagram which shows an example of the conventional distortion compensation apparatus.

Explanation of symbols

11 PA
12 Distortion compensation circuit 13 D / A
14 Q-MOD
15 Oscillator 16 HYB
17 Q-DEM
18 A / D
21 Delay Correction Circuit 22 Phase Correction Circuit 23 Error Determination Circuit 24 Distortion Compensation Value Update Circuit 25 Analog System Error Correction Circuit 25a ADC
25b ALC
25c AQC
31 Adding circuit 32 Averaging circuit 33 Equalizing circuit 34 Multiplying circuit 101 Digital signal processing unit 102 Analog signal processing unit 111 PA
107 Feedback signal 122 FFT
123 ACLR calculation unit 124 μ adjustment unit

Claims (8)

In a distortion compensation device that compensates for nonlinear distortion of an amplifier circuit,
A distortion compensation circuit that is connected to the preceding stage of the amplifier circuit and that performs distortion compensation based on a reference table in which a distortion compensation value is defined according to input signal power;
A delay correction circuit that detects a delay error of the feedback signal from the amplifier circuit with respect to the input signal and corrects the delay error;
Detecting a phase error of the signal from the delay correction circuit with respect to the input signal, and correcting the phase error; and
An error determination circuit for determining whether the delay error detected by the delay correction circuit or the phase error detected by the phase correction circuit is within a predetermined normal range;
Distortion compensation that detects distortion of the feedback signal corrected by the phase correction circuit with respect to the input signal, creates an update table with a distortion compensation value that reduces the distortion, and replaces the reference table with the update table A value update circuit;
With
The distortion compensation value update circuit includes:
When the error determination circuit determines that it is within the normal range, the reference table is replaced with the update table,
When the error determination circuit determines that it is not within the normal range, the reference table is not replaced with the update table. An analog circuit including a modulation circuit that orthogonally modulates the input signal, a demodulation circuit that orthogonally demodulates a feedback signal from the amplifier circuit, an AD conversion circuit that converts an analog signal into a digital signal, and a DA conversion circuit that converts the digital signal into an analog signal A signal processing unit;
An analog system error correction circuit for detecting an analog system error generated in the analog signal processing unit out of errors included in the feedback signal from the amplifier circuit and correcting the analog system error;
2. The distortion compensation apparatus according to claim 1, wherein the error determination circuit further determines whether or not the analog system error detected by the analog system error correction circuit is within a predetermined normal range. . The analog system error correction circuit, as the analog system error,
A quadrature error caused by a phase difference of a carrier wave that is orthogonally modulated by the modulation circuit or a phase difference of a carrier wave that is demodulated by the demodulation circuit;
IQ imbalance resulting from imbalance between I component (In-phase component) and Q component (Quadrature phase component) that the modulation circuit performs quadrature modulation, or imbalance between I component and Q component that the demodulation circuit performs quadrature demodulation The distortion compensation apparatus according to claim 2, wherein an error or a DC offset error caused by a DC (Direct Current) offset process in the AD converter circuit or the DA converter circuit is detected. The error determination circuit further determines whether or not the delay error or the phase error is within a predetermined abnormal range;
4. The distortion compensation value updating circuit replaces the reference table with a predetermined spare table when the error determination circuit determines that the error determination circuit is within the abnormal range. Distortion compensation device. The error determination circuit further determines whether or not the delay error or the phase error and the analog system error are within a predetermined abnormal range,
5. The distortion compensation apparatus according to claim 4, wherein the distortion compensation value update circuit replaces the reference table with the spare table when the error determination circuit determines that the error determination circuit is within the abnormal range.   6. The distortion compensation apparatus according to claim 4, wherein the distortion compensation value update circuit stores the reference table in a state before being replaced with the update table as the spare table for a certain period.   6. The distortion compensation apparatus according to claim 4, wherein the preliminary table is the reference table in an initial state that has not been replaced by the distortion compensation value update circuit.   6. The distortion compensation apparatus according to claim 4, wherein the preliminary table defines a distortion compensation value for maintaining an input signal waveform.

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