JP2010123063A - Automatic wiring shaping method and computer program therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an automatic wiring shaping method shaping the route of wiring such that a clearance is secured on a virtual plane corresponding to a substrate surface of a semiconductor package. <P>SOLUTION: This method has steps of: setting first, second and third reference vias; detecting via connection wiring; temporarily arranging the via connection wiring and the wiring on the first reference via side thereof such that a clearance is secured; setting a virtual circle with a distance between a position of the via connection wiring and the first reference via as a radius, and with the first reference via as a center; temporarily arranging the via connection wiring and the wiring on the third reference via side thereof such that a clearance is secured; setting a virtual circle with a distance between a position of the via connection wiring and the third reference via as a radius, and with the third reference via as a center; deciding whether the two virtual circles cross; and making a straight line connecting the first and third reference vias an auxiliary line when they cross. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  An automatic wiring shaping method for shaping a wiring path on a substrate on a virtual plane corresponding to a substrate surface of a semiconductor package so as to ensure at least a predetermined clearance with respect to a via and another wiring adjacent to the wiring, and The present invention relates to a computer program for causing a computer to execute this automatic wiring shaping process.

  In a semiconductor package such as PBGA or EBGA, a pad (for example, a bonding pad or a flip chip pad) electrically connected to an electrode terminal of a semiconductor chip and a via (land) provided around the pad or between via portions. Are designed to be connected by wiring patterns. Wiring in semiconductor packages has a design rule that ensures a certain clearance (line & space) between wirings and between wirings and vias or obstacles, and that there is no unnecessary wiring crossing. It is necessary to satisfy at least. For example, a designer generally designs a wiring route of a semiconductor package on a virtual plane by trial and error using a CAD system.

  If the computer recognizes the figure of the layout of wiring and vias on the virtual plane corresponding to the substrate surface of the semiconductor package, and all the wirings and vias are arithmetically processed by the so-called brute force method, the calculation amount is enormous. Takes time. In addition, in the semiconductor package, it is considered that the density and the number of pins will further increase in the future, and it is becoming difficult to shorten the design time.

  For the purpose of reducing the amount of computer processing and shortening the design time, as an example of the wiring pattern design method, only the wiring route is determined in advance by the rough wiring process, and then the actual design rule is determined by the wiring forming process. In view of the above, there has been proposed a method of determining the position of the wiring while checking the clearance (see, for example, Patent Document 1). In this method, a virtual auxiliary line connecting elements such as vias, bonding pads, and obstacles is formed on a virtual plane corresponding to the substrate surface of the semiconductor package on which wiring and vias are formed by computer processing. A plurality of lines are set, and the crossing relationship between the auxiliary line and the wiring is checked for each auxiliary line. Based on the result of the crossing, the position of the wiring is set at least a predetermined clearance between the wiring and the via and between the wirings Decide to secure

JP 2002-92061 A

  The invention described in Patent Document 1 (that is, Japanese Patent Laid-Open No. 2002-92061) that performs wiring shaping using an auxiliary line reduces the amount of calculation processing and designs compared to the conventional calculation processing using a brute force method. There is a certain effect in terms of time reduction.

  However, as the number of auxiliary lines to be set is increased, more appropriate wiring shaping can be realized, but the calculation processing amount increases in proportion to the number of auxiliary lines. Setting auxiliary lines at locations with high wiring density is effective in reducing wiring shaping processing time, but even if auxiliary lines are set up at locations where wiring density is not so high, reducing the time of wiring shaping processing is expected to be less effective. Rather, the amount of computation may increase. The designer himself uses the CAD system to manually set the auxiliary line on the virtual plane, depending on his skill, experience and intuition, but depending on how the auxiliary line is set, the time for wiring shaping processing The effect of shortening is not obtained so much. In addition, since the auxiliary line setting operation itself must be manually performed after all, it can be said to be a complicated operation for the designer. If the desired shaping result is not obtained even though the wiring is shaped using the set auxiliary line, the auxiliary line must be set again.

  Therefore, in view of the above problems, an object of the present invention is to provide a wiring path on a substrate on a virtual plane corresponding to the substrate surface of the semiconductor package with at least a predetermined clearance with respect to vias and other wires adjacent to the wiring. It is an object to provide an automatic wiring shaping method for shaping with high computational efficiency so as to ensure the above and a computer program for causing a computer to execute this automatic wiring shaping process.

  In order to achieve the above object, in the present invention, the intersection of the auxiliary line and the wiring set to connect the vias on a virtual plane corresponding to the substrate surface of the semiconductor package on which the wiring and vias are formed. Based on the relationship, the automatic wiring shaping method for determining the position of the wiring so as to secure at least a predetermined clearance between the wiring and the via on the auxiliary line and between the wiring is the first reference via among the plurality of vias. And a first reference via located on a first auxiliary line which is an auxiliary line set in advance in a via row direction or a direction orthogonal to the first reference via. A second setting step of setting a via adjacent to the second reference via as a second reference via, and a second auxiliary line preset in a direction substantially orthogonal to the first auxiliary line with respect to the second reference via 2 A third setting step of setting a via adjacent to the second reference via located on the auxiliary line as a third reference via; and a first setting between the first reference via and the second reference via. A detection step for detecting a via connection wiring that intersects with the auxiliary line and is connected to one of the vias; the via connection wiring; and the first reference via side with respect to the first auxiliary line and the via connection wiring First provisional placement step of temporarily placing wirings intersecting at the first reference via side at a position that secures at least a predetermined clearance between the respective wirings in order from the first reference via side, and provisional placement in the first temporary placement step A first virtual circle centered on the first reference via is set with a distance between the position of the via connection wiring on the first auxiliary line and the first reference via as a radius. Virtual circle setting step and via connection And a third auxiliary line parallel to the first auxiliary line set in advance with respect to the third reference via and a wiring intersecting at a position closer to the third reference via than the via connection wiring, Sequentially from the reference via side, a second temporary placement step for temporarily placing at least a predetermined clearance between the wirings, and a third auxiliary for the via connection wiring temporarily placed in the second temporary placement step A second virtual circle setting step for setting a second virtual circle centered on the third reference via, the distance between the position on the line and the third reference via being a radius, and a first virtual When it is determined in the determination step that determines whether or not the circle and the second virtual circle intersect, and in the determination step that the first virtual circle and the second virtual circle intersect, the first reference via and the first virtual circle A straight line connecting the three reference vias, the first reference via and the first reference via And an auxiliary line setting step of additionally setting the position of the wiring between the three reference vias as an auxiliary line used for determining at least a predetermined clearance between the wirings.

  An automatic wiring shaping method according to the present invention sets each of a plurality of vias as a first reference via in a first setting step, a second setting step, a third setting step, a detection step, and a first provisional arrangement. A step, a first virtual circle setting step, a second temporary placement step, a second virtual circle setting step, a determination step, and an auxiliary line setting step are executed.

  The series of processes can be realized in the form of a computer program that can be executed by an arithmetic processing unit such as a computer. Further, it is obvious to those skilled in the art that the computer program is stored in a recording medium. As described above, in the automatic wiring shaping method according to the present invention, auxiliary lines are set in advance between vias in the column direction of vias and the direction orthogonal thereto. In addition to the set auxiliary line, the auxiliary line generated by the series of steps executed by the computer is additionally set.

  That is, on the virtual plane corresponding to the substrate surface of the semiconductor package on which the wiring and via are formed, the position of the wiring is set on the auxiliary line based on the crossing relationship between the wiring and the auxiliary line set to connect the vias. The computer program for causing the computer to execute automatic wiring shaping processing for determining at least a predetermined clearance between wirings and vias sets a first reference via from among a plurality of vias Adjacent to the first reference via, which is located on the first auxiliary line which is an auxiliary line set in advance in the via row direction or the direction orthogonal to the first reference via. A second setting step for setting the via to be used as the second reference via, and the second reference via is set in advance in a direction substantially orthogonal to the first auxiliary line with respect to the second reference via. A third setting step of setting, as a third reference via, a via adjacent to the second reference via located on the second auxiliary line, which is an auxiliary line, and the first reference via and the second reference via A detection step of detecting a via connection wiring that intersects with the first auxiliary line and connected to any via, via connection wiring, and the first auxiliary line and via connection wiring A first temporary placement step of temporarily placing wirings that intersect at a position on the first reference via side in order from the first reference via side at a position that secures at least a predetermined clearance between the wirings; A first virtual line centered on the first reference via, the radius being the distance between the position on the first auxiliary line of the via connection wiring temporarily arranged in the temporary placement step and the first reference via. First virtual circle setting to set a circle The top, the via connection wiring, and the third auxiliary line parallel to the first auxiliary line set in advance with respect to the third reference via intersect at a position closer to the third reference via than the via connection wiring. A second temporary placement step in which wiring is provisionally arranged in order from the third reference via side at a position that secures at least a predetermined clearance between the wirings; and the via connection wiring temporarily arranged in the second temporary placement step A second virtual circle setting step of setting a second virtual circle centered on the third reference via, with a distance between the position on the third auxiliary line and the third reference via as a radius, and When it is determined in the determination step that determines whether or not the first virtual circle and the second virtual circle intersect, and in the determination step that the first virtual circle and the second virtual circle intersect, the first A straight line connecting the reference via and the third reference via An auxiliary line setting step for additionally setting the position of the wiring between the first reference via and the third reference via as an auxiliary line used to determine at least a predetermined clearance between the wirings; .

  A computer program for causing a computer to execute automatic wiring shaping processing according to the present invention sets a plurality of vias as first reference vias in a first setting step, a second setting step, and a third setting step. The detection step, the first temporary placement step, the first virtual circle setting step, the second temporary placement step, the second virtual circle setting step, the determination step, and the auxiliary line setting step are executed.

  According to the present invention, on the virtual plane corresponding to the substrate surface of the semiconductor package in which the wiring and the via are formed, the position of the wiring is based on the intersection relationship between the auxiliary line and the wiring set to connect the vias. In the automatic wiring shaping process for determining at least a predetermined clearance between the wiring and the via and between the wirings on the auxiliary line, the setting of the auxiliary line can be automated by a calculation process by a computer. Accordingly, it is possible to easily realize stable quality wiring shaping in a short time without being influenced by the designer's own skill, experience, intuition, and the like as in the prior art. In addition, according to the present invention, auxiliary lines are set in advance between the vias in the row direction of the vias and the direction perpendicular thereto, and the vias having a high wiring density are set to the previously set auxiliary lines. In addition, since the auxiliary line generated by the series of steps executed by the computer is additionally set, useless auxiliary lines are not set. Therefore, the above-mentioned Patent Document 1 (that is, Japanese Patent Application Laid-Open No. 2002-92061). The amount of calculation processing can be reduced as compared with the invention described in. Further, since it is not necessary to perform manual design through trial and error as in the prior art, the wiring can be shaped efficiently and accurately even if the content of the required wiring becomes complicated. As a result of shortening the design time and reducing the burden on the designer, the manufacturing cost of the semiconductor package can also be reduced.

  FIG. 1 is a flowchart showing an operation flow of an automatic wiring shaping method according to an embodiment of the present invention. 2 to 5 are diagrams showing one specific example of the relationship between vias and wirings on a virtual plane corresponding to the substrate surface of the semiconductor package to which the automatic wiring shaping method according to the embodiment of the present invention is applied. 2 to 5, double circles “◎” in the drawings indicate vias on a virtual plane, and reference signs V1 to V4 are assigned to the vias. Further, in the drawing, a white bold line indicates wiring on a virtual plane. In the drawing, a thick solid line indicates a virtual auxiliary line preset between vias.

  In the design data to which the automatic wiring shaping process according to the embodiment of the present invention is applied, the position of the via is determined on the substrate surface of the semiconductor package. The design data is determined only about whether or not to pass. By applying the automatic wiring shaping process according to the embodiment of the present invention to such design data, the wiring for which only the route has been determined should be arranged at the position to be arranged, that is, how far away from the via. Can decide. This automatic wiring shaping process is based on the invention described in Patent Document 1 (that is, Japanese Patent Application Laid-Open No. 2002-92061) that performs wiring shaping using an auxiliary line. That is, on the virtual plane corresponding to the substrate surface of the semiconductor package on which the wiring and via are formed, the position of the wiring is set on the auxiliary line based on the crossing relationship between the wiring and the auxiliary line set to connect the vias. Is determined to ensure at least a predetermined clearance between the wiring and the via and between the wiring.

  In the embodiment of the present invention, when the auxiliary line is set in advance between the vias in the row direction of the vias and the direction perpendicular thereto, the above-described auxiliary auxiliary is particularly set between the vias having a high wiring density. In addition to the lines, auxiliary lines generated by steps S101 to S112 in FIG. 1 executed by the computer are additionally set. For example, in the specific example shown in FIG. 2, it is assumed that the auxiliary lines H1 and H3 are set in advance in the via row direction and the auxiliary line H2 is set in a direction orthogonal to the via row direction. The auxiliary lines H1 to H3 are indicated by thick solid lines in the figure.

  Steps S101 to S112 in FIG. 1 are executed on a virtual plane corresponding to the substrate surface of the semiconductor package by an arithmetic processing unit such as a computer. Therefore, before executing step S101, design data, rules relating to clearance, coordinates of each via, shape, size and orientation, board information, via column direction, and auxiliary lines between vias are orthogonal to each other. Is input in advance to a computer that executes automatic wiring shaping processing according to an embodiment of the present invention.

  First, in step S101 in FIG. 1, the computer sets (selects) a first reference via from among a plurality of vias on a virtual plane corresponding to the substrate surface of the semiconductor package. In the specific example shown in FIG. 2, the computer sets the via V1 as the first reference via.

  Next, in step S102, the computer sets the first reference via located on the first auxiliary line, which is an auxiliary line set in advance in the via row direction or the direction orthogonal to the first reference via. An adjacent via is set as a second reference via. In the specific example shown in FIG. 2, the computer selects a via V2 adjacent to the first reference via V1 located on the auxiliary line H1 set in advance in the via row direction with respect to the first reference via V1. Set as second reference via.

  Next, in step S103, the computer sets the second reference line that is located on the second auxiliary line that is an auxiliary line set in advance in a direction substantially orthogonal to the first auxiliary line with respect to the second reference via. A via adjacent to the via is set as a third reference via. In the specific example shown in FIG. 2, the computer has a second reference located on the auxiliary line H2 set in advance in a direction substantially orthogonal to the first auxiliary line H1 with respect to the second reference via V2. A via V3 adjacent to the via V2 is set as a third reference via.

  Next, in step S104, the computer detects a via connection wiring that intersects with the first auxiliary line between the first reference via and the second reference via and is connected to one of the vias. To do. In the specific example shown in FIG. 2, the computer replaces the wiring X that intersects the auxiliary line H1 between the first reference via V1 and the second reference via V2 and is connected to the via V4 with the via connection wiring. Detect as.

  Next, in step S105, the computer sequentially connects the via connection wiring and the wiring that intersects the first auxiliary line at a position closer to the first reference via than the via connection wiring from the first reference via side. Temporarily arrange at a position that secures at least a predetermined clearance. In other words, the wiring that intersects the first auxiliary line at a position closer to the first reference via than the via connection wiring has a path (route) between the via connection wiring and the first reference via. It is wiring. In the specific example shown in FIG. 2, the wiring that intersects the auxiliary line H1 at a position closer to the first reference via V1 than the via connection wiring X is between the via connection wiring X and the first reference via V1. The wirings W1 to W3 having the route (route). The computer sequentially connects the via connection wiring X and the wirings W1 to W3 that intersect the auxiliary line and the H1 via connection wiring X on the first reference via V1 side from the first reference via V1 side. Are temporarily arranged at positions where at least a predetermined clearance is secured.

  Next, in step S106, the computer uses the distance between the position of the via connection wiring temporarily placed in step S105 on the first auxiliary line and the first reference via as a radius, and sets the first reference via as the radius. A first virtual circle as the center is set. The first virtual circle generated in steps S105 and S106 ensures a predetermined clearance between the wirings that pass between the first reference via and the position of the via connection wiring on the first auxiliary line. The limit line at the position closest to the first reference via of the via connection wiring is shown. In the specific example shown in FIG. 3, the distance between the position of the temporarily arranged via connection wiring X on the auxiliary line H1 and the first reference via V1 is a radius, and the first reference via V is the center. A first virtual circle P1 is set.

  Next, in step S107, the computer uses the third reference via than the via connection wiring and the third auxiliary line and via connection wiring parallel to the first auxiliary line set in advance for the third reference via. Wirings that intersect at the position on the side are provisionally arranged sequentially from the third reference via side at a position that secures at least a predetermined clearance between the respective wirings. In the specific example shown in FIG. 2, the auxiliary line parallel to the auxiliary line H1 is indicated by H3. In addition, the auxiliary line H3 set in advance with respect to the third reference via V3 and the wiring intersecting at a position closer to the third reference via V3 than the via connection wiring X are the via connection wiring X and the third reference via. The wirings Z1 to Z4 having the path (route) between the via V3. The computer replaces the auxiliary lines H3 set in advance with respect to the third reference via V3 and the wirings Z1 to Z4 that intersect at the third reference via V3 side of the via connection wiring X with the third reference via V3. In order from the side, the wires are provisionally arranged at positions where at least a predetermined clearance is secured between the wirings.

  Next, in step S108, the computer uses the distance between the position of the via connection wiring temporarily arranged in step S107 on the third auxiliary line and the third reference via as a radius, and sets the third reference via as the radius. A second virtual circle is set as the center. The second virtual circle generated in steps S107 and S108 secures a predetermined clearance between the wirings that pass between the third reference via and the position of the via connection wiring on the third auxiliary line. The limit line at the position closest to the third reference via of the via connection wiring is shown. In the specific example shown in FIG. 4, the distance between the position of the temporarily arranged via connection wiring X on the auxiliary line H3 and the third reference via V3 is a radius, and the third reference via V3 is the center. A second virtual circle P2 is set.

  Note that the processes in steps S105 and S106 described above and the processes in steps S107 and S108 may be executed interchangeably.

  Next, in step S109, the computer determines whether or not the first virtual circle and the second virtual circle intersect. If it is determined that the first virtual circle and the second virtual circle intersect, the process proceeds to step S110. If it is determined that the first virtual circle and the second virtual circle do not intersect, the process returns to step S101. . In the specific example shown in FIG. 4, since the virtual circle P1 and the virtual circle P2 intersect, the process proceeds to step S110.

  As described above, the first virtual circle can secure a predetermined clearance between the wirings for the wiring that passes between the first reference via and the position of the via connection wiring on the first auxiliary line. The limit line of the position near the first reference via of the via connection wiring is shown. In addition, the second virtual circle can secure a predetermined clearance between the wirings that pass between the third reference via and the position of the via connection wiring on the third auxiliary line. The limit line of the position closest to the third reference via of the wiring is shown. That is, the intersection of the first virtual circle and the second virtual circle in step S110 means that the first virtual circle is the center of the first virtual circle so that it is difficult to secure a predetermined clearance between the wirings. This means that the wiring density between the reference via and the third reference via which is the center of the second virtual circle is high. In such a case, an auxiliary line is additionally set between the first reference via and the third reference via. Then, the invention described in Patent Document 1 (that is, Japanese Patent Application Laid-Open No. 2002-92061) is executed using the preset auxiliary line and the additionally set auxiliary line, and at least predetermined between each wiring The position of the wiring is determined so as to ensure the clearance.

  That is, in step S110, the computer sets a straight line connecting the first reference via and the third reference via, and sets the position of the wiring between the first reference via and the third reference via between the wirings. It is additionally set as an auxiliary line used for determining to ensure at least a predetermined clearance. Data regarding the auxiliary line additionally set in step S110 is stored in a storage device in the computer. As described above, before the automatic wiring livelihood processing according to the embodiment of the present invention is performed, auxiliary lines are set in advance between the vias in the row direction of the vias and the direction perpendicular thereto. For high vias, in addition to the preset auxiliary lines, auxiliary lines generated by steps S101 to S112 in FIG. 1 executed by the computer are additionally set. Since the virtual circle P1 and the virtual circle P2 intersect in the specific example shown in FIG. 4, the auxiliary line H4 is newly set as shown in FIG.

  The processing in steps S101 to S110 described above is executed for all vias on a virtual plane corresponding to the substrate of the semiconductor package. That is, in step S111, the computer determines whether or not the processing in steps S101 to S110 has been performed on all vias on a virtual plane corresponding to the substrate of the semiconductor package.

  If it is determined that the processing in steps S101 to S110 has not been executed for all the vias, the process returns to step S101 to set a new first reference via. The new first reference via may be a via that is not yet used as the first reference via among the vias on the virtual plane corresponding to the substrate of the semiconductor package. For example, the first reference via may be the first reference via. A via that is adjacent to the set via in the via row direction or in a direction perpendicular thereto may be set as a new first via.

  When the processing in steps S101 to S110 is executed for all the vias on the virtual plane corresponding to the substrate of the semiconductor package, the process proceeds to step S112. In step S112, the computer secures at least a predetermined clearance between the wirings using the auxiliary line set in advance in the via row direction or a direction orthogonal thereto and the auxiliary line additionally set in the auxiliary line setting step. The position of the wiring is determined at the position to be performed. That is, the invention described in Patent Document 1 (that is, Japanese Patent Application Laid-Open No. 2002-92061) is executed to determine the position of the wiring so as to ensure at least a predetermined clearance between the wirings. Data on the position of the wiring determined in step S112 is stored in a storage device in the computer.

  The automatic wiring shaping apparatus according to this embodiment described above is realized using a computer. FIG. 6 is a block diagram showing a configuration of an automatic wiring shaping apparatus according to an embodiment of the present invention that operates according to a program stored in a recording medium.

  A program for causing a computer to execute automatic wiring shaping according to the present invention is stored in a storage medium (external storage medium such as a flexible disk or a CD-ROM) 110 as shown in FIG. It is installed in a computer having a simple configuration and operates as an automatic wiring shaping device.

  The CPU 111 controls the entire automatic wiring shaping device. The CPU 111 is connected to a ROM 113, a RAM 114, an HD (hard disk device) 115, an input device 116 such as a mouse and a keyboard, an external storage medium drive device 117, and a display device 118 such as an LCD, CRT, plasma display, and organic EL via a bus 112. Is connected. A control program for the CPU 111 is stored in the ROM 113.

  A program (automatic wiring shaping processing program) for executing automatic wiring shaping processing according to the present invention is installed (stored) in the HD 115 from the storage medium 110. Further, the RAM 114 has a work area when the CPU 111 executes the automatic wiring shaping process and an area for storing a part of a program for executing the automatic wiring shaping process. The HD 115 stores input data, final data, OS (operating system), and the like in advance.

  First, when the computer is turned on, the CPU 111 reads a control program from the ROM 110, further reads an OS from the HD 115, and starts the OS. As a result, the computer is ready to install the automatic wiring shaping processing program from the storage medium 110.

  Next, the storage medium 110 is mounted on the external storage medium drive device 117, a control command is input from the input device 116 to the CPU 111, and an automatic wiring shaping processing program stored in the storage medium 110 is read and stored in the HD 115 or the like. That is, the automatic wiring shaping program is installed in the computer.

  Thereafter, when the automatic wiring shaping processing program is activated, the computer operates as an automatic wiring shaping device. The operator can execute the above-described automatic wiring shaping process by operating the input device 116 in accordance with the interactive work content and procedure displayed on the display device 118. The “data relating to the optimal route of wiring” obtained as a result of the processing is stored in the HD 115 so that it can be used later, or is used for visually displaying the processing result on the display device 118. Also good.

  In the computer shown in FIG. 6, the program stored in the storage medium 110 is installed in the HD 115. However, the present invention is not limited to this, and the program may be installed in the computer via an information transmission medium such as a LAN. It may be installed in advance in the HD 115 built in the computer.

  The present invention can be applied to shaping processing of wiring of a semiconductor package such as PBGA or EBGA. If the present invention is implemented in combination with the invention described in Japanese Patent Laid-Open No. 2002-92061 (that is, Patent Document 1), more efficient automatic wiring design can be realized. According to the present invention, a so-called wiring shaping operation for shaping a wiring route on a substrate so as to secure at least a predetermined clearance with respect to an adjacent object facing a wiring portion to be shaped is facilitated. be able to.

It is a flowchart which shows the operation | movement flow of the automatic wiring shaping method by the Example of this invention. It is FIG. (1) which shows one specific example of the relationship of the via | veer and wiring on the virtual plane equivalent to the board | substrate surface of the semiconductor package to which the automatic wiring shaping method by the Example of this invention is applied. It is FIG. (2) which shows one specific example of the relationship between the via | veer and wiring on the virtual plane equivalent to the board | substrate surface of the semiconductor package to which the automatic wiring shaping method by the Example of this invention is applied. It is FIG. (3) which shows one specific example of the relationship of the via | veer and wiring on the virtual plane equivalent to the board | substrate surface of the semiconductor package to which the automatic wiring shaping method by the Example of this invention is applied. It is FIG. (4) which shows one specific example of the relationship between the via | veer and wiring on the virtual plane equivalent to the board | substrate surface of the semiconductor package to which the automatic wiring shaping method by the Example of this invention is applied. It is a block diagram which shows the structure of the automatic wiring shaping apparatus by the Example of this invention which operate | moves by the program stored in the recording medium.

Explanation of symbols

110 Recording medium 111 CPU
112 bus 113 ROM
114 RAM
115 Hard Disk Device 116 Input Device 117 External Storage Medium Drive Device 118 Display Device

Claims (10)

On the virtual plane corresponding to the substrate surface of the semiconductor package in which the wiring and via are formed, the position of the wiring is determined based on the crossing relationship between the wiring and the auxiliary line set to connect the vias. In the automatic wiring shaping method for determining to ensure at least a predetermined clearance between the wiring and the via and between the wiring on the auxiliary line,
A first setting step for setting a first reference via from a plurality of vias;
A via adjacent to the first reference via, which is located on a first auxiliary line which is an auxiliary line set in advance in a via row direction or a direction orthogonal to the first reference via, A second setting step for setting as a reference via of
A via adjacent to the second reference via, which is located on a second auxiliary line that is a preset auxiliary line in a direction substantially orthogonal to the first auxiliary line with respect to the second reference via. A third setting step for setting as a third reference via;
Detecting a via connection wiring that is a wiring that intersects the first auxiliary line between the first reference via and the second reference via and is connected to any via;
The via connection wiring and the wiring that intersects the first auxiliary line at a position closer to the first reference via than the via connection wiring are sequentially provided at least between the respective wirings sequentially from the first reference via side. A first temporary placement step of temporarily placing the clearance in a position for securing the clearance;
A distance between the position of the via connection wiring temporarily arranged in the first temporary arrangement step on the first auxiliary line and the first reference via is a radius, and the first reference via is A first virtual circle setting step for setting a first virtual circle as a center;
The via connection wiring and a third auxiliary line parallel to the first auxiliary line preset for the third reference via and a position closer to the third reference via than the via connection wiring. A second temporary placement step of temporarily placing the intersecting wirings sequentially from the third reference via side at a position that secures at least a predetermined clearance between the wirings;
A distance between the position of the via connection wiring temporarily arranged in the second temporary arrangement step on the third auxiliary line and the third reference via is a radius, and the third reference via is A second virtual circle setting step for setting a second virtual circle as a center;
A determination step of determining whether or not the first virtual circle and the second virtual circle intersect;
When it is determined in the determination step that the first virtual circle and the second virtual circle intersect, a straight line connecting the first reference via and the third reference via is defined as the first reference via. And an auxiliary line setting step of additionally setting the position of the wiring between the wiring and the third reference via as the auxiliary line used to determine at least a predetermined clearance between the wirings;
An automatic wiring shaping method comprising:   Setting each of the plurality of vias as the first reference via in the first setting step, the second setting step, the third setting step, the detection step, the first temporary placement step, The automatic wiring shaping method according to claim 1, wherein the first virtual circle setting step, the second temporary placement step, the second virtual circle setting step, the determination step, and the auxiliary line setting step are executed.   The automatic wiring shaping method according to claim 1 or 2, wherein data relating to the auxiliary line additionally set in the auxiliary line setting step is stored in a storage device in a computer.   Wiring at a position that secures at least a predetermined clearance between wirings using the auxiliary line preset in the via row direction or a direction orthogonal thereto and the auxiliary line additionally set in the auxiliary line setting step The automatic wiring shaping method according to any one of claims 1 to 3, further comprising a wiring shaping step for determining the position.   The automatic wiring shaping method according to claim 4, wherein data relating to the position of the wiring determined in the wiring shaping step is stored in a storage device in the computer. On the virtual plane corresponding to the substrate surface of the semiconductor package in which the wiring and via are formed, the position of the wiring is determined based on the crossing relationship between the wiring and the auxiliary line set to connect the vias. A computer program for causing a computer to execute automatic wiring shaping processing for determining at least a predetermined clearance between the wiring and the via and between the wiring on the auxiliary line,
A first setting step for setting a first reference via from a plurality of vias;
A via adjacent to the first reference via, which is located on a first auxiliary line which is an auxiliary line set in advance in a via row direction or a direction orthogonal to the first reference via, A second setting step for setting as a reference via of
A via adjacent to the second reference via, which is located on a second auxiliary line that is a preset auxiliary line in a direction substantially orthogonal to the first auxiliary line with respect to the second reference via. A third setting step for setting as a third reference via;
Detecting a via connection wiring that is a wiring that intersects the first auxiliary line between the first reference via and the second reference via and is connected to any via;
The via connection wiring and the wiring that intersects the first auxiliary line at a position closer to the first reference via than the via connection wiring are sequentially provided at least between the respective wirings sequentially from the first reference via side. A first temporary placement step of temporarily placing the clearance in a position for securing the clearance;
A distance between the position of the via connection wiring temporarily arranged in the first temporary arrangement step on the first auxiliary line and the first reference via is a radius, and the first reference via is A first virtual circle setting step for setting a first virtual circle as a center;
The via connection wiring and a third auxiliary line parallel to the first auxiliary line preset for the third reference via and a position closer to the third reference via than the via connection wiring. A second temporary placement step of temporarily placing the intersecting wirings sequentially from the third reference via side at a position that secures at least a predetermined clearance between the wirings;
A distance between the position of the via connection wiring temporarily arranged in the second temporary arrangement step on the third auxiliary line and the third reference via is a radius, and the third reference via is A second virtual circle setting step for setting a second virtual circle as a center;
A determination step of determining whether or not the first virtual circle and the second virtual circle intersect;
When it is determined in the determination step that the first virtual circle and the second virtual circle intersect, a straight line connecting the first reference via and the third reference via is defined as the first reference via. An auxiliary line setting step of additionally setting the position of the wiring between the via and the third reference via as the auxiliary line used for determining at least a predetermined clearance between the wirings;
A computer program for causing a computer to execute automatic wiring shaping processing characterized by comprising:   Setting each of the plurality of vias as the first reference via in the first setting step, the second setting step, the third setting step, the detection step, the first temporary placement step, The automatic wiring shaping process according to claim 6, wherein the first virtual circle setting step, the second temporary placement step, the second virtual circle setting step, the determination step, and the auxiliary line setting step are executed. A computer program for causing a computer to execute.   The computer program for making a computer perform the automatic wiring shaping process of Claim 6 or 7 with which the data regarding the said auxiliary line additionally set in the said auxiliary line setting step are memorize | stored in the memory | storage device in a computer.   Wiring at a position that secures at least a predetermined clearance between wirings using the auxiliary line preset in the via row direction or a direction orthogonal thereto and the auxiliary line additionally set in the auxiliary line setting step The computer program for making a computer perform the automatic wiring shaping process as described in any one of Claims 6-8 further provided with the wiring shaping step which determines the position of.   The computer program for making a computer perform the automatic wiring shaping process of Claim 9 with which the data regarding the position of the wiring determined in the said wiring shaping step are memorize | stored in the memory | storage device in a computer.

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