JP2010074032A - Wiring board and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high design flexibility wiring board that forms a belt-shape wiring conductor between adjacent semiconductor element connection pads with sufficient spacing between both sides of the semiconductor connection pads even if an array pitch of the semiconductor element connection pad to which an electrode of the semiconductor element is connected is as narrow as to be less than 150 &mu;m, and to provide a method of manufacturing the same. <P>SOLUTION: An upper surface of a semiconductor element connection pad 2A is not only protruded to an upper direction than that of a belt-shape wiring conductor 2C but also entirely exposed from a solder resist layer 3. Further, the size from the upper surface to the lower one is the same. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a wiring board and a manufacturing method thereof, and more particularly to a wiring board suitable for mounting, for example, an area array type semiconductor element by flip chip connection and a manufacturing method thereof.

2. Description of the Related Art Conventionally, as a semiconductor integrated circuit element that is a semiconductor element, there is a so-called area array type semiconductor integrated circuit element in which a large number of electrode terminals are arranged in a lattice pattern over substantially the entire main surface.
As a method of mounting such a semiconductor integrated circuit element on a wiring board, a method of connecting by flip chip connection is employed. In flip chip connection, the upper surface of the semiconductor element connection pad provided on the wiring board is exposed corresponding to the arrangement of the electrode terminals of the semiconductor integrated circuit element, and the exposed upper surface of the semiconductor element connection pad and the electrode of the electronic component are exposed. This is a method in which terminals are opposed to each other and electrically connected via conductive bumps made of solder, gold, or the like.
Recently, a semiconductor element is mounted on a wiring board by such flip-chip connection, and another electronic component is mounted on the wiring board by solder ball connection or wire bond connection. Increasing the mounting density of electronic components is being carried out.

  FIG. 14 shows an example of a conventional wiring board in which an area array type semiconductor integrated circuit element as a semiconductor element is mounted by flip-chip connection, and a semiconductor element mounting substrate as another electronic component is further soldered to the substrate. FIG. 15 is a plan view showing the wiring board of FIG. 14.

  As shown in FIG. 14, a conventional wiring board 110 has a core wiring inside and on the surface of an insulating base 101 in which a plurality of build-up insulating layers 101b are laminated on the upper and lower surfaces of a core insulating board 101a. A conductor 102a and a build-up wiring conductor 102b are deposited, and a protective solder resist layer 103 is deposited on the outermost surface thereof. The insulating base 101 has a semiconductor element mounting portion 101A on which the semiconductor integrated circuit element E1 is mounted at the center of the upper surface, and an electronic component mounting portion 101B on which the semiconductor element mounting substrate E2 is mounted on the outer periphery of the upper surface. .

  A plurality of through holes 104 are formed from the upper surface to the lower surface of the core insulating substrate 101a, and the core wiring conductor 102a is attached to the upper and lower surfaces of the insulating substrate 101a and the inner surface of the through hole 104. The interior of 104 is filled with an embedded resin 105. A plurality of via holes 106 are formed in each of the build-up insulating layers 101b, and a build-up wiring conductor 102b is formed on the surface of each insulating layer 101b and the inner surfaces of the via holes 106. .

  A part of the wiring conductor 102b deposited on the outermost insulating layer 101b on the upper surface side of the wiring substrate 110 is connected to the electrode terminal of the semiconductor integrated circuit element E1 in the semiconductor element mounting portion 101A via the conductive bump B1. Thus, a circular semiconductor element connection pad 102A to be electrically connected by flip chip connection is formed, and a plurality of these semiconductor element connection pads 102A are formed in a lattice pattern. Furthermore, the other part of the wiring conductor 102b deposited on the outermost insulating layer 101b on the upper surface side of the wiring substrate 110 is an electrode of the semiconductor element mounting substrate E2 as an electronic component in the electronic component mounting portion 101B. A circular electronic component connection pad 102B that is electrically connected to the terminal by solder ball connection via the solder ball B2 is formed, and a plurality of the electronic component connection pads 102B are formed side by side. The semiconductor element connection pad 102A and the electronic component connection pad 102B are covered with the solder resist layer 103 at the outer periphery thereof, and the center part of the upper surface is exposed from the solder resist layer 103. The semiconductor element connection pad 102A The electrode terminal of the semiconductor integrated circuit element E1 is electrically connected to the exposed part of the semiconductor element via the conductive bump B1 made of solder, gold or the like, and the electrode terminal of the semiconductor element mounting substrate E2 is soldered to the exposed part of the electronic component connection pad 102B. Electrical connection is made via the ball B2.

  Furthermore, a part of the lower surface side of the wiring board 110 that is deposited on the outermost insulating layer 101b is a circular external connection pad 102C that is electrically connected to the wiring conductor of the external electric circuit board. A plurality of connection pads 102C are formed in a grid and arranged side by side. The external connection pad 102C is covered with a solder resist layer 103 at the outer periphery thereof, and the central portion of the upper surface is exposed from the solder resist layer 103. The external connection pad 102C is exposed to the exposed portion of the external electric circuit board. The wiring conductor is electrically connected via the solder ball B3.

  The solder resist layer 103 protects the outermost wiring conductor 102b and defines exposed portions of the semiconductor element connection pads 102A, the electronic component connection pads 102B, and the external connection pads 102C. Such a solder resist layer 103 is formed by laminating a photosensitive thermosetting resin paste or film on the outermost insulating layer 101b on which the wiring conductor 102b is formed, and then connecting the semiconductor element connection pad 102A and the electronic component connection pad. It is formed by exposing, developing, and curing so as to have an opening that covers the outer peripheral portion of 102B and external connection pad 102C and exposes the central portion. Therefore, the exposed portions of the semiconductor element connection pads 102A and the electronic component connection pads 102B are recessed from the surface of the solder resist layer 103, and the outer peripheral portion is buried under the solder resist layer 103 with a predetermined width. Will be.

  Then, after electrically connecting the electrode terminal of the semiconductor integrated circuit element E1 and the semiconductor element connection pad 102A via the conductive bump B1, the gap between the semiconductor integrated circuit element E1 and the wiring substrate 110 is made of epoxy resin or the like. Filling resin U <b> 1 called underfill made of thermosetting resin is filled, and semiconductor integrated circuit element E <b> 1 is mounted on wiring substrate 110. Furthermore, the semiconductor element mounting board E2 is mounted on the wiring board 110 by electrically connecting the electrode terminals of the semiconductor element mounting board E2 and the electronic component connection pads 102B via the solder balls B2 thereon. Semiconductor elements and electronic components are mounted on the wiring board 110 with high density.

  Recently, however, the degree of integration of the semiconductor integrated circuit element E1 has rapidly increased, and the arrangement pitch of the electrode terminals in the semiconductor integrated circuit element E1 has become a narrow pitch of less than 150 μm. Along with this, the arrangement pitch of the semiconductor element connection pads 102A to which the electrode terminals of the semiconductor integrated circuit element E1 are flip-chip connected is also narrowed to less than 150 μm. In order to reduce the pitch of the semiconductor element connection pads 102A, at least one of the diameters of the semiconductor element connection pads 102A and the adjacent semiconductor element connection pads 102A must be reduced. When the diameter of the semiconductor element connection pad 102A is reduced, the diameter of the exposed portion from the solder resist layer 103 in the semiconductor element connection pad 102A is also reduced. When the diameter of the exposed portion of the semiconductor element connection pad 102A is small, the development is insufficient when forming the solder resist layer 103, and the resin residue of the solder resist layer 103 tends to remain in the exposed portion of the semiconductor element connection pad 102A. In order to improve the connection between the electrode terminal of the semiconductor integrated circuit element E1 and the semiconductor element connection pad 102A without leaving the resin residue of the solder resist layer 103 in the exposed portion of the semiconductor element connection pad 102A, the semiconductor element connection pad 102A The diameter of the exposed portion is preferably about 70 μm or more. The width that the solder resist layer 103 covers the outer periphery of the semiconductor element connection pad 102A needs to be about 15 μm or more due to the positional accuracy problem between the semiconductor element connection pad 102A and the solder resist layer 103. Therefore, when the diameter of the exposed portion of the semiconductor element connection pad 102A is secured to about 70 μm, the diameter of the semiconductor element connection pad 102A is about 100 μm. For example, when the arrangement pitch of the semiconductor element connection pads 102A is 140 μm, if the diameter of the semiconductor element connection pads 102A is 100 μm, the interval between adjacent semiconductor element connection pads 102A is 40 μm. If the interval between adjacent semiconductor element connection pads 102A is 40 μm, a band-shaped wiring conductor having a width of, for example, about 15 μm is formed between them with a sufficient interval of about 15 μm between the semiconductor element connection pads 102A on both sides. It becomes impossible.

If a wiring conductor cannot be formed between the adjacent semiconductor element connection pads 102A, the outermost layers other than the semiconductor element connection pads 102A arranged in the outermost periphery among the semiconductor element connection pads 102A arranged in a grid pattern are arranged. In this wiring conductor 102b, the wiring conductor 102b extending outside the mounting portion 101A cannot be provided, and the design freedom in the wiring board 110 is reduced.
JP 2000-244088 A

  The problem of the present invention is that, in a wiring board on which an area array type semiconductor element is mounted by flip chip connection, even if the arrangement pitch of the semiconductor element connection pads to which the electrodes of the semiconductor element are connected is less than 150 μm, To provide a wiring board with a high degree of design freedom and a manufacturing method thereof capable of forming a strip-like wiring conductor between adjacent semiconductor element connection pads with sufficient spacing between the semiconductor element connection pads on both sides. It is in.

The wiring board according to the present invention includes an insulating base having a mounting portion on which a semiconductor element is mounted on the upper surface, and a grid-like deposit on the mounting portion of the insulating base, and the electrode of the semiconductor element is conductive on the upper surface. A plurality of circular semiconductor element connection pads made of plating layers connected via bumps, and a plating layer that is attached to the upper surface of the insulating base and extends from the semiconductor element connection pads to the outside of the mounting portion And a solder resist layer that is attached to the insulating base so as to cover the band-shaped wiring conductor, exposes the upper surface of the semiconductor element connection pad, and adheres to the side surface of the semiconductor element connection pad The semiconductor element connection pad has an upper surface protruding upward from an upper surface of the strip-shaped wiring conductor, and the solder resist layer. Together are al completely exposed, the size of the over the lower surface from the upper surface and is characterized in that it is the same.
Furthermore, in the wiring board of the present invention, an electronic component connection pad made of a plating layer to which an electronic component other than the semiconductor element is connected is formed outside the mounting portion on the upper surface of the insulating base, and the electronic component connection The center part of the upper surface of the pad is exposed from the solder resist layer.

  The method for manufacturing a wiring board according to the present invention includes a step of depositing a base plating layer made of an electroless plating layer on the entire upper surface of an insulating substrate having a mounting portion on which a semiconductor element is mounted on the upper surface; A first plating mask having a grid-like and circular semiconductor element connection pad formation opening and a strip-shaped wiring conductor formation opening extending from the semiconductor element connection pad formation opening to the outside of the mounting portion; A step of depositing on the layer; a step of forming a first plating layer made of an electrolytic plating layer on the base plating layer in the opening for forming the semiconductor element connection pad and in the opening for forming the strip-shaped wiring conductor; Depositing a second plating mask on the first plating mask to expose the semiconductor element connection pad formation opening and cover the strip-shaped wiring conductor formation opening; Forming a second plating layer comprising a deplating layer on the first plating layer in the opening for forming a semiconductor element connection pad, and after removing the first plating mask and the second plating mask The base plating layer other than the portion covered with the first plating layer is removed by etching, and the base plating layer, the first plating layer, and the first are disposed at positions corresponding to the openings for forming the semiconductor element connection pads. A circular semiconductor element connection pad having the same size from the upper surface to the lower surface is formed, and the base plating layer and the first plating are formed at positions corresponding to the opening for forming the strip-shaped wiring conductor. A step of forming a strip-shaped wiring conductor comprising layers, and a solder resist layer that completely fills the semiconductor element connection pad and the strip-shaped wiring conductor. Forming above is characterized in that performing the step of polishing removal until the upper surface of the semiconductor element connection pads at least a portion of the solder resist layer is completely exposed.

  The method for manufacturing a wiring board according to the present invention includes a step of depositing a base plating layer made of an electroless plating layer on the entire upper surface of an insulating substrate having a mounting portion on which a semiconductor element is mounted on the upper surface, and the mounting A lattice-shaped and circular semiconductor element connection pad forming opening on the part, a strip-shaped wiring conductor forming opening extending from the semiconductor element connection pad forming opening to the outside of the mounting part, and an electronic component outside the mounting part A step of depositing a first plating mask having an opening for forming a connection pad on the underlying plating layer; and a first plating layer made of an electrolytic plating layer in the opening for forming a semiconductor element connection pad and the strip-shaped wiring conductor Forming on the base plating layer in the formation opening and in the electronic component connection pad formation opening, and exposing the semiconductor element connection pad formation opening; Applying a second plating mask on the first plating mask and the first plating layer to cover the inside of the opening for forming the strip-shaped wiring conductor and the opening for forming the electronic component connection pad; and electrolytic plating Forming a second plating layer composed of a layer on the first plating layer in the opening for forming a semiconductor element connection pad, and after removing the first plating mask and the second plating mask, The base plating layer other than the portion covered with the first plating layer is removed by etching, and the base plating layer, the first plating layer, and the second plating layer are formed at positions corresponding to the semiconductor element connection pad forming openings. A circular semiconductor element connection pad made of a plating layer and having the same size from the upper surface to the lower surface is formed, and at a position corresponding to the opening for forming the band-shaped band-shaped wiring conductor The electronic component connection pad including the base plating layer and the first plating layer is formed at a position corresponding to the strip-shaped wiring conductor including the base plating layer and the first plating layer and the opening for forming the electronic component connection pad. Forming a solder resist layer on the insulating substrate that completely fills the semiconductor element connection pad and the strip-shaped wiring conductor and exposes an upper surface central portion of the electronic component connection pad; and the solder resist And a step of polishing and removing at least a part of the layer until the upper surface of the semiconductor element connection pad is completely exposed.

According to the wiring board of the present invention, the upper surface of the semiconductor element connection pad protrudes above the upper surface of the band-shaped wiring conductor extending from the semiconductor element connection pad to the outside of the mounting portion and covered with the solder resist layer. Since the size from the upper surface to the lower surface of the solder resist layer is completely exposed, the exposed area of the upper surface of the semiconductor element connection pad is sufficiently secured and the diameter of the semiconductor element connection pad is maintained. Can be made small. Therefore, even if the arrangement pitch of the semiconductor element connection pads is a narrow pitch of, for example, less than 150 μm, a wide interval between adjacent semiconductor element connection pads can be secured, and the semiconductor resist connection pads are covered with the solder resist layer therebetween. The strip-shaped wiring conductor can be formed with sufficient space between the semiconductor element connection pads on both sides, and a wiring board having a high degree of design freedom can be provided.
Further, when an electronic component connection pad for connecting an electronic component other than the semiconductor element is formed outside the mounting portion, the semiconductor element of the narrow pitch electrode and the other electronic component are placed on the wiring board. Can be mounted to the density.

  According to the method for manufacturing a wiring board of the present invention, a base plating layer made of an electroless plating layer is deposited on the entire upper surface of an insulating base having a mounting portion on which a semiconductor element is mounted on the upper surface, and then the mounting is performed. A first plating mask having a grid-like and circular semiconductor element connection pad formation opening on the portion and a band-shaped wiring conductor formation opening extending from the semiconductor element connection pad formation opening to the outside of the mounting portion; Depositing on the underlying plating layer, and then forming a first plating layer comprising an electrolytic plating layer on the underlying plating layer in the opening for forming the semiconductor element connection pad and in the opening for forming the strip-shaped wiring conductor; Next, a second plating mask that exposes the opening for forming the semiconductor element connection pad and covers the opening for forming the strip-shaped wiring conductor is deposited on the first plating mask, and then electrolytic plating is performed. A second plating layer is formed on the first plating layer in the opening for forming a semiconductor element connection pad, and after removing the first plating mask and the second plating mask, The base plating layer other than the portion covered with the first plating layer is removed by etching, and the base plating layer, the first plating layer, and the second plating are formed at positions corresponding to the openings for forming the semiconductor element connection pads. A circular semiconductor element connection pad having the same size from the upper surface to the lower surface is formed, and the base plating layer and the first plating layer are formed at positions corresponding to the strip-shaped wiring conductor formation openings Forming a strip-shaped wiring conductor, and then forming a solder resist layer on the insulating substrate to completely fill the semiconductor element connection pad and the strip-shaped wiring conductor; Since at least a part of the solder resist layer is polished and removed until the upper surface of the semiconductor element connection pad is completely exposed, the diameter of the semiconductor element connection pad is increased while ensuring a sufficient exposed area of the upper surface of the semiconductor element connection pad. Therefore, even when the arrangement pitch of the semiconductor element connection pads is a narrow pitch of, for example, less than 150 μm, a wide interval between adjacent semiconductor element connection pads can be secured, and A strip-shaped wiring conductor covered with a solder resist layer in between can be formed with sufficient space between the semiconductor element connection pads on both sides, and a wiring board with a high degree of design freedom can be provided.

  Further, according to the method for manufacturing a wiring board of the present invention, a base plating layer made of an electroless plating layer is deposited on the entire upper surface of the insulating base having a mounting portion on which a semiconductor element is mounted on the upper surface. A lattice-shaped and circular semiconductor element connection pad forming opening on the mounting portion, a strip-shaped wiring conductor forming opening extending from the semiconductor element connection pad forming opening to the outside of the mounting portion, and outside the mounting portion A first plating mask having an opening for forming an electronic component connection pad is deposited on the base plating layer, and then the first plating layer made of an electrolytic plating layer is formed in the opening for forming the semiconductor element connection pad and in the strip shape. Formed on the underlying plating layer in the wiring conductor forming opening and in the electronic component connection pad forming opening, and then exposing the semiconductor element connection pad forming opening and A second plating mask covering the opening for forming the band-shaped wiring conductor and the opening for forming the electronic component connection pad is deposited on the first plating mask and the first plating layer, and then from the electrolytic plating layer The second plating layer is formed on the first plating layer in the opening for forming the semiconductor element connection pad, and then the first plating mask and the second plating mask are removed, and then the first plating layer is removed. The base plating layer other than the portion covered with the plating layer is removed by etching, and the base plating layer, the first plating layer, and the second plating layer are formed at positions corresponding to the openings for forming the semiconductor element connection pads. A circular semiconductor element connection pad having the same size from the upper surface to the lower surface is formed, and the base plating layer is formed at a position corresponding to the opening for forming the strip-shaped wiring conductor. And forming the electronic component connection pad including the base plating layer and the first plating layer at a position corresponding to the band-shaped wiring conductor including the first plating layer and the opening for forming the electronic component connection pad. A solder resist layer is formed on the insulating substrate to completely fill the semiconductor element connection pad and the strip-shaped wiring conductor and expose the central portion of the upper surface of the electronic component connection pad. Next, at least one of the solder resist layers is formed. In addition to the above, a wiring board capable of high-density mounting of a semiconductor element of a narrow pitch electrode and other electronic components is provided because the portion is polished and removed until the upper surface of the semiconductor element connection pad is completely exposed. can do.

Hereinafter, a wiring board and a manufacturing method thereof according to the present invention will be described in detail with reference to the drawings.
FIG. 1 shows a wiring according to the present invention in which an area array type semiconductor integrated circuit element as a semiconductor element is mounted by flip chip connection, and a semiconductor element mounting substrate as another electronic component is mounted thereon by solder ball connection. FIG. 2 is a schematic cross-sectional view showing an example of a substrate, and FIG. 2 is a plan view showing the wiring substrate of FIG.

  As shown in FIG. 1 and FIG. 2, the wiring board 10 according to the present invention is used for the core inside and on the surface of the insulating base 1 in which the insulating layer 1b for buildup is laminated on the upper and lower surfaces of the insulating board 1a for the core. The wiring conductor 2a and the build-up wiring conductor 2b are deposited, and the protective solder resist layer 3 is deposited on the outermost surface thereof. The insulating base 1 has a semiconductor element mounting portion 1A on which the semiconductor integrated circuit element E1 is mounted at the center of the upper surface and an electronic component mounting portion 1B on which the semiconductor element mounting substrate E2 is mounted on the outer periphery of the upper surface. .

  The core insulating substrate 1a has a thickness of about 0.05 to 1.5 mm. For example, a glass cloth in which glass fiber bundles are woven vertically and horizontally is impregnated with a thermosetting resin such as a bismaleimide triazine resin or an epoxy resin. Made of electrically insulating material. The insulating substrate 1 a functions as a core member of the insulating base 1.

  A plurality of through holes 4 having a diameter of about 0.05 to 0.3 mm are formed in the core insulating substrate 1a from the upper surface to the lower surface, and the upper and lower surfaces of the insulating substrate 1a and the inner surface of the through hole 4 are formed on the inner surface of the through hole 4. The core wiring conductor 2a is attached. The core wiring conductor 2a is mainly formed of copper foil or electroless copper plating and electrolytic copper plating thereon on the upper and lower surfaces of the insulating substrate 1a, and the electroless copper plating and its inner surface on the through hole 4 It is formed from the above electrolytic copper plating.

  The through hole 4 is filled with an embedded resin 5 made of a thermosetting resin such as an epoxy resin, and the wiring conductors 2a formed on the upper and lower surfaces of the insulating substrate 1a are connected to each other in the through hole 4. It is electrically connected via the conductor 2a.

  Such an insulating substrate 1a is obtained by sticking a copper foil for the wiring conductor 2a on the upper and lower surfaces of a sheet in which a glass fabric is impregnated with an uncured thermosetting resin, and then thermally curing the sheet, It is produced by drilling for the through hole 4 from the bottom to the bottom.

  The core wiring conductor 2a has a copper foil having a thickness of about 2 to 18 μm adhered to the entire upper and lower surfaces of the sheet for the insulating substrate 1a as described above. After the through hole 4 is drilled, electroless copper plating and electrolytic copper plating are sequentially applied to the inner surface of the through hole 4 and the copper foil surface, and then the inside of the through hole 4 is filled with the embedded resin 5. The copper foil and the copper plating are etched into a predetermined pattern using a photolithography technique, so that the upper and lower surfaces of the insulating substrate 1a and the inner surface of the through hole 4 are formed.

  The embedding resin 5 is for allowing the build-up insulating layer 1b to be formed immediately above and immediately below the through-hole 4 by closing the through-hole 4, and through the uncured paste-like thermosetting resin. The hole 4 is formed by filling the hole 4 by screen printing, thermally curing it, and then polishing the upper and lower surfaces thereof to be substantially flat.

  The insulating layers 1b for buildup laminated on the upper and lower surfaces of the insulating substrate 1a each have a thickness of about 20 to 60 μm. Similarly to the insulating substrate 1a, an electrically insulating material in which a glass cloth is impregnated with a thermosetting resin Or, it is made of an electrically insulating material in which an inorganic filler such as silicon oxide is dispersed in a thermosetting resin such as an epoxy resin. A plurality of via holes 6 having a diameter of about 30 to 100 μm are formed in each insulating layer 1 b, and a buildup wiring conductor 2 b is attached to the surface of each insulating layer 1 b and the via hole 6.

  These insulating layers 1b are bonded with a resin sheet containing an uncured thermosetting resin composition on the surface of the insulating substrate 1a on which the wiring conductor 2a is formed or on the surface of the insulating layer 1b on which the wiring conductor 2b is formed. Then, after thermosetting, the via hole 6 is formed by drilling the predetermined position by laser processing.

  The build-up wiring conductor 2b is composed of electroless copper plating and electrolytic copper plating thereon, and the wiring conductor 2b located in the upper layer and the wiring conductor 2a or 2b located in the lower layer across the insulating layer 1b are connected to the via hole 6. High density wiring can be formed three-dimensionally by being electrically connected via the inner wiring conductor 2b.

  Such a build-up wiring conductor 2b has a thickness of about 5 to 20 μm and is formed by a method called a semi-additive method. In the semi-additive method, for example, a base plating layer for electrolytic plating is formed by electroless copper plating on the surface of the build-up insulating layer 1b in which the via hole 6 is formed, and an opening corresponding to the wiring conductor 2b is formed thereon. After forming a plating resist layer having, and then forming the wiring conductor 2b by applying electrolytic copper plating on the base plating layer exposed from the opening using the base plating layer as an electrode for feeding, and after peeling the plating resist In this method, each wiring conductor 2b is electrically independent by etching away the exposed underlying plating layer.

  A part of the build-up wiring conductor 2b deposited on the outermost insulating layer 1b on the upper surface side of the wiring substrate 10 is soldered to the electrode of the semiconductor integrated circuit element E1 in the semiconductor element mounting portion 1A. Circular semiconductor element connection pads 2A that are electrically connected via the conductive bumps B1 are formed, and a plurality of these semiconductor element connection pads 2A are formed in a grid. Further, of the build-up wiring conductor 2b, another part of the wiring conductor 2b deposited on the outermost insulating layer 1b on the upper surface side of the wiring substrate 10 is an electrode of the semiconductor element mounting substrate E2 in the electronic component mounting portion 1B. Circular electronic component connection pads 2B that are electrically connected to terminals by solder ball connection via solder balls B2 are formed, and a plurality of pads are formed side by side. Some of these semiconductor element connection pads 2A and some of the electronic component connection pads 2B extend from the semiconductor element mounting portion 1A to the electronic component mounting portion 1B on the outermost insulating layer 1b on the upper surface side of the wiring board 10. They are connected to each other by a strip-like wiring conductor 2C formed of a part of the wiring conductor 2b. In addition, a portion of the lower surface side of the wiring board 10 deposited on the outermost insulating layer 1b is electrically connected to the wiring conductor of the external electric circuit board via the solder balls B3. A connection pad 2D is formed, and a plurality of connection pads 2D are formed side by side.

  The semiconductor element connection pad 2A has a thickness of about 10 to 30 μm, and has the same size from the top surface to the bottom surface as shown in FIG. Protrudes about 5 to 15 μm above the upper surface of the strip-shaped wiring conductor 2C and the upper surface of the electronic component connection pad 2B. The semiconductor element connection pads 2A have a narrow pitch with an arrangement pitch of less than 150 μm, and between the adjacent semiconductor element connection pads 2A, a strip-shaped wiring conductor 2C having a width of about 15 μm is placed between the semiconductor element connection pads 2A on both sides and 15 μm. For example, if the arrangement pitch is 140 μm, the diameter is 85 μm or less, and if the arrangement pitch is 130 μm, the diameter is set. If the diameter is 75 μm or less and the arrangement pitch is 120 μm, the diameter is set to 65 μm or less. The electronic component connection pads 2B have a thickness of about 10 to 15 μm and a diameter of about 200 to 450 μm, and are formed on the outer peripheral portion of the upper surface of the insulating base 1 with a frame shape and an array pitch of 400 to 650 μm.

  The strip-shaped wiring conductor 2C has a strip shape with a thickness of about 10 to 15 μm and a width of about 10 to 15 μm, which is the same as the electronic component connection pad 2B, and the outermost semiconductor element connection pad 2A and the semiconductor element connection inside it. It extends from the pad 2A to the outside of the semiconductor element mounting portion 1A. The strip-shaped wiring conductor 2C extending from the inner semiconductor element connection pad 2A has a space of about 15 μm or more between the outer semiconductor element connection pad 2A and the semiconductor element connection pad 2A. It is formed to pass through. Thus, since the wiring conductor 2C extends from the semiconductor element connection pad 2A inside the outermost semiconductor element connection pad 2A to the outside of the semiconductor element mounting portion 1A, a large number of semiconductor element connection pads 2A and electronic components It becomes possible to directly connect the connection pad 2B on the outermost insulating layer 1b. Therefore, according to the wiring board of the present invention, the degree of freedom in designing the wiring board can be increased.

  Further, a solder resist layer 3 is deposited on the outermost insulating layer 1b. The solder resist layer 3 is a protective film for protecting the outermost wiring conductor 2b from heat and the external environment. The upper surface of the solder resist layer 3 covers the belt-like wiring conductor 2C and the entire upper surface of the semiconductor element connection pad 2A. In addition, the electronic component connection pad 2B is attached so as to expose the central portion of the upper surface. Further, the solder resist layer 3 on the lower surface side is attached so as to expose the central portion of the external connection pad 2D.

  The solder resist layer 3 on the upper surface side has a circular recess 3A that exposes each semiconductor element connection pad 2A individually at the center of the bottom surface with the upper surface of the semiconductor element connection pad 2A and its periphery as the bottom surface. As a result, the entire upper surface of each semiconductor element connection pad 2 </ b> A is exposed from the solder resist layer 3, and its side surface is in close contact with the solder resist layer 3. The solder resist layer 3 on the upper surface side has a circular opening 3B that exposes the center of the upper surface of the electronic component connection pad 2B. As a result, the outer peripheral portion of the electronic component connection pad 2B is covered with the solder resist layer 3, and the central portion of the electronic component connection pad 2B is exposed from the solder resist layer 3. Also, the solder resist layer 3 on the lower surface side has a circular opening 3C that exposes the center of the lower surface of the external connection pad 2D. As a result, the outer peripheral portion of the external connection pad 2D is covered with the solder resist layer 3, and the central portion of the external connection pad 2D is exposed from the solder resist layer 3.

  In the wiring substrate 10 of the present invention, the size from the upper surface to the lower surface of the semiconductor element connection pad 2A is the same, and the entire upper surface of the semiconductor element connection pad 2A is exposed from the solder resist layer 3. Even if the arrangement pitch of the semiconductor element connection pads 2A is a narrow pitch of less than 150 μm, it is adjacent to the upper surface of the semiconductor element connection pad 2A while ensuring a sufficient area for connection to the electrode terminal of the semiconductor integrated circuit element E1. The space between the semiconductor element connection pads 2A can be secured widely, whereby the strip-like wiring conductor 2C is formed between the semiconductor element connection pads 2A with a sufficient distance between the semiconductor element connection pads 2A on both sides. can do. Furthermore, since the upper surface of the semiconductor element connection pad 2A protrudes above the upper surface of the strip-shaped wiring conductor 2C, the strip-shaped wiring conductor 2C is covered with the solder resist layer 3 while the entire upper surface of the semiconductor element connection pad 2A is exposed. be able to. Therefore, although the arrangement pitch of the semiconductor element connection pads 2A is a narrow pitch of less than 150 μm, it is possible to form the strip-shaped wiring conductor 2C covered with the solder resist layer 3 between the semiconductor element connection pads 2A. Therefore, it is possible to provide a wiring board having a high degree of design freedom. Further, the recess 3A formed in the solder resist layer 3 on the upper surface side connects the conductive bump B1 and the semiconductor element when the electrode terminal of the semiconductor integrated circuit element E1 is connected to the semiconductor element connection pad 2A via the conductive bump B1. It can be used as a guide for positioning with the pad 2A, whereby the mounting of the semiconductor integrated circuit element E1 on the wiring board 10 can be facilitated.

  The recess 3A formed in the solder resist layer 3 on the upper surface side preferably has a diameter of about 15 μm or more larger than the diameter of the semiconductor element connection pad 2A. When the diameter of the recess 3A is larger than the diameter of the semiconductor element connection pad 2A by less than 15 μm, it is difficult to satisfactorily expose the entire surface of the semiconductor element connection pad 2A in the recess 3A. The depth of the recess 3A is preferably about 2 to 10 μm. If the depth of the recess 3A is less than 2 μm, it becomes difficult to position the conductive bump B1 using the recess 3A and the semiconductor element connection pad 2A, and if it exceeds 10 μm, the strip-like wiring conductor 2C between the semiconductor element connection pads 2A is formed. The risk of exposure increases, and it becomes difficult to ensure electrical insulation in the uppermost wiring conductor 2b. When the arrangement pitch of the semiconductor element connection pads 2A is extremely narrow and it is difficult to provide the recesses 3A that individually surround the semiconductor element connection pads 2A in the solder resist layer 3, as described later, It is preferable to expose the upper surface of the semiconductor element connection pad 2A by providing a recess 3AA that collectively surrounds the mounting portion 1A.

  Further, the central portion of the upper surface of the electronic component connection pad 2B is exposed in the opening 3B provided in the solder resist layer 3, and forms the bottom surface of the recess formed by the opening 3B. As a result, when the semiconductor element mounting board E2 is mounted on the wiring board 10, the solder balls B2 that connect the electrode terminals of the semiconductor element mounting board E2 and the electronic component connection pads 2B are satisfactorily formed on the electronic component connection pads 2B. Thus, the semiconductor element mounting substrate E2 can be satisfactorily mounted on the wiring substrate 10.

The upper surface of the semiconductor element connection pad 2A and the upper surface of the electronic component connection pad 2B exposed from the solder resist layer 3 prevent the semiconductor element connection pad 2A and the electronic component connection pad 2B from being oxidatively corroded and conductive bumps. In order to improve the connection with B1 and solder ball B2, nickel plating and gold plating are sequentially applied by electroless plating or electrolytic plating, or a solder layer containing tin, indium, or the like is applied. You may leave it.
Then, after electrically connecting the electrode terminal of the semiconductor integrated circuit element E1 and the semiconductor element connection pad 2A via the conductive bump B1, the gap between the semiconductor integrated circuit element E1 and the wiring substrate 10 is made of epoxy resin or the like. Filling resin U <b> 1 called an underfill made of thermosetting resin is filled, and semiconductor integrated circuit element E <b> 1 is mounted on wiring substrate 10. Furthermore, the semiconductor element mounting board E2 is mounted on the wiring board 10 by electrically connecting the electrode terminals of the semiconductor element mounting board E2 and the electronic component connection pads 2B via the solder balls B2 thereon. Semiconductor elements and electronic components are mounted on the wiring board 10 with high density.

  Next, the manufacturing method of the wiring board of the present invention is based on the formation of the semiconductor element connection pad 2A, the electronic component connection pad 2B, the strip-shaped wiring conductor 2C, and the solder resist layer 3 as an example, based on FIGS. Explained.

First, as shown in FIG. 4A, a via hole 6 is formed in the outermost insulating layer 1b on the upper surface side. For example, a carbon dioxide laser or a YAG laser is used to form the via hole 6. Next, as shown in FIG. 4B, a base plating layer 51 for electrolytic plating is deposited on the surface of the insulating layer 1b and the entire surface of the via-ho 6 by electroless plating. As the electroless plating for forming the base plating layer 51, electroless copper plating is preferable.
Next, as shown in FIG. 5 (c), a first photosensitive alkali development dry film resist DFR1 is attached to the surface of the base plating layer 51, and this is exposed and developed using a photolithography technique. By doing so, as shown in FIG. 5D, the semiconductor element connection pad forming opening M1A having a shape corresponding to the semiconductor element connection pad 2A and the electronic component connection pad forming opening having a shape corresponding to the electronic component connection pad 2B are obtained. A first plating mask layer M1 having a strip-shaped wiring conductor forming opening M1C having a shape corresponding to M1B and the strip-shaped wiring conductor 2C is formed. The thickness of the first plating mask M1 is preferably slightly thicker than the thickness of the semiconductor element connection pad 2A to be formed later.

  Next, as shown in FIG. 6E, the base plating exposed in the semiconductor element connection pad formation opening M1A, the electronic component connection pad formation opening M1B, and the strip-like wiring conductor formation opening M1C of the first plating mask M1. On the layer 51, the 1st plating layer 52 of the shape corresponding to the semiconductor element connection pad 2A, the electronic component connection pad 2B, and the strip-shaped wiring conductor 2C is deposited by electrolytic plating. As the electrolytic plating for forming the first plating layer 52, electrolytic copper plating is preferable. Here, the thickness of the first plating layer 52 is thinner than that of the first plating mask M1. Specifically, the thickness of the first plating layer 52 is 8 to 20 μm, preferably 10 to 15 μm.

  Next, as shown in FIG. 6 (f), a second photosensitive alkali development dry film resist DFR2 is attached to the surfaces of the first plating mask M1 and the first plating layer 52, and this is applied to photolithography. By performing exposure and development using a technique, as shown in FIG. 7 (g), an opening M1A for exposing the semiconductor element connection pad formation opening M1A and an electronic component connection pad formation opening M1B and a strip-like wiring are provided. A second plating mask M2 is formed to cover the conductor forming opening M1C. The diameter of the opening M2A of the second plating mask M2 is preferably about 15 to 25 μm larger than the diameter of the semiconductor element connection pad forming opening M1A of the first plating mask M1. The thickness is preferably 5 μm or more on the first plating mask M1.

  Next, as shown in FIG. 7H, a second plating layer 53 is formed by electrolytic plating on the first plating layer 52 in the semiconductor element connection pad formation opening M1A exposed from the second plating mask M2. To do. As the second plating layer 53, electrolytic copper plating is preferable. The height of the second plating layer 53 is set slightly lower than the upper surface of the first plating mask M1. At this time, the side surfaces of the first plating layer 52 and the second plating conductor 53 formed in the same semiconductor element connection pad forming opening M1A are not shifted from each other, and the size from the upper surface to the lower surface is not different. It will be the same.

Next, as shown in FIG. 8I, the first plating mask M1 and the second plating mask M2 are removed. The removal of the first plating mask M1 and the second plating mask M2 can be performed, for example, by immersion in an aqueous sodium hydroxide solution.
Next, as shown in FIG. 8J, the base plating layer 51 other than the portion covered with the first plating layer 52 is removed. As a result, the semiconductor element connection pad 2A including the base plating layer 51, the first plating layer 52, and the second plating layer 53, the electronic component connection pad 2B including the base plating layer 51 and the first plating layer 52, and the belt-like shape. A wiring conductor 2C is formed. At this time, the upper surface of the semiconductor element connection pad 2A protrudes upward by the thickness of the second plating layer 53 from the upper surface of the electronic component connection pad 2B and the upper surface of the strip-shaped wiring conductor 2C. In order to remove the base plating layer 51 other than the portion covered with the first plating layer 52, the base plating layer 51 exposed after the removal of the first plating mask M1 and the second plating mask M2 is removed. For example, a method of etching and removing with an etching solution containing hydrogen peroxide, sodium persulfate, or the like may be employed.

  Next, as shown in FIG. 9 (k), a resin 3a for a solder resist layer that covers the semiconductor element connection pad 2A, the electronic component connection pad 2B, and the strip-shaped wiring conductor 2C over the entire surface on the outermost insulating layer 1b on the upper surface side. As shown in FIG. 9L, a solder resist having an opening 3B that exposes the central portion of the upper surface of the electronic component connection pad 2B is obtained by performing exposure and development using a photolithography technique. Layer 3 is formed. As the resin 3a for the solder resist layer, various known resins that function as a solder resist layer for protecting the surface of the wiring board can be employed. Specifically, for example, silicon oxide or acryl-modified epoxy resin or the like can be used. A photosensitive thermosetting resin in which about 30 to 70% by mass of an inorganic powder filler such as talc is dispersed is preferable.

  Next, as shown in FIG. 10 (m), a third photosensitive alkaline development type dry film resist DFR3 covering the opening 3B is attached to the entire surface of the solder resist layer 3, and this is applied using a photolithography technique. By performing exposure and development, as shown in FIG. 10 (n), a polishing mask M3 having a portion corresponding to the semiconductor element connection pad 2A on the upper surface of the solder resist layer 3 and an opening M3A exposing the periphery thereof is formed. . The diameter of the opening M3A of the polishing mask M3 is preferably about 20 to 50 μm larger than the diameter of the first semiconductor element connection pad 2A. The thickness is preferably 15 μm or more on the solder resist layer 3.

  Next, as shown in FIG. 11 (o), after the portion exposed from the opening M3A of the polishing mask M3 in the solder resist layer 3 is polished until the entire upper surface of the semiconductor element connection pad 2A is exposed, the polishing mask M3 is removed. By removing, the entire upper surface of the semiconductor element connection pad 2A is exposed and formed in the solder resist layer 3 in the recess 3A formed in the solder resist layer 3 by the polishing as shown in FIG. A wiring substrate 10 is obtained in which the central portion of the upper surface of the electronic component connection pad 2B is exposed in the opening 3B and the belt-like wiring conductor 2C is covered with the solder resist layer 3. Thus, according to the method for manufacturing a wiring board of the present invention, the diameter of the semiconductor element connection pad 2A can be reduced while sufficiently securing the exposed area of the upper surface of the semiconductor element connection pad 2A. Even if the arrangement pitch of the semiconductor element connection pads 2A is a narrow pitch of, for example, less than 150 μm, a wide interval between the adjacent semiconductor element connection pads 2A can be secured, and the solder resist layer 3 is covered between them. The strip-like wiring conductor 2C can be formed with a sufficient space between the semiconductor element connection pads 2A on both sides, thereby providing a wiring board with a high degree of design freedom. In addition, what is necessary is just to employ | adopt the various well-known mechanical grinding | polishing methods and the laser scribing method including the wet blasting method for the said grinding | polishing.

  In the wiring substrate 10 on which the solder resist layer 3 is deposited as described above, as shown in FIG. 1, the electrode terminals (pitch is less than 150 μm) of the area array type semiconductor integrated circuit element E1 are connected to the semiconductor element. By electrically connecting the pad 2A via the conductive bump B1 (flip chip connection), the electrode terminal of the semiconductor integrated circuit element E1 and the wiring conductor 2b are electrically connected.

  After electrically connecting the electrode terminal of the semiconductor integrated circuit element E1 and the wiring conductor 2b, the gap between the semiconductor integrated circuit element E1 and the wiring substrate 10 is filled with the filling resin U1, thereby the semiconductor integrated circuit element E1. Is mounted on the wiring board 10. Here, since the upper surface of the semiconductor element connection pad 2A protrudes upward from the upper surface of the strip-shaped wiring conductor 2C by the thickness of the second plating layer 53, it is sufficient between the semiconductor integrated circuit element E1 and the wiring substrate 10. A gap with a high height can be secured, and a wiring board excellent in filling property of the filling resin U1 can be provided.

  Further, by further connecting the electrode terminal of the semiconductor element mounting board E2 as an electronic component and the electronic component connection pad 2B via the solder ball B2, the wiring conductor of the semiconductor element mounting board E2 and the wiring board 10 is further provided. The semiconductor element mounting board E2 is mounted on the wiring board 10 by solder ball connection. In this way, the semiconductor element and the electronic component are mounted with high density on the wiring board of the present invention. Here, since the upper surface of the electronic component connection pad 2B forms the bottom surface of the recess formed by the opening of the solder resist layer 3, the solder ball B2 is well positioned in the recess, and the semiconductor element mounting substrate It becomes possible to connect E2 on the wiring board 10 satisfactorily.

  In the example described above, the example in which the recesses 3A for individually exposing the respective semiconductor element connection pads 2A are provided in the solder resist 3 on the upper surface side is shown. However, as shown in FIGS. By providing the solder resist layer 3 with a recess 3AA that collectively surrounds the semiconductor element mounting portion 1A, the entire upper surface of the semiconductor element connection pad 2A may be exposed at the bottom surface of the recess 3AA. In this case, when the filling resin U1 is filled in the gap between the semiconductor integrated circuit element E1 and the wiring substrate 20, the edge of the recess 3AA functions as a dam that prevents the filling resin U1 from flowing out to the outside. Unnecessary outflow of the resin U1 to the outer peripheral portion of the insulating substrate 1 can be prevented.

It is a schematic sectional drawing which shows one example of embodiment in the wiring board of this invention. It is a top view which shows the wiring board of FIG. It is a principal part perspective view in the wiring board of FIG. (A)-(b) is a schematic explanatory drawing which shows the manufacturing method of the wiring board concerning this invention. (C)-(d) is a schematic explanatory drawing which shows the manufacturing method of the wiring board concerning this invention. (E)-(f) is a schematic explanatory drawing which shows the manufacturing method of the wiring board concerning this invention. (G)-(h) is a schematic explanatory drawing which shows the manufacturing method of the wiring board concerning this invention. (I)-(j) is a schematic explanatory drawing which shows the manufacturing method of the wiring board concerning this invention. (K)-(l) is a schematic explanatory drawing which shows the manufacturing method of the wiring board concerning this invention. (M)-(n) is a schematic explanatory drawing which shows the manufacturing method of the wiring board concerning this invention. (O)-(p) is a schematic explanatory drawing which shows the manufacturing method of the wiring board concerning this invention. It is a schematic sectional drawing which shows the other embodiment example in the wiring board of this invention. It is a top view which shows the wiring board of FIG. It is a schematic sectional drawing which shows the conventional wiring board. It is a top view which shows the wiring board of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Insulation base | substrate 1A Mounting part 2A Semiconductor element connection pad 2B Electronic component connection pad 2C Band-shaped wiring conductor 3 Solder resist layer 51 Base plating layer 52 1st plating layer 53 2nd plating layer M1 1st plating mask M1A Semiconductor element connection Pad forming opening M1B Electronic component connection pad forming opening M1C Band-shaped wiring conductor forming opening M2 Second plating mask

Claims (4)

  An insulating base having a mounting portion on which a semiconductor element is mounted on the upper surface, and a grid-like coating is applied to the mounting portion of the insulating base, and the electrodes of the semiconductor element are connected to the upper surface via conductive bumps. A plurality of circular semiconductor element connection pads made of a plating layer; a belt-like wiring conductor made of a plating layer that is attached to the upper surface of the insulating base and extends from the semiconductor element connection pad to the outside of the mounting portion; A wiring formed on the insulating substrate so as to cover the strip-shaped wiring conductor, and having a solder resist layer that exposes an upper surface of the semiconductor element connection pad and adheres closely to a side surface of the semiconductor element connection pad The semiconductor element connection pad is a substrate, the upper surface of which protrudes above the upper surface of the strip-shaped wiring conductor and is completely exposed from the solder resist layer. Together with the wiring board size of over the lower surface from the upper surface thereof, characterized in that the same.   An electronic component connection pad made of a plating layer to which an electronic component other than the semiconductor element is connected is formed outside the mounting portion on the upper surface of the insulating base, and the central portion of the upper surface of the electronic component connection pad is the solder resist. The wiring board according to claim 1, wherein the wiring board is exposed from the layer.   A step of depositing a base plating layer made of an electroless plating layer on the entire upper surface of the insulating substrate having a mounting portion on which a semiconductor element is mounted; and a grid-like and circular semiconductor element connection on the mounting portion Depositing a first plating mask having a pad forming opening and a band-shaped wiring conductor forming opening extending from the semiconductor element connection pad forming opening to the outside of the mounting portion on the base plating layer; Forming a first plating layer comprising a plating layer on the underlying plating layer in the opening for forming the semiconductor element connection pad and in the opening for forming the strip-like wiring conductor; and exposing the opening for forming the semiconductor element connection pad Depositing a second plating mask covering the opening for forming the strip-shaped wiring conductor on the first plating mask, and a second plating comprising an electrolytic plating layer. Forming a layer on the first plating layer in the opening for forming the semiconductor element connection pad, and removing the first plating mask and the second plating mask, and then covering the first plating layer with the first plating layer. Etching away the base plating layer other than the cracked portion, and comprising the base plating layer, the first plating layer, and the second plating layer at a position corresponding to the opening for forming the semiconductor element connection pad, from the top surface A circular semiconductor element connection pad having the same size on the lower surface is formed, and a band-shaped wiring conductor composed of the base plating layer and the first plating layer is formed at a position corresponding to the opening for forming the band-shaped wiring conductor. Forming a solder resist layer on the insulating substrate to completely fill the semiconductor element connection pad and the strip-shaped wiring conductor; and Method for manufacturing a wiring substrate, characterized by performing the step of polishing removal until the upper surface of the semiconductor element connection pads at least a portion of the over the resist layer is completely exposed.   A step of depositing a base plating layer made of an electroless plating layer on the entire upper surface of the insulating substrate having a mounting portion on which a semiconductor element is mounted; and a grid-like and circular semiconductor element connection on the mounting portion A first plating mask having a pad forming opening, a band-shaped wiring conductor forming opening extending from the semiconductor element connection pad forming opening to the outside of the mounting portion, and an electronic component connection pad forming opening outside the mounting portion And a first plating layer comprising an electrolytic plating layer in the opening for forming a semiconductor element connection pad, the opening for forming a strip-shaped wiring conductor, and the opening for forming an electronic component connection pad. And forming the semiconductor element connection pad forming opening and exposing the band-shaped wiring conductor forming opening and the front A step of depositing a second plating mask covering the opening for forming an electronic component connection pad on the first plating mask and the first plating layer; and a second plating layer formed of an electrolytic plating layer as the semiconductor A step of forming on the first plating layer in the element connection pad forming opening, and a portion other than the portion covered with the first plating layer after removing the first plating mask and the second plating mask The base plating layer is etched away, and the base plating layer, the first plating layer, and the second plating layer are formed at positions corresponding to the openings for forming the semiconductor element connection pads. Forming a circular semiconductor element connection pad having the same length, and forming the base plating layer and the first plating layer at a position corresponding to the opening for forming the belt-like strip-like wiring conductor Forming the electronic component connection pad comprising the base plating layer and the first plating layer at a position corresponding to the band-shaped wiring conductor and the opening for forming the electronic component connection pad, and the semiconductor element connection pad and the band shape Forming a solder resist layer on the insulating substrate that completely fills the wiring conductor and exposes the central portion of the upper surface of the electronic component connection pad; and at least part of the solder resist layer is the semiconductor element connection pad And a step of polishing and removing until the upper surface of the substrate is completely exposed.