JP2010003990A - Manufacturing method of semiconductor device - Google Patents

Abstract

Two types of semiconductor layers are selected and formed with high accuracy and ease in as few steps as possible to simplify the steps and greatly reduce the number of steps and manufacturing costs. A semiconductor device with high element performance is realized by adapting.
A SiC layer is selectively formed simultaneously in both the element region of the P-type MOS transistor and the element region of the N-type MOS transistor by, for example, an epitaxial growth method, and a mask layer is formed in the element region of the N-type MOS transistor. Then, the SiC layer formed in the element region of the P-type MOS transistor is removed using the mask layer, and after the SiGe layer is selectively formed by, for example, an epitaxial growth method, the mask layer is removed.
[Selection] Figure 2

Description

  The present invention relates to a method of manufacturing a semiconductor device including a P-type transistor and an N-type transistor, and particularly to a semiconductor device whose operating speed is improved by applying strain to a source / drain.

  In an LSI of a so-called 90 nm node or later, it has become difficult to improve the capability of a transistor with miniaturization and high integration. This is because the standby off-leakage current increases with the miniaturization of the gate length, and it is extremely difficult to improve the current driving capability when trying to keep the standby off-leakage current constant. Therefore, it is important to improve the transistor performance by a new approach other than miniaturization.

One such attempt is strained silicon technology. This technique applies strain (stress) to a channel in a MOS transistor. By applying stress to the channel, the band structure changes, thereby reducing the effective mass of the carrier and improving the carrier mobility.
As a technique to increase stress on the channel in the strained silicon technology, a semiconductor having a lattice constant different from Si of the substrate so as to fill the recess by forming a groove in the source / drain portion of the substrate. Some make layers epitaxially grow. By this method, stress is applied to the channel from the semiconductor layer, and the mobility of the channel is improved. As a semiconductor layer used in this method, as a combination for improving the device performance, SiGe (mixed crystal semiconductor in which Si is doped with Ge) is used for the P-type MOS transistor, and SiC (Si is used for the N-type MOS transistor). A mixed crystal semiconductor doped with C) has been proposed.

JP 2007-184427 A JP 2006-261283 A

FIG. 1 shows a specific conventional method for manufacturing a CMOS transistor including a P-type MOS transistor having a SiGe layer and an N-type MOS transistor having a SiC layer.
In this case, it is necessary to selectively form a SiGe layer and a SiC layer in each element region. For example, when the SiC layer is formed first, a mask layer is formed in the element region (P-type formation region) of the P-type MOS transistor (step S101). Since the SiGe layer and the SiC layer are epitaxially grown, a hard mask of an insulating film is generally used as a mask for suppressing the growth. Next, a SiC layer is selectively formed in the element region (N-type formation region) of the N-type MOS transistor by the epitaxial growth method using the mask layer (step S102). Next, the mask layer is removed by wet etching or the like (step S103). Next, a mask layer is formed next in the element region of the N-type MOS transistor (step S104). Next, a SiGe layer is selectively formed by epitaxial growth in the element region of the P-type MOS transistor using the mask layer (step S105). Then, the mask layer is removed by wet etching or the like (step S106).

However, in the above manufacturing process, the selective formation of the SiGe layer and the SiC layer requires two mask formation steps and two mask removal steps, and the steps become complicated, resulting in an increase in the number of steps and manufacturing costs. become.
Further, the manufacturing processes in Patent Documents 1 and 2 require at least two mask forming steps.

  This case has been made in view of the above-mentioned problems, and by selecting and forming two types of semiconductor layers with high accuracy and ease with as few steps as possible, the number of steps and the manufacturing cost can be greatly simplified. An object of the present invention is to provide a method of manufacturing a semiconductor device that can realize a semiconductor device having high element performance that is suitable for each conductivity type transistor.

  According to the method for manufacturing a semiconductor device of the present invention, a first transistor including a first gate electrode having a first sidewall insulating film formed in a first region of a semiconductor substrate, and a second transistor of the semiconductor substrate. And a second transistor having a second gate electrode having a second sidewall insulating film formed in the region, wherein the first region includes the first sidewall. Simultaneously forming a first semiconductor layer of the first conductivity type in a portion adjacent to the insulating film and in a portion adjacent to the second sidewall insulating film in the second region; and Forming a mask layer so as to cover only the first region, and using the mask layer, leaving the first semiconductor layer in the first region and the first semiconductor layer in the second region And removing the second layer using the mask layer. Only in the region, and forming a second semiconductor layer of the second conductivity type adjacent to said second sidewall insulation film.

  According to this case, two types of semiconductor layers can be selected and formed with high accuracy and ease in as few steps as possible, and the number of steps and manufacturing cost can be greatly reduced. A semiconductor device with high element performance that is compatible with a transistor can be realized.

―Basic outline of this case―
In the present case, intensive studies were made to selectively form two types of semiconductor layers (for example, a SiGe layer and a SiC layer) with high precision and ease with as few steps as possible, and the following manufacturing process was conceived. FIG. 2 is a flowchart showing a specific manufacturing method for manufacturing a CMOS transistor including a P-type MOS transistor having a SiGe layer and an N-type MOS transistor having a SiC layer in the present case.

  For example, when the SiC layer is formed first, both the element region of the P-type MOS transistor (P-type formation region) and the element region of the N-type MOS transistor (N-type formation region) are formed without forming the mask layer. For example, an SiC layer is selectively formed simultaneously by an epitaxial growth method (step S1). Next, a mask layer is formed in the element region of the N-type MOS transistor (step S2). Next, the SiC layer formed in the element region of the P-type MOS transistor is removed using the mask layer (step S3a). Subsequently, using the mask layer, a SiGe layer is selectively formed in the element region of the P-type MOS transistor, for example, by epitaxial growth (step S3b). Here, it is preferable to perform steps S3a and S3b continuously in the same processing chamber (processing chamber for epitaxial film formation). Since step S3a is performed as a pre-process of step S3b, steps S3a and S3b become step S3 which is a substantially continuous single process. In step S3a, specifically, for example, a halide gas is introduced into the processing chamber as an etching gas, and the SiC layer formed in the element region of the P-type MOS transistor is selectively removed by etching. Then, the mask layer is removed by wet etching or the like (step S4).

  As described above, in this case, when the two types of semiconductor layers (here, the SiGe layer and the SiC layer) are selectively formed, the mask formation step and the mask removal step may be performed once, and the manufacturing process is possible. Simplification is realized.

-Preferred embodiments to which this case is applied-
Hereinafter, specific embodiments in which the present invention is applied to a CMOS transistor will be described in detail with reference to the drawings.

(First embodiment)
3 and 4 are schematic cross-sectional views showing the method of manufacturing the CMOS transistor according to the first embodiment in the order of steps.
First, as shown in FIG. 3A, the gate electrode 3 is formed on the element region (N-type formation region 1a) of the N-type MOS transistor of the semiconductor substrate (silicon substrate) 1 via the gate insulating film 2, and the P-type. A gate electrode 103 is formed in each element region (P-type formation region 1b) of the MOS transistor via a gate insulating film 102. Thereafter, a silicon nitride film 4 is formed on the entire surface of the silicon substrate 1 so as to cover the gate electrodes 3 and 103.

  Specifically, first, an element isolation structure (not shown) is formed in the element isolation region of the P-type silicon substrate 1, and the N-type formation region 1a and the P-type formation region 1b are appropriately defined. Here, as the element isolation structure, a field oxide film by a so-called LOCOS method, an STI (Shallow Trench Isolation) element isolation structure in which a trench formed in the element isolation region is buried with an insulator, and the like are preferable.

Next, an N-type impurity, for example, phosphorus (P) with a dose of about 1 × 10 ¹³ / cm ^{2 to} 5 × 10 ¹³ / cm ² with an implantation energy of 100 keV to 200 keV by an ion implanter only in the P-type formation region 1b. ⁺ ) Is appropriately introduced to form the N-type well 1c.
Next, after a gate insulating film made of thermal oxidation or SiON film is formed on the entire surface of the silicon substrate 1 to a film thickness of, for example, about 1.2 nm, a polycrystalline silicon film is formed on the gate insulating film by a CVD method or the like. Deposited to about 100 nm. Then, the polycrystalline silicon film and the silicon oxide film are processed by lithography and dry etching, and the gate electrode 3 through the gate insulating film 2 is formed on the N-type forming region 1a, and the gate insulating film is formed on the P-type forming region 1b. A gate electrode 103 is formed through 102.

  Next, an insulating film, here, a silicon nitride film 4 is deposited on the entire surface of the silicon substrate 1 to a thickness of, for example, about 7 nm by the CVD method or the like so as to cover the gate electrodes 3 and 103.

Subsequently, as shown in FIG. 3B, inner layers 5A and 105A are formed on the gate electrodes 3 and 103 in the formation regions 1a and 1b. Thereafter, extension regions 6 and 106 are formed in the formation regions 1a and 1b.
Specifically, first, the entire surface of the silicon nitride film 4 is subjected to anisotropic dry etching (etch back). Thereby, the silicon nitride film 4 remains only on both side surfaces of the gate electrodes 3 and 103, and the inner layers 5A and 105A are formed.

Next, after forming a resist mask (not shown) covering the formation region 1a, the gate electrode 103 and the inner layer 105A are used as a mask, and a P-type impurity such as boron (B ⁺ ) is dosed to the P-type formation region 1b at a dose of 1 ×. Ion implantation is performed at 10 ¹⁵ / cm ² and an acceleration energy of 0.5 keV. Thereby, the extension region 106 is formed.
Next, after removing the resist mask covering the N-type formation region 1a by ashing or the like, a resist mask (not shown) covering the P-type formation region 1b is formed, and the gate electrode 3 and the inner layer 5A are used as a mask. N-type impurities such as arsenic (As ⁺ ) are ion-implanted into the mold formation region 1a at a dose of 1 × 10 ¹⁵ / cm ² and an acceleration energy of 3 keV. Thereby, the extension region 6 is formed.
Then, the resist mask covering the P-type forming region 1b is removed by ashing or the like.

  Thereafter, the silicon substrate 1 is annealed, for example, at 1200 ° C. in a short time of less than 1 minute to diffuse the impurities in the extension regions 6 and 106. This annealing process may be omitted.

Subsequently, as shown in FIG. 3C, outer layers 5B and 105B covering the inner layers 5A and 105A are formed. Thereafter, source / drain regions 7 and 107 are formed in the formation regions 1a and 1b.
Specifically, first, an insulating film, here a silicon oxide film, is deposited to a thickness of, for example, about 5 nm by CVD or the like so as to cover the gate electrodes 3 and 103 and the inner layers 5A and 105A. Then, a silicon nitride film is deposited to a thickness of, for example, about 30 nm by a CVD method or the like.
Next, the entire surface of the laminated structure of the silicon nitride film and the silicon oxide film is subjected to anisotropic dry etching (etch back). Thus, the silicon oxide film remains so as to cover the inner layers 5A and 105A, the first layers 5a and 105a made of the silicon oxide film are formed, and the silicon nitride film covers only the first layers 5a and 105a. The second layers 5b and 105b are formed.

The outer layers 5B and 105B are formed by the first layers 5a and 105a and the second layers 5b and 105b.
Then, the sidewall insulating film 5 covering both side surfaces of the gate electrode 3 with the inner layer 5A and the outer layer 5B is formed, and the sidewall insulating film 105 covering both side surfaces of the gate electrode 103 with the inner layer 105A and the outer layer 105B, respectively. Is done.

Next, after forming a resist mask (not shown) covering the N-type formation region 1a, a P-type impurity such as boron (B ⁺ ) is applied to the P-type formation region 1b using the gate electrode 103 and the sidewall insulating film 105 as a mask. Ions are implanted at a dose of 3 × 10 ¹³ / cm ² and an acceleration energy of 10 keV. As a result, a source / drain region 107 partially overlapping with the extension region 106 is formed.
Next, after removing the resist mask covering the N-type formation region 1a by ashing or the like, a resist mask (not shown) covering the P-type formation region 1b is formed, and the gate electrode 3 and the sidewall insulating film 5 are used as a mask. Then, an N-type impurity such as phosphorus (P ⁺ ) is ion-implanted into the N-type formation region 1a at a dose of 5 × 10 ¹³ / cm ² and an acceleration energy of 15 keV. As a result, the source / drain region 7 partially overlapping with the extension region 6 is formed.
Then, the resist mask covering the P-type forming region 1b is removed by ashing or the like.

Subsequently, as shown in FIG. 3D, SiC layers 8 and 108 are simultaneously formed on the source / drain regions 7 and 107.
Specifically, an SiC layer 8 containing about 1 × 10 ²⁰ / cm ^{3 of} N-type impurities, here phosphorus (P) and about 1% of C, is formed on the source / drain regions 7 and 107 by epitaxial growth. 108 are formed simultaneously.

Subsequently, as shown in FIG. 4A, a mask layer 9 covering only the N-type formation region 1a is formed.
Specifically, first, an insulating film on the entire surface of the silicon substrate 1, here, an insulating film having the same etching rate as that of the second layer 5b of the outer layer 5B of the sidewall insulating film 5, for example, the same material as the second layer 5b. The silicon nitride film is deposited to a thickness of, for example, about 30 nm by a CVD method or the like. For the mask layer 9, a material having an etching rate different from that of the second layer 5b of the outer layer 5B of the sidewall insulating film 5 may be selected. In this case, when the mask layer 9 is removed, the outer layer 5B remains. In the present embodiment, as an example, a case where the mask layer 9 and the outer layer 5B have the same etch rate will be described.
Then, the silicon nitride film is processed by lithography and dry etching to form a mask layer 9 that covers the N-type formation region 1a and exposes the P-type formation region 1b.

Subsequently, as shown in FIG. 4B, the SiC layer 108 exposed in the P-type formation region 1 b is removed using the mask layer 9.
Specifically, as a pretreatment of the epitaxial growth step of FIG. 4C described later, a halogenated gas, here, a mixed gas of Cl ₂ gas and H ₂ gas is introduced into the processing chamber for epitaxial growth as an etching gas, Etching process. Thereby, SiC layer 108 exposed from mask layer 9, that is, exposed in P-type formation region 1b is etched away.

Subsequently, as shown in FIG. 4C, a SiGe layer 109 is formed by an epitaxial growth method.
Specifically, without removing the silicon substrate 1 from the processing chamber used in the etching process of FIG. 4B, the processing chamber continues as a process continuous with the etching process of FIG. 4B in the processing chamber. Epitaxial growth of SiGe is performed. At this time, a SiGe layer 109 containing about 1 × 10 20 / cm ^{3 of} P-type impurities, here boron (B) and about 20% Ge, is formed on the source / drain regions 107.

Subsequently, as shown in FIG. 4D, the mask layer 9 is removed.
Specifically, the silicon substrate 1 is wet etched using a silicon nitride film having a high etching rate, for example, phosphoric acid as an etchant. At this time, since the mask layer 9 and the second layers 5b and 105b of the outer layers 5B and 105B are made of the same silicon nitride film as the mask layer 9, the second layers 5b and 105b are etched together with the mask layer 9. Removed. Under the second layers 5b and 105b, the first layers 5a and 105a made of a silicon oxide film whose etching rate with respect to phosphoric acid is lower than that of the silicon nitride film are present, so that the first layers 5a and 105a are exposed. Then, the wet etching is finished.

  Thereafter, the silicon substrate 1 is annealed at 1200 ° C. for less than 1 minute, for example, to diffuse the impurities in the source / drain regions 7 and 107.

  Thereafter, a silicide metal such as Ni, Ti, Co or the like is deposited on the entire surface by a sputtering method or the like and heat-treated. Thereby, each upper layer part of the gate electrodes 3 and 103, the SiC layer 8 and the SiGe layer 109 reacts with the silicide metal, and a silicide layer (not shown) is formed. Unreacted silicide metal is removed. Then, through a process of forming an interlayer insulating film, contact plug, wiring layer, etc., a CMOS transistor having an N-type MOS transistor 10a in the N-type formation region 1a and a P-type MOS transistor 10b in the P-type formation region 1b is completed. Let

  The completed CMOS transistor has a configuration in which the SiC layer 8 and the SiGe layer 109 are formed on the source / drain regions 7 and 107, respectively. SiC layer 8 and SiGe layer 109 are electrically insulated from gate electrodes 3 and 103 through sidewall insulating films 5 and 105. In this case, it is possible to increase the concentration of each impurity (phosphorus (P) and boron (B)) in the SiC layer 8 and the SiGe layer 109. With this configuration, the parasitic resistance of the source / drain regions 7 and 107 is reduced. Further, in this configuration, since it is not necessary to introduce impurities at a high concentration in the depth direction of the silicon substrate 1, the short channel effect can be suppressed.

  As described above, according to the present embodiment, the SiC layer 8 and the SiGe layer 109, which are the two types of semiconductor layers, are selectively formed with high precision and ease with as few steps as possible. As a result, although the process is simplified and the number of processes and the manufacturing cost are greatly reduced, a CMOS transistor having high device performance suitable for each of the conductivity type MOS transistors 10a and 10b is realized.

  It should be noted that without forming the source / drain regions 7 and 107 in the step of FIG. 3C, the mask layer 9 and the first layers 5b and 105b are removed by etching in the step of FIG. The source / drain regions 7 and 107 may be formed by the same process.

(Modification)
Here, a modification of the first embodiment will be described. In this modification, a CMOS transistor is manufactured in substantially the same manner as in the first embodiment, but differs from the first embodiment in that the material of the mask layer is different.
FIG. 5 is a schematic cross-sectional view showing only main steps in the method of manufacturing a CMOS transistor according to a modification of the first embodiment.

In this example, first, the steps of FIGS. 3A to 3D are executed as in the first embodiment.
Subsequently, instead of forming the mask layer 9 with a silicon nitride film in the step of FIG. 4A, an insulating film having an etching rate different from that of the second layer 5b of the outer layer 5B of the sidewall insulating film 5, for example, silicon oxide A mask layer is formed from the film.
In this case, for example, as shown in FIG. 5A, a silicon oxide film is deposited on the entire surface of the silicon substrate 1 to a film thickness of, for example, about 30 nm by the CVD method or the like. Thereafter, the silicon oxide film is processed by lithography and dry etching to form a mask layer 11 that covers the N-type formation region 1a and exposes the P-type formation region 1b.

Subsequently, similarly to the first embodiment, the steps shown in FIGS. 4B and 4C are performed using the mask layer 11.
Then, as a process corresponding to FIG. 4D, for example, as shown in FIG. 5B, the silicon substrate 1 is wet etched using a silicon oxide film having a high etching rate, for example, hydrofluoric acid as an etchant. . At this time, since the mask layer 11 is made of a silicon oxide film, the mask layer 11 is removed by etching. On the other hand, the second layers 5b and 105b are made of a silicon nitride film whose etching rate for hydrofluoric acid is lower than that of the silicon oxide film. Therefore, the first layers 5a and 105a covered with the second layers 5b and 105b together with the second layers 5b and 105b are not etched, and the sidewall insulating films 5 and 105 are almost left. Wet etching is finished.

  According to this example, in addition to the various effects exhibited by the first embodiment, electrical insulation between the SiC layer 8 and the gate electrode 3 and the SiGe layer 109 and the gate are achieved by the sidewall insulating films 5 and 105. Electrical insulation between the electrodes 103 can be reliably ensured. Therefore, when the silicide layer is formed on the SiC layer 8 and the SiGe layer 109, a short circuit between the gate electrodes 3 and 103 and the silicide layer is surely prevented.

(Second Embodiment)
In the present embodiment, a CMOS transistor is manufactured in substantially the same manner as in the first embodiment, but differs from the first embodiment in that a groove is appropriately formed at the formation position of the SiGe layer in the P-type formation region. In addition, the same code | symbol is attached | subjected about the structural member etc. similar to 1st Embodiment.
6 and 7 are schematic cross-sectional views showing the method of manufacturing the CMOS transistor according to the second embodiment in the order of steps.

First, as shown in FIGS. 6A to 6D and FIG. 7A, the steps of FIGS. 3A to 3D and 4A are executed as in the first embodiment. .
Subsequently, as shown in FIG. 7B, the mask layer 9 is used to remove the SiC layer 108 exposed in the P-type formation region 1b, and a groove (recess) 121 is formed at the position where the source / drain region 107 is formed. Form.

Specifically, the SiC layer 108 exposed from the mask layer 9, that is, exposed in the P-type formation region 1b is removed by dry etching. Subsequently, the dry etching is continuously performed, and a groove 121 is formed at the formation position of the source / drain region 107 in the P-type formation region 1b by overetching.
Here, the trench 121 is formed in the source / drain region 107 to a depth of about 30 nm, for example. The trench 121 does not protrude from the source / drain region 107 but has a depth corresponding to the optimum thickness of the SiGe layer 109 of the P-type MOS transistor described later so that the source / drain region 107 remains at the edge portion of the trench 121. Formed.

Subsequently, as shown in FIG. 7C, a SiGe layer 109 is formed by an epitaxial growth method.
Specifically, SiGe is epitaxially grown to a thickness slightly thicker than the groove 121, for example, about 50 nm so as to fill the groove 121. At this time, a SiGe layer 109 doped with a P-type impurity, here boron (B), is formed in the groove 121 having the source / drain regions 107 so as to surround the edge portion.

  Here, in principle, an interface state is formed at the heterointerface between the SiGe layer 109 and the silicon substrate 1. SiGe has a smaller band gap (narrower) than Si. Therefore, when the SiGe layer 109 is in contact with the silicon substrate 1 in the groove 121, a lot of junction leakage occurs. Therefore, as described above, the trench 121 is formed so that the source / drain region 107 remains at the edge portion of the trench 121, and the SiGe layer 109 is buried, whereby the P-type Si of the SiGe layer 109 and the N of the silicon substrate 1 are filled. A P / N junction is formed with the N-type Si in the mold well 1c. Thereby, junction leakage between the SiGe layer 109 and the N-type well 1c of the silicon substrate 1 is significantly reduced. Specifically, it is considered that by forming a P / N junction between the SiGe layer 109 and the groove 121 of the silicon substrate 1, junction leakage is reduced to the same extent as that of a normal bulk type MOS transistor.

Subsequently, similarly to FIG. 4D of the first embodiment, the mask layer 9 is removed as shown in FIG.
Thereafter, for example, the silicon substrate 1 is annealed at 1200 ° C. for a short time of less than 1 minute to diffuse the impurities in the source / drain regions 7 and 107.
Thereafter, similarly to the first embodiment, a silicide layer (not shown) is formed in each upper layer portion of the gate electrodes 3, 103, the SiC layer 8 and the SiGe layer 109. Unreacted silicide metal is removed. Then, through a process of forming an interlayer insulating film, contact plug, wiring layer, etc., a CMOS transistor having an N-type MOS transistor 10a in the N-type formation region 1a and a P-type MOS transistor 10b in the P-type formation region 1b is completed. Let

The completed CMOS transistor has a configuration in which the SiC layer 8 is formed on the source / drain region 7 and the SiGe layer 109 is formed in the groove 121 formed in the source / drain region 107. In this case, it is possible to increase the concentration of each impurity (phosphorus (P) and boron (B)) in the SiC layer 8 and the SiGe layer 109. With this configuration, the parasitic resistance of the source / drain regions 7 and 107 is reduced. Further, in this configuration, since it is not necessary to introduce impurities at a high concentration in the depth direction of the silicon substrate 1, the short channel effect can be suppressed.
Furthermore, by forming the trench 121 to a desired depth within a range that does not protrude from the source / drain region 107, the SiGe layer 109 can be appropriately formed to an optimum thickness, and the short channel effect can be sufficiently suppressed. Become.

  As described above, according to the present embodiment, the SiC layer 8 and the SiGe layer 109, which are the two types of semiconductor layers, are selectively formed with high precision and ease with as few steps as possible. As a result, although the process is simplified and the number of processes and the manufacturing cost are greatly reduced, a CMOS transistor having high device performance suitable for each of the conductivity type MOS transistors 10a and 10b is realized.

  Similarly to the first embodiment, the source / drain regions 7 and 107 are not formed in the step of FIG. 6C, and the mask layer 9 and the second layer 5b, After removing 105b by etching, the source / drain regions 7 and 107 may be formed by the same process as described above.

  Similarly to the modification of the first embodiment, instead of forming the mask layer 9 with a silicon nitride film in the step of FIG. 7A, the second layer 5b of the outer layer 5B of the sidewall insulating film 5 is used. It is also preferable to form the mask layer with an insulating film having a different etching rate, such as a silicon oxide film.

(Third embodiment)
In this embodiment, a CMOS transistor is manufactured in substantially the same manner as in the first embodiment, except that grooves are appropriately formed in the formation position of the SiC layer in the N-type formation region and the formation position of the SiGe layer in the P-type formation region, respectively. This is different from the first embodiment. In addition, the same code | symbol is attached | subjected about the structural member etc. similar to 1st Embodiment.
8 and 9 are schematic cross-sectional views showing the method of manufacturing the CMOS transistor according to the third embodiment in the order of steps.

First, as shown in FIGS. 8A and 8B, the steps of FIGS. 3A and 3B are executed in the same manner as in the first embodiment.
Subsequently, as shown in FIG. 8C, outer layers 5B and 105B covering the inner layers 5A and 105A are formed. Thereafter, source / drain regions 7 and 107 are formed in the formation regions 1a and 1b, and grooves (recesses) 21 and 122 are formed at the positions where the source / drain regions 7 and 107 are formed.
Specifically, first, the inner layers 5A and 105A and the outer layers 5B and 105B are sequentially formed as in the step of FIG. 3C of the first embodiment. Sidewall insulating films 5 covering both side surfaces of the gate electrode 3 with the inner layers 5A and 105A, and sidewall insulating films 105 covering both side surfaces of the gate electrode 103 with the inner layer 105A and the outer layer 105B are formed.
Next, as in the step of FIG. 3C, source / drain regions 7 and 107 that partially overlap the extension regions 6 and 106 are formed.

Next, by using the gate electrodes 3 and 103 and the sidewall insulating films 5 and 105 as a mask, the trench 21 is formed at the formation position of the source / drain region 7 in the N-type formation region 1a and the P-type formation region 1b by dry etching. The trench 122 is formed simultaneously at the position where the source / drain region 107 is formed.
Here, the trenches 21 and 122 are formed in the source / drain regions 7 and 107 to a depth of about 20 nm, for example. The trenches 21 and 122 are formed so that the source / drain regions 7 and 107 remain at the respective edge portions of the trenches 21 and 122 without protruding from the source / drain regions 7 and 107. Here, grooves 21 and 122 are formed to a depth corresponding to the optimum thickness of SiC layer 8 of an N-type MOS transistor described later.

Subsequently, as shown in FIG. 8D, SiC layers 8 and 108 are simultaneously formed by an epitaxial growth method.
Specifically, SiGe is epitaxially grown to a thickness of, for example, about (30) nm, which is slightly thicker than the grooves 21 and 122 so as to fill the grooves 21 and 122. At this time, SiC layers 8 and 108 doped with N-type impurities, here phosphorus (P), are simultaneously formed in grooves 21 and 122 having source / drain regions 7 and 107 at respective edge portions.

  Subsequently, similarly to FIG. 4A of the first embodiment, as shown in FIG. 9A, a mask layer 9 covering only the N-type formation region 1a is formed.

Subsequently, as shown in FIG. 9B, the SiC layer 108 exposed in the P-type formation region 1 b is removed using the mask layer 9.
Specifically, the SiC layer 108 exposed from the mask layer 9, that is, exposed in the P-type formation region 1b is removed by dry etching. Subsequently, the dry etching is continuously performed, and the groove 122 of the P-type formation region 1b is further deeply etched by overetching.
Here, the trench 122 has a depth of, for example, about 40 nm in the source / drain region 107. The overetching is performed within a range that does not protrude from the source / drain region 107. As a result, the trench 122 is formed to a depth corresponding to the optimum thickness of the SiGe layer 109 of the P-type MOS transistor described later so that the source / drain region 107 remains at the edge portion of the trench 121.

Subsequently, as shown in FIG. 9C, a SiGe layer 109 is formed by an epitaxial growth method.
More specifically, SiGe is epitaxially grown to a thickness of, for example, about 60 nm that is slightly thicker than the groove 122 so as to fill the groove 122. At this time, a SiGe layer 109 doped with a P-type impurity, here boron (B), is formed in the groove 122 having the source / drain region 107 at the edge portion.

  Here, in principle, interface states are formed at the heterointerfaces between the SiC layer 8 and the SiGe layer 109 and the silicon substrate 1. SiC and SiGe have a smaller (narrower) band gap than Si. Therefore, when the SiC layer 8 is in contact with the silicon substrate 1 in the groove 21 and the SiGe layer 109 is in contact with the silicon substrate 1 in the groove 122, many junction leaks are generated. Therefore, as described above, the groove 21 is formed so that the source / drain region 7 remains in the edge portion of the groove 21, and the groove 122 is formed so that the source / drain region 107 remains in the edge portion of the groove 122. The layer 8 and the SiGe layer 109 are embedded. As a result, the P / N junction is formed by the N-type Si of the SiC layer 8 and the P-type Si of the silicon substrate 1, and the P / N junction is formed by the P-type Si of the SiGe layer 109 and the N-type Si of the N-type well 1c of the silicon substrate 1. N junctions are respectively formed. In this case, junction leakage between the SiC layer 8 and the silicon substrate 1 and junction leakage between the SiGe layer 109 and the N-type well 1c of the silicon substrate 1 are significantly reduced. Specifically, by forming P / N junctions between the SiC layer 8 and the groove 21 of the silicon substrate 1 and between the SiGe layer 109 and the groove 122 of the silicon substrate 1, a normal bulk type MOS is formed. It is considered that junction leakage is reduced to the same extent as a transistor.

Subsequently, similarly to FIG. 4D of the first embodiment, the mask layer 9 is removed as shown in FIG.
Thereafter, the silicon substrate 1 is annealed at 1200 ° C. for a short time of less than 1 minute, for example, so that the impurities in the source / drain regions 7 and 107 are diffused.
Thereafter, similarly to the first embodiment, a silicide layer (not shown) is formed in each upper layer portion of the gate electrodes 3, 103, the SiC layer 8 and the SiGe layer 109. Unreacted silicide metal is removed. Then, through a process of forming an interlayer insulating film, contact plug, wiring layer, etc., a CMOS transistor having an N-type MOS transistor 10a in the N-type formation region 1a and a P-type MOS transistor 10b in the P-type formation region 1b is completed. Let

The completed CMOS transistor has a configuration in which the SiC layer 8 is formed on the source / drain region 7 and the SiGe layer 109 is formed in the groove 121 formed in the source / drain region 107. In this case, it is possible to increase the concentration of each impurity (phosphorus (P) and boron (B)) in the SiC layer 8 and the SiGe layer 109. With this configuration, the parasitic resistance of the source / drain regions 7 and 107 is reduced. Further, in this configuration, since it is not necessary to introduce impurities at a high concentration in the depth direction of the silicon substrate 1, the short channel effect can be suppressed.
Further, in the present embodiment, a desired depth (for example, the groove 21, the groove 21, and the like is independently within a range where the groove 21 does not protrude from the source / drain region 7 and the groove 122 does not protrude from the source / drain region 107. 122 can be formed at different optimum depths. As a result, the SiC layer 8 and the SiGe layer 109 can be appropriately formed to have optimum thicknesses, respectively, and the short channel effect can be sufficiently suppressed.

  As described above, according to the present embodiment, the SiC layer 8 and the SiGe layer 109, which are the two types of semiconductor layers, are selectively formed with high precision and ease with as few steps as possible. As a result, although the process is simplified and the number of processes and the manufacturing cost are greatly reduced, a CMOS transistor having high device performance suitable for each of the conductivity type MOS transistors 10a and 10b is realized.

  Similarly to the first embodiment, without forming the source / drain regions 7 and 107 in the step of FIG. 8C, the mask layer 9 and the second layer 5b in the step of FIG. After removing 105b by etching, the source / drain regions 7 and 107 may be formed by the same process as described above.

  Similarly to the modification of the first embodiment, instead of forming the mask layer 9 with a silicon nitride film in the step of FIG. 9A, the second layer 5b of the outer layer 5B of the sidewall insulating film 5 is used. It is also preferable to form the mask layer with an insulating film having a different etching rate, such as a silicon oxide film.

(Fourth embodiment)
In this embodiment, a CMOS transistor is manufactured in substantially the same manner as in the first embodiment, but the formation position of the SiC layer in the N-type formation region and the formation position of the SiGe layer in the P-type formation region are slightly extended. This is different from the first embodiment. In addition, the same code | symbol is attached | subjected about the structural member etc. similar to 1st Embodiment.
10 to 12 are schematic cross-sectional views showing the method of manufacturing the CMOS transistor according to the fourth embodiment in the order of steps.

First, as shown in FIGS. 10A and 10B, the steps of FIGS. 3A and 3B are executed as in the first embodiment.
Subsequently, as shown in FIG. 10C, SiC layers 8 and 108 are simultaneously formed on both side portions of the inner layers 5A and 105A in the formation regions 1a and 1b.
Specifically, SiC layers 8 and 108 doped with an N-type impurity, here phosphorus (P), are simultaneously formed on each of the both side portions by an epitaxial growth method.

Subsequently, as shown in FIG. 10D, outer layers 5B and 105B covering the inner layers 5A and 105A are formed. Thereafter, source / drain regions 7 and 107 are formed in the formation regions 1a and 1b.
Specifically, first, an insulating film, here a silicon oxide film is deposited to a thickness of, for example, about 5 nm by CVD or the like so as to cover the gate electrodes 3 and 103 and the inner layers 5A and 105A, and then a silicon nitride film is formed by CVD. For example, the film is deposited to a thickness of about 30 nm by a method or the like.
Next, anisotropic dry etching (etchback) is performed on the entire surface of the laminated structure of the silicon oxide film and the silicon nitride film. As a result, the silicon oxide film covers the upper portions of the side surfaces of the inner layers 5A and 105A (the portions exposed from the SiC layers 8 and 108), remains on the SiC layers 8 and 108, and is a first layer 5a made of a silicon oxide film. , 105a are formed. Further, the silicon nitride film remains so as to cover only the first layers 5a and 105a, and the second layers 5b and 105b are formed.

The outer layers 5B and 105B are formed by the first layers 5a and 105a and the second layers 5b and 105b.
Then, the sidewall insulating film 5 covering both side surfaces of the gate electrode 3 with the inner layer 5A and the outer layer 5B is formed, and the sidewall insulating film 105 covering both side surfaces of the gate electrode 103 with the inner layer 105A and the outer layer 105B, respectively. Is done. Here, the sidewall insulating films 5 and 105 cover the entire surfaces of both sides of the gate electrodes 3 and 103 with the inner layers 5A and 105A, and cover only the upper portions of the both sides of the inner layers 5A and 105A with the outer layers 5B and 105B. It is made into a shape.

Next, after forming a resist mask (not shown) covering the N-type formation region 1a, a P-type impurity such as boron is added to the P-type formation region 1b under the SiC layer 108 using the gate electrode 103 and the sidewall insulating film 105 as a mask. (B ⁺ ) is ion-implanted at a dose of 3 × 10 ¹³ / cm ² and an acceleration energy of 10 keV so as to pass through the SiC layer 108. As a result, a source / drain region 107 partially overlapping with the extension region 106 is formed.
Next, after removing the resist mask covering the N-type formation region 1a by ashing or the like, a resist mask (not shown) covering the P-type formation region 1b is formed, and the gate electrode 3 and the sidewall insulating film 5 are used as a mask. Then, an N-type impurity such as phosphorus (P ⁺ ) is ion-implanted into the N-type formation region 1 a under the SiC layer 8 at a dose of 5 × 10 ¹³ / cm ² and an acceleration energy of 15 keV so as to pass through the SiC layer 8. As a result, the source / drain region 7 partially overlapping with the extension region 6 is formed.
Then, the resist mask covering the P-type forming region 1b is removed by ashing or the like.

  Subsequently, similarly to FIG. 4A of the first embodiment, as shown in FIG. 11A, a mask layer 9 covering only the N-type formation region 1a is formed.

Subsequently, as shown in FIG. 11 (b), the portion exposed in the P-type formation region 1 b of the SiC layer 108 is first removed using the mask layer 9.
Specifically, the exposed portion of the SiC layer 108 is removed by reactive ion etching (RIE) using the mask layer 9 and the gate electrode 103 and the sidewall insulating film 105 in the P-type formation region 1b as a mask.

Subsequently, as shown in FIG. 11C, the remaining portion of the SiC layer 108 is removed using the mask layer 9.
Specifically, as a pretreatment of the epitaxial growth step of FIG. 11D described later, a halogenated gas, here, a mixed gas of Cl ₂ gas and H ₂ gas is introduced as an etching gas into a processing chamber for epitaxial growth, Etching process. Thereby, the remaining portion of SiC layer 108, that is, the portion remaining under outer layer 105B of SiC layer 108 is etched away. At this time, all of the SiC layer 108 is removed.

Subsequently, as shown in FIG. 11D, a SiGe layer 109 is formed by an epitaxial growth method.
Specifically, without removing the silicon substrate 1 from the processing chamber used in the etching process of FIG. 11C, epitaxial growth of SiGe is performed in the processing chamber as a process continuous with the etching process of FIG. 11C. . At this time, a SiGe layer 109 doped with a P-type impurity, here boron (B), is formed so as to fill the gap 123 formed below the inner layer 105A and below the outer layer 105B on the source / drain region 107. The

Subsequently, as in FIG. 4D of the first embodiment, the mask layer 9 is removed as shown in FIG.
Thereafter, for example, the silicon substrate 1 is annealed at 1200 ° C. for less than 1 minute to diffuse the impurities in the source / drain regions 7 and 107.
Thereafter, similarly to the first embodiment, a silicide layer (not shown) is formed in each upper layer portion of the gate electrodes 3, 103, the SiC layer 8 and the SiGe layer 109. Unreacted silicide metal is removed. Then, through a process of forming an interlayer insulating film, contact plug, wiring layer, etc., a CMOS transistor having an N-type MOS transistor 10a in the N-type formation region 1a and a P-type MOS transistor 10b in the P-type formation region 1b is completed. Let

The completed CMOS transistor has a configuration in which the SiC layer 8 is formed on the source / drain region 7 and the SiGe layer 109 is formed on the source / drain region 107. In this case, it is possible to increase the concentration of each impurity (phosphorus (P) and boron (B)) in the SiC layer 8 and the SiGe layer 109. With this configuration, the parasitic resistance of the source / drain regions 7 and 107 is reduced. Further, in this configuration, since it is not necessary to introduce impurities at a high concentration in the depth direction of the silicon substrate 1, the short channel effect can be suppressed.
Further, since the SiC layer 8 and the SiGe layer 109 are extended to the inner layers 5A and 105A of the sidewall insulating films 5 and 105, respectively (in contact with and adjacent to the inner layers 5A and 105A), the parasitic resistance is further reduced. Is realized.

  As described above, according to the present embodiment, the SiC layer 8 and the SiGe layer 109, which are the two types of semiconductor layers, are selectively formed with high precision and ease with as few steps as possible. As a result, although the process is simplified and the number of processes and the manufacturing cost are greatly reduced, a CMOS transistor having high device performance suitable for each of the conductivity type MOS transistors 10a and 10b is realized.

  The steps similar to the above are performed after the mask layer 9 and the second layers 5b and 105b are removed by etching in the step of FIG. 12 without forming the source / drain regions 7 and 107 in the step of FIG. 10D. Thus, the source / drain regions 7 and 107 may be formed.

  Similarly to the modification of the first embodiment, instead of forming the mask layer 9 with a silicon nitride film in the step of FIG. 11A, the second layer 5b of the outer layer 5B of the sidewall insulating film 5 is used. It is also preferable to form the mask layer with an insulating film having a different etching rate, such as a silicon oxide film.

(Fifth embodiment)
In the present embodiment, a CMOS transistor is manufactured in substantially the same manner as in the fourth embodiment, but differs from the fourth embodiment in that a groove is appropriately formed at the formation position of the SiGe layer in the P-type formation region. In addition, the same code | symbol is attached | subjected about the structural member etc. similar to 4th Embodiment.
13 and 14 are schematic cross-sectional views showing the method of manufacturing the CMOS transistor according to the fifth embodiment in the order of steps.

First, as shown in FIGS. 13A to 13D and FIG. 14A, the steps of FIGS. 10A to 10D and FIG. 11A are executed as in the fourth embodiment. .
Subsequently, as shown in FIG. 14B, the mask layer 9 is used to remove the SiC layer 108 existing in the P-type formation region 1b, and grooves (recesses) 124 are formed at the positions where the source / drain regions 107 are formed. Form.

Specifically, the SiC layer 108 exposed from the mask layer 9, that is, existing in the P-type formation region 1 b is removed by chemical dry etching. Subsequently, the dry etching is continuously performed, and etching is performed to the formation position of the source / drain region 107 in the P-type formation region 1b, here, the portion below the outer layer 105B by overetching, thereby forming the groove 124.
Here, the trench 124 is formed in the source / drain region 107 to a depth of, for example, about (30) nm. The trench 124 does not protrude from the source / drain region 107, and the depth corresponding to the optimum thickness of the SiGe layer 109 of the P-type MOS transistor described later so that the source / drain region 107 remains at the edge portion of the trench 124. Formed.

Subsequently, as shown in FIG. 14C, a SiGe layer 109 is formed by an epitaxial growth method.
Specifically, SiGe is epitaxially grown to a thickness of about (50) nm, for example, slightly thicker than the groove 124 so as to fill the groove 124. At this time, in the groove 124 having the source / drain regions 107 so as to surround the edge portion, a P-type impurity, boron in this case, is buried so as to fill the gap 124 formed below the inner layer 105A and under the outer layer 105B. A SiGe layer 109 doped with (B) is formed.

  Here, in principle, an interface state is formed at the heterointerface between the SiGe layer 109 and the silicon substrate 1. SiGe has a smaller band gap (narrower) than Si. Therefore, when the SiGe layer 109 is in contact with the silicon substrate 1 in the groove 124, a lot of junction leakage occurs. Therefore, as described above, the trench 124 is formed so that the source / drain region 107 remains at the edge portion of the trench 124, and the SiGe layer 109 is buried, whereby the P-type Si of the SiGe layer 109 and the N of the silicon substrate 1 are filled. A P / N junction is formed with the N-type Si in the mold well 1c. Thereby, junction leakage between the SiGe layer 109 and the N-type well 1c of the silicon substrate 1 is significantly reduced. Specifically, it is considered that by forming a P / N junction between the SiGe layer 109 and the groove 124 of the silicon substrate 1, junction leakage is reduced to the same extent as that of a normal bulk type MOS transistor.

Subsequently, similarly to FIG. 4D of the first embodiment, the mask layer 9 is removed as shown in FIG.
Thereafter, for example, the silicon substrate 1 is annealed at 1200 ° C. for less than 1 minute to diffuse the impurities in the source / drain regions 7 and 107.
Thereafter, similarly to the first embodiment, a silicide layer (not shown) is formed in each upper layer portion of the gate electrodes 3, 103, the SiC layer 8 and the SiGe layer 109. Unreacted silicide metal is removed. Then, through a process of forming an interlayer insulating film, contact plug, wiring layer, etc., a CMOS transistor having an N-type MOS transistor 10a in the N-type formation region 1a and a P-type MOS transistor 10b in the P-type formation region 1b is completed. Let

The completed CMOS transistor has a configuration in which the SiC layer 8 is formed on the source / drain region 7 and the SiGe layer 109 is formed in the groove 124 formed in the source / drain region 107. In this case, it is possible to increase the concentration of each impurity (phosphorus (P) and boron (B)) in the SiC layer 8 and the SiGe layer 109. With this configuration, the parasitic resistance of the source / drain regions 7 and 107 is reduced. Further, in this configuration, since it is not necessary to introduce impurities at a high concentration in the depth direction of the silicon substrate 1, the short channel effect can be suppressed.
Further, by forming the groove 124 to a desired depth within a range that does not protrude from the source / drain region 107, it is possible to appropriately form the SiGe layer 109 to an optimum thickness and sufficiently suppress the short channel effect. Become.
Further, since the SiC layer 8 and the SiGe layer 109 are extended to the inner layers 5A and 105A of the sidewall insulating films 5 and 105, respectively (in contact with and adjacent to the inner layers 5A and 105A), the parasitic resistance is further reduced. Is realized.

  As described above, according to the present embodiment, the SiC layer 8 and the SiGe layer 109, which are the two types of semiconductor layers, are selectively formed with high precision and ease with as few steps as possible. As a result, although the process is simplified and the number of processes and the manufacturing cost are greatly reduced, a CMOS transistor having high device performance suitable for each of the conductivity type MOS transistors 10a and 10b is realized.

  As in the fourth embodiment, the source / drain regions 7 and 107 are not formed in the step of FIG. 13D, and the mask layer 9 and the second layer 5b, After removing 105b by etching, the source / drain regions 7 and 107 may be formed by the same process as described above.

  Similarly to the modification of the first embodiment, instead of forming the mask layer 9 with a silicon nitride film in the step of FIG. 14A, the second layer 5b of the outer layer 5B of the sidewall insulating film 5 is used. It is also preferable to form the mask layer with an insulating film having a different etching rate, such as a silicon oxide film.

  Hereinafter, various aspects of the present case will be collectively described as additional notes.

(Additional remark 1) The 1st transistor provided with the 1st gate electrode which has the 1st side wall insulating film formed in the 1st field of a semiconductor substrate,
And a second transistor provided with a second gate electrode having a second sidewall insulating film formed in the second region of the semiconductor substrate, comprising:
The first region of the first conductivity type is located in the first region adjacent to the first sidewall insulating film, and the second region is adjacent to the second sidewall insulating film. A step of simultaneously forming a semiconductor layer;
Forming a mask layer so as to cover only the first region;
Etching the first semiconductor layer in the second region, leaving the first semiconductor layer in the first region, using the mask layer;
Forming a second semiconductor layer of the second conductivity type so as to be adjacent to the second sidewall insulating film only in the second region using the mask layer. A method for manufacturing a semiconductor device.

(Supplementary note 2) The first and second sidewall insulating films are each laminated so as to cover the first layer having a different etching selectivity from the mask layer and the first layer, and the mask layer. And a second layer having an equivalent etching selectivity,
The semiconductor according to claim 1, further comprising a step of etching and removing the second layer in the first and second regions together with the mask layer after the step of forming the second semiconductor layer. Device manufacturing method.

(Supplementary note 3) The first and second sidewall insulating films are laminated so as to cover the first layer having the same etching selectivity as that of the mask layer and the first layer, respectively. And a second layer having a different etching selectivity,
2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of etching away the mask layer leaving the second layer after the step of forming the second semiconductor layer.

(Supplementary Note 4) Before the step of simultaneously forming the first semiconductor layer, a first portion of the semiconductor substrate adjacent to the first sidewall insulating film is formed in both the first and second regions. Further comprising the step of forming a second groove in a portion of the semiconductor substrate adjacent to the second sidewall insulating film,
In the step of simultaneously forming the first semiconductor layer, the first region is filled with the first groove, and the second region is filled with the second groove. Forming a first semiconductor layer of one conductivity type simultaneously;
4. The semiconductor device according to claim 1, wherein in the step of forming the second semiconductor layer, the second semiconductor layer is formed so as to fill the second groove. Production method.

  (Supplementary Note 5) In the step of etching and removing the first semiconductor layer in the second region, the first semiconductor layer in the second region is removed by etching and the second groove is formed to a predetermined depth. The method for manufacturing a semiconductor device according to appendix 4, wherein etching is performed.

(Appendix 6) Before the step of simultaneously forming the first semiconductor layer, a step of forming a groove in a portion of the semiconductor substrate adjacent to the second sidewall insulating film only for the second region. Including
In the step of simultaneously forming the first semiconductor layer, the first region is embedded in a portion adjacent to the first sidewall insulating film on the semiconductor substrate, and the groove is embedded in the second region. And simultaneously forming the first conductive type first semiconductor layers,
4. The method of manufacturing a semiconductor device according to any one of appendices 1 to 3, wherein in the step of forming the second semiconductor layer, the second semiconductor layer is formed so as to fill the groove.

  (Supplementary Note 7) In the step of etching and removing the first semiconductor layer in the second region, the first semiconductor layer exposed in the second region is removed by etching and the groove is etched to a predetermined depth. The manufacturing method of a semiconductor device according to appendix 6, wherein:

(Supplementary Note 8) The first and second sidewall insulating films are laminated so as to cover only an inner layer that covers both side surfaces of the first and second gate electrodes and an upper portion of the inner layer, respectively. Including an outer layer,
In the step of simultaneously forming the first semiconductor layer, the first semiconductor layer is simultaneously formed in a state where only the inner layer is formed on both side surfaces of the first and second gate electrodes,
In the step of forming the mask layer, the mask layer is formed in a state where the outer layer is formed from the upper part of the inner layer to the first semiconductor layer,
In the step of etching away the first semiconductor layer in the second region, the first semiconductor layer is etched away in the second region, and the lower portion of the inner layer of the second sidewall insulating film is removed. From the bottom surface of the outer layer to form a void,
2. The method of manufacturing a semiconductor device according to appendix 1, wherein in the step of forming the second semiconductor layer, the second semiconductor layer is formed so as to fill the gap and extend.

  (Supplementary Note 9) In the step of etching and removing the first semiconductor layer in the second region, the first semiconductor layer in the second region is removed by etching and adjacent to the inner layer of the semiconductor substrate. 9. The method of manufacturing a semiconductor device according to appendix 8, wherein a groove having a predetermined depth is formed in a portion to be processed.

(Additional remark 10) The said outer layer is laminated | stacked so that the 1st layer from which the said mask layer and an etching selection ratio differ, and the said 1st layer may be covered, The 2nd which has an etching selection ratio equivalent to the said mask layer And including a layer of
The supplementary note 8 or 9, further comprising a step of etching and removing the second layer in the first and second regions together with the mask layer after the step of forming the second semiconductor layer. Semiconductor device manufacturing method.

(Supplementary Note 11) The outer layer is laminated so as to cover the first layer having the same etching selectivity as the mask layer and the first layer, and the second layer having a different etching selectivity from the mask layer. And including a layer of
10. The method of manufacturing a semiconductor device according to appendix 8 or 9, further comprising a step of etching away the mask layer leaving the second layer after the step of forming the second semiconductor layer.

  (Supplementary note 12) The supplementary notes 1 to 4, wherein the step of etching away the first semiconductor layer and the step of forming the second semiconductor layer are continuously performed in the same processing chamber. The method for manufacturing a semiconductor device according to any one of 6, 8, 10, and 11.

It is a flowchart which shows the concrete conventional method of manufacturing the CMOS transistor provided with the P-type MOS transistor which has a SiGe layer, and the N-type MOS transistor which has a SiC layer. In this case, it is a flowchart which shows the specific manufacturing method which manufactures the CMOS transistor provided with the P-type MOS transistor which has a SiGe layer, and the N-type MOS transistor which has a SiC layer. It is a schematic sectional drawing which shows the manufacturing method of the CMOS transistor by 1st Embodiment in order of a process. FIG. 4 is a schematic cross-sectional view illustrating the method of manufacturing the CMOS transistor according to the first embodiment in order of processes subsequent to FIG. 3. It is a schematic sectional drawing which shows only the main processes in the manufacturing method of the CMOS transistor by the modification of 1st Embodiment. It is a schematic sectional drawing which shows the manufacturing method of the CMOS transistor by 2nd Embodiment to process order. FIG. 7 is a schematic cross-sectional view illustrating the method of manufacturing the CMOS transistor according to the second embodiment in order of processes subsequent to FIG. 6. It is a schematic sectional drawing which shows the manufacturing method of the CMOS transistor by 3rd Embodiment in order of a process. FIG. 9 is a schematic cross-sectional view illustrating the manufacturing method of the CMOS transistor according to the third embodiment in order of processes following FIG. 8. It is a schematic sectional drawing which shows the manufacturing method of the CMOS transistor by 4th Embodiment in order of a process. FIG. 11 is a schematic cross-sectional view illustrating the manufacturing method of the CMOS transistor according to the fourth embodiment in order of processes following FIG. 10. FIG. 12 is a schematic cross-sectional view showing the method of manufacturing the CMOS transistor according to the fourth embodiment in order of processes following FIG. 11. It is a schematic sectional drawing which shows the manufacturing method of the CMOS transistor by 5th Embodiment in order of a process. FIG. 14 is a schematic cross-sectional view showing the method of manufacturing the CMOS transistor according to the fifth embodiment in order of processes subsequent to FIG. 13.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 1a N type formation area 1b P type formation area 2,102 Gate insulating film 3,103 Gate electrode 4 Silicon nitride film 5,105 Side wall insulating film 5A, 105A Inner layer 5B, 105B Outer layer 5a, 105a 1st Layer 5b, 105b second layer 6, 106 extension region 7, 107 source / drain region 8, 108 SiC layer 9, 11 mask layer 10a N-type MOS transistor 10b P-type MOS transistor 21, 121, 122, 124 groove 109 SiGe layer 123 gap

Claims (5)

A first transistor having a first gate electrode having a first sidewall insulating film formed in a first region of a semiconductor substrate;
And a second transistor provided with a second gate electrode having a second sidewall insulating film formed in the second region of the semiconductor substrate, comprising:
The first region of the first conductivity type is located in the first region adjacent to the first sidewall insulating film, and the second region is adjacent to the second sidewall insulating film. A step of simultaneously forming a semiconductor layer;
Forming a mask layer so as to cover only the first region;
Etching the first semiconductor layer in the second region, leaving the first semiconductor layer in the first region, using the mask layer;
Forming a second semiconductor layer of the second conductivity type so as to be adjacent to the second sidewall insulating film only in the second region using the mask layer. A method for manufacturing a semiconductor device. Before the step of simultaneously forming the first semiconductor layer, a first groove is formed in a portion of the semiconductor substrate adjacent to the first sidewall insulating film for both the first and second regions. Forming a second groove in a portion of the semiconductor substrate adjacent to the second sidewall insulating film,
In the step of simultaneously forming the first semiconductor layer, the first region is filled with the first groove, and the second region is filled with the second groove. Forming a first semiconductor layer of one conductivity type simultaneously;
The method of manufacturing a semiconductor device according to claim 1, wherein in the step of forming the second semiconductor layer, the second semiconductor layer is formed so as to fill the second groove.   In the step of etching away the first semiconductor layer in the second region, the first semiconductor layer in the second region is etched away, and the second groove is etched to a predetermined depth. The method of manufacturing a semiconductor device according to claim 2, wherein: Before the step of simultaneously forming the first semiconductor layer, the method further includes a step of forming a groove in a portion of the semiconductor substrate adjacent to the second sidewall insulating film only for the second region;
In the step of simultaneously forming the first semiconductor layer, the first region is embedded in a portion adjacent to the first sidewall insulating film on the semiconductor substrate, and the groove is embedded in the second region. And simultaneously forming the first conductive type first semiconductor layers,
The method for manufacturing a semiconductor device according to claim 1, wherein in the step of forming the second semiconductor layer, the second semiconductor layer is formed so as to fill the groove. Each of the first and second sidewall insulating films includes an inner layer that covers both side surfaces of the first and second gate electrodes, and an outer layer that is laminated so as to cover only the upper portion of the inner layer. Including
In the step of simultaneously forming the first semiconductor layer, the first semiconductor layer is simultaneously formed in a state where only the inner layer is formed on both side surfaces of the first and second gate electrodes,
In the step of forming the mask layer, the mask layer is formed in a state where the outer layer is formed from the upper part of the inner layer to the first semiconductor layer,
In the step of etching away the first semiconductor layer in the second region, the first semiconductor layer is etched away in the second region, and the lower portion of the inner layer of the second sidewall insulating film is removed. From the bottom surface of the outer layer to form a void,
2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of forming the second semiconductor layer, the second semiconductor layer is formed so as to fill the gap and extend.

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