JP2009294426A - Display apparatus - Google Patents

Abstract

There is provided a display device capable of suppressing burn-in during precharge driving even when a plurality of panels having different panel characteristics are driven simultaneously.
In a display device 1 that drives two panels 20 and 30 having different panel characteristics, a precharge voltage DSD is written to all pixels of each display panel in an ineffective display period of one horizontal scanning period. Charge drive is performed. At this time, the precharge voltage DSD is set to the center voltage of the video voltage amplitude in the panel in the non-display state. When the sub-monitor 20 is in the non-display state, the voltage V _DSDs and the main monitor 30 are in the non-display state. In this case, the voltage is set to _DSDm .
[Selection] Figure 1

Description

  The present invention relates to a display device that drives a plurality of display panels having different panel characteristics.

As a conventional active matrix display device, one in which a predetermined precharge signal is supplied to each signal line immediately before a video signal is written to pixels for one row is known (for example, see Patent Document 1). Here, a precharge signal having a halftone level is supplied to a video signal that changes between a white level and a black level.
Also, as a display device that performs polarity inversion driving for each line, the positive polarity precharge signal in the positive polarity voltage drive and the negative polarity precharge signal in the negative polarity voltage drive are set asymmetrically with respect to the amplitude center of the image data voltage. Is known (for example, see Patent Document 2).

On the other hand, as a display device including two display panels such as a digital video camera and a digital still camera, there is known a device that simultaneously drives the two display panels with a one-chip IC as a control circuit (for example, And Patent Document 3). In such a display device, when two display panels are displayed with each other, only the precharge drive for supplying only the precharge voltage to the pixels is performed on the panel that is not displayed.
Japanese Patent Laid-Open No. 7-295521 JP 2003-202847 A JP 2006-154225 A

  By the way, the display panel may have different panel characteristics such as a driving frequency and a driving voltage depending on a driving method, a panel size, and the like. When two display panels with different panel characteristics are driven simultaneously with a single chip IC, the optimum precharge voltage is different, but the precharge voltage for the precharge drive depends on the characteristics of the display panel. It is common to apply a voltage (for example, the center voltage of the image data voltage amplitude in the display panel) correspondingly set.

However, in this case, a different pixel voltage is written for each frame on the non-displayed panel side (the panel side on which precharge driving is performed), so that a DC voltage is constantly applied and burn-in occurs. Cause it.
Accordingly, an object of the present invention is to provide a display device capable of suppressing burn-in during precharge driving even when a plurality of panels having different panel characteristics are driven simultaneously.

  In order to solve the above problems, a display device according to the present invention includes a plurality of pixels provided corresponding to intersections of a plurality of scanning lines and a plurality of data lines, and a drive for supplying image data to the data lines. A display device comprising a plurality of display panels each having a circuit and a control circuit for controlling a drive circuit of the plurality of display panels, wherein the plurality of display panels have different panel characteristics, and any one of them The control circuit includes a precharge circuit that supplies a common precharge voltage to each data line of each display panel, and the precharge voltage is not displayed. It is characterized in that it is set to a voltage value corresponding to the panel characteristics of the display panel to be in a state.

As described above, since the precharge voltage is supplied to each data line, pixel writing can be sufficiently performed even when the writing polarity is different for each frame, and the display quality of the display panel in the display state is improved. Can be made.
In addition, since a voltage corresponding to the panel characteristics of the display panel to be in the non-display state is supplied as the precharge voltage, even if the writing polarity is reversed for each frame, a frame is applied to each pixel of the display panel in the non-display state. It is possible to prevent different voltages from being written every time. As a result, it is possible to prevent a DC voltage from being constantly applied, and it is possible to prevent image sticking from occurring in a non-display state display panel.

Therefore, even when the panel characteristics of the plurality of display panels are different from each other, the display panels can be simultaneously driven (mutual display) without causing a problem.
Furthermore, the display device according to the present invention is characterized in that, in the above, the precharge voltage is set to a center voltage of an amplitude of an image data voltage in a display panel to be in a non-display state.

As a result, the precharge voltage can be set to an appropriate value corresponding to the panel characteristics, and the burn-in of the display panel that is more effectively brought into the non-display state can be prevented.
In the display device according to the present invention described above, the precharge circuit is connected to a precharge line that supplies the precharge voltage and the data lines, and the precharge line is connected to the precharge line at a predetermined timing. A switch for turning on each data line; controlling the switch to turn on the precharge line and each data line; and controlling each data line to the precharge voltage. It is characterized by being composed.

Thereby, a precharge circuit can be realized with a relatively simple circuit configuration.
In the display device according to the invention, in the above, the precharge circuit supplies a common precharge voltage to each data line of each display panel in an ineffective display period in one horizontal scanning period. It is a feature.
As described above, since the precharge voltage is supplied before the image signal is supplied to each data line (ineffective display period), pixel writing can be sufficiently performed even when the writing polarity is different for each frame. And the display quality of the display panel in the display state can be improved.

Furthermore, in the display device according to the present invention, in the above, a display panel that is in a non-display state among the plurality of display panels stops the driving circuit and applies the precharge voltage held in the data line. It is characterized by writing in each pixel.
Accordingly, power consumption can be suppressed, and the precharge voltage held in the data line can be written to each pixel of the display panel that is easily in the non-display state.

The display device according to the present invention is characterized in that, in the above, each pixel of the display panel in the non-display state among the plurality of display panels holds the precharge voltage for approximately one vertical scanning period. Yes.
Thereby, in the non-display state, the voltage applied to the liquid crystal can be made appropriate, and the burn-in of the display panel that effectively makes the non-display state can be prevented.

Furthermore, in the display device according to the present invention, in the above, a display panel that is in a non-display state among the plurality of display panels stops the drive circuit, and the precharge circuit has approximately one horizontal scanning period, The precharge voltage is supplied to each data line of the display panel which is in a non-display state among the plurality of display panels.
As a result, in the non-display state, the precharge voltage can be written to the pixel without being lowered by the data line, so that the display panel in the non-display state can be more effectively prevented from being burned.

In the display device according to the present invention described above, the display panel that is in the non-display state among the plurality of display panels has the precharge voltage applied to each pixel at the same timing as the display panel in the display state. It is characterized by writing.
As a result, in the non-display state, the voltage applied to the liquid crystal can be easily made appropriate, and the display panel in the non-display state can be more effectively prevented from being burned.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing the configuration of the display device 1 of the present embodiment.
In the present embodiment, for example, a case where the present invention is applied to a liquid crystal display device including two liquid crystal panels of an LCD monitor and a liquid crystal viewfinder (EVF), which is applied to a digital video camera, a digital still camera, or the like will be described. . Here, a liquid crystal panel using an active matrix thin film transistor (TFT) is applied to both the LCD monitor and the EVF.

As shown in FIG. 1, the display device 1 includes an EVF liquid crystal panel (sub monitor) 20, an LCD monitor liquid crystal panel (main monitor) 30, and a control circuit 10 that drives and controls the two panels 20 and 30. It is prepared for. As described above, in the display device 1 according to the present embodiment, the two panels 20 and 30 are driven by the single control circuit 10.
The control circuit 10 is configured as a one-chip IC, and a timing controller 11 is formed therein. The timing controller 11 generates various drive signals to be supplied to the panels 20 and 30.

  The timing controller 11 includes, as individual drive signals for each monitor, a sub-monitor drive signal generator 12 that generates a horizontal start signal STHEV for the sub-monitor 20 and horizontal clock signals CKH1EV and CKH2EV for the sub-monitor 20, and a main monitor 30 The main monitor drive signal generator 13 for generating the horizontal start signal STH and the horizontal clock signals CKH1 and CKH2 for the main monitor 30, and the vertical start signal STV and the vertical drive signal as the common drive signals for the sub monitor 20 and the main monitor 30 are used. And a common drive signal generator 14 for generating a clock signal CKV, an enable signal ENB, and a precharge signal DSG.

Thus, the timing controller 11 generates a horizontal start signal and a horizontal clock signal for the panel. The display state of the two panels can be switched by individually controlling the operation states of the horizontal start signal and the horizontal clock signal for each panel.
Here, it is assumed that each liquid crystal panel is driven and controlled by a dot sequential driving method. Further, it is assumed that the horizontal clock signals CKH1EV and CKH2EV are in an opposite phase relationship, and the horizontal clock signals CKH1 and CKH2 are also in an opposite phase relationship.

  The two panels 20 and 30 have the same basic configuration. The image display units 21 and 31, the input terminals 22 and 32, the vertical scanning circuits 23 and 33, the horizontal scanning circuits 24 and 34, and the precharge circuit 25, respectively. And 35.

FIG. 2 is a circuit diagram showing the configuration of the sub-monitor 20, and FIG. 3 is a circuit diagram showing the configuration of the main monitor 30.
A plurality of gate lines (scanning lines) GL are provided in the horizontal direction and drain lines (data lines) DL are provided in the vertical direction in the image display portions 21 and 31 of the panels 20 and 30, respectively. In the image display portions 21 and 31, pixels 110 are arranged corresponding to the intersections of the gate lines and the drain lines.
Each pixel 110 includes an n-channel thin film transistor (hereinafter referred to as TFT) 114 that functions as a pixel switching element and a pixel capacitor. Note that the pixel capacity of the pixel 110 of the sub monitor 20 is LC ′, and the pixel capacity of the pixel 110 of the main monitor 30 is LC.

  Since each pixel 110 has the same configuration, the pixel 110 in the first row and the first column will be described as a representative example of the pixel 110 located in the first row and the first column of the sub-monitor 20. The gate electrode of the TFT 114 is the first gate line GL. The source electrode is connected to the drain line DL of the first column, and the drain electrode is connected to the pixel electrode 116 that is one end of the pixel capacitor LC ′.

The other end of the pixel capacitor LC ′ is connected to the common electrode 118. The common electrode 118 is common to all the pixels 110, and the common voltage COM is supplied from the control circuit 10. Here, the common voltage COM is configured to periodically invert the polarity according to the writing polarity.
The common drive signals (STV, CKV, DSG, ENB), power supply (Vcc, PVDD), video signal, etc. (Video, COM, DSD) output from the control circuit 10 are connected to the input terminals 22 and 32 of the panels 20 and 30. ) Are input in common.

In addition, a horizontal start signal STHEV and horizontal clock signals CKH1EV and CKH2EV are further input to the input terminal 22 of the sub monitor 20. Further, a horizontal start signal STH and horizontal clock signals CKH 1 and CKH 2 are further input to the input terminal 32 of the main monitor 30.
The vertical scanning circuits 23 and 33 of the panels 20 and 30 each include a vertical shift register and a plurality of switching circuits provided for each gate line of the image display units 21 and 31. The switching circuit of each gate line is configured to apply a driving voltage to the corresponding gate line by being driven according to a driving signal from the vertical shift register. A vertical start signal STV and a vertical clock signal CKV are input to the vertical scanning circuits 23 and 33 of both panels 20 and 30 through the input terminals 22 and 32, respectively.

  Further, the horizontal scanning circuits 24 and 34 of the panels 20 and 30 are respectively configured to include a horizontal shift register and a plurality of sample and hold circuits provided for each drain line of the image display units 21 and 31. . These horizontal scanning circuits 24 and 34 each have a function as a sampling circuit that samples image data to be displayed on each pixel from an input video signal.

A video output (Video, COM), a horizontal start signal STHEV, and horizontal clock signals CKH1EV, CKH2EV are input to the horizontal scanning circuit 24 through the input terminal 22.
Further, the video output (Video, COM), the horizontal start signal STH, and the horizontal clock signals CKH 1 and CKH 2 are input to the horizontal scanning circuit 34 through the input terminal 32.

The precharge circuit 25 of the sub-monitor 20 includes a precharge switch 254 that makes each drain line DL and precharge line 252 conductive, and each precharge switch 254 is turned on for a predetermined period at a predetermined timing. At the same time, a predetermined precharge voltage DSD is supplied to each drain line DL by controlling the ON state.
In addition, the precharge circuit 35 of the main monitor 30 includes a precharge switch 354 that makes each drain line DL and precharge line 352 conductive, and each precharge is performed at a predetermined timing for a predetermined period. A predetermined precharge voltage DSD is supplied to each drain line DL by simultaneously controlling the switch 354 to be in an ON state.

A precharge signal DSG and a precharge voltage DSD are commonly input to the precharge circuits 25 and 35 through the input terminals 22 and 35, respectively.
Here, the precharge signal DSG is configured to be in an ON state within a horizontal blanking period (ineffective display period) in each horizontal scanning period. Then, in synchronization with the timing when the precharge signal DSG is turned on, the precharge switches 254 and 354 are turned on, whereby the drain lines DL and the precharge lines 252 and 352 are brought into conduction, and the precharge voltage DSD. Is supplied to each drain line DL.

The two panels 20 and 30 are configured such that when one of them is in a display state, the other is in a non-display state.
In this embodiment, a voltage corresponding to the characteristics of the panel in the non-display state is set as the precharge voltage DSD. Specifically, when the sub monitor 20 is in the non-display state, the voltage V _DSDs corresponding to the panel characteristics of the sub monitor 20 is set as the precharge voltage DSD, and when the main monitor 30 is in the non-display state, A precharge voltage V _DSDm corresponding to the panel characteristics is set as the precharge voltage DSD.

4A and 4B are diagrams showing the precharge voltage DSD in each display state. FIG. 4A shows the precharge voltage DSD when the main monitor 30 is in the display state, and FIG. 4B shows the sub monitor 20 in the display state. The precharge voltage DSD is shown in FIG.
As shown in FIG. 4A, when the main monitor 30 is in the display state, the center voltage V _DSDs having the amplitude of the video voltage (two-dot chain line) in the sub monitor 20 is set as the precharge voltage DSD. ), When the sub-monitor 20 is in the display state, the center voltage V _DSDm having the amplitude of the video voltage (two-dot chain line) in the main monitor 30 is set as the precharge voltage DSD.

  In addition, the control circuit 10 uses a plurality of frame periods (as a initialization sequence) when the panel is turned on / off, when the display is switched from the sub-monitor 20 to the main monitor 30, and when the display is switched from the main monitor 30 to the sub-monitor 20. For example, an off voltage is applied to all the pixels of each panel during a period of two frames. In the case of a liquid crystal panel, the off voltage is a state in which no voltage is applied to the liquid crystal. For example, 0 V is applied to the pixel.

  At this time, it is desirable that the timing controller 11 generates a horizontal clock signal that is inverted at a timing divided from the input frequency so that a margin is provided in the pixel writing time.

FIG. 5 is a flowchart showing a driving sequence when the power is turned on.
First, in step S1 of FIG. 5, the video writing power source Vcc and the panel driving power source PVDD are raised to turn on the panel power source, and the process proceeds to step S2.
In step S2, IC reset is performed to set each panel in the sleep mode. Specifically, video output (Video, COM, DSD), common drive signals (STV, CKV, DSG, ENB), and panel drive signals (STH, CKH1, CKH2, STHEV, CKH1EV, CKH2EV) are all in a standby state. And
In step S3, a video signal having an input frequency corresponding to the panel to be displayed is input, and the process proceeds to step S4.

In step S4, the panel mode to be displayed is set (gamma setting, normally white / normally black setting, etc.).
In step S4, the precharge voltage DSD is set to a voltage corresponding to the panel to be in the non-display state. That is, when the sub-monitor 20 is in the non-display state, the precharge voltage DSD is set to the voltage V _DSDs, and when the main monitor 30 is set to the non-display state, the pre-charge voltage DSD is set to the voltage V _DSDm . This output switching of the precharge voltage DSD can be realized only by changing the register setting in the control circuit 10.
As a result, the normal display of the panel can be started.

  Next, in step S5, an initialization sequence is performed. At this time, the standby state of the common drive signals (STV, CKV, DSG, ENB) and the panel drive signals (STH, CKH1, CKH2, STHEV, CKH1EV, CKH2EV) is canceled. Here, as an initialization sequence, it is assumed that 0 V is written to all the pixels of both panels during a two-frame period.

In step S6, one of the two panels is set to the display state, and the other panel is set to the non-display state. Specifically, the horizontal start signal and horizontal clock signal of the panel to be in the non-display state are stopped, and the standby state of the video output (Video, COM, DSD) is canceled.
In step S7, normal display is started by turning on the backlight of the panel that is in the display state of the two panels.
Next, a driving sequence at the time of switching the display of the panel will be described.

FIG. 6 is a flowchart showing a driving sequence at the time of switching the panel display.
First, in step S11 of FIG. 6, a display switching command is input, and a drive sequence for performing display switching from the sub monitor 20 to the main monitor 30 or display switching from the main monitor 30 to the sub monitor 20 is started.
In step S12, the backlight of the panel in the display state is turned off, and the process proceeds to step S13.

  In step S13, an IC reset is performed to set each panel in the sleep mode. Specifically, video output (Video, COM, DSD), common drive signals (STV, CKV, DSG, ENB), and panel drive signals (STH, CKH1, CKH2, STHEV, CKH1EV, CKH2EV) are all in a standby state. And As a result, the video output of both panels is stopped.

Next, in step S14, 0V is applied to all the pixels of both panels as an initialization sequence for two frame periods.
In this initialization sequence, the video output (Video, COM, DSD) is maintained in a standby state for two frame periods, the common drive signal (STV, CKV, DSG, ENB), and the drive signals for each panel (STH, CKH1). , CKH2, STHEV, CKH1EV, CKH2EV).

  After two frame periods have elapsed, the common drive signals (STV, CKV, DSG, ENB) and the panel drive signals (STH, CKH1, CKH2, STHEV, CKH1EV, CKH2EV) are set to the standby state again, and both panels are set to sleep. State. As a result, both panels are completely hidden.

In step S15, a video signal having an input frequency corresponding to the panel to be displayed next is input.
In step S16, the panel mode to be displayed is set (gamma setting, normally white / normally black setting, etc.).

In step S16, the precharge voltage DSD is set to a voltage corresponding to the panel to be in the non-display state. That is, when the sub-monitor 20 is in the non-display state, the precharge voltage DSD is set to the voltage V _DSDs, and when the main monitor 30 is set to the non-display state, the pre-charge voltage DSD is set to the voltage V _DSDm .
As a result, the normal display of the panel can be started.

  Next, in step S17, an initialization sequence is performed. Again, 0V is applied to all pixels in both panels for a period of two frames. At this time, the common drive signals (STV, CKV, DSG, ENB) and the panel drive signals (STH, CKH1, CKH2, STHEV, CKH1EV, CKH2EV) are released from the standby state.

In step S18, one of the two panels is set to the display state, and the other panel is set to the non-display state. Specifically, the horizontal start signal and horizontal clock signal of the panel to be in the non-display state are stopped, and the standby state of the video output (Video, COM, DSD) is canceled.
In step S19, normal display is started by turning on the backlight of the panel that is in the display state of the two panels.

Next, the precharge drive operation will be described.
FIG. 7 is a timing chart during precharge driving. Here, a case where the main monitor 30 is in the display state and the sub-monitor 20 is in the non-display state will be described.
At time t1, for example, when a horizontal synchronization signal Hsync indicating the start timing of the nth one horizontal scanning period is input, the enable signal ENB is turned off at time t2, thereby stopping the vertical scanning circuits 23 and 33. The

Thereafter, from time t3 to time t4, the precharge signal DSG is turned on, so that all the precharge switches 254 and 354 of the precharge circuits 25 and 35 are turned on simultaneously. At this time, since the sub-monitor 20 is in the non-display state, the precharge voltage DSD set to the voltage V _DSDs is supplied from the control circuit 10 to the panels 20 and 30 in common. Precharge voltage V _DSDs is supplied from 252 and 352 to each drain line DL.

At time t5, the enable signal ENB is turned on, and the vertical scanning circuits 23 and 33 start operating. Thus, all the TFT114 connected to the gate line GL of the n-th row of each panel 20 and 30 are turned on, the pixel capacitor LC, the precharge voltage V _DSDS to LC' written.

Next, the video signal Video is supplied from the control circuit 10 to the panels 20 and 30 at time t6. At this time, on the main monitor 30 side in the display state, the horizontal scanning circuit 34 operates, and writing according to the video signal Video is performed in the pixel capacitor LC. On the other hand, since the start signal STHEV and the clock signals CKH1EV and CKH2EV are stopped and the horizontal scanning circuit 24 does not operate on the sub-monitor 20 side in the non-display state, the precharge voltage V _DSDs is held in the pixel capacitor LC ′. Is done.

  By the way, in general, when two display panels are simultaneously driven by a one-chip IC, the precharge voltage is set at a level set corresponding to the panel to be in the display state as shown by a one-dot chain line in FIG. Generally, it is set to (the center level of the video voltage amplitude of the panel to be displayed). Therefore, the pixel of the display panel that is in the non-display state holds the precharge voltage set at the above level for one vertical scanning period.

However, in this case, if the panel characteristics of the two display panels are different, the center voltage of the video voltage amplitude on the display panel side (the panel side on which precharge driving is performed) in the non-display state is performed. A DC voltage corresponding to the difference between the (two-dot chain line) and the precharge voltage (one-dot chain line) is constantly applied, causing burn-in.
On the other hand, in this embodiment, the precharge voltage DSD is set to a level corresponding to the panel to be in the non-display state, specifically, the center voltage of the video voltage amplitude of the panel to be in the non-display state.

Therefore, when the sub monitor 20 is set in the non-display state and the main monitor 30 is set in the display state, the precharge voltage DSD = V _DSDs is set. On the main monitor 30 side, the precharge voltage V _DSDs corresponding to the panel characteristics of the sub monitor 20 is set. Thus, pixel writing is performed. At this time, since the precharge voltage V _DSDs is not the center voltage of the video voltage amplitude of the main monitor 30, it differs from the precharge level that should be originally present, but does not have a large influence on the display.

On the sub-monitor 20 side, the precharge voltage V _DSDs is held even during the effective display period. Since the precharge voltage V _DSDs is the center voltage of the video voltage amplitude of the sub monitor 20, no DC voltage is applied to the pixels of the sub monitor 20.
Therefore, even when two panels having different panel characteristics are displayed on each other, it is possible to prevent burn-in during precharge driving of the non-displayed panel.

On the other hand, when the main monitor 30 is in the non-display state and the sub-monitor 20 is in the display state, the precharge voltage DSD = V _DSDm is set, so that the precharge is performed for a period corresponding to the time t3 to time t4 in FIG. When the signal DSG is turned on, the precharge voltage V _DSDm is supplied from the precharge lines 252 and 352 to the drain lines DL.

When the video signal Video is supplied from the control circuit 10 to each of the panels 20 and 30 at the timing corresponding to the time t6, the horizontal scanning circuit 24 operates on the side of the sub monitor 20 that is in the display state, and the pixel Since the writing according to the video signal Video is performed on the capacitor LC ′ and the horizontal scanning circuit 34 does not operate on the main monitor 30 side that is not displayed, the precharge voltage V _DSDm is held in the pixel capacitor LC.

  As described above, in the above embodiment, since the precharge voltage is supplied before the image signal is supplied to each data line (ineffective display period), pixel writing is performed even when the writing polarity is different for each frame. This can be performed sufficiently and the display quality of the display panel in the display state can be improved.

  Further, in each pixel of the panel in the non-display state, the precharge voltage written in the non-effective display period is held in one horizontal scanning period. At this time, as a precharge voltage, a voltage corresponding to the panel characteristics of the display panel to be in the non-display state is supplied, so even if the writing polarity is reversed for each frame, each pixel of the display panel in the non-display state is It is possible to prevent different voltages from being written for each frame. As a result, it is possible to prevent a DC voltage from being constantly applied, and it is possible to prevent image sticking from occurring in a non-display state display panel.

Therefore, even when the panel characteristics of the plurality of display panels are different from each other, the display panels can be simultaneously driven (mutual display) without causing a problem.
Further, since the precharge voltage is set to the center voltage of the amplitude of the image data voltage in the display panel to be in the non-display state, it is possible to more effectively prevent the display panel from being in the non-display state from being burned.

In addition, in a non-effective display period in one horizontal scanning period, the precharge line and each data line are made conductive by controlling a switch connected to the precharge line and each data line, and each data line is precharged. Since the voltage is controlled, the precharge circuit can be realized with a relatively simple circuit configuration.
Further, in a display panel that is in a non-display state among a plurality of display panels, the driving circuit (horizontal scanning circuit) is stopped and the precharge voltage held in the data line is written to each pixel, thereby consuming The power can be suppressed, and the precharge voltage held in the data line can be written to each pixel of the display panel that is easily in a non-display state.

Further, each pixel of the display panel that is in the non-display state among the plurality of display panels holds the precharge voltage for approximately one vertical scanning period, so that the voltage applied to the liquid crystal is set to an appropriate voltage in the non-display state. This can prevent burn-in of the display panel that is more effectively in a non-display state.
In the above embodiment, when the main monitor 30 is in the display state and the sub-monitor 20 is in the non-display state, as shown in FIG. 7, the time t5 when the vertical scanning circuits 23 and 33 start operation is defined as the display state. It may be after time t6 when the horizontal scanning circuit 34 on the main monitor 30 side operates. This is the same when the main monitor 30 is in the non-display state and the sub-monitor 20 is in the display state.

  In the above-described embodiment, the case where the precharge signal DSG is a common drive signal has been described. However, an individual signal for each monitor may be used. In this case, the precharge voltage is supplied to the display panel data lines in the display state during the ineffective display period in one horizontal scanning period, and the display panel data lines in the non-display state are supplied. A precharge voltage may be supplied for one horizontal scanning period.

For example, when the main monitor 30 is in the display state and the sub-monitor 20 is in the non-display state, on the sub-monitor 20 side, the precharge signal DSG is turned on after time t3, so that all the precharge switches of the precharge circuit 25 are turned on. At the same time, control is performed so that the precharge voltage V _DSDs is supplied from the precharge line 252 to each drain line DL for one horizontal scanning period. At time t5, the enable signal ENB is turned on, and the vertical scanning circuit 23 starts to operate. All the TFTs 114 connected to the gate line GL of the nth row of the sub monitor 20 are turned on, and the pixel capacitor LC ′ Is written with the precharge voltage V _DSDs . As a result, the pixel can be written without lowering the precharge voltage with the data line, so that the display panel can be prevented from being burned more effectively. This is the same when the main monitor 30 is in the non-display state and the sub-monitor 20 is in the display state.

In the above embodiment, the case where the precharge voltage is set at the center of the video voltage amplitude of the panel to be in the non-display state has been described. However, during precharge driving, the DC voltage is applied to the pixel of the panel to be in the non-display state. Any voltage value can be used as long as the voltage is not applied.
In the above embodiment, a display device including two liquid crystal panels having different panel characteristics has been described. However, the present invention can also be applied to a display device including three or more liquid crystal panels having different panel characteristics. In this case, the timing controller 11 may generate a horizontal start signal and a horizontal clock signal for the liquid crystal panel.

  In the above-described embodiment, the case where the present invention is applied to a display device using liquid crystal has been described. However, the present invention can also be applied to a display device using an electro-optical material other than liquid crystal.

It is a block diagram which shows the structure of the display apparatus in this embodiment. It is a circuit diagram which shows the structure of a sub monitor. It is a circuit diagram which shows the structure of a main monitor. It is a figure which shows the precharge voltage in each display state. It is a flowchart which shows the drive sequence at the time of power-on. It is a flowchart which shows the drive sequence at the time of panel display switching. It is a timing chart at the time of precharge drive. It is a figure which shows a general precharge voltage.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Display apparatus, 10 ... Control circuit, 11 ... Timing controller, 12 ... Sub monitor drive signal generation part, 13 ... Main monitor drive signal generation part, 14 ... Common drive signal generation part, 20 ... EVF liquid crystal panel (sub monitor , 21 ... Image display section, 22 ... Input terminal, 23 ... Vertical scanning circuit, 24 ... Horizontal scanning circuit, 25 ... Precharge circuit, 30 ... LCD monitor liquid crystal panel (main monitor), 31 ... Image display section, 32 ... Input terminal, 33 ... Vertical scanning circuit, 34 ... Horizontal scanning circuit, 35 ... Precharge circuit

Claims (8)

A plurality of display panels each having a plurality of pixels provided corresponding to intersections of a plurality of scanning lines and a plurality of data lines, and a drive circuit for supplying image data to the data lines, and the plurality of display panels A control circuit that controls the driving circuit of the display device,
The plurality of display panels have different panel characteristics, and any one of them is configured to be in a non-display state,
The control circuit includes a precharge circuit that supplies a common precharge voltage to each data line of each display panel,
The display device according to claim 1, wherein the precharge voltage is set to a voltage value corresponding to a panel characteristic of the display panel to be in a non-display state.   The display device according to claim 1, wherein the precharge voltage is set to a center voltage of an amplitude of an image data voltage in a display panel to be in a non-display state. The precharge circuit is connected to a precharge line for supplying the precharge voltage and the data lines, and has a switch for making the precharge line and the data lines conductive at a predetermined timing. And
3. The configuration according to claim 1, wherein the switch is controlled so that the precharge line and the data lines are in a conductive state, and the data lines are controlled to the precharge voltage. The display device described.   4. The precharge circuit according to claim 1, wherein a common precharge voltage is supplied to each data line of each display panel during an ineffective display period in one horizontal scanning period. The display device described in 1.   5. The display panel in a non-display state among the plurality of display panels stops the driving circuit and writes the precharge voltage held in the data line to each pixel. 6. Display device.   6. The display device according to claim 5, wherein each pixel of the display panel in the non-display state among the plurality of display panels holds the precharge voltage for approximately one vertical scanning period.   The display panel in the non-display state among the plurality of display panels stops the drive circuit, and the precharge circuit displays in the non-display state among the plurality of display panels for approximately one horizontal scanning period. 4. The display device according to claim 1, wherein the precharge voltage is supplied to each data line of the panel.   4. The display panel in a non-display state among the plurality of display panels writes the precharge voltage to each pixel at the same timing as the display panel in a display state. Item 1. A display device according to item 1.

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