JP2009283136A - Nonvolatile memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile memory device capable of stably operating by reducing the mutual noises existing among signal lines. <P>SOLUTION: A data line BDE is formed on a metal wiring layer 202 of a first layer (1M) and electrically connected to a sense amplifier group SAG via a contact hole 213. A ground line to which a grounding voltage GND to be used in a sub-column decoder 125a is supplied, is formed on a metal wiring layer 204 of a second layer (2M). A ground line to which the grounding voltage GND to be used in the sense amplifier group SAG is supplied, is formed on a metal wiring layer 209 of a second layer of upper layer of a metal wiring layer 202. The device has a configuration such that a ground line is formed for supplying the grounding voltage GND to a metal wiring layer 206 of a third layer (3M) of the upper layer of metal wiring layers 207, 208 so as to be electrically connected to the metal wiring layers 204, 209 of the second layer (2M), respectively via contact holes 215 and 216. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a nonvolatile memory device, and more particularly to a nonvolatile memory device capable of low voltage operation.

  Along with the recent progress in miniaturization processing technology, the size of a transistor (such as the thickness of an oxide film) has been reduced along with the reduction in the memory cell size in order to reduce the chip size. However, in a memory device, since the operating voltage used when performing various operations is different, all circuit regions should be composed of transistors with small oxide film thickness (hereinafter also referred to as thin film transistors). Is difficult. In particular, since various operating voltages are used in various operation sequences in a flash memory or the like, a thick and relatively large transistor (hereinafter referred to as a thick film transistor) is used in a memory to which a high voltage or the like is applied. Is generally used. On the other hand, in a sense amplifier or the like that requires high speed, a thin transistor having a relatively small size and capable of high speed operation at a low operating voltage is used. Accordingly, it is possible to reduce the size of the chip as a whole. Conventionally, various methods for reducing the transistor size in order to reduce the size of the chip have been proposed. In Japanese Patent Laid-Open No. 8-329690, a memory cell is improved by improving the well structure of the memory cell. A nonvolatile memory device that can reduce the operating voltage of the peripheral circuit and thereby reduce the film thickness of the transistor in the peripheral circuit is disclosed.

JP-A-8-329690

  However, when there are two types of transistors in the chip as described above, that is, when a thin film transistor and a thick film transistor are used, it is necessary to control so that a high voltage is not applied to the thin film transistor. .

  In particular, in a flash memory, various voltage levels are supplied to the memory cell and its peripheral circuits by various operation sequences. Therefore, when a high voltage is used as an operating voltage, a thin film transistor having a thin film thickness must not be destroyed.

  An object of the present invention is to provide a nonvolatile memory device which is made to solve the above-described problem and prevents a circuit formed of a thin film transistor from being destroyed.

  In addition, as the operating voltage becomes relatively low due to the recent reduction in transistor size, the difference between the threshold voltage of the transistors constituting the driver circuit and the voltage level of the operating voltage is also getting smaller. For this reason, it has become difficult to supply a desired operating voltage from the driver circuit due to the influence of the threshold voltage of the transistor.

  Another object of the present invention is to solve such a problem, and provides a nonvolatile memory device having a driver circuit capable of reliably supplying a desired operating voltage even at a low operating voltage. It is.

  Still another object of the present invention is to provide a nonvolatile memory device capable of high-speed and stable operation by improving the driving capability of various driver circuits.

  Another object of the present invention is to provide a nonvolatile memory device capable of stable operation by reducing noise between signal lines.

  A nonvolatile memory device according to an aspect of the present invention includes a memory array having a plurality of memory cells arranged in a matrix, and a plurality of sources each provided corresponding to each predetermined number of memory cell rows in the memory array And a plurality of driver transistors provided corresponding to one end sides of the plurality of source lines, each electrically coupling a fixed voltage and the corresponding source line in response to a control signal. Along the row direction, the memory array is divided into first and second memory blocks. Of the plurality of source lines electrically coupled to the memory cells of the first memory block, the number of the first group and the plurality of source lines electrically coupled to the memory cells of the second memory block It is different from the number of the second group.

  A non-volatile memory device according to another aspect of the present invention includes a memory array having a plurality of memory cells arranged in a matrix, a data line for transmitting write data and read data to the memory array, and an external address instruction In response to a column decoder for performing a column selection operation of the memory array, a column selection gate for electrically coupling the selected memory cell of the memory array and the data line, and in response to an instruction from the column decoder And a gate driver for driving the column selection gate. The gate driver drives the column selection gate in response to an instruction from the column decoder at the time of data reading, using a predetermined voltage equal to or lower than the boosted voltage applied to the memory cell at the time of data reading as an operating voltage.

  Preferably, the operating voltage of the gate driver is set to a voltage higher than the boost voltage during data writing. A voltage adjustment circuit is further provided for setting the operating voltage of the gate driver to the boosted voltage or less after data writing.

  In particular, after the data is written, the voltage adjustment circuit sets the voltage level so as to drop from the boosted voltage by the threshold voltage of the transistor.

  A non-volatile memory device according to another aspect of the present invention includes a memory array having a plurality of memory cells arranged in a matrix, a plurality of first data lines for transmitting read data to the memory array, and a plurality of first data A sense amplifier that amplifies read data transmitted to the data line, a control signal line that is disposed along the same direction as the plurality of first data lines, and that transmits a control signal for controlling the sense amplifier; A first power line that is arranged along the same direction as one data line and supplies a fixed voltage used for the operation of the sense amplifier; and a plurality of first data lines arranged along the same direction; And a second power supply line for supplying a fixed voltage used for the operation of the peripheral circuit. The plurality of first data lines are formed in the same wiring layer as the first and second power supply lines, and are arranged between the first and second power supply lines. The control signal lines adjacent to the plurality of first data lines are formed in a wiring layer different from the wiring layer. The first power supply line and the second power supply line are electrically coupled using contact holes so as to cover the plurality of first data lines using different wiring layers.

  Preferably, a plurality of second data lines provided corresponding to the plurality of first data lines, each of which is electrically coupled to the corresponding first data line and transmits read data to the sense amplifier. Further prepare. The plurality of first data lines and the plurality of second data lines are orthogonal to each other. A first data line electrically coupled to a first group located in a first region of the plurality of second data lines; and a second region of the plurality of second data lines. The second group located and the first data line electrically coupled are alternately arranged.

  A nonvolatile memory device according to still another aspect of the present invention includes a memory array having a plurality of memory cells. The memory array includes a spare memory area provided for storing redundant information to be replaced with a plurality of defective memory cells and predetermined fixed information. The spare memory area includes a plurality of redundant bit lines provided for transmitting redundant information and a fixed bit line provided for transmitting predetermined fixed information. The plurality of redundant bit lines are divided by fixed bit lines into first and second groups, and one of the first and second groups is selected at the time of data reading, and fixed bits are selected. The line is electrically coupled with a fixed voltage.

  Preferably, at the time of data reading, redundant bit lines other than the selected redundant bit line in the first and second groups are electrically coupled to a fixed voltage.

  According to one embodiment of the present invention, when the memory array is divided into the first and second memory blocks, the number of source lines provided in each memory block is different. By changing the number of memory blocks according to the load applied to the source line, the load on the source line can be reduced, fluctuations in the voltage level of the source line can be suppressed, and the driving capability of the driver transistor can be improved. Can do.

  According to another embodiment of the present invention, the operation voltage applied to the gate driver by the column decoder during data reading is set to a predetermined voltage higher than the device voltage and lower than the word line boost voltage. Thereby, the driving capability of the gate driver can be improved by supplying an operating voltage higher than the device voltage to the gate driver.

  According to another embodiment of the present invention, the plurality of first data lines are disposed between the first and second power supply lines. In addition, the first and second power supply lines are electrically coupled to each other using different wiring layers via contact holes so as to cover the plurality of first data lines. Accordingly, since the wiring layer is provided so as to straddle the first data line, noise from the adjacent control signal line can be reduced.

  According to still another embodiment of the present invention, in a spare memory area for storing redundant information and fixed information, first and second groups of redundant bit lines for transmitting redundant information to fixed bit lines for transmitting fixed information Provide between. Thereby, the fixed bit line functions as a shield line, and the influence of coupling noise can be suppressed.

1 is a schematic block diagram of a memory device 1 according to an embodiment of the present invention. 1 is a conceptual diagram illustrating a read / write system circuit according to a first embodiment of the present invention. It is a diagram illustrating voltage levels applied to the read / write system circuit according to the first embodiment of the present invention in various sequences. FIG. 5 is a timing chart illustrating the operation of the sense amplifier during reading. It is a timing chart explaining operation | movement at the time of writing. It is a circuit block diagram of the row selection type | system | group circuit according to Embodiment 2 of this invention. It is a schematic block diagram of VP generation circuit 15c and VPWL distribution circuit 20a. It is a figure explaining the voltage level at the time of each operation | movement sequence given to the row selection type | system | group circuit according to Embodiment 2 of this invention. It is a conceptual diagram explaining the threshold distribution of the memory cell of an overerased state. It is a flowchart figure of the erasure | elimination sequence which gave the countermeasure with respect to the over-erasure problem. It is a circuit block diagram of the conventional column selection system circuit. It is a cross-sectional structure diagram of a transistor constituting a driver circuit. It is a block diagram of the column selection type | system | group circuit according to Embodiment 3 of this invention. It is a figure explaining the voltage level given to the column selection system circuit according to Embodiment 3 of this invention in various sequences. FIG. 10 is a timing chart illustrating a voltage VPY generated by a VPY voltage generation circuit 20h accompanying the operation of a column selection system circuit at the time of writing. It is a conceptual diagram explaining the system which reinforces the drive capability of a source line driver. FIG. 3 is a configuration diagram illustrating in detail memory array 70 and its peripheral circuits according to the embodiment of the present invention. 3 is a conceptual diagram illustrating details of a spare area SBLK of a memory array 70. FIG. FIG. 11 is a cross-sectional structure diagram illustrating a wiring structure of data line BDE electrically coupled to a sense amplifier band between ZZ #. It is a figure explaining the arrangement | positioning method of the connection wiring of this invention used in order to share the data line BDE provided corresponding to block BLK <0> and block BLK <1>.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same code | symbol in a figure shall show the same or an equivalent part.

(Embodiment 1)
FIG. 1 is a schematic block diagram of a memory device 1 according to an embodiment of the present invention.

  Referring to FIG. 1, memory device 1 according to the embodiment of the present invention includes an address buffer 5 that receives an input of external address ADD and outputs an internal address IAD, and a memory device 1 that receives an input of internal address IAD. A control circuit 10 that executes various operation controls, a voltage generation circuit 15 that generates a voltage used in the memory device 1, and a voltage generated from the voltage generation circuit 15 is received and adjusted and distributed. And a voltage distribution circuit 20. In the embodiment of the present invention, one power supply voltage VCC (also referred to as device voltage) (1.8 V) is applied as the power supply voltage of the memory device. Using the supplied power supply voltage VCC, the voltage generation circuit 15 generates a word line boosted voltage or a step-down voltage used in various operation sequences.

  The memory device 1 also receives a predecoder 30 that receives an internal address IAD output from the address buffer 5 and generates a predecode signal, and a memory array that receives a predecode signal output from the predecoder 30. A selection circuit 25 that performs a selection operation of 70 rows and columns, a memory array 70 including memory cells integrated and arranged in a matrix, and a plurality of word lines and source lines respectively provided corresponding to the memory cell rows Each of the word line / source line driver band 65 for driving the gate, the gate control unit 60 for selecting a column in the memory array according to the selection operation of the selection circuit 25, and read data and write data at the time of data reading and data writing, respectively. Read / write control circuit 55 for amplifying and outputting the data, and data at the time of data reading The data output circuit 50 to be input and the read data received from the data output circuit 50 are buffered and output to the external terminal 46, and the write data input from the external terminal 46 is written to the read / write control circuit 55. And an input / output buffer 45 for transmitting to the write driver, and a sense amplifier control circuit 35 for controlling a sense amplifier in the read / write control circuit 55. Detailed configurations of the memory array 70 and the gate controller 60 will be described later.

  The selection circuit 25 selects a word line provided corresponding to the memory cell row based on the predecode signal from the predecoder 30 and a memory cell column based on the predecode signal from the predecoder 30. And a column decoder 25b for selecting a bit line provided corresponding to the above.

  The control circuit 10 includes a command control circuit 10 a that generates commands for instructing various operation sequences in the memory device 1 based on the internal address IAD input from the address buffer 5, and each circuit in the voltage generation circuit 15. To each circuit, a voltage control circuit 10b for controlling the operation voltage, a verify control circuit 10c for controlling a verify operation at the time of data reading and data writing different from reading, writing, and erasing in the normal operation mode, And a control signal generation circuit 10d for generating the control signal.

  The voltage generation circuit 15 includes a VPS generation circuit 15a that generates a voltage VPS, a VN generation circuit 15b and a VP generation circuit 15c that generate a voltage VN and a voltage VP, respectively, used to drive a word line, and a source line When activating a word line WL, a VPSW generation circuit 15d and a VNSW generation circuit 15e for generating driver operating voltages VPSW and VNSW, a PW generation circuit 15f for generating a well voltage PW for the memory cells of the memory array, etc. Includes a VBOOST generation circuit 15g for generating a word line boosted voltage VBOOST used for the above and a VPL generation circuit 15h for generating a high voltage VPL to be supplied to the write driver during data writing.

  Voltage distribution circuit 20 receives voltage VP and distributes it as voltages VPWL1 and VPWL2, respectively, VPWL distribution circuit 20a that receives voltage VN and distributes it as voltages VNWL1 and VNWL2, respectively, voltage VPS and word line boosting A VPY generation circuit 20h that receives the voltage VBOOST and outputs it as the voltage VPY.

  In the first embodiment, in a sense amplifier band formed of thin film transistors, a memory array 70 formed of thick film transistors, a gate control unit 60, and the like (hereinafter also referred to as read / write circuit), A method for preventing a high voltage from being applied to a transistor in a sense amplifier band composed of thin film transistors will be described.

FIG. 2 is a conceptual diagram illustrating a read / write system circuit according to the first embodiment of the present invention.
Referring to FIG. 2, the read / write system circuit according to the first embodiment of the present invention includes a sense amplifier SA and a write driver WDRV included in read / write control circuit 55, a gate control unit 60, a matrix. And a memory array 70 having a plurality of memory cells arranged in a shape. Here, the sense amplifier SA is formed of a thin film transistor, and the write driver WDRV, the gate control unit 60, and the memory array 70 are formed of thick film transistors. In this example, one memory cell MC is shown in the memory array 70 as an example. Memory cell MC is a so-called memory cell transistor, and its gate is electrically coupled to word line WL. One end side which is the source side is electrically coupled to the bit line BL, and the other end side which is the drain side is electrically coupled to the source line SL. The same applies to the other memory cells MC.

  The sense amplifier SA includes a constant current generation unit 71, inverters 74 and 81, transistors 75 to 80, and a precharge transistor 82. In this example, transistors 75, 76, and 82 are P-channel MOS transistors as an example. Transistors 77 to 80 are N-channel MOS transistors.

  Constant current generating unit 71 includes a gate level adjusting circuit 73 and a transistor 72 (P channel MOS transistor).

  Transistor 72 is arranged between power supply voltage VCC and output node Nb, and has a gate receiving control voltage VRSA from gate level adjustment circuit 73.

  The gate level adjustment circuit 73 adjusts the voltage level of the control voltage VRSA so that the gate-source voltage of the transistor 72 becomes constant, and makes the amount of current flowing through the transistor 72 constant. In the present embodiment, the power supply voltage VCC is set to 1.8V.

  Transistors 75 to 77 are connected in series between power supply voltage VCC and ground voltage GND, respectively, and the gate of transistor 75 receives an input of an inverted signal of control signal SAE via inverter 74. Transistors 76 and 77 have their gates electrically coupled to node Nc. Transistor 78 is arranged between nodes Nb and Nc, and has its gate electrically coupled to connection node Na of transistors 76 and 77. Transistor 79 is arranged between node Na and ground voltage GND, and has its gate receiving an inverted signal of control signal SAE via inverter 74. Transistor 80 is arranged between node Nc and ground voltage GND, and has a gate receiving control signal RSTBD.

  Sense amplifier SA senses and amplifies data stored in memory cell MC based on the amount of current flowing through memory cell MC selected via data line BDE electrically coupled to node Nc during data reading. And output as read data SAOUT.

  Specifically, the voltage level of node Nb is set based on the voltage level of node Nc set based on the passing current flowing through the selected memory cell, and read data SAOUT is output. For example, when the passing current is large and the node Nc is at a relatively low voltage level, the transistor 76 is turned on, the voltage level of the node Na increases, and the transistor 78 further decreases the voltage level of the node Nb. That is, the voltage level of node Nb is amplified to “L” level.

  On the other hand, when the passing current is small and node Nc is set to a relatively high voltage level, transistor 77 is turned on, the voltage level at node Na is lowered, and transistor 78 is raised at the voltage level at node Nb. That is, the voltage level of node Nb is amplified to “H” level. Based on this amplification operation, inverter 81 inverts the voltage level signal applied to node Nb and outputs it as read data SAOUT.

  Next, the gate control unit 60 will be described. Although described in detail later, a brief description will be given here.

  The gate control unit 60 includes transistors 61 and 62, a column selection circuit CASG, a gate transistor SG, and a data line BDE. Transistors 61, 62, and SG are N-channel MOS transistors as an example.

  Transistor 61 is arranged between node Nc of sense amplifier SA and data line BDE, and its gate receives input of control signal SEL. Transistor 62 is arranged between data line BDE and ground voltage GND, and has a gate receiving control signal ISEL. The control signals SEL and ISEL are output from the control signal generation circuit 10d. Here, the transistor 61 functions as a separation circuit that electrically separates the sense amplifier SA and the data line BDE. Transistor 62 functions as a reset circuit for electrically coupling data line BDE and ground voltage GND before reading.

  Column selection circuit CASG receives control signals CAU and CAL from column decoder 25b of the selection circuit for selecting a column, and electrically couples main bit line MBL and data line BDE. Gate transistor SG electrically couples bit line BL and selected memory cell MC in response to control signal SGL.

  Column selection circuit CASG includes transistors CAGa and CAGb. In this example, transistors CAGa and CAGb are N-channel MOS transistors as an example.

  Transistors CAGa and CAGb are arranged between data line BDE and main bit line MBL, and receive control signals CAU and CAL, respectively. For example, when control signals CAU and CAL are both “H”, data line BDE and main bit line MBL are electrically coupled.

  FIG. 3 is a diagram illustrating voltage levels applied to the read / write system circuit according to the first embodiment of the present invention in various sequences.

First, the operation during reading will be described.
Gate control unit 60 sets control signal SEL to 5 V (“H” level) to electrically couple node Nc of sense amplifier SA and data line BDE. In column selection circuit CASG, selected main bit line MBL and data line BD are electrically coupled in response to input predetermined control signals CAU and CAL (5V−Vth = “H” level). Is done. In response to control signal SGL (5V = “H” level), bit line BL electrically coupled to selected memory cell MC and main bit line MBL are electrically coupled. Next, the sense amplifier SA is activated. That is, by setting control signal SAE to 1.8 V (“H” level), a current path from sense amplifier SA to selected memory cell MC is formed. In this example, the control signal TXLATD (“L” level) is input to turn on the transistor 82 and precharge the voltage level of the data line BD to 0.7V. In this state, by activating word line WL electrically coupled to selected memory cell MC, a passing current flows through the memory cell, and a data read operation based on the passing current is performed. The control signal VRSA is set to 1.8V-α, where α is a predetermined voltage for supplying a desired constant current.

  The operation of the sense amplifier at the time of reading will be described using the timing chart of FIG.

  Referring to FIG. 4, at time T <b> 3 a, read is executed as control signal SAE rises to “H” level. Further, at the same timing, the control signal TXLATD (“L” level) is input to the transistor 82. Along with this, the transistor 82 is turned on, and the data line BDE is precharged to a predetermined voltage (0.7 V). Here, the sense amplifier SA according to the first embodiment of the present invention includes a transistor 76 and a transistor 77 that feed back the voltage level of the node Nc to the gate electrode of the transistor 78. Conventionally, only the transistor 77 is provided. Conventionally, the transistor 75 is used to increase the voltage level of the node Na and finely adjust. However, since the gain is small, the voltage level of the node Na is not sufficiently finely adjusted, and it takes a relatively long time to set the voltage level of the node Nc.

  With this configuration, fine adjustment of the voltage level of the node Na can be performed using the transistors 77 and 76, so that the voltage level of the node Nc, that is, the voltage level of the data line BDE is set to a desired voltage level, that is, 0.7V. The period to be set is shortened (time t3b). That is, by providing an adjustment mechanism for adjusting the gate voltage of the transistor 78, the time of the voltage level set at the node Nc (precharge period) is shortened, and a high-speed data read operation can be executed. In this example, by providing the transistor 76, the read data SAOUT is determined at time t3. On the other hand, when transistor 76 is not provided, read data SAOUT is determined at time t4 as shown by the dotted line.

Next, the operation during writing will be described.
Referring to FIG. 3, column select circuit CASG electrically couples selected main bit line MBL and data line BDE in response to control signals CAU and CAL (10V = “H” level). In response to control signal SGL (10V = “H” level), bit line BL electrically coupled to selected memory cell MC and main bit line MBL are electrically coupled. Accordingly, write driver WDRV is electrically coupled to selected memory cell MC. Write driver WDRV is activated in response to control signal DVE (1.8V = “H” level), and receives a voltage of 5V / 0V from VPL generation circuit 10h based on the data level of input write data WD. Is supplied to the data line BDE. In this state, by activating the word line WL that is electrically coupled to the selected memory cell MC, a voltage corresponding to the write data is supplied to the memory cell, and the desired data is supplied by CHE (channel hot electrons). A data write operation based on the write data is executed. The control signal DVE is output from the control signal generation circuit 10d.

  In this case, a high voltage (5 V) is applied to the data line BDE. Here, the control signal SEL (0V = “L” level) is applied to the gate of the transistor 61. That is, the transistor 61 is turned off. As a result, a high voltage is applied to the data line BDE during writing, but the data line BDE and the sense amplifier SA are electrically separated by the transistor 61. With this configuration, it is possible to prevent a high voltage from being applied to the sense amplifier SA including the thin film transistor, and the thickness of the transistor can be reduced, that is, the thin film transistor can be protected.

The operation during writing will be described with reference to the timing chart of FIG.
Referring to FIG. 5, a write pulse for executing data writing is applied in a period up to time t1. Here, control signals SEL and ISEL are set to the “L” level. Therefore, the transistor 61 is off, and the data line BDE and the sense amplifier SA are electrically separated. At time t1, application of the write pulse is completed. Accordingly, control signal DVE is set to “L” level to inactivate write driver WDRV. Further, the control signal ISEL is set to the “H” level. Accordingly, the transistor 62 is turned on. As transistor 62 is turned on, ground voltage GND and data line BDE are electrically coupled to each other and set to the ground voltage level, that is, 0 V, and data line BDE is reset. At time t2 when fully reset, control signal ISEL is set to “L” level and control signal SEL is set to “H” level. Accordingly, data line BDE ends electrical coupling with ground voltage GND and is electrically coupled with sense amplifier SA, and thereafter determines whether or not a desired data write operation has been executed. A so-called verify read is performed.

Next, the operation at the time of erasing will be described.
Referring again to FIG. 3, at the time of erasing, the voltage levels of word line WL and source line SL in memory array 70 change. On the other hand, read / write control circuit 55 is inactive. Specifically, the control signal SAE for activating the sense amplifier SA is set to 0V. Further, the control signal DVE for activating the write driver WDRV is set to 0V. Control signals CAU, CAL and SGL are all set to 0V, and the column selection operation is not executed. The control signal SEL is set to 5V (“H” level), and the data line BDE and the sense amplifier SA are electrically coupled. Since control signal RSTBD is set to 1.8 V (“H” level), data line BDE and ground voltage GND are electrically coupled, and data line BDE is reset. Word line WL, source line SL, and memory cell well voltage PW are set to −10V, 10V, and 10V. As a result, an erasing operation for extracting electrons injected into the floating gate of the memory cell MC into the source region is executed.

  As described above, in the first embodiment, a thin film transistor is provided by providing the transistor 61 that electrically separates the sense amplifier SA and the data line BDE so that a high voltage is not applied to the sense amplifier SA, particularly at the time of writing. The configured sense amplifier SA can be protected.

(Embodiment 2)
In the second embodiment, a circuit configuration (hereinafter also referred to as a row selection system circuit) of a decoder unit constituting a row decoder for executing a row selection operation and a word line driver constituting a word line / source line driver band 65. Will be described.

FIG. 6 is a circuit configuration diagram of a row selection system circuit according to the second embodiment of the present invention.
Referring to FIG. 6, the row selection circuit according to the second embodiment of the present invention includes decoder units DCU0 and DCU1 and word line drivers GDV0 and GDV1 for driving global word lines GWL <0> and GWL <1>, respectively. And a word line driver LDV0 for driving the local word line LWL. In this example, the word line includes a global word line GWL provided for each group of a predetermined memory cell row and a local word line LWL which is electrically coupled to the global word line GWL and has a hierarchical structure. . In this specification, global word lines and local word lines are collectively referred to as word lines WL.

  The decoder units DCU0 and DCU1 receive the block selection signal BA output from the row decoder 25a, the control signal RAU for selecting the word line, and the control signals RAL <0> and RAL <1>, and receive the global word line GWL. select. The detailed configuration of the memory array will be described later.

  The word line drivers GDV0 and GDV1 selectively drive the global word lines GWL <0> and GWL <1> based on control signals from the decoder units DCU0 and DCU1, respectively. Word line driver LDV0 is electrically coupled to global word line GWL <0>, and selectively drives corresponding local word line LWL based on the input of control signal HAL. In this example, one local word line LWL corresponding to global word line GWL <0> is representatively shown. The other global word lines GWL <1> have the same configuration.

  Decoder unit DCU0 includes transistors NT1-NT3 and PT1-PT3. Transistors NT1-NT3 are respectively connected in series between node Nd1 and voltage VNWL1, and each gate receives input of control signal RAL <0>, control signal RAU, and block selection signal BA. Transistors PT1 to PT3 are connected in parallel between voltage VPWL1 and node Nd1, and each gate receives control signal RAL <1>, control signal RAU, and block selection signal BA. Decoder unit DCU0 constitutes a three-input NAND circuit. For example, when control signal RAL <0>, control signal RAU, and block selection signal BA are all at "H" level, all of transistors NT1-NT3 are turned on. The voltage level of the node Nd1 is set to the voltage VNWL1. On the other hand, when any one of the control signal RAL <0>, the control signal RAU, and the block selection signal BA is “L”, the voltage level of the node Nd1 is because any one of the transistors PT1 to PT3 is turned on. Is set to the voltage VPWL1.

  Word line driver GDV0 includes transistors P0 and N0. Transistor P0 is arranged between voltage VPWL2 and global word line GWL <0>, and has its gate electrically coupled to node Nd1. Transistor N0 is arranged between voltage VNWL2 and global word line GWL <0>, and has its gate electrically coupled to node Nd1. For example, when the voltage level of node Nd1 is “H” level, transistor N0 is turned on, and the voltage level of global word line GWL <0> is set to voltage VNWL2. On the other hand, when the voltage level of node Nd1 is set to “L” level, transistor P0 is turned on, and the voltage level of global word line GWL <0> is set to voltage VPWL2.

  Word line driver LDV0 includes transistors NT5, NT6 and PT7 and an inverter IV0. Transistor PT7 is arranged between local word line LWL and global word line GWL <0>, and has a gate receiving control signal HAL. Transistor NT6 is connected in parallel with transistor PT7 between local word line LWL and global word line GWL <0>, and its gate receives an input of an inverted signal of control signal HAL via inverter IV0. Transistor NT5 is arranged between local word line LWL and voltage VNWL2, and its gate receives control signal HAL. For example, when control signal HAL is at “H” level as an example, transistor NT5 is turned on, and voltage VNWL2 and local word line LWL are electrically coupled. On the other hand, when control signal HAL is at "L" level, transistor PT7 and transistor NT6 are turned on, and local word line LWL and global word line GWL <0> are electrically coupled.

  Decoder unit DCU1 includes transistors PT4 to PT6 and transistor NT4.

  In decoder unit DCU1, transistor NT4 is electrically coupled in series with transistors NT2 and NT3 of decode unit DCU0. That is, since the control signal RAU and the block selection signal BA are signals input to both the decoder units DCU0 and DCU1, the number of circuit components is reduced by using the transistors in common. Further, the configurations of the transistors PT4 to PT6 are the same as those described for the transistors PT1 to PT3 of the decoder unit DCU0, and the respective gates receive the control signal RAL1 <1>, the control signal RAU, and the block selection signal BA. Receive. This decoder unit DCU1 also constitutes a three-input NAND circuit. For example, when control signal RAL <1>, control signal RAU, and block selection signal BA are all at "H" level, transistors NT2-NT4 are all turned on. Then, the voltage level of the node Nd2 is set to the voltage VNWL1. On the other hand, when any one of the control signal RAL <1>, the control signal RAU, and the block selection signal BA is “L”, the voltage level of the node Nd2 is set so that any one of the transistors PT4 to PT6 is turned on. Is set to the voltage VPWL1.

  Word line driver GDV1 includes transistors P1 and N1. The connection relation of the transistors is the same as that described for the global word line driver GDV0, and the global word line GWL <1> is set to a predetermined voltage level based on the voltage level of the node Nd2. In this example, transistors NT1-NT6, N0, and N1 are N-channel MOS transistors as an example. Transistors PT0 to PT7, P0, and P1 are P-channel MOS transistors.

  FIG. 7 is a schematic block diagram of the configuration in the VP generation circuit 15c and the VPWL distribution circuit 20a.

  Referring to FIG. 7, VP generation circuit 15c includes a VP pump 300 that generates voltage VP. VPWL distribution circuit 20a receives voltage VP and outputs voltages VPWL1 and VPWL2. The VPWL distribution circuit 20a includes a voltage adjustment circuit 301, adjusts the voltage level of the voltage VP output from the VP pump 300 based on the input of the control signal VPCT, and outputs the voltage VPWL2. The VP pump 300 receives the voltage level of the power supply voltage VCC (1.8 V), boosts it to a desired voltage level based on various operation sequences, and outputs it as a voltage VP.

  The VPWL distribution circuit 20a distributes the input voltage VP to each circuit as voltages VPWL1 and VPWL2 under normal conditions. However, when the control signal VPCT is input under a predetermined condition, the voltage level of the voltage VPWL2 is set. Adjust and output. The control signal VPCT is output from the control signal generation circuit 10d during various operation sequences.

  The same applies to the VN generation circuit 15b and the VNWL distribution circuit 20b that output the voltages VNWL1 and VNWL2.

  FIG. 8 is a diagram illustrating voltage levels at the time of each operation sequence applied to the row selection circuit according to the second embodiment of the present invention.

  Referring to FIGS. 6 and 8, voltage VPWL1 is set to 5V and voltage VPWL2 is set to 5V-Vth during standby. The voltages VNWL1 and VNWL2 are set to 0V, respectively. Note that Vth represents the threshold voltage of the transistor in this example.

  In standby, since the word line is not selected, the voltage level of node Nd1 is set to the “H” level. That is, at least one of control signal RAL <1>, control signal RAU, and block selection signal BA is at “L” level during standby, so that at least one of transistors PT1 to PT3 is turned on. Accordingly, node Nd1 is set to the voltage level (5 V) of voltage VPWL1. Here, the source side of the transistor P0, that is, the voltage VBWL2, is set to 5V-Vth. Therefore, at the time of standby, the source side voltage VPWL2 of the transistor P0 of the final stage driver circuit is set to a value obtained by dropping a predetermined voltage from 5V. That is, the source potential is set lower than the gate potential applied to the gate of the transistor P0. As a result, the channel leakage current of the transistor P0 can be sufficiently cut to reduce the leakage current. This control method can reduce power consumption by suppressing the leakage current of the P-channel MOS transistor during standby in the row selection circuit according to the second embodiment of the present invention. Here, the decoding unit DCU0 and the word line driver GDV0 have been mainly described, but the same applies to the decoding unit DCU1 and the word line driver GDV1.

  At the time of reading, voltages VPWL1 and VPWL2 are each set to 5V. The voltages VNWL1 and VNWL2 are set to 0V, respectively. Therefore, for example, when decoder unit DCU0 is selected, that is, when control signal RAL <0>, control signal RAU and block selection signal BA are all at "H" level, transistors NT1-NT3 are both turned on, and node The voltage level of Nd1 is set to 0V. Accordingly, transistor P0 of word line driver GDV0 is turned on, and the voltage level of selected global word line GWL <0> is set to 5V. Along with the selection operation of the global word line GWL <0>, one of the local word lines LWL having a hierarchical word line configuration is selected based on the control signal HAL and is electrically coupled to the local word line LWL. A data read operation is performed.

  At the time of writing, voltages VPWL1 and VPWL2 are each set to 10V. The voltages VNWL1 and VNWL2 are set to 0V, respectively. For example, the transistors NT1 to NT3 are all turned on by the same selection operation as described above, and the voltage level of the node Nd1 is set to 0V. Accordingly, transistor P0 of word line driver GDV0 is turned on, and the voltage level of selected global word line GWL <0> is set to 10V. Along with the selection operation of the global word line GWL <0>, one of the local word lines LWL having a hierarchical word line configuration is selected based on the control signal HAL and is electrically coupled to the local word line LWL. A data write operation is performed.

  At the time of erasing, voltages VPWL1 and VPWL2 are each set to 0V. The voltages VNWL1 and VNWL2 are set to −10V, respectively. At the time of erasing, the transistor NT5 of the word line driver LDV0 is turned on. Any one of the control signal RAL <0>, the control signal RAU, and the block selection signal is set to the “L” level. Accordingly, the voltage level of node Nd1 is set to −10V. Transistor P0 of word line driver GDV0 is turned on, and the voltage level of global word line GWL <0> is set to 0V. On the other hand, the control signal HAL (0 V) is input to the word line driver LDV0. Accordingly, transistor NT5 is turned on. The local word line LWL having the hierarchical word line configuration is selected based on the control signal HAL, and the voltage VNWL2 (−10 V) and the local word line LWL are electrically coupled to execute the data erasing operation of the memory cell.

Next, an over-erase verify operation according to the embodiment of the present invention will be described.
FIG. 9 is a conceptual diagram illustrating the threshold distribution of memory cells in an overerased state.

  Referring to FIG. 9, ideally, a state where data is “0” and “1” and converged and distributed to each of threshold values Mth1 and Mth2 in the state of data “0” and “1” is desired. In this example, the threshold value Mth1 corresponds to the programmed state, and the threshold value Mth2 corresponds to the erased state. In the over-erased state, as shown by the dotted line in FIG. 9, the state diagram of the threshold distribution is in a state of being distributed with a threshold value lower than the threshold value Mth2 of data “1”. In this case, the threshold value becomes low and variation occurs. That is, the distribution width of the threshold voltage becomes wide. When comparing such over-erased memory cells with normal erased memory cells, the over-erased memory cell is a depletion transistor and the gate voltage is 0 V, that is, the memory transistor is in a non-selected state. In addition, a large amount of leakage current flows. If such an overerased memory cell exists, when verify and read are performed, a large amount of leak current flows from the non-selected overerased memory cell on the same bit line, and the sum of the leak currents is selected. The detected current value of the memory cell becomes undetectable. That is, since reading becomes impossible, there arises a problem that accurate verify and read operations cannot be executed.

  FIG. 10 is a flowchart of an erasing sequence in which measures against the overerasing problem indicated by the dotted line in FIG. 9 are taken.

  Referring to FIG. 10, when an erase command is input in step S0, an erase pulse is applied in step S1, and the threshold voltage is changed by the FN tunnel current. Subsequently, erase verification is executed in step S2. Steps S1 and S2 are repeated until erasure of all the memory cells selected in the erase verify is confirmed. If erasure of all the memory cells is confirmed in step S2, the process proceeds to step S3. In step S3, overerase verify 1 is executed to check whether the memory cell is in an overerase state. That is, after the erase verify is completed, a memory cell having a threshold voltage equal to or lower than a certain value is detected. When a memory cell in an overerased state is detected, the process proceeds to step S4, where overerase recovery is performed.

  The over-erase recovery is a function of writing data back to an over-erased memory cell using channel hot electrons (CHE), that is, a function of increasing a threshold voltage in the positive direction for each memory cell. Then, the process proceeds to step S3, and it is determined again whether the memory cell is in an overerased state. If it is determined that the over-erasure state of the over-erase verify 1 is not over-erased, the process proceeds to the next step S5 where over-erase verify 2 is executed again. In the over-erase verify 2, a verify operation is performed under the same voltage condition as in normal data reading, and it is performed as a check operation to check whether normal operation is performed. If it is determined that the overerasure verify 2 is not normal, the process proceeds to the over-erase recovery in step S7, and the determination in step S5 is repeated again. In this overerase verify 2, when it is determined that the overerase state is not established, the erase is completed (step S6).

  Referring again to FIG. 8, the voltage level at the time of over-erase verification applied to the row selection system circuit is shown.

  In overerase verify 1, voltage VPWL1 is set to 5V and voltage VPWL2 is set to 1.5V. Further, both voltages VNWL1 and VNWL2 are set to -2V. For example, in this example, it is assumed that global word line GWL <0> is selected. Specifically, control signal RAL <0>, control signal RAU, and block selection signal BA are all set to the “H” level. Accordingly, the voltage level of node Nd1 is set to -2V, transistor P0 is turned on, and global word line GWL <0> is set to 1.5V. On the other hand, unselected global word line GWL <1> is set to −2V. Along with this, a verify operation, that is, a data read operation is executed, and overerase verify 1 is performed. In this case, unselected global word line GWL <1> is set to −2V, and the voltage level of local word line LWL (not shown) that is electrically coupled to global word line GWL <1> is also set to −2V. . Along with this voltage level, the leak current of the non-selected memory cell can be cut reliably and a stable verify operation can be executed.

  The overerase verify 2 differs in that the voltage VNWL2 is changed from −2V to 0V, and the other voltage levels and operations are the same. That is, the voltage level of the unselected global word line GWL <1> is set from −2V to 0V. In this case, the verify operation is executed in the same situation as in normal data reading. In other words, a method is employed in which a verify operation is executed under the same conditions as at the time of reading to more reliably eliminate over-erased memory cells.

  In the verify operation, unlike the standby, read, and write operations, a low operating voltage of 1.5 V is supplied to the global word line GWL <0> selected using the transistor P0. In this case, the threshold voltage of the transistor P0 increases due to the substrate drop, and it may be difficult to supply a desired operating voltage of 1.5 V to the global word line GWL <0>. Therefore, in this example, the voltage VNWL1 is set to -2V in order to ensure the driving power, thereby setting the node Nd1 to -2V and increasing the driving power of the transistor P0, so that even with a low operating voltage, it is ensured. A system for supplying to global word lines is adopted.

FIG. 11 is a circuit configuration diagram of a conventional column selection circuit.
Referring to FIG. 11, in this example, word line driver GDV0 # that drives global word line GWL based on control signal RAL <0>, control signal RAU, and block selection signal BA is shown. Since decoder unit DCU0 is similar to that described in FIG. 6, detailed description thereof will not be repeated.

  When supplying the power supply voltage VPWL having a low operating voltage to the global word line GWL as in the configuration shown in FIG. 11, not only the P channel MOS transistor P0 but also the voltage level of the node Nd1 is output and an inverted signal is output. In this configuration, inverter IV # and N channel MOS transistor N0 # receiving the output signal of inverter IV # at the gate are further provided. Therefore, by setting the gate voltage supplied to node Nd1 low as in this configuration, the drive capability of the P-channel MOS transistor is increased, and a desired voltage level is supplied to global word line GWL even when the operating voltage is low. can do. In other words, the configuration of the present embodiment eliminates the need to use inverter IV # and N-channel MOS transistor N0 # as in the prior art, thereby reducing the circuit area and increasing the layout efficiency by reducing the number of circuit components. it can.

Next, a cross-sectional structure of a transistor used in the column selection circuit will be described.
FIG. 12 is a cross-sectional structure diagram of a transistor constituting the driver circuit.

  Referring to FIG. 12, in this example, a transistor N0 and a transistor P0 are shown.

  Bottom N well 101 is formed in the upper layer of P-type Si substrate 100. An N well 110 and a P well 111 are formed so as to be stacked on the bottom N well 101. In this N well 110, a P channel MOS transistor (P type field effect transistor) P0 is formed (PMOS region). Specifically, P-type (P +) impurity regions 102 and 103 are provided as a source and a drain of the transistor P0, respectively. Transistor P0 has a source side electrically coupled to voltage VPWL2, and a drain side electrically coupled to global word line GWL <0>. Gate electrode 104 is electrically coupled to node Nd1. Further, N type (N +) impurity region 105 is formed in N well 110 and is electrically coupled to voltage VPWL1.

  On the other hand, for the transistor N0, an N-channel MOS transistor (N-type field effect transistor) N0 is formed in the P well 111 (NMOS region). Specifically, impurity regions 106 to 108 are respectively provided in the P well, and a P-type (P +) impurity region 106 that applies a well voltage of the P well and the voltage VNWL1 are electrically coupled. N-type impurity region 107 on the source side of N-channel MOS transistor N0 is electrically coupled to voltage VNWL2, and impurity region 108 on the drain side is electrically coupled to global word line GWL <0>. Gate electrode 109 is electrically coupled to node Nd1.

  The configuration of this embodiment is a configuration in which the N well is merged with the NMOS region and the PMOS region. That is, by forming the NMOS region and the PMOS region on the common bottom N well, the area can be reduced in terms of layout.

  Also, with this configuration, the potential difference between the P well and the bottom N well in the NMOS region can be suppressed during erasing, and the voltage can be relaxed.

(Embodiment 3)
In the third embodiment of the present invention, a driver configuration of a column selection circuit CASG that performs a column selection operation and a column decoder (hereinafter also referred to as a column selection system circuit) that controls a gate selection circuit will be described.

FIG. 13 is a configuration diagram of a column selection circuit according to the third embodiment of the present invention.
Referring to FIG. 13, the column selection circuit according to the third embodiment supplies power to column selection circuit CASG, column decoder 25 that outputs control signals CAU and CAL, and the final stage driver of column decoder 25. VPY voltage generation circuit 20h.

  Column decoder 25 includes driver circuits 84 and 85 provided at the final stage for transmitting control signals CAU and CAL transmitted to column selection circuit CASG. Driver circuits 84 and 85 drive voltage VPY as an operating voltage.

  VPY voltage generation circuit 20h includes transistors 81-83. Transistor 81 is arranged between a power supply line supplying voltage VPY and voltage VPS, and its gate receives input of control signal ICONVPS. Transistor 82 is arranged between voltage VBOOST and a power supply line that supplies voltage VPY, and has a gate receiving control signal CONVB. Transistor 83 is diode-connected, its source and gate are electrically coupled to voltage VBOOST, and its drain is electrically coupled to a power supply line supplying voltage VPY. Transistor 81 is a P-channel MOS transistor. Transistors 82 and 83 are N-channel MOS transistors. Here, voltage VBOOST corresponds to a word line boosted voltage applied to word line WL electrically coupled to the gate of the memory cell at the time of data reading.

  FIG. 14 is a diagram illustrating voltage levels applied to the column selection system circuit according to the third embodiment of the present invention in various sequences.

  At the time of reading, in the VPY voltage generation circuit 20h, both the voltage VPS and the voltage VBOOST are set to 5V. The control signal ICONVPS is set to 5V, and the control signal CONVB is set to 0V. Accordingly, the transistors 81 and 82 are both in the off state, and the voltage VPY is set to 5V-Vth, which is a drop of the threshold voltage of the transistor 83 from the voltage VBOOST (5V). Driver circuits 84 and 85 of column decoder 25 output control signals CAU and CAL to column selection circuit CASG using voltage VPY as an operating voltage. The data line BDE is set to 0.7 V based on the precharge operation of the sense amplifier SA as described above. As described above, as control signals CAU, CAL and SGL are set to 5V, memory cell MC and data line BDE are electrically coupled via bit line BL and main bit line MBL. Memory cell MC is electrically coupled to source line SL set to 0V. Accordingly, a current path is formed in response to word line WL (5 V), and a data read operation is executed.

  In this system, the driving capability of the transistor is improved by applying a high voltage higher than the normal power supply voltage VCC (1.8 V) to the gates of the transistors CAGa and CAGb of the column selection circuit CASG, thereby reliably ensuring the main bit line MBL. A voltage can be supplied to the bit line BL. Further, the voltage VPY is set to 5 V−Vth which is lowered by the threshold voltage due to the diode connection by the transistor 83. Here, the voltage level of the voltage VPY is set to a value that is higher than the device power supply voltage VCC (1.8 V) but lower by the threshold voltage so as to be lower than the high voltage VBOOST (5 V). Here, the transistor 83 is provided to adjust the voltage level. However, the voltage level can be adjusted using other methods such as a resistor.

  At the time of writing, voltage VPS is set to 10V. The control signal ICONVPS is set to 0V. Accordingly, the VPY voltage generation circuit 20h turns on the transistor 81, and the voltage VPY is set to 10V. Driver circuits 84 and 85 of column decoder 25 output control signals CAU and CAL to column selection circuit CASG using voltage VPY as an operating voltage. The data line BDE may be set to 5V in accordance with the write data by the write driver WDRV described above. In this case as well, the high voltage of 5V is reliably supplied to the column selection circuit CASG. The bit line MBL and the bit line BL can be supplied.

  FIG. 15 is a timing chart illustrating the voltage VPY generated by the VPY voltage generation circuit 20h accompanying the operation of the column selection system circuit at the time of writing.

  Referring to FIG. 15, in the verify operation before time T5, voltage VPY is set to 5V-Vth. At time T5, the control signal ICONVPS is set to 0V when the write pulse is applied. Accordingly, transistor 81 is turned on as described above, and the voltage level of voltage VPS, that is, 10 V, is applied as the operating voltage to the driver circuit of column decoder 25 as voltage VPY. In this case, the control signal CONVB is set to 0V. When application of the write pulse is completed at time T6, the control signal ICONVPS is set to 10V and the transistor 81 is turned off. Further, the control signal CONVB is set to 5V and the transistor 82 is turned on. Accordingly, voltage VPY is set to 5V. Next, at time T7, the control signal CONVB is set to 0V. Along with this, the transistor 82 is turned off, and the voltage VPY is gradually lowered and maintained at a value lowered by the threshold voltage of the diode-connected transistor 83, that is, 5 V-Vth.

  This method employs a two-stage reset method in which the voltage level of the voltage VPY is set from 10 V to 5 V and further reset from 5 V to 5 V-Vth during the reset period.

  At the time of erasing, the voltage levels of word line WL and source line SL in memory array 70 change. Specifically, as described above, a voltage of −10 V is applied to the word line WL, the source line SL is set to 10 V, and the well voltage PW is set to 10 V. On the other hand, the column selection system circuit is in an inactive state. Specifically, as described above, control signals CAU and CAL are set to 0 V (“L” level), and data line BDE and main bit line MBL are electrically disconnected.

  In the third embodiment, as described above, a high voltage is applied to the gates of the transistors CAGa and CAGb of the column selection circuit CASG, thereby improving the driving capability of the transistors and ensuring the main bit line MBL and the bit line BL. It is possible to supply a desired voltage.

(Embodiment 4)
In the fourth embodiment, a method for sufficiently securing the capability of the source line driver and reinforcing the driving capability will be described.

FIG. 16 is a conceptual diagram illustrating a method for reinforcing the drive capability of the source line driver.
Referring to FIG. 16, in this example, source line driver band SLDRV and two blocks BU0 and BU1 obtained by dividing the memory array are shown.

  Source line driver band SLDRV includes source line drivers SLDV0 and SLDV1 provided corresponding to blocks BU0 and BU1 that divide the memory array, and driver transistors SLG0 and SLG1, respectively.

  Source line driver SLDV 0 includes transistors 90 and 91. Transistor 90 is arranged between voltage VPSW and node Nd, and has a gate receiving control signal ESL0. Transistor 91 is arranged between node Nd and voltage VNSW, and has a gate receiving control signal ESL0. Transistors 90 and 91 are, for example, a P-channel MOS transistor and an N-channel MOS transistor. One of the transistors 90 and 91 is turned on in response to the input of the control signal ESL0, and supplies one of the corresponding voltages VPSW and VNSW as the control signal VG0 to the driver transistor SLG0. Driver transistor SLG0 is arranged between source line SL0 and ground voltage GND, and has a gate receiving control signal VG0.

  The source line driver SLDV1 includes transistors 92 and 93, and the connection relationship is the same as that of the source line driver SLDV0. Specifically, one of the transistors 92 and 93 is turned on in response to the input of the control signal ESL1, and one of the corresponding voltages VPSW and VNSW is supplied to the driver transistor SLG1 as the control signal VG1. Driver transistor SLG1 is arranged between source line SL1 and ground voltage GND, and has a gate receiving control signal VG1. Transistors 92 and 93 are a P-channel MOS transistor and an N-channel MOS transistor, respectively. In this method, a voltage VPSW (5 V) is applied. That is, since the control signals VG0 and VG1 are supplied with a high voltage of 5V and drive the source line driver, it is possible to ensure sufficient driving capability to drive the source line SL0. Here, voltage VPSW corresponds to the same voltage level as the word line boosted voltage applied to word line WL electrically coupled to the gate of the memory cell at the time of data reading.

  Further, in the configuration of the fourth embodiment, the number of source lines SL arranged for each of the blocks BU0 and BU1 is changed. Specifically, as shown in FIG. 16, six source lines SL0 are provided for the block BU1 located far from the source line driver band SLDRV, and the block BU0 located in the vicinity of the source line driver band SLDRV is provided. For this, three source lines SL1 are provided. Here, source lines SL0 and SL1 will be described in detail later, for example, six and three of nine source lines arranged along the row direction corresponding to a predetermined number of memory cell rows, respectively. Each of the source lines SL is a generic name.

  By adopting this configuration, by changing the number of source lines of the block BU0 located in the vicinity and the block BU1 located far away, the number of the source lines provided for the block BU1 can be increased even when the line length of the source line is increased. By increasing the wiring resistance, it is possible to suppress the wiring resistance and secure a sufficient driving capability to drive the source line SL0.

  The source voltage can be supplied more efficiently by making the thickness of the source line provided in the block BU1 located farther thicker than that of the block BU0. Specifically, the width of the source line can be increased according to the length of the source line.

(Embodiment 5)
In the fifth embodiment of the present invention, a method for suppressing noise to a data line electrically coupled to a sense amplifier band will be described.

  FIG. 17 is a configuration diagram illustrating in detail memory array 70 and its peripheral circuits according to the embodiment of the present invention.

  Referring to FIG. 17, memory array 70 according to the fifth embodiment of the present invention has two blocks BU and BU #, and blocks BU and BU # have memory area BLK <0> and memory area BLK <1, respectively. > And redundant spare area SBLK. Since the blocks BU and BU # have the same configuration, the configuration of the block BU will be mainly described.

  The memory region BLK <0> has main bit lines MBL0 to MBL255. The memory region BLK <1> has main bit lines MBL256 to MBL511. Spare region SBLK has spare main bit lines SMBLa0, SMBLa1, SMBLb0, SMBLb1, and main bit line MBLc.

FIG. 18 is a conceptual diagram illustrating details of the spare area SBLK of the memory array 70.
Referring to FIG. 18, spare region SBLK includes a plurality of memory cells MC arranged in a matrix, a plurality of word lines WL provided corresponding to each memory cell row, and a predetermined number of memory cell rows. A plurality of source lines SL provided corresponding to the memory cells, a plurality of bit lines SB provided corresponding to the memory cell columns, and a plurality of main lines provided corresponding to the four memory cell columns, respectively. A bit line MBL. In this example, word lines WL0 to WL9 provided corresponding to the memory cell rows are shown as an example. In the above description, the bit lines BL are described, but in this configuration, the bit lines SB00 to SB03, SB10 to SB13, SB20 to SB23, SB30 to SB33, and SB40 to SB43 are labeled as similar bit lines. Has been shown. In this configuration, as an example, source lines SL provided corresponding to two memory cell rows are also provided. Since the spare area SBLK is used, the main bit line MBL used as a redundant bit line is shown as spare main bit lines SMBLa0, SMBLa1, SMBLb0, and SMBLb1. The main bit line MBLc is a main bit line for a lock bit, and is provided corresponding to a memory cell that stores special information.

  Gate transistor regions SGA0 and SGA1 having a plurality of gate transistors SG for controlling connection to spare main bit line SMBL or MBL are provided on both sides of spare region SBLK.

  Gate transistor regions SGA0 and SGA1 include gate transistors SG00 to SG43. Specifically, for example, spare main bit line SMBLa0 provided corresponding to each of four bit lines SB00 to SB03 will be described.

  Gate transistor regions SGA0 and SGA1 include gate transistors SG provided corresponding to each bit line SB. Here, a gate transistor SG00 is provided corresponding to the bit line SB00, a gate transistor SG01 is provided corresponding to the bit line SB01, a gate transistor SG02 is provided corresponding to the bit line SB02, and corresponding to the bit line SB03. Thus, a gate transistor SG03 is provided. Each of gate transistors SG00 to SG03 receives control signals SGL0 to SGL3 (collectively, control signal SGL) at their gates. In this configuration, gate transistors are alternately arranged in the gate transistor regions SGA0 and SGA1 for each memory cell column. The same applies to the configurations of other bit lines SB and spare main bit lines SMBL. Thereby, it is possible to sufficiently secure the arrangement interval of the gate transistors, and to increase the layout margin. Spare main bit line SMBL and main bit line MBL are electrically coupled to sub-gate control unit 160c through gate transistor SG.

  In this configuration, a spare area SBLK having spare main bit lines SMBLa0, SMBLa1, SMBLb0, SMBLb1 and a main bit line MBLc is shown, but the memory areas BLK <0> and BLK <1> Although the number of main bit lines is different, the array configuration is the same.

  Referring again to FIG. 17, memory region BLK <0> has main bit lines MBL0-MBL255 provided corresponding to the memory cell columns, respectively, and one set is provided for every four main bit lines. Is formed. Further, the data lines BDE are provided corresponding to the bit line groups constituting the group of four, and the data lines BDE0 to BDE63 are respectively provided.

  The gate control unit 60 corresponds to the memory regions BLK <0>, BLK <1> and the spare memory region SBLK of the block BU in addition to the gate transistors SG arranged in the gate transistor regions SGA0 and SGA1, respectively. Sub-gate control units 160a, 160b and 160c for controlling the electrical connection with the sense amplifier band SAG. Gate control unit 60 includes sub-gate control units 161a, 161b, 161c provided corresponding to memory regions BLK <0>, BLK <1> and spare memory region SBLK of block BU #, respectively.

  The sub gate control unit 160a includes 16 gate control units IO0 to IO15. Specifically, gate control units IO are provided corresponding to 16 main bit lines. One gate control unit IO is composed of four sub control units SIO, and one sub control unit SIO is provided corresponding to a set of four bit lines.

  The sub control unit SIO includes a reset unit BRSTG0 and a column selection circuit CASG0.

  Reset unit BRSTG0 electrically couples corresponding bit lines MBL0-MBL3 to ground voltage GND in response to the input of control signals BRSTA <0> -BRSTa <3> ("H" level), respectively. To reset to 0V.

  Column selection circuit CASG0 electrically couples one of main bit lines MBL0 to MBL3 and the corresponding BDE line in response to inputs of control signals CALa <0> to CALa <3> and CAU0. Note that the control signals CAL and CAU described above are simply described by collectively referring to the control signals CALa <0> to CALa <3> and CAU0.

  Here, the gate control unit IO0 transmits a 4-bit data signal to the data lines BDE0 to BDE3 based on the inputs of the control signals CAL and CAU. Therefore, considering the entire sub-gate control unit 160a, a 64-bit data signal is transmitted to the sense amplifier band via the data lines BDE0 to BDE63.

  Next, consider the sub-gate control unit 160b on the memory region BLK <1> side. Sub-gate controller 160b has the same configuration as sub-gate controller 160a, and instead of control signals CALa <3: 0> and BRSTA <3: 0> output from sub-column decoder 126a on the memory area BLK <1> side. In addition, the control signals CALb <3: 0> and BRSTb <3: 0> are output from the sub column decoder 126b, and the same column selection operation as described above is performed.

  Specifically, 64-bit data signals are transmitted to the data lines BDE0 to BDE63 from the gate control units IO0 to IO15 of the sub-gate control unit 160b.

  In this configuration, the memory regions BLK <0> and BLK <1> share the sense amplifier SA provided in the sense amplifier band SAG, and share the data line BDE with the sub-gate control unit SIO in each memory region BLK.

  The data signal transmitted to sense amplifier band SAG is amplified as read data SAOUT <63: 0> and transmitted to data output circuit 50.

  On the other hand, for spare area SBLK, sub-gate control unit 160c is provided corresponding to spare area SBLK. Spare region SBLK has spare main bit lines SMBLa0, SMBLa1, SMBLb0, and SMBLb1 and main bit line MBLc as described above, and sub-gate control unit 160c responds to control signal CALsp and control signal CAU0 in spare bits. The line SMBL or the main bit line MBL is selected. The control signal CALsp is a generic term for signals for selecting each spare bit line SMBL and main bit line MBL. Here, the main bit line MBLc is a so-called main bit line for a lock bit, as described above, and is not used in a normal redundant operation, and transmits a predetermined data signal at a predetermined command. In this example, the main bit line MBLc is arranged between the spare bit lines SMBLa and SMBLb. In this example, it is assumed that spare column decoder 125c selects one of two spare bit lines SMBLa and two spare bit lines SMBLb in parallel and performs a redundant replacement operation.

  Spare bit lines SMBLa0 and SMBLa1, main bit line MBLc, and spare bit lines SMBLb0 and SMBLb1 are electrically coupled to data lines BDEsp0 to BDEsp4, respectively.

  Spare column decoder 125c selects two spare bit lines out of four spare bit lines SMBLa0, SMBLa1, SMBLb0, and SMBLb1 of spare block SBLK based on internal address IAD to provide spare sense amplifier band SSAG. The data signal is transmitted to.

  In this configuration, spare sense amplifier band SSAG has two sense amplifiers SA, and read data SAOUT # <1: 0> is output to data output circuit 50 from spare sense amplifier band SSAG.

  The data output circuit 50 uses the read data SAOUT # <1: 0> read from the spare area SBLK based on the internal address IAD for some bits of the normal read data SAOUT <63: 0> read from the memory area BLK. A data swap circuit 51 to be replaced is included.

  The lock bit bit line MBLc of this configuration is a bit line that transmits special data in a special command and is not normally selected. Therefore, when reading special data such as lock bit information, other spare bit lines are read. SMBL resets spare bit line SMBL in response to the input of control signals BRSTspa and BRSTspb ("H" level). Therefore, the influence of coupling noise is suppressed. Conversely, the bit line MBLc is reset during normal access. Accordingly, along with this, even if spare bit lines SMBLa1 and SMBLb0 are simultaneously selected, the bit line MBLC arranged in the center works as a shield wiring and coupling noise is suppressed.

  FIG. 19 is a cross-sectional structure diagram illustrating a wiring structure of data line BDE electrically coupled to the sense amplifier band between ZZ # of FIG.

  In this example, a configuration for suppressing coupling noise of the data line BDE will be described. Although the sub-column decoder 125a side and the sub-column decoder 126a side are shown here, since they have the same configuration, the sub-column decoder 125a side will be described representatively.

  As shown in FIG. 19, the data line BDE from the memory region BLK <0> is formed on the first (1M) metal wiring layer 202 of the upper layer of the sub column decoder 125a provided on the substrate 201, and the sense The amplifier band SAG and the contact hole 213 are electrically coupled. Further, a power supply line to which the voltage VCC used in the sub-column decoder 125a is supplied is formed on the metal wiring layer 203 of the second layer (2M) which is an upper layer of the first layer (1M). Further, a ground line to which the ground voltage GND used in the sub column decoder 125a is supplied is formed in the same second layer (2M) metal wiring layer 204. In addition, a control line for transmitting a control signal CTL used in the sub-column decoder 125a is formed in the metal wiring layer 205 of the third layer (3M), which is an upper layer of the second layer (2M).

  On the other hand, on the sense amplifier band SAG side, a ground line to which the ground voltage GND used in the sense amplifier band SAG is supplied is formed in the second metal wiring layer 209 which is the upper layer of the metal wiring layer 202. In addition, a power supply line to which the voltage VCC used in the sense amplifier band SAG is supplied is formed in the second metal wiring layer 212 which is the upper layer of the metal wiring layer 202. Also, a control line for transmitting a control signal CTL used in the sense amplifier band SAG to the metal wiring layer 210 of the third layer (3M) above the second layer (2M), and a sense operation of the sense amplifier band SAG. A sense power supply line 211 to which a predetermined voltage is supplied is formed.

  In this configuration, since the memory region BLK <0> and BLK <1> share the data line BDE, the memory region BLK <1> is formed using the second (2M) metal wiring layers 207 and 208. The data signal is transmitted and is electrically coupled to the data line BDE of the metal wiring layer 202 of the first layer (1M) through the contact hole 214.

  In addition, a ground line for supplying the ground voltage GND is formed on the third (3M) metal wiring layer 206, which is an upper layer of the metal wiring layers 207 and 208, and the second layer (2M) is connected via the contact holes 215 and 216, respectively. And the metal wiring layers 204 and 209 of FIG. That is, this structure is a structure in which the ground line is formed in the third layer (3M), which is the upper layer of the data line BDE running through the second layer (2M).

  With this structure, the influence from the coupling noise from the metal wiring layers 205 and 210 to which the control signal CTL used for the column decoder 125a and the sense amplifier band SAG is transmitted to the data line BDE running on the second layer (2M). Can be suppressed.

  FIG. 20 is used to share data line BDE provided corresponding to memory region BLK <0> and memory region BLK <1> in data line BDE electrically coupled to a sense amplifier used as a share. It is a figure explaining the arrangement | positioning system of the connection wiring of this invention.

  As shown in FIG. 20, in this configuration, the data line of the memory region BLK <0> and the data line of the memory region BLK <1> are the first of the data lines of the memory region BLK <0>. The data line of the memory region BLK <1> electrically coupled to the data line of the first group located in the first region and the second region among the data lines of the memory region BLK <0>. Memory regions BLK <1> electrically coupled to the two groups of data lines are alternately arranged. By adopting this configuration, it is possible to reduce the capacitance between adjacent connection wirings, and to further reduce coupling noise.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1 memory device, 5 address buffer, 10 control circuit, 15 voltage generation circuit, 20 voltage distribution circuit, 25 selection circuit, 30 predecoder, 35 sense amplifier control circuit, 45 input / output buffer, 50 data output circuit, 55 read / write Control circuit, 60 gate control unit, 65 word line / source line driver band, 70 memory array.

Claims (2)

A memory array having a plurality of memory cells arranged in a matrix;
A plurality of first data lines for transmitting read data to the memory array;
A sense amplifier for amplifying the read data transmitted to the plurality of first data lines;
A control signal line that is disposed along the same direction as the plurality of first data lines and that transmits a control signal for controlling the sense amplifier;
A first power supply line arranged along the same direction as the plurality of first data lines and supplying a fixed voltage used for the operation of the sense amplifier;
A second power supply line that is arranged along the same direction as the plurality of first data lines and that supplies the fixed voltage used for the operation of a peripheral circuit;
The plurality of first data lines are formed in the same wiring layer as the first and second power supply lines, and are disposed between the first and second power supply lines,
The control signal lines adjacent to the plurality of first data lines are formed in a wiring layer different from the wiring layer,
The non-volatile memory device, wherein the first power line and the second power line are electrically coupled using a contact hole so as to cover the plurality of first data lines using the different wiring layers. A plurality of second data lines provided corresponding to the plurality of first data lines, each of which is electrically coupled to the corresponding first data line and transmits the read data to the sense amplifier; In addition,
The plurality of first data lines and the plurality of second data lines are orthogonal to each other,
A first data line electrically coupled to a first group located in a first region of the plurality of second data lines; and a second of the plurality of second data lines. 2. The nonvolatile memory device according to claim 1, wherein the first data lines electrically coupled to the second group located in the region are alternately arranged.

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