JP2009224364A - Container of semiconductor chip, and process for manufacturing semiconductor device - Google Patents

Abstract

A semiconductor chip storage container capable of reducing breakage of a semiconductor chip during transportation of the semiconductor chip, and a semiconductor device manufacturing method using the storage container.
In a chip tray 10, a first cushioning material 12 is provided in a first recess 11A formed on a first plate 11, and the surface of a second plate 13 facing the first recess 11A is provided. Is provided with a second cushioning material 14. When the first plate 11 and the second plate 13 are overlaid, the semiconductor chip 15 is stored between the first buffer material 12 and the second buffer material 14 in the space 11C of the first recess 11A. Is done. Thereby, an impact during transportation of the chip tray 10 is less likely to be applied to the semiconductor chip 15, and damage to the semiconductor chip 15 can be prevented. In addition, since at least one of the first buffer material 12 and the second buffer material 14 is made of a conductive material, the semiconductor chip 15 can be prevented from being damaged or damaged by static electricity.
[Selection] Figure 2

Description

  The present invention relates to a storage container for storing a semiconductor chip and a method for manufacturing a semiconductor device using the storage container.

  Conventionally, a flat chip tray or a tape-shaped chip storage body is known as one of storage containers for efficiently transporting a plurality of semiconductor chips. For example, as shown in FIG. 8, a plurality of recesses 111A are arranged on the surface of the chip tray 111, and the semiconductor chip 115 is placed in the recesses 111A. The semiconductor chip 115 is transported while being held on the chip tray 111.

The chip tray is described in Patent Document 1.
JP 2001-97349 A

  However, the semiconductor chip 115 placed in the recess 111 </ b> A of the chip tray 111 may be damaged due to mechanical stress applied by an impact during transportation of the chip tray 111.

  The semiconductor chip storage container of the present invention has been made in view of the above problems, and includes a first plate having a first recess formed on the surface and a first plate provided in the first recess. A second cushioning material, a second plate that can be superimposed on the surface of the first plate, and a second cushioning material provided on the surface of the second plate facing the first recess, A semiconductor chip is housed between the first buffer material and the second buffer material.

  Further, in the semiconductor chip storage container of the present invention, in the above configuration, the second recess is formed on the surface of the second plate so as to face the first recess, and the second cushioning material is the second recess. It is provided inside.

  The semiconductor chip storage container of the present invention includes a plurality of plates that can be stacked on top of each other, a first recess formed on the surface of the plate, and a first recess provided in the first recess. A cushioning material and a second cushioning material provided on the back surface of the plate so as to overlap the first recess, and in the two plates stacked on each other, the first cushioning material of the lower layer plate, A semiconductor chip is housed between the second buffer material of the upper layer plate.

  In the semiconductor chip storage container of the present invention, in the above configuration, the second recess is formed on the back surface of the plate so as to overlap the first recess, and the second cushioning material is provided in the second recess. It is characterized by being.

  The semiconductor chip storage container of the present invention has a storage member having a semiconductor chip storage portion, a first buffer material provided in the storage portion, and a second buffer material bonded to the surface. And a tape base material that covers the storage portion and can be attached to the storage member. The semiconductor chip is stored between the first buffer material and the second buffer material.

  In the semiconductor chip storage container of the present invention, in any one of the above-described configurations, at least one of the first buffer material and the second buffer material is obtained by adding carbon particles to a base material containing an organic resin, for example. It consists of the electroconductive material which becomes.

  The semiconductor device manufacturing method of the present invention includes a first step of back grinding a semiconductor wafer, a second step of dicing the back ground semiconductor wafer into a plurality of semiconductor chips, and a semiconductor chip. A third step of transporting to the next step, wherein the third step includes a first plate in which a recess is formed and a first cushioning material is provided in the recess, and a second plate on the surface. And a second plate provided with the buffer material, the first plate and the second plate are overlapped, and the semiconductor chip is accommodated between the first buffer material and the second buffer material. It is characterized by being transported.

  According to the semiconductor chip storage container and the semiconductor device manufacturing method using the storage container of the present invention, damage to the semiconductor chip due to impact or the like can be reduced during transport of the semiconductor chip.

[First Embodiment]
In the first embodiment of the present invention, a case where a semiconductor chip storage container is a chip tray will be described with reference to the drawings. FIG. 1 is a plan view showing a semiconductor chip storage container according to the present embodiment, showing only a planar configuration of a first plate 11 and its first recess A, which will be described later, and omitting the other components. ing. 2 is a cross-sectional view taken along the line XX of FIG. 1, and FIG. 2A shows a state before a first plate 11 and a second plate 13 described later are overlapped. FIG. 2B shows a state when the first plate 11 and the second plate 13 are overlapped. FIG. 3 is a cross-sectional view showing a case in which the semiconductor chip storage container according to the present embodiment includes a third plate 17 to be described later, and corresponds to a cross section taken along line XX in FIG.

  In the present invention, the semiconductor chip 15 to be stored is, for example, a CSP (Chip Size Package) type semiconductor device that is attracting attention as a new packaging technology, and a back grinding process for a semiconductor wafer and the back grinding process. The dicing process is performed on the thinned semiconductor wafer.

  Here, the CSP refers to a small package having an outer shape that is substantially the same size as the outer shape of the semiconductor chip. In order to increase the mounting density, the semiconductor chip needs to be thinned, and the semiconductor wafer needs to be thin.

  In the back grinding process, the semiconductor wafer is extremely thin for stacking, and is mechanically polished to, for example, about 50 μm to 150 μm. Even if the distortion due to the residual stress is removed by performing etching or the like of the semiconductor wafer after the back grinding process, the semiconductor wafer is easily broken because of its thinness. Further, since many films are formed on the surface of the semiconductor wafer, a difference in residual stress occurs between the front surface side and the back surface side of the semiconductor wafer, resulting in warping of the semiconductor chip 15.

  Further, in such a semiconductor wafer or semiconductor chip 15, a through electrode may be further formed. The semiconductor chip 15 of a model that employs a through electrode is mainly a laminated type, that is, an MCP (Multi Chip Package). In this case as well, the semiconductor wafer is made as thin as possible.

  After these steps, the chip tray 10 described below is used in the step of transporting the semiconductor chip 15 to the line where the next step (for example, bump electrode forming step) is performed.

  As shown in FIGS. 1 and 2A, in the chip tray 10, a plurality of first recesses 11A are provided on the surface of a first plate 11 made of, for example, plastic, and each of the first recesses 11A is provided. A first cushioning material 12 is provided inside. The bottom part and opening part of the 1st recessed part 12 are formed in rectangular shape, for example. The first buffer material 12 covers at least the bottom of the first recess 11A, and may extend to the side wall of the first recess 11A as necessary. Then, facing the first recess 11A of the first plate 11, a second plate 13 made of, for example, plastic and superposed on the surface of the first plate 11 is disposed. A second cushioning material 14 is provided on the surface of the second plate 13 facing the first recess 11 </ b> A of the first plate 11. The second cushioning material 14 is preferably formed separately for each first recess 11A so as to be fitted to each first recess 11A.

  At least one of the first buffer material 12 and the second buffer material 14 is made of a conductive material, and includes, for example, a material obtained by adding carbon particles to an organic resin. In this case, urethane resin or the like is used as the organic resin. The conductive material may be in the form of a fiber or a sponge having fine bubbles.

  As shown in FIG. 2B, when the first plate 11 and the second plate 13 are overlapped, the semiconductor chip 15 placed on the first cushioning material 12 has the first recess 11A. In the space 11 </ b> C, the space is stored between the first buffer material 12 and the second buffer material 14. The semiconductor chip 15 may be fixed by being sandwiched between the first buffer material 12 and the second buffer material 14, or may not be fixed.

  The thickness T1 of the first cushioning material 12 and the thickness T2 of the second cushioning material 14 do not necessarily match each other. Thicknesses T1 and T2 necessary for absorbing an impact during transportation of the chip tray 10 depend on the materials of the first buffer material 12 and the second buffer material 14. For example, when the material of the first cushioning material 12 and the second cushioning material 14 is a general sponge containing a plurality of bubbles that serve as cushioning, the thicknesses T1 and T2 are reduced to reduce the specified impact. It needs to be as thick as possible. On the other hand, when the material of the first cushioning material 12 and the second cushioning material 14 is a packing material that absorbs impact even if it is thin, the thicknesses T1 and T2 are adjusted to the prescribed impact according to the material. It must be thick enough to withstand.

  Further, when the chip tray 10 is transported, the semiconductor chip 15 accommodated in the space 11C of the first recess 11A vibrates away from the first buffer material 12 or the second buffer material 14 in the space 11C. Should be reduced as much as possible. Therefore, the materials of the first buffer material 12 and the second buffer material 14 and the thicknesses T1 and T2 also depend on the thickness of the semiconductor chip 15. In addition, the distance D1 between the first buffer material 12 and the second buffer material 14 when the first plate 11 and the second plate 13 are overlaid also depends on the thickness of the semiconductor chip 15.

  Preferably, the thicknesses T1 and T2 of the first buffer material 12 and the second buffer material 14 are about one third of the thickness of the semiconductor chip 15, and the first plate 11 and the second plate 13 are the same. The distance D1 between the first cushioning material 12 and the second cushioning material 14 when the first cushioning material 12 and the second cushioning material 14 are overlapped is the thickness T1, T2 of the first cushioning material 12 and the second cushioning material 14. This is the reflected distance.

  As shown in FIG. 3, a plurality of third plates 17 may be overlapped between the first plate 11 and the second plate 13. In the example shown in the figure, two third plates 17 are overlaid, but more third plates 17 may be overlaid. A plurality of first recesses 17A are formed on the surface of the third plate 17, and the first cushioning material 12 is provided in each first recess 17A. A second cushioning material 14 is provided on the back surface of the third plate 17 so as to overlap the first recess 17A.

  In the two third plates 17 that are overlapped with each other, a semiconductor is interposed between the first buffer material 12 of the lower third plate 17 and the second buffer material 14 of the upper third plate 17. The chip 15 is stored. The second cushioning material 14 on the back surface of the lowermost third plate 17 opposes the first cushioning material 12 of the first plate 11 superimposed on the lower layer, and the uppermost third plate 17 The first cushioning material 12 on the surface is opposed to the second cushioning material 14 of the second plate 13 superimposed on the upper layer.

  The plurality of third plates 17 overlapped with each other is not formed between the first plate 11 and the second plate 13, and only the stacked body of the plurality of third plates 17 may be used as a chip tray. Good. Alternatively, a stacked body in which one third plate 17 is overlapped between the first plate 11 and the second plate 13 may be used as a chip tray.

  According to the chip tray 10 configured as described above, since the semiconductor chip 15 is accommodated between the first buffer material 12 and the second buffer material 14, the impact during the transportation of the chip tray 10 is applied to the semiconductor chip 15. It becomes difficult to join. Therefore, even if the semiconductor chip 15 is warped or distorted, or even if the semiconductor chip 15 is a very thin model, the semiconductor chip 15 can be prevented from being damaged as in the conventional example.

  Furthermore, since at least one of the first buffer material 12 and the second buffer material 14 is made of a conductive material, the friction between the first buffer material 12 or the second buffer material 14 and the semiconductor chip 15 The generation of static electricity due to contact between the pick-up jig and the semiconductor chip 15 or the like can be suppressed. That is, the destruction and damage of the semiconductor chip 15 due to static electricity can be prevented.

[Second Embodiment]
Hereinafter, as a second embodiment of the present invention, a modification of the chip tray 10 of the first embodiment will be described with reference to the drawings. FIG. 4 is a cross-sectional view showing the semiconductor chip storage container, that is, the chip tray 30 according to the present embodiment. The planar configuration of the chip tray 30 is the same as the planar configuration of FIG. 1 in the first embodiment, and FIG. 4 corresponds to a cross section taken along line XX of FIG. FIG. 4A shows a state before the first plate 11 and the second plate 33 are overlaid, and FIG. 4B shows a state when the first plate 11 and the second plate 33 are overlaid. Shows the state. FIG. 5 is a cross-sectional view showing the case where the semiconductor chip storage container according to the present embodiment includes the third plate 37, and corresponds to a cross section taken along line XX of FIG. 4 and 5, the same components as those shown in FIGS. 1 to 3 are denoted by the same reference numerals.

  As shown in FIG. 4A, in the chip tray 30, the first plate 11 is opposed to the first concave portion 11A and is made of, for example, plastic and can be superimposed on the surface of the first plate 11. Two plates 33 are arranged. A plurality of second recesses 33 </ b> A are formed on the surface of the second plate 33 so as to face the first recesses 11 </ b> A formed on the first plate 11. The bottom and opening of the second recess 33A are formed in a rectangular shape, for example, corresponding to the first recess 11A. A second cushioning material 34 is provided in the second recess 33A. The second cushioning material 34 covers at least the bottom of the second recess 33A, and may extend to the side wall of the second recess 33A as necessary. At least one of the first buffer material 12 and the second buffer material 14 is made of the same conductive material as that of the first buffer material 12 in the first embodiment.

  As shown in FIG. 4B, when the first plate 11 and the second plate 33 are overlapped with each other, the semiconductor chip 15 placed on the first buffer material 12 has the first recess 11A and In the space 33 </ b> C of the second recess 33 </ b> A, the space is accommodated between the first buffer material 12 and the second buffer material 34. The semiconductor chip 15 may be fixed between the first buffer material 12 and the second buffer material 34, or may not be fixed. The distance D2 between the first cushioning material 12 and the second cushioning material 34 when the first plate 11 and the second plate 33 are overlaid is such that the second recess 33A is formed on the second plate 33. The formed portion can be made larger than the distance D1 between the first buffer material 12 and the second buffer material 14 in the first embodiment. Or thickness T1 of the 1st shock absorbing material 12 or thickness T2 of the 2nd shock absorbing material 34 can be thickened compared with 1st Embodiment. However, the distance D2 may be the same as the distance D1 in the first embodiment, and the thicknesses T1 and T2 may be the same as in the first embodiment.

  As shown in FIG. 5, a plurality of third plates 37 may be overlapped between the first plate 11 and the second plate 33. In the example shown in the figure, two third plates 37 are overlapped, but more third plates 37 may be overlapped. A plurality of first recesses 37A are formed on the surface of the third plate 37, and a first cushioning material 32 is provided in each first recess 37A. A plurality of second recesses 37B are formed on the back surface of the third plate 37 so as to overlap the first recesses 37A, and a second cushioning material 34 is provided in the second recesses 37B. ing. The bottom and opening of the first recess 37A and the second recess 37B are formed in a rectangular shape, for example.

  In the two third plates 37 that are overlapped with each other, a semiconductor is interposed between the first buffer member 32 of the lower third plate 37 and the second buffer member 34 of the upper third plate 37. The chip 15 is stored. The second cushioning material 34 of the lowermost third plate 37 faces the first cushioning material 12 of the first plate 11 superimposed on the lower layer, and the first of the uppermost third plate 37. The buffer material 32 is opposed to the second buffer material 34 of the second plate 33 superimposed on the upper layer.

  Note that the plurality of third plates 37 stacked on each other are not formed between the first plate 11 and the second plate 33, and only a stack of the plurality of third plates 37 may be used as a chip tray. Good. Alternatively, a stacked body in which one third plate 37 is overlapped between the first plate 11 and the second plate 33 may be used as a chip tray.

  Also in the chip tray 30 having the above configuration, the same effect as that of the first embodiment can be obtained.

[Third embodiment]
Hereinafter, as a third embodiment of the present invention, a case in which a semiconductor chip storage container is wound around a reel in place of the chip trays 10 and 30 will be described with reference to the drawings. . Hereinafter, this storage container is referred to as a chip storage tape. FIG. 6 is a plan view showing the semiconductor chip storage container according to the present embodiment. FIG. 7 is a cross-sectional view taken along line YY of FIG. In FIG. 6, only a planar configuration of a storage member 51 and a storage portion 51 </ b> A, which will be described later, is shown, and the other components are not shown.

  As shown in FIGS. 6 and 7, in this chip storage tape 50, a plurality of storage portions 51A are formed on a storage member 51 having elasticity such as plastic by blow molding or the like. A first cushioning material 52 is formed in the accommodating portion 51A so as to cover at least the bottom portion thereof. After the semiconductor chip 15 is placed in the storage portion 51A, the storage member 51 is secondly bonded to the surface of the tape base material 53 so as to face the first buffer material 52 of each storage portion 51A. The buffer material 54 is affixed. In this pasting, as long as the first cushioning material 52 and the second cushioning material 54 face each other, the second cushioning material 54 does not have to be adhered to the entire tape base 53, and the storage member 51 and the tape The base material 53 may be stuck in contact. Thereby, the semiconductor chip 15 is accommodated between the first buffer material 52 and the second buffer material 54 in the space 51C of the storage part 51A. The semiconductor chip 15 may be fixed by being sandwiched between the first buffer material 52 and the second buffer material 54 or may not be fixed.

  The materials and thicknesses of the first buffer material 52 and the second buffer material 54 are the same as those of the first buffer material 12 and the second buffer material 14 in the first embodiment. Further, the distance D3 between the first buffer material 52 and the second buffer material 54 depends on the thickness of the semiconductor chip 15 as in the case of the distance D1 in the first embodiment.

  Also in the chip storage tape 50 having the above configuration, the same effect as that of the first embodiment can be obtained.

  Needless to say, the present invention is not limited to the above-described embodiments, and modifications can be made without departing from the scope of the invention. For example, in the first embodiment and the second embodiment, the shapes of the first recesses 11A, 17A, and 37A and the second recesses 33A and 37B may be other than a rectangular shape, and only the semiconductor chip 15 is used. Instead, the semiconductor wafer before the dicing process is stored may be stored.

It is a top view which shows the storage container of the semiconductor chip by the 1st Embodiment of this invention. It is sectional drawing which shows the storage container of the semiconductor chip by the 1st Embodiment of this invention. It is sectional drawing which shows the storage container of the semiconductor chip by the 1st Embodiment of this invention. It is sectional drawing which shows the storage container of the semiconductor chip by the 2nd Embodiment of this invention. It is sectional drawing which shows the storage container of the semiconductor chip by the 2nd Embodiment of this invention. It is a top view which shows the storage container of the semiconductor chip by the 3rd Embodiment of this invention. It is sectional drawing which shows the storage container of the semiconductor chip by the 3rd Embodiment of this invention. It is sectional drawing which shows the storage container of the semiconductor chip by a prior art example.

Explanation of symbols

10, 111 Chip tray 11 First plate 11A, 17A, 37A, 111A First recess 12, 32, 52 First buffer material 13, 33 Second plate 14, 34, 54 Second buffer material 15, 115 Semiconductor wafers 17 and 37 Third plate 33A and 37B Second recess 50 Chip storage tape 51 Storage member 53 Tape base material

Claims (8)

A first plate having a first recess formed on the surface;
A first cushioning material provided in the first recess;
A second plate that can be superimposed on the surface of the first plate;
A second cushioning material provided on the surface of the second plate facing the first recess,
A semiconductor chip storage container, wherein a semiconductor chip is stored between the first buffer material and the second buffer material. 2. A second recess facing the first recess is formed on a surface of the second plate, and the second cushioning material is provided in the second recess. Item 14. A semiconductor chip storage container according to Item 1. A plurality of plates that can be stacked on top of each other;
A first recess formed on the surface of the plate;
A first cushioning material provided in the first recess;
A second cushioning material provided on the back surface of the plate overlapping the first recess,
A semiconductor chip characterized in that a semiconductor chip is housed between the first buffer material of a lower-layer plate and the second buffer material of an upper-layer plate in the two plates stacked on each other. Storage container. The second recess is formed on the back surface of the plate so as to overlap the first recess, and the second cushioning material is provided in the second recess. A storage container for the semiconductor chip as described. A housing member having a semiconductor chip housing portion;
A first cushioning material provided in the storage portion;
A second base material, and a tape base material that covers the storage unit and can be attached to the storage member; and between the first buffer material and the second buffer material. A semiconductor chip storage container, wherein a semiconductor chip is stored. 6. The semiconductor chip storage container according to claim 1, wherein at least one of the first buffer material and the second buffer material is made of a conductive material. . The semiconductor chip storage container according to claim 6, wherein the conductive material is formed by adding carbon particles to a base material containing an organic resin. A first step of back grinding a semiconductor wafer;
A second step of dicing the back-ground semiconductor wafer into a plurality of semiconductor chips;
A third step of transporting the semiconductor chip to the next step, and
In the third step, a recess is formed, and a first plate having a first cushioning material provided in the recess and a second plate having a second cushioning material provided on the surface are prepared. And
Manufacturing the semiconductor device, wherein the first plate and the second plate are overlapped, and a semiconductor chip is accommodated and transported between the first buffer material and the second buffer material. Method.

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