JP2006143246A - Tool for storage, and semi-conductor manufacturing method using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the cost price of a semi-conductor product by providing a plurality of pocket parts capable of storing semi-conductor chips. <P>SOLUTION: A tool for storage has a tray body part 4a in which a plurality of the pocket parts 4c capable of storing the semi-conductor chips respectively are arrayed in a lattice, and three kinds of recesses of different opening areas from each other are formed in a plurality of the pocket parts 4c in a stepped manner. Thus, the semi-conductor chips of three kinds of sizes, including a first semi-conductor chip 1, a second semi-conductor chip 2 and a third semi-conductor chip 3 of different sizes from each other can be stored in each pocket part 4c. Since the semi-conductor chips of a plurality of kinds of sizes can be stored in a tray of one kind, the kinds of trays 4 can be reduced, and the cost price of the semi-conductor products can be reduced thereby. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor manufacturing technique, and more particularly to a technique effective when applied to a semiconductor chip accommodation technique using a tray.

A conventional tray (tray) has a plate-shaped tray having a recessed receiving recess for storing an object (semiconductor chip) on the upper surface, and an object in the receiving recess that is stacked on the upper surface of the tray. A protective sheet, a cover overlaid on the upper surface of the tray, and a detachable fixture that integrally fixes a predetermined number of trays with protective sheets and a stack of the cover on the uppermost tray. And the said tray becomes a structure which mutually fits and overlaps (for example, refer patent document 1).
JP-A-10-194376 (FIG. 1)

  The separated semiconductor chips are mainly stored and transported in a resin-made dedicated jig (storage jig such as a tray) in order to be transported to a process of mounting on a semiconductor package. The size of the pocket is determined according to the size of the semiconductor chip to be stored so that the semiconductor chip does not move or break in the jig during transportation. A tray is manufactured for each type of semiconductor chip.

  Therefore, in order to accommodate various sizes of semiconductor chips, it is necessary to manufacture a tray having a pocket portion having a size corresponding to each chip size, so that the cost performance is very bad.

  An object of the present invention is to provide a technique capable of reducing the cost.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

  That is, the present invention has a plurality of pocket portions each capable of accommodating a semiconductor chip, and each of the plurality of pocket portions is formed with a plurality of types of recesses in a step shape, and It has the plurality of pocket portions formed so that the size of the concave portion becomes smaller toward the lower stage.

  Further, the present invention provides the plurality of recesses having a plurality of types of sizes in each of the plurality of pocket portions, and the plurality of recesses formed so that the size of the recesses decreases toward the lower level in the step. A step of preparing a storage jig having a pocket portion, and storing the same size or different sizes of semiconductor chips in the plurality of pocket portions with respect to the plurality of pocket portions of the storage jig. It has a process.

  Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  In the storage jig, a plurality of types of recesses are formed in a step shape in each of the plurality of pocket portions, and the plurality of recesses are formed such that the size of the recesses decreases toward the lower stage in the step. By having the pocket portion, it is possible to store a plurality of types of semiconductor chips with one type of storage jig, and therefore it is possible to reduce the cost of the semiconductor product.

  In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  Further, in the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments, but they are not irrelevant to each other unless otherwise specified. The other part or all of the modifications, details, supplementary explanations, and the like are related.

  Also, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), particularly when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and it may be more or less than the specific number.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

(Embodiment)
FIG. 1 is a plan view showing an example of the structure of a storage jig used in the semiconductor manufacturing method of the embodiment of the present invention, a cross-sectional view cut along the line AA, and can be stored in a pocket portion. FIG. 2 is a cross-sectional view showing an example of a structure in which a large-sized semiconductor chip is mounted in the storage jig shown in FIG. 1, and FIG. 3 is a plan view of the storage jig shown in FIG. 4 is a cross-sectional view showing an example of a structure in which a small semiconductor chip is mounted, FIG. 4 is a cross-sectional view showing an example of a method for arranging an interlayer material in the storage jig shown in FIG. 1, and FIG. 5 uses the interlayer material shown in FIG. 6 is a cross-sectional view showing an example of a laminated structure of the storage jig, FIG. 6 is a cross-sectional view showing a method of arranging an interlayer material according to a modification of the embodiment of the present invention, and FIG. 7 uses the interlayer material shown in FIG. Sectional drawing which shows an example of the laminated structure of a storage jig, FIG. 8 is a modification of embodiment of this invention Plan view showing a structure of a housing jig, FIG. 9 is the structure of the pocket portion of the housing jig shown in FIG. 8 is a plan view of a semiconductor chip of three sizes that can be accommodated in the pocket portion.

  In the present embodiment, a tray 4 that is a storage jig capable of storing a plurality of semiconductor chips and a semiconductor manufacturing method using the tray 4 will be described.

  First, the structure of the tray 4 will be described. As shown in FIG. 1, a tray main body 4a in which a plurality of pockets 4c, which are recesses for housing semiconductor chips, are arranged in a lattice shape, and a frame provided on the outer periphery thereof. And a plurality of pockets 4c each having a plurality of types of recesses formed in a stepped shape, and the recesses are formed such that the size of the recesses decreases toward the lower step. It is.

  That is, in each pocket 4c, the first recess 4d that is the recess having the largest opening area from the upper stage side, the second recess 4e that is the recess having the second largest opening area in the middle stage, and the smallest opening area in the lower stage The third concave portion 4f is formed in a state where a step is provided concentrically at the center of the pocket portion 4c, and a bottom surface 4g is formed at the center of the lower third concave portion 4f.

  That is, the tray 4 of the present embodiment has three types of recesses having different opening areas formed in steps in the respective pocket portions 4c.

  As a result, it is possible to store three types of semiconductor chips of the first semiconductor chip 1, the second semiconductor chip 2, and the third semiconductor chip 3, which are semiconductor chips of different sizes, in each pocket portion 4 c. It is. Here, the largest semiconductor chip is the first semiconductor chip 1, the medium semiconductor chip smaller than the first semiconductor chip 1 is the second semiconductor chip 2, and the smallest semiconductor chip is the third semiconductor chip. 3.

  Here, the length of one side of each concave portion in the pocket portion 4c is defined as E for the first concave portion 4d, F for the second concave portion 4e, and G for the third concave portion 4f, respectively. When the length of one side is X, the length X of one side of the semiconductor chip that can be stored in the first recess 4d is E> X ≧ F, and one side of the semiconductor chip that can be stored in the second recess 4e. The length X of the semiconductor chip is F> X ≧ G, and the length X of one side of the semiconductor chip that can be accommodated in the third recess 4f is X <G.

  In this way, semiconductor chips having different sizes can be stored in the recesses corresponding to the respective sizes in each pocket portion 4c. For example, FIG. 2 shows a state in which the largest first semiconductor chip 1 is accommodated in the first recess 4d having the largest opening area at the uppermost stage, and FIG. 3 shows the smallest third semiconductor chip 3 at the lower stage. Is shown in a state of being housed in the third recess 4f having the smallest opening area. In the third recess 4f, the third semiconductor chip 3 is supported by its bottom surface 4g.

  It should be noted that the depth of each recess is approximately the same as or slightly deeper than the thickness of the semiconductor chip housed therein.

  The tray 4 is preferably formed of, for example, an ABS (acrylonitrile-butadiene-styrene) resin capable of preventing charging.

  In the tray 4 (storage jig) of the present embodiment, a plurality of sizes of recesses (first recess 4d, second recess 4e, and third recess 4f) are formed in a stepped shape in each of the plurality of pockets 4c. In addition, since the size of the concave portion becomes smaller as it goes downward in the step, it becomes possible to store a plurality of types of semiconductor chips in the pocket portion 4c. The plurality of sizes of semiconductor chips can be stored in the tray 4.

  The tray 4 can also be stacked. That is, as shown in FIG. 5, when the trays 4 are stacked, the upper tray 4 serves as an upper lid of the lower tray 4. Furthermore, when stacking trays 4 and storing a plurality of semiconductor chips in multiple stages and carrying them, the interlayer material 5 is formed as shown in FIGS. 4 and 5 so that the semiconductor chips do not vibrate or rattle in the recesses. It is preferable to interpose.

  That is, when stacking the trays 4, the interlayer material 5 is interposed between the semiconductor chip housed in the pocket portion 4 c of the lower tray 4 and the upper tray 4 in each layer. The interlayer material 5 is, for example, a thin and flexible sheet-like material in which protective layers are formed on both front and back surfaces of a polyester film substrate, and the thickness is, for example, about 50 μm.

  In the case of the tray 4 according to the present embodiment, the pocket portion 4c is formed with the three-step concave portion, and thus the convex portion 5a is formed at a location corresponding to each pocket portion 4c in the interlayer material 5. By virtue of 5a, it is possible to prevent the semiconductor chip housed in the pocket portion 4c from vibrating or rattling. As shown in FIG. 4, the plurality of convex portions 5a formed on the interlayer material 5 all have the same amount of protrusion. For example, the convex amount Q of the convex portion 5a is the height of the concave portion at the lowest level from the surface of the pocket portion 4c. It is preferable that the depth P is approximately equal to the support surface of the upper step (here, the second recess 4e in the middle step).

  As a result, the semiconductor chip housed in the lowermost concave portion (here, the third concave portion 4f) is the limit as to whether or not the convex portion 5a comes into contact with the semiconductor chip. Even if it continues, these can be suppressed by the convex part 5a. Furthermore, the semiconductor chip housed in the uppermost concave portion (here, the first concave portion 4d) or the middle concave portion (here, the second concave portion 4e) has the convex portion 5a in contact with the semiconductor chip. The rattling can be surely prevented.

  Thus, the convex part 5a is formed in the location corresponding to each pocket part 4c in the interlayer material 5, and also the convex amount of the convex part 5a is one of the concave parts at the lowest level from the surface of the pocket part 4c. Since the depth to the support surface of the upper step (here, the second concave portion 4e in the middle step) is approximately equal to the support surface, all the concave portions are transported to the semiconductor chips accommodated in these concave portions. The vibration or backlash of the semiconductor chip such as time can be suppressed or prevented by the convex portion 5a.

  That is, since the interlayer material 5 is a thin and flexible sheet, even when the amount of warpage of the interlayer material 5 varies depending on the size of the semiconductor chip, the pressure applied to the semiconductor chip is sufficiently high. Therefore, no damage is formed on the semiconductor chip. Further, the semiconductor chip does not jump out of the pocket portion 4c during transportation or the like, and the positional relationship between the semiconductor chip and the recess does not shift. .

  For example, in the case of a semiconductor chip having a thickness of 300 μm, if the pressure applied from the outside is about 2 MPa or less, the semiconductor chip is not damaged by the load received from the interlayer material 5, and therefore the semiconductor chip is removed from the protrusion 5 a. It is preferable that the load received is sufficiently smaller than 2 MPa.

  Next, in the semiconductor manufacturing method of the present embodiment, the semiconductor chip is accommodated in each pocket portion 4c of the tray 4 shown in FIG. 1, and further, in each layer as shown in FIG. A plurality of trays 4 are stacked in multiple layers with an interlayer material 5 interposed between the semiconductor chip housed in the portion 4c and the upper layer side tray 4, and then transported to the next process in a state where the trays 4 are stacked. It is.

  Thereby, even when the semiconductor chip is transported, it is possible to suppress or prevent the vibration and backlash of the semiconductor chip accommodated in the concave portions of all the steps. As a result, it is possible to prevent the semiconductor chip from being broken or damaged during transportation.

  When the trays 4 are stacked and transported in multiple stages as shown in FIG. 5, it is preferable to bundle and transport the trays 4 stacked in multiple stages.

  According to the tray 4 and the semiconductor manufacturing method using the same according to the present embodiment, a plurality of types of recesses are formed in a step shape in each of the plurality of pockets 4c, and the recesses become lower in the step. Is formed so that the size of the plurality of semiconductor chips can be accommodated in the pocket portion 4c. As a result, a plurality of types of sizes can be stored in one type (one specification) of the tray 4. The semiconductor chip can be accommodated.

  Therefore, the types (specifications) of the tray 4 can be reduced, and as a result, the cost of the semiconductor product can be reduced.

  Next, a storage jig (tray) according to a modification of the present embodiment will be described.

  FIG. 6 shows a modified interlayer material 6. The interlayer material 6 is preferably formed of a material having a substantially uniform thickness and being flexible and having sufficient stretchability. The material is, for example, low-resilience urethane. Further, the thickness is, for example, similar to the length P shown in FIG. 4, from the surface of the pocket portion 4 c to the support surface of the step one level above the lowermost recess (here, the second recess 4 e in the middle step). It is preferable to be approximately equal to the depth of.

  By using such an interlayer material 6, as shown in FIG. 7, when stacking the tray 4, in each layer, the semiconductor chip housed in the pocket portion 4 c of the lower layer side tray 4 and the upper layer side tray are disposed. Interlayer material 6 is interposed between the plurality of trays 4 and a plurality of trays 4 are stacked in multiple stages, and transport or the like is performed in this state. As a result, as in the case of the stacked state shown in FIG. 5, the vibration and backlash of the semiconductor chips housed in these recesses can be suppressed or prevented with respect to the recesses of all steps. As a result, it is possible to prevent the semiconductor chip from being broken or damaged during transportation.

  Next, FIG. 8 shows a tray 7 which is a storage jig of a modified example. Like the tray 4, the tray 7 includes a tray main body portion 7a and a frame portion 7b, and the tray main body portion 7a has a plurality of pocket portions 7c arranged in a lattice pattern. Further, in each pocket portion 7c, a first concave portion 7d, a second concave portion 7e, and a third concave portion 7f, which are concave portions of a plurality of sizes, have the same bottom surface 7g, and the bottom surface 7g Each of the types is formed in a horizontal direction so as to be shifted in the rotation direction.

  That is, in each pocket portion 7c, concave portions of a plurality of types of sizes are formed by changing the angle in the rotational direction little by little with respect to the common bottom surface 7g.

  As a result, like the tray 4, each pocket portion 7c of the tray 7 has three types of semiconductor chips (first semiconductor chip 1 and second semiconductor chip 2) corresponding to the sizes of the three types of recesses. And the third semiconductor chip 3) can be accommodated.

  As shown in FIG. 9, the length of one side of each recess in the pocket portion 7c is set to E for the first recess 7d, F for the second recess 7e, and G for the third recess 7f, respectively. A semiconductor that can be stored in the first recess 7d, where H is the distance between the two intersections of each side of 7d and the third recess 7f, and X is the length of one side of the semiconductor chip that can be stored in each recess. The length X of one side of the chip is E> X ≧ F, and the length X of one side of the semiconductor chip that can be stored in the second recess 7e is F> X ≧ G, and the third recess 7f The length X of one side of the storable semiconductor chip is G> X ≧ H.

  In this way, semiconductor chips having different sizes can be stored in the recesses corresponding to the size of each semiconductor chip in each pocket portion 4c.

  Accordingly, in the tray 7 according to the modified example, similarly to the tray 4, it is possible to store a plurality of types of semiconductor chips in the pocket portion 7 c, so that one type (one specification) of the tray 7 has a plurality of types of sizes. A semiconductor chip can be accommodated.

  As a result, the types (specifications) of the tray 7 can be reduced, and as a result, the cost of the semiconductor product can be reduced.

  Although the invention made by the present inventor has been specifically described based on the embodiments of the invention, the present invention is not limited to the embodiments of the invention, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

  For example, in the above-described embodiment, the case where the number of the recessed portions formed in the pocket portions 4c and 7c of the tray 4 and the tray 7 is three has been described. However, the number of the recessed portions formed in one pocket portion 4c and 7c. May be any number as long as it is two or more.

  Further, in the above-described embodiment, the case of the storage jig (tray 4, 7) in which the storage jig can be stacked has been described, but the storage jig has a plurality of types of recesses formed in each pocket portion. If it is, it may be of a single layer structure type that cannot be laminated.

  Furthermore, even if it is a stackable storage jig or a single layer structure type storage jig that cannot be stacked, it is stored in the uppermost layer during transportation or storage. A dedicated lid 8 (see FIGS. 5 and 7) may be disposed on the upper side of the jig.

  The present invention is suitable for a semiconductor manufacturing method.

The top view which shows an example of the structure of the storage jig | tool used with the semiconductor manufacturing method of embodiment of this invention, sectional drawing cut | disconnected along the AA line, and three types which can be accommodated in a pocket part It is a top view of a semiconductor chip of size. It is sectional drawing which shows an example of the structure which mounted the large sized semiconductor chip in the storage jig | tool shown in FIG. It is sectional drawing which shows an example of the structure which mounted the small semiconductor chip in the storage jig | tool shown in FIG. It is sectional drawing which shows an example of the arrangement | positioning method of an interlayer material in the storage jig | tool shown in FIG. It is sectional drawing which shows an example of the laminated structure of the storage jig | tool using the interlayer material shown in FIG. It is sectional drawing which shows the arrangement | positioning method of the interlayer material of the modification of embodiment of this invention. It is sectional drawing which shows an example of the laminated structure of the storage jig | tool using the interlayer material shown in FIG. It is a top view which shows the structure of the storage jig | tool of the modification of embodiment of this invention. It is a top view of the structure of the pocket part of the storage jig | tool shown in FIG. 8, and the semiconductor chip of three types of sizes which can be accommodated in this pocket part.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 1st semiconductor chip 2 2nd semiconductor chip 3 3rd semiconductor chip 4 Tray (storage jig | tool)
4a Tray body part 4b Frame part 4c Pocket part 4d 1st recessed part 4e 2nd recessed part 4f 3rd recessed part 4g Bottom face 5 Interlayer material 5a Convex part 6 Interlayer material 7 Tray (storage jig)
7a Tray body part 7b Frame part 7c Pocket part 7d 1st recessed part 7e 2nd recessed part 7f 3rd recessed part 7g Bottom face 8 Lid

Claims (5)

  A storage jig having a plurality of pocket portions each capable of storing a semiconductor chip, wherein each of the plurality of pocket portions is formed with a plurality of types of recesses in a step shape, and at the bottom of the step. A storage jig comprising the plurality of pocket portions formed so that the size of the concave portion decreases as it goes.   Each of the plurality of pockets has a plurality of pockets, each of which has a plurality of pockets capable of storing a semiconductor chip, and each of the plurality of pockets has a plurality of types of recesses formed in a step shape, and In the step, the plurality of pocket portions are formed so that the size of the concave portion becomes smaller toward the lower step, and when the storage jig is stacked, the storage jig on the lower layer side A storage jig, wherein an interlayer material is interposed between the semiconductor chip stored in the pocket portion and the storage jig on the upper layer side.   A storage jig having a plurality of pocket portions each capable of storing a semiconductor chip, each of the plurality of pocket portions having a plurality of types of recesses, each having the same bottom surface, and A storage jig characterized by being formed so as to be shifted in the rotational direction for each of the types in a direction horizontal to the bottom surface. (A) The plurality of pocket portions each having a plurality of types of recesses formed in a step shape in each of the plurality of pocket portions, and the recesses becoming smaller in size toward the lower step in the step. A step of preparing a storage jig having,
(B) A step of storing a semiconductor chip of the same size or a different size in the plurality of pocket portions with respect to the plurality of pocket portions of the storage jig. Method. (A) The plurality of pocket portions each having a plurality of types of recesses formed in a step shape in each of the plurality of pocket portions, and the recesses becoming smaller in size toward the lower step in the step. And a step of preparing a stackable storage jig,
(B) storing a semiconductor chip of the same size or a different size in the plurality of pocket portions with respect to the plurality of pocket portions of the storage jig;
(C) An interlayer material is disposed on the semiconductor chip stored in the pocket portion of the storage jig, the semiconductor chip stored in the pocket portion of the storage jig on the lower layer side, and the storage layer on the upper layer side Laminating the storage jig with the interlayer material interposed between the jig,
(D) After the step (c), the method includes a step of transporting the storage jig in a stacked state.

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