JP2009212300A - Back grinding method of semiconductor wafer, dicing method of semiconductor wafer, and method of mounting semiconductor chip - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a back grinding method of a semiconductor wafer, a dicing method of the semiconductor wafer, and a method of mounting a semiconductor chip, which prevent the degradation of performance of an adhesive layer formed on a semiconductor wafer. <P>SOLUTION: The back grinding method of the semiconductor wafer 10 includes: an adhesive layer formation step wherein an insulating adhesive layer 13 is formed on the principal plane S1 of the semiconductor wafer 10 in such a manner as to embed a salient electrode 10a; a tape installation step wherein a back grinding tape BT is installed on the insulating adhesive layer 13 formed in the adhesive layer formation step; and a grinding step wherein the backside S2 of the semiconductor wafer opposite to the face whereon the back grinding tape BT is installed is ground to thin the semiconductor wafer 10. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor wafer back grinding method, a semiconductor wafer dicing method, and a semiconductor chip mounting method.

Conventionally, as a technique in such a field, a semiconductor device manufacturing method described in Patent Document 1 below is known. In the manufacturing method described in this document, a wafer processing tape having an adhesive layer and an adhesive layer on a base film is prepared. Then, the back grinding process of the semiconductor wafer is performed in a state where the processing tape is bonded to the surface of the semiconductor wafer where the convex electrodes are formed.
JP 2006-49482 A

  In backgrinding of a semiconductor wafer, it is necessary to apply a load evenly over the entire wafer surface, and the wafer processing tape is required to be attached to the wafer without biting air voids or the like. However, in order to paste the semiconductor wafer on which the convex electrode is formed without air voids, the convex electrode is heated by mechanical pressure such as a pressure roller or pressure by air pressure in a state where the viscosity of the tape is lowered. It is necessary to stick around the air void so that it does not bite.

  However, when the wafer processing tape on which the pressure-sensitive adhesive layer and the adhesive layer are formed is heated and pressed, component diffusion of the pressure-sensitive adhesive layer and the adhesive layer occurs, and fusion occurs. For this reason, there is a problem that it is difficult to peel the base film and the pressure-sensitive adhesive layer from the adhesive layer after the back grinding process. Furthermore, component transfer between the pressure-sensitive adhesive layer and the adhesive layer occurs during long-term storage, making it more difficult to peel off. Furthermore, even when peeled off, there is a problem that the properties as an adhesive are hindered by the component transfer of the adhesive material component into the adhesive.

  Accordingly, the present invention provides a semiconductor wafer back-grinding method, a semiconductor wafer dicing method, and a semiconductor chip mounting method that solve the above-described problems and suppress performance degradation of the adhesive layer formed on the semiconductor wafer. For the purpose.

  A backgrinding method of a semiconductor wafer according to the present invention is a backgrinding method for thinning a semiconductor wafer in which protruding electrodes protrude from the main surface, and is formed on the main surface of the semiconductor wafer so as to embed the protruding electrodes. Adhesive layer forming process for forming an adhesive layer, a tape installation process for installing a back grind tape on the adhesive layer formed in the adhesive layer forming process, and a side opposite to the surface on which the back grind tape is installed And a grinding step of grinding the back surface of the semiconductor wafer positioned to thin the semiconductor wafer.

  In this back grinding method, when grinding the back surface of a semiconductor wafer, an adhesive layer is first formed on the main surface of the semiconductor wafer in an adhesive layer forming step, and then a back grind tape can be installed. That is, the process of forming an adhesive layer by heating and pressing to suppress the biting of air voids on the semiconductor wafer on which convex electrodes are formed, and the installation of a back grind tape that does not require heating and pressing The steps can be performed sequentially and separately. Therefore, fusion and component transfer due to heating and pressurization between the adhesive layer and the back grind tape can be avoided. As a result, it is possible to suppress the difficulty in peeling off the back grind tape after the grinding process and the deterioration of the performance of the adhesive layer due to the component transfer.

  A dicing method for a semiconductor wafer according to the present invention is a dicing method for separating a semiconductor wafer in which protruding electrodes protrude from a main surface, and is bonded onto the main surface of the semiconductor wafer so as to embed the protruding electrodes. Position on the opposite side of the surface on which the backgrind tape is installed, and the adhesive layer formation process for forming the adhesive layer, the tape installation process for installing the backgrind tape on the adhesive layer formed in the adhesive layer formation process Grinding the back surface of the semiconductor wafer to be thinned and thinning the semiconductor wafer, and the dicing process of dicing the back grind tape, adhesive layer and semiconductor wafer laminate obtained from the grinding process from the back grind tape side And.

  In this dicing method, when grinding the back surface of a semiconductor wafer, an adhesive layer is first formed on the main surface of the semiconductor wafer in an adhesive layer forming step, and then a back grind tape is set. Therefore, the back grind tape can be installed under conditions where heating is not performed, and fusion of the back grind tape and the adhesive layer after installation can be suppressed. That is, the process of forming an adhesive layer by heating and pressing to suppress the biting of air voids on the semiconductor wafer on which convex electrodes are formed, and the installation of a back grind tape that does not require heating and pressing The steps can be performed sequentially and separately. Therefore, fusion and component transfer due to heating and pressurization between the adhesive layer and the back grind tape can be avoided. As a result, it is possible to suppress the difficulty in peeling off the back grind tape after the grinding process and the deterioration of the performance of the adhesive layer due to the component transfer. Further, in the dicing step, the semiconductor wafer is diced from the back grind tape side with the laminate without removing the back grind tape. Therefore, it is possible to prevent the semiconductor wafer from being contaminated by chips generated by dicing.

  A dicing method for a semiconductor wafer according to the present invention is a dicing method for separating a semiconductor wafer in which protruding electrodes protrude from a main surface, and is bonded onto the main surface of the semiconductor wafer so as to embed the protruding electrodes. Position on the opposite side of the surface on which the backgrind tape is installed, and the adhesive layer formation process for forming the adhesive layer, the tape installation process for installing the backgrind tape on the adhesive layer formed in the adhesive layer formation process Grinding the backside of the semiconductor wafer, thinning the semiconductor wafer, and attaching the backgrind tape side of the laminate of the backgrind tape, adhesive layer and semiconductor wafer obtained in the grinding process to the dicing tape And a dicing step of dicing the laminated body from the back side of the semiconductor wafer.

  In this dicing method, when grinding the back surface of a semiconductor wafer, an adhesive layer is first formed on the main surface of the semiconductor wafer in an adhesive layer forming step, and then a back grind tape is set. Therefore, in the adhesive forming process, it is possible to attach the wafer to the wafer while suppressing the formation of air voids by means such as heating and pressurization, and then attach the back grind tape under conditions that can suppress the fusion with the adhesive layer. be able to. That is, a process for forming an adhesive layer by heating and pressing to suppress biting of air voids on a semiconductor wafer on which convex electrodes are formed, and installation of a back grind tape that does not require heating and pressing The steps can be performed sequentially and separately. Therefore, fusion and component transfer due to heating and pressurization between the adhesive layer and the back grind tape can be avoided. As a result, it is possible to suppress the difficulty in peeling off the back grind tape after the grinding process and the deterioration of the performance of the adhesive layer due to the component transfer. Further, in the dicing step, the back grind tape is attached to the dicing tape with the laminated body from which the back grind tape is not removed, and dicing is performed from the back side of the semiconductor wafer. Therefore, in the pickup after dicing, the back grind tape and the dicing tape can be removed together from the semiconductor chip, and the process can be simplified.

  A mounting method of a semiconductor chip according to the present invention is a mounting method for mounting a semiconductor chip formed with protruding electrodes protruding from a main surface on a mounting substrate, on the main surface of a semiconductor wafer so as to embed the protruding electrodes. It was obtained by the tape installation process to install the back grind tape on the surface, the grinding process to thin the semiconductor wafer by grinding the back surface of the semiconductor wafer located on the opposite side of the surface on which the back grind tape was installed, and the grinding process A dicing process for dicing the laminated body of the back grind tape and the semiconductor wafer, and the laminated chip of the back grind tape and the semiconductor chip obtained in the dicing process are mounted on the mounting board with the back grind tape side facing the mounting board. A chip bonding process for mounting and bonding the semiconductor chip to the mounting substrate by back grinding tape Characterized by comprising a.

  In this mounting method, a back grind tape is installed on the main surface of the semiconductor wafer, and the back surface of the semiconductor wafer is ground. In the chip bonding step, the back grind tape functions as an insulating adhesive to bond the semiconductor chip to the mounting substrate. Therefore, it is not necessary to remove the back grind tape in the bonding process, and the process can be simplified.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor wafer back grinding method, the semiconductor wafer dicing method, and the semiconductor chip mounting method which can suppress the performance fall of the adhesive bond layer formed on a semiconductor wafer can be provided.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of a semiconductor device manufacturing method using a semiconductor wafer back grinding method, a semiconductor wafer dicing method, and a semiconductor chip mounting method according to the present invention will be described in detail with reference to the drawings.

(First embodiment)
First, a semiconductor wafer 10 as shown in FIG. 1 is prepared. The semiconductor wafer 10 has a circuit surface (main surface) S1 on which a circuit is formed by a semiconductor process, and a back surface S2 that is a surface opposite to the circuit surface S1. A plurality of protruding electrodes 10 a protruding from the circuit surface S 1 are formed on the circuit surface S 1 of the semiconductor wafer 10. In addition, the thickness of the semiconductor wafer 10 at this time is a state before the back grinding, and is usually about 550 μm to 750 μm.

  Furthermore, an adhesive film F <b> 1 in which a film-like insulating adhesive layer 22 is formed on the base film 18 is prepared. Then, the adhesive film F1 is attached to the circuit surface S1 of the semiconductor wafer 10 with the insulating adhesive layer 22 side facing the circuit surface S1. The adhesive film F1 can be attached to the semiconductor wafer 10 using, for example, a laminate roll.

  At this time, the insulating adhesive layer 22 is filled so that the space between the protruding electrodes 10a is filled by pressurizing the base film 18 with a predetermined pressure. Then, the insulating adhesive layer 22 is left on the circuit surface S1 by removing the base film 18. Thereby, as shown in FIG. 2, the insulating adhesive layer 13 is formed on the circuit surface S1 so as to embed the protruding electrode 10a (adhesive layer forming step). A soft base material that can be deformed is used for the base material film. The insulating adhesive layer 13 as described above may be generally called “NCF (Non Conductive Film)” or the like.

  Subsequently, as shown in FIG. 3, the back grind tape BT is pasted on the insulating adhesive layer 13 (tape installation step). This back grind tape BT has a base film BTa and an adhesive layer BTb formed on the surface of the base film. Here, the adhesive layer BTb and the insulating adhesive layer 13 are bonded to each other.

  Subsequently, as shown in FIG. 4, the semiconductor wafer 10 is ground from the back surface S 2 side by the back surface grinding device (back grinder) 12 while applying pressure to the back grind tape BT to reduce the thickness of the semiconductor wafer 10. Specifically, the semiconductor wafer 10 is ground so that the thickness of the semiconductor wafer 10 is about 50 μm to 550 μm (grinding step). Here, since the back grind tape BT is affixed to the circuit surface S1 side of the semiconductor wafer 10, pressure can be applied uniformly. As a result, the back surface S2 of the semiconductor wafer 10 can be flattened by grinding. Further, the back grind tape BT can suppress damage to the semiconductor wafer 10 during back grinding. In this manner, a laminated body R1 including the thinned semiconductor wafer 10 and the back grind tape BT attached to the circuit surface S1 is manufactured.

  Subsequently, as shown in FIG. 5, the back grind tape BT is stuck on the circuit surface S1 side of the semiconductor wafer 10 and the rear surface S2 side of the laminate R1 and the lower edge 14a of the dicing frame 14 are attached. A dicing tape 16 is affixed. Here, the dicing frame 14 is an annular metal member, and is used as a fixing jig for the semiconductor wafer 10 when the semiconductor wafer 10 is diced. The dicing frame 14 has an inner diameter larger than the outer shape of the semiconductor wafer 10 and is disposed on the dicing tape 16 so as to surround the semiconductor wafer 10. Moreover, the dicing tape 16 has the base film 16a and the adhesion layer 16b formed in the surface of the base film 16a.

  Although not shown, since a positioning pattern for positioning a dicing position by a dicing blade DB (described later) is formed on the circuit surface S1 of the semiconductor wafer 10, the back grinding tape BT has the above-described positioning. It is preferable that the transmittance of the pattern is visible (for example, the visible light transmittance of the back grind tape BT as a whole is 20% or more).

  Subsequently, as shown in FIG. 6, the semiconductor wafer 10 is diced from the back grind tape BT together with the back grind tape BT by the dicing blade DB with the circuit surface S1 of the semiconductor wafer 10 facing upward (so-called “so-called”). , Face-up dicing) to form a plurality of semiconductor chips 24 (dicing step). At this time, the size of the semiconductor chip 24 is set to about 0.5 mm × 0.5 mm. Here, by employing face-up dicing, the dicing position can be positioned relatively easily using the positioning pattern.

  Subsequently, as shown in FIG. 7, the adhesive tape 26 is attached to the entire surface of the back grind tape BT. Then, as shown in FIG. 8, the separated back grind tape BT is peeled from the insulating adhesive layer 13 together with the adhesive tape 26. At this time, if the adhesive layer BTb of the back grind tape BT has radiation curability, the adhesive force of the adhesive layer BTb can be reduced by irradiation with radiation (for example, ultraviolet rays) prior to peeling.

  Thereafter, although details are omitted, after reducing the adhesive force of the adhesive layer 16b of the dicing tape 16 by irradiation with ultraviolet rays or the like, one semiconductor chip 24 having the insulating adhesive layer 13 formed on the circuit surface S1 is provided. A semiconductor device including the semiconductor chip 24 can be obtained through a process of picking up one piece and flip-chip mounting the semiconductor chip 24 on a mounting substrate.

  In grinding the back surface S2 in the above grinding step, the back grind tape BT is installed after the insulating adhesive layer 13 is formed on the main surface S1 of the semiconductor wafer 10. That is, when the adhesive layer 13 is applied, it is embedded by heating and pressurization so that air voids are not caught at the interface between the wafer and the adhesive layer, and then the adhesive layer of the back grind tape and the adhesive layer are fused. A back grind tape is applied under conditions that do not occur, that is, at room temperature or the like to form a flat processed state. Therefore, after the back grinding is completed, the back grinding tape can be easily peeled off. In addition, since heating and pressurization are not performed in a state where the adhesive layer of the back grind tape and the adhesive are in contact with each other, there is almost no transfer of the adhesive material to the adhesive layer, and the capability of the adhesive layer is hardly reduced. In the dicing step, the semiconductor wafer 10 is diced from the back grind tape BT side without removing the back grind tape BT from the laminate R1. Therefore, it is possible to prevent the semiconductor wafer 10 from being contaminated by chips generated by dicing.

  In addition, although the effect of the contamination suppression by the above-mentioned chips cannot be obtained, the back grind tape BT was removed from the semiconductor wafer 10 of the laminated body R1 to which the dicing tape 16 was attached as shown in FIG. Later, dicing may be performed.

  Examples of the base film 18 in the above-described adhesive film F1 include a PET base material whose surface is release-treated with, for example, silicone. The insulating adhesive layer 22 is formed, for example, by applying an adhesive composition to the base film 18 and then drying it. The insulating adhesive layer 22 is solid at room temperature, for example. The insulating adhesive layer 22 includes a thermosetting resin. The thermosetting resin is cured by three-dimensionally crosslinking with heat.

  Examples of the thermosetting resin include epoxy resin, bismaleimide resin, triazine resin, polyimide resin, polyamide resin, cyanoacrylate resin, phenol resin, unsaturated polyester resin, melamine resin, urea resin, polyurethane resin, polyisocyanate resin, furan. Examples thereof include resins, resorcinol resins, xylene resins, benzoguanamine resins, diallyl phthalate resins, silicone resins, polyvinyl butyral resins, siloxane-modified epoxy resins, siloxane-modified polyamideimide resins, and acrylate resins. These can be used alone or as a mixture of two or more.

  The insulating adhesive layer 22 may include a curing agent for promoting the curing reaction. The insulating adhesive layer 22 preferably contains a latent curing agent in order to achieve both high reactivity and storage stability.

  The insulating adhesive layer 22 may include a thermoplastic resin. The thermoplastic resin includes polyester resin, polyether resin, polyamide resin, polyamideimide resin, polyimide resin, polyarylate resin, polyvinyl butyral resin, polyurethane resin, phenoxy resin, polyacrylate resin, polybutadiene, acrylonitrile butadiene copolymer (NBR). ), Acrylonitrile butadiene rubber styrene resin (ABS), styrene butadiene copolymer (SBR), acrylic acid copolymer and the like. These can be used alone or in combination of two or more. Among these, a thermoplastic resin having a softening point in the vicinity of room temperature is preferable in order to ensure stickability to the semiconductor wafer 10, and an acrylic acid copolymer containing glycidyl methacrylate as a raw material is preferable.

  A filler (inorganic fine particles) for reducing the linear expansion coefficient may be added to the insulating adhesive layer 22. Such fillers may be crystalline or non-crystalline. When the linear expansion coefficient after curing of the insulating adhesive layer 22 is small, thermal deformation is suppressed. Therefore, even after the semiconductor chip manufactured from the semiconductor wafer 10 is mounted on the wiring board, the electrical connection between the protruding electrode 10a and the wiring of the wiring board can be maintained. The reliability of the semiconductor device manufactured by connecting can be improved.

  The insulating adhesive layer 22 may include an additive such as a coupling agent. Thereby, the adhesiveness of a semiconductor chip and a wiring board can be improved.

  Conductive particles may be dispersed in the insulating adhesive layer 22. In this case, it is possible to reduce an adverse effect due to variations in the height of the protruding electrode 14a. Further, the connection can be maintained even when the wiring board is not easily deformed due to compression, such as a glass substrate. Furthermore, the insulating adhesive layer 22 can be an anisotropic conductive adhesive layer.

  The thickness of the insulating adhesive layer 22 is preferably such that the insulating adhesive layer 22 can sufficiently fill the space between the semiconductor chip and the wiring board. Usually, if the thickness of the insulating adhesive layer 22 is equivalent to the sum of the height of the protruding electrode 10a and the wiring height of the wiring board, the space between the semiconductor chip and the wiring board can be sufficiently filled.

  The dicing tape 16 has a base film 16a and an adhesive layer 16b formed on the surface of the base film 16a. The base film 16a is preferably radiolucent, and specifically, plastic, rubber or the like can be usually used. The base film 16a is not particularly limited as long as it transmits radiation. However, when the radiation curable pressure-sensitive adhesive is cured by ultraviolet irradiation, a film having good light transmittance can be selected.

  Examples of polymers that can be selected as the base film 16a include polyethylene, polypropylene, ethylene-propylene copolymer, polybutene-1, poly-4-methylpentene-1, ethylene-vinyl acetate copolymer, ethylene. -Ethyl acrylate copolymer, ethylene-methyl acrylate copolymer, ethylene-acrylic acid copolymer, α-olefin homopolymer or copolymer such as ionomer, or a mixture thereof, polyethylene terephthalate, polycarbonate, poly Engineering plastics such as methyl methacrylate, thermoplastic elastomers such as polyurethane, styrene-ethylene-butene or pentene copolymers, polyamide-polyol copolymers, and mixtures thereof can be listed.

  In order to increase the gap between elements, it is preferable that necking (occurrence of partial elongation due to poor propagation of force that occurs when the base film 16a is radially stretched) is as small as possible, including polyurethane, molecular weight, and styrene content For example, styrene-ethylene-butene or pentene copolymer with a limited amount can be exemplified, and it is effective to use a cross-linked substrate film 16a in order to prevent elongation or deflection during dicing. The thickness of the base film 16a is usually suitably 30 to 300 μm from the viewpoint of strong elongation characteristics and radiation transparency. In addition, when the surface opposite to the side on which the adhesive layer 16b of the base film 16a is applied is textured or coated with a lubricant, blocking is prevented and friction between the dicing tape 16 and the jig during radial stretching of the dicing tape 16 is reduced. This is preferable because there is an effect such as prevention of necking of the base film 16a.

  On the other hand, in the present embodiment, the adhesive layer 16b includes a compound (A) having a radiation curable carbon-carbon double bond having an iodine value of 0.5 to 20 in the molecule, a polyisocyanate, a melamine / formaldehyde resin, and It consists of an acrylic adhesive containing at least one compound (B) selected from epoxy resins. Here, the radiation refers to light rays such as ultraviolet rays or ionizing radiations such as electron beams.

  The compound (A) that is one of the main components of the adhesive layer 16b will be described. The amount of the radiation curable carbon-carbon double bond introduced into the compound (A) is 0.5 to 20, preferably 0.8 to 10 in terms of iodine value. If the iodine value is 0.5 or more, an effect of reducing the adhesive strength after irradiation can be obtained. If the iodine value is 20 or less, the fluidity of the adhesive after irradiation is sufficient and after stretching. Therefore, the problem that the image recognition of each element becomes difficult at the time of pick-up can be suppressed. Furthermore, the compound (A) itself is stable and easy to manufacture.

  The compound (A) preferably has a glass transition point of −70 ° C. to 0 ° C., more preferably −66 ° C. to −28 ° C. If the glass transition point (hereinafter also referred to as “Tg”) is −70 ° C. or higher, the heat resistance against heat associated with radiation irradiation is sufficient, and if it is 0 ° C. or lower, after dicing on a wafer having a rough surface state. The effect of preventing scattering of the element is sufficiently obtained.

  The compound (A) may be produced by any method, and has, for example, a radiation curable carbon-carbon double bond such as an acrylic copolymer or a methacrylic copolymer, and a functional group. A compound obtained by reacting a compound having the functional group ((1)) with a compound having a functional group capable of reacting with the functional group ((2)) is used.

  Among these, the compound ((1)) having a radiation curable carbon-carbon double bond and a functional group is a single compound having a radiation curable carbon-carbon double bond such as an acrylic acid alkyl ester or a methacrylic acid alkyl ester. It can be obtained by copolymerizing a monomer ((1) -1) and a monomer having a functional group ((1) -2).

  As a monomer ((1) -1), C6-C12 hexyl acrylate, n-octyl acrylate, isooctyl acrylate, 2-ethylhexyl acrylate, dodecyl acrylate, decyl acrylate, or a single quantity having 5 or less carbon atoms The pentyl acrylate, n-butyl acrylate, isobutyl acrylate, ethyl acrylate, methyl acrylate, or methacrylates similar to these can be listed.

  As the monomer ((1) -1) is used, the glass transition point becomes lower as the monomer having a larger carbon number is used, so that the desired glass transition point can be produced. In addition to the glass transition point, a monomer ((1) -1) may be blended with a low molecular compound having a carbon-carbon double bond such as vinyl acetate, styrene, or acrylonitrile for the purpose of improving compatibility and various performances. ) In the range of 5% by weight or less of the total weight.

  Examples of the functional group of the monomer ((1) -2) include a carboxyl group, a hydroxyl group, an amino group, a cyclic acid anhydride group, an epoxy group, and an isocyanate group. The monomer ((1)- Specific examples of 2) include acrylic acid, methacrylic acid, cinnamic acid, itaconic acid, fumaric acid, phthalic acid, 2-hydroxyalkyl acrylates, 2-hydroxyalkyl methacrylates, glycol monoacrylates, glycol monomethacrylates. N-methylolacrylamide, N-methylolmethacrylamide, allyl alcohol, N-alkylaminoethyl acrylates, N-alkylaminoethyl methacrylates, acrylamides, methacrylamides, maleic anhydride, itaconic anhydride, fumaric anhydride, Phthalic anhydride, glycidyl acrylate, It can be enumerated those urethanization a monomer having a carbon-carbon double bond and - glycidyl methacrylate, allyl glycidyl ether, a portion of the isocyanate groups of the polyisocyanate compound a hydroxyl group or a carboxyl group and a radiation-curable carbon.

  In the compound ((2)), the functional group used is when the functional group of the compound ((1)), that is, the monomer ((1) -2), is a carboxyl group or a cyclic acid anhydride group. Can include a hydroxyl group, an epoxy group, an isocyanate group, and in the case of a hydroxyl group, it can include a cyclic acid anhydride group, an isocyanate group, and the like, and in the case of an amino group, an epoxy group, an isocyanate group In the case of an epoxy group, a carboxyl group, a cyclic acid anhydride group, an amino group, and the like can be exemplified. Specific examples of the monomer ((1) -2) The same thing as what was enumerated by can be enumerated.

  In the reaction between the compound ((1)) and the compound ((2)), by leaving an unreacted functional group, it is possible to produce what is prescribed in this embodiment with respect to characteristics such as acid value or hydroxyl value. it can.

  In the synthesis of the above compound (A), as the organic solvent when the reaction is carried out by solution polymerization, ketone, ester, alcohol, and aromatic solvents can be used, among which toluene, ethyl acetate , Isopropyl alcohol, benzene, methyl cellosolve, ethyl cellosolve, acetone, methyl ethyl ketone, etc. are generally good solvents for acrylic polymers, preferably having a boiling point of 60-120 ° C., and α, α′-azobis as a polymerization initiator A radical generator such as an azobis type such as isobutyl nitrile or an organic peroxide type such as benzoyl peroxide is usually used. At this time, a catalyst and a polymerization inhibitor can be used together as necessary, and the compound (A) having a desired molecular weight can be obtained by adjusting the polymerization temperature and the polymerization time. In terms of adjusting the molecular weight, it is preferable to use a mercaptan or carbon tetrachloride solvent. This reaction is not limited to solution polymerization, and other methods such as bulk polymerization and suspension polymerization may be used.

  As described above, the compound (A) can be obtained. In the present embodiment, the molecular weight of the compound (A) is preferably about 300,000 to 1,000,000. If it is less than 300,000, the cohesive force due to radiation irradiation becomes small, and when the semiconductor wafer 10 is diced, the element is likely to be displaced and image recognition may be difficult. In order to prevent the deviation of the element as much as possible, the molecular weight is preferably 400,000 or more. Further, if the molecular weight exceeds 1,000,000, there is a possibility of gelation at the time of synthesis and coating. In addition, the molecular weight in this invention is a weight average molecular weight of polystyrene conversion.

  In addition, it is preferable that the compound (A) has an OH group having a hydroxyl value of 5 to 100 because the risk of pick-up mistakes can be further reduced by reducing the adhesive strength after radiation irradiation. Moreover, it is preferable that a compound (A) has a COOH group used as the acid value of 0.5-30.

  Here, if the hydroxyl value of the compound (A) is too low, the effect of reducing the adhesive strength after irradiation is not sufficient, and if it is too high, the fluidity of the adhesive after irradiation tends to be impaired. If the acid value is too low, the effect of improving the tape restoring property is not sufficient, and if it is too high, the fluidity of the pressure-sensitive adhesive tends to be impaired.

  Next, the compound (B) which is another main component of the adhesion layer 16b will be described. The compound (B) is a compound selected from at least one of polyisocyanates, melamine / formaldehyde resins, and epoxy resins, and can be used alone or in combination of two or more. This compound (B) acts as a cross-linking agent, and the cohesive force of the pressure-sensitive adhesive mainly composed of the compounds (A) and (B) is reduced by the cross-linking structure formed as a result of reaction with the compound (A) or the base film 16a. It can be improved after applying the agent.

  The polyisocyanates are not particularly limited, and examples thereof include 4,4′-diphenylmethane diisocyanate, tolylene diisocyanate, xylylene diisocyanate, 4,4′-diphenyl ether diisocyanate, 4,4 ′-[2,2-bis (4 -Phenoxyphenyl) propane] aromatic isocyanate such as diisocyanate, hexamethylene diisocyanate, 2,2,4-trimethyl-hexamethylene diisocyanate, isophorone diisocyanate, 4,4'-dicyclohexylmethane diisocyanate, 2,4'-dicyclohexylmethane diisocyanate Lysine diisocyanate, lysine triisocyanate and the like. Specifically, Coronate L etc. can be used as a commercial item.

  Further, as the melamine / formaldehyde resin, specifically, Nicalac MX-45 (manufactured by Sanwa Chemical Co., Ltd.), Melan (manufactured by Hitachi Chemical Co., Ltd.), etc. can be used as commercial products. Furthermore, as the epoxy resin, TETRAD-X (registered trademark, manufactured by Mitsubishi Chemical Corporation) or the like can be used. In this embodiment, it is particularly preferable to use polyisocyanates.

  As addition amount of a compound (B), it is preferable to set it as 0.1-10 weight part with respect to 100 weight part of compounds (A), and it is more preferable to set it as 0.4-3 weight part. If the amount is less than 0.1 parts by weight, the effect of improving the cohesive force tends to be insufficient. If the amount exceeds 10 parts by weight, the curing reaction proceeds rapidly during the formulation and application of the adhesive, and a crosslinked structure is formed. Therefore, workability tends to be impaired.

  Moreover, in this embodiment, it is preferable that the photoinitiator (C) is contained in the adhesion layer 16b. There is no particular limitation on the photopolymerization initiator (C) contained in the adhesive layer 16b, and any conventionally known photopolymerization initiator (C) can be used. For example, benzophenones such as benzophenone, 4,4′-dimethylaminobenzophenone, 4,4′-diethylaminobenzophenone, 4,4′-dichlorobenzophenone, acetophenones such as acetophenone and diethoxyacetophenone, 2-ethylanthraquinone, t- Examples include anthraquinones such as butylanthraquinone, 2-chlorothioxanthone, benzoin ethyl ether, benzoin isopropyl ether, benzyl, 2,4,5-triallylimidazole dimer (rophine dimer), and acridine compounds. These can be used alone or in combination of two or more.

  As addition amount of a photoinitiator (C), it is preferable to set it as 0.01-5 weight part with respect to 100 weight part of compounds (A), and it is more preferable to set it as 0.01-4 weight part.

  Furthermore, the radiation curable pressure-sensitive adhesive layer 16b used in the present embodiment can be blended with a tackifier, a tackifier, a surfactant, or other modifiers and conventional components as required. Although the thickness of an adhesive layer is not specifically limited, Usually, it is 2-50 micrometers.

(Second Embodiment)
In this embodiment, in the dicing step, as shown in FIG. 10, the dicing tape 16 is attached to the back grind tape BT side of the laminate R1. Then, as shown in FIG. 11, the semiconductor wafer 10 is diced together with the back grind tape BT from the back surface S2 side by the dicing blade DB with the back surface S2 of the semiconductor wafer 10 facing upward (so-called face-down dicing). .

  Then, as shown in FIG. 12, the boundary between the adhesive layer BTb of the back grind tape BT and the insulating adhesive layer 13 is peeled off, and the semiconductor chip 124 in a state where the insulating adhesive layer 13 is formed on the main surface S1. To pick up. Thereafter, a semiconductor device including the semiconductor chip 124 can be obtained through a process of flip-chip mounting the picked-up semiconductor chip 124 on the mounting substrate. In addition, in this embodiment, about the structure same or equivalent to the above-mentioned 1st Embodiment, the same code | symbol is attached | subjected to drawing and the overlapping description is abbreviate | omitted.

  According to the dicing process as described above, the back grind tape BT and the dicing tape 16 can be simultaneously removed from the semiconductor chip 124 when the semiconductor chip 124 is picked up, so that the process of peeling the back grind tape BT is omitted. be able to. Further, since face-down dicing is performed, it is possible to prevent the circuit surface S1 from being contaminated by chips generated by dicing.

(Third embodiment)
As shown in FIG. 13, first, a semiconductor wafer 10 and a back grind tape F2 are prepared. The back grind tape F2 has an original function as a back grind tape that suppresses breakage of the semiconductor wafer 10 and realizes stable back grinding in a grinding process described later, and as an insulating adhesive in a chip bonding process described later. It has both functions. Specifically, the back grind tape F2 has a two-layer structure in which an elastic layer 31 and an adhesive layer 33 are laminated. The elastic layer 31 is made of a material having a higher elastic modulus and lower adhesiveness than the adhesive layer 33. The elastic layer 31 exhibits a function of suppressing damage to the semiconductor wafer 10 in a grinding process described later, and functions as an insulating adhesive. To demonstrate. On the other hand, the adhesive layer 33 has a function of fixing the back grind tape F2 to the semiconductor wafer 10 and a function as an insulating adhesive.

  Subsequently, as shown in FIG. 14, the back grind tape F2 is attached to the circuit surface S1 of the semiconductor wafer 10 with the adhesive layer 33 side facing the circuit surface S1 (tape setting step). The back grind tape F2 can be attached to the semiconductor wafer 10 using, for example, a laminate roll. At this time, the back grind tape F2 is pressurized at a predetermined pressure, so that the insulating adhesive of the adhesive layer 33 is filled so as to fill between the protruding electrodes 10a, and the protruding electrodes 10a are formed on the circuit surface S1. An adhesive layer 33 is formed so as to embed. And the elastic layer 31 which exhibits the function as a back grind tape is formed on the adhesion layer 33.

  Subsequently, as shown in FIG. 15, while applying pressure to the elastic layer 31, the semiconductor wafer 10 is ground from the back surface S 2 side by the back surface grinding device (back grinder) 12 to reduce the thickness of the semiconductor wafer 10. Specifically, the semiconductor wafer 10 is ground so that the thickness of the semiconductor wafer 10 is about 50 μm to 550 μm (grinding step). Here, the pressure can be uniformly applied by the presence of the back grind tape F2 on the circuit surface S1 side of the semiconductor wafer 10, and as a result, the back surface S2 of the semiconductor wafer 10 can be flattened by grinding. Moreover, damage to the semiconductor wafer 10 during grinding is suppressed. In this way, a laminated body R2 (FIG. 16) composed of the thinned semiconductor wafer 10 and the back grind tape F2 attached to the circuit surface S1 is manufactured.

  Subsequently, as shown in FIG. 16, dicing is performed on the back surface S 2 side of the laminated body R 2 and the lower edge 14 a of the dicing frame 14 with the back grind tape F 2 attached to the circuit surface S 1 side of the semiconductor wafer 10. A tape 16 is applied. Although not shown, since a positioning pattern for positioning a dicing position by a dicing blade DB (described later) is formed on the circuit surface S1 of the semiconductor wafer 10, the back grind tape F2 is positioned on the positioning surface. It is preferable that the transmittance is such that the pattern can be visually recognized (for example, the visible light transmittance of the back grind tape F2 as a whole is 20% or more).

  Subsequently, as shown in FIG. 17, the semiconductor wafer 10 is diced from the back grind tape F2 side together with the back grind tape F2 by the dicing blade DB with the circuit surface S1 of the semiconductor wafer 10 facing upward (so-called “so-called”). , Face-up dicing) and a plurality of semiconductor chips 224 (dicing process). At this time, the size of the semiconductor chip 224 is set to about 0.5 mm × 0.5 mm. In this way, a laminated chip C1 in which the back grind tape F2 and the semiconductor chip 224 are laminated is manufactured.

  Thereafter, the laminated chips C1 are picked up one by one from the dicing tape 16, and mounted on the mounting substrate 41 with the back grind tape F2 side facing the mounting substrate 41 as shown in FIG. Here, the laminated chip C1 is heat-pressed toward the mounting substrate 41, and the protruding electrode 10a of the semiconductor chip 224 and the electrode portion 41a of the mounting substrate 41 are connected (so-called flip chip mounting).

  At this time, as shown in FIG. 19, the elastic layer 31 and the adhesive layer 33 of the back grind tape F <b> 2 are crushed and filled between the circuit surface S <b> 1 and the mounting substrate 41. Since the elastic layer 31 and the adhesive layer 33 function as an insulating adhesive, the elastic layer 31 and the adhesive layer 33 are cured by heating, and the semiconductor chip 224 is bonded and fixed to the mounting substrate 41 (chip bonding step). . Thereafter, a semiconductor device including the semiconductor chip 224 can be obtained through a predetermined process or the like. In addition, in this embodiment, about the structure same or equivalent to the above-mentioned 1st or 2nd embodiment, the same code | symbol is attached | subjected to drawing and the overlapping description is abbreviate | omitted.

  In the dicing process described above, face-up dicing is adopted. However, as shown in FIG. 20, the back-grind tape F2 side of the laminate R2 may be attached to the dicing tape 16 and face-down dicing may be performed. Good.

According to the mounting method of the semiconductor chip 224 described above, the main surface S of the semiconductor wafer 10.
A back grind tape F2 is installed on the surface 1, and in the grinding process, the back grind tape F2 exhibits its original function as a back grind tape, and stable grinding of the back surface S2 is performed. In the chip bonding step, the back grind tape F2 functions as an insulating adhesive. Therefore, in the chip bonding step, it is not necessary to remove the back grind tape F2, and the process can be simplified.

It is sectional drawing which shows the semiconductor wafer and insulating adhesive to which the back grinding method and dicing method of 1st Embodiment concerning this invention are applied. It is sectional drawing which shows the state in which the insulating adhesive bond layer was formed on the circuit surface of the semiconductor wafer of FIG. FIG. 3 is a cross-sectional view showing a state where a back grind tape is further installed on the semiconductor wafer of FIG. 2. It is a figure which shows the process of grinding the back surface side of the semiconductor wafer of FIG. It is sectional drawing which shows the state which set the laminated body produced in FIG. 4 to the dicing frame. It is sectional drawing which shows the dicing process of the laminated body of FIG. It is sectional drawing which shows the process of removing a back grind tape from the laminated body diced in FIG. It is sectional drawing which shows the semiconductor wafer from which the back grinding tape was removed after dicing. It is sectional drawing which shows the other example of the dicing process of a semiconductor wafer. In 2nd Embodiment of this invention, it is sectional drawing which shows the state which set the laminated body to the dicing frame. It is sectional drawing which shows the state which diced the laminated body of FIG. It is sectional drawing which shows the process of picking up the diced semiconductor chip. It is sectional drawing which shows the semiconductor wafer and back grind tape to which the mounting method of this invention is applied. It is sectional drawing which shows the state which installed the back grind tape on the circuit surface of the semiconductor wafer of FIG. It is a figure which shows the process of grinding the back surface side of the semiconductor wafer of FIG. It is sectional drawing which shows the state which set the laminated body produced in FIG. 15 to the dicing frame. It is sectional drawing which shows the process of picking up a laminated chip after dicing of a laminated body. FIG. 18 is a cross-sectional view showing a laminated chip and a mounting substrate picked up in FIG. 17. It is sectional drawing which shows the state which adhere | attached the laminated chip of FIG. 18 on the mounting board | substrate. It is sectional drawing which shows the other example of the dicing process of a semiconductor wafer.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Semiconductor wafer, 10a ... Protruding electrode, 13 ... Insulating adhesive layer, 22 ... Insulating adhesive layer, 41 ... Mounting substrate, 224 ... Semiconductor chip, BT ... Back grind tape, C1 ... Multilayer chip, F2 ... Back Grind tape, R1, R2 ... laminate, S1 ... main surface, S2 ... back surface.

Claims (4)

A back grinding method for thinning a semiconductor wafer in which protruding electrodes protrude from a main surface,
An adhesive layer forming step of forming an adhesive layer on the main surface of the semiconductor wafer so as to embed the protruding electrodes;
A tape installation step of installing a back grind tape on the adhesive layer formed in the adhesive layer formation step;
Grinding the back surface of the semiconductor wafer located on the opposite side of the surface on which the back grind tape is installed, and grinding the semiconductor wafer; and
A backgrinding method for a semiconductor wafer, comprising: A dicing method for separating a semiconductor wafer formed by projecting electrodes protruding from a main surface,
An adhesive layer forming step of forming an adhesive layer on the main surface of the semiconductor wafer so as to embed the protruding electrodes;
A tape installation step of installing a back grind tape on the adhesive layer formed in the adhesive layer formation step;
Grinding the back surface of the semiconductor wafer located on the opposite side of the surface on which the back grind tape is installed, and grinding the semiconductor wafer; and
A dicing step of dicing a laminate of the back grind tape, the adhesive layer and the semiconductor wafer obtained in the grinding step from the back grind tape side;
A method of dicing a semiconductor wafer, comprising: A dicing method for separating a semiconductor wafer formed by projecting electrodes protruding from a main surface,
An adhesive layer forming step of forming an adhesive layer on the main surface of the semiconductor wafer so as to embed the protruding electrodes;
A tape installation step of installing a back grind tape on the adhesive layer formed in the adhesive layer formation step;
Grinding the back surface of the semiconductor wafer located on the opposite side of the surface on which the back grind tape is installed, and grinding the semiconductor wafer; and
The back grind tape side of the laminate of the back grind tape, the adhesive layer and the semiconductor wafer obtained in the grinding step is attached to a dicing tape, and the laminate is diced from the back side of the semiconductor wafer. Dicing process to
A method of dicing a semiconductor wafer, comprising: A mounting method for mounting a semiconductor chip on which a protruding electrode protrudes from a main surface on a mounting substrate,
A tape installation step of installing a back grind tape on the main surface of the semiconductor wafer so as to embed the protruding electrodes;
Grinding the back surface of the semiconductor wafer located on the opposite side of the surface on which the back grind tape is installed, and grinding the semiconductor wafer; and
A dicing step of dicing the laminate of the back grind tape and the semiconductor wafer obtained in the grinding step;
The laminated chip of the back grind tape and the semiconductor chip obtained in the dicing step is mounted on the mounting substrate with the back grind tape side facing the mounting substrate, and the semiconductor chip is backed by the back grind tape. A chip adhering step for adhering to the mounting substrate;
A method of mounting a semiconductor chip, comprising:

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