JP2009200415A - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 41
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- B29C45/14336—Coating a portion of the article, e.g. the edge of the article
- B29C45/14418—Sealing means between mould and article
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- B—PERFORMING OPERATIONS; TRANSPORTING
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- B29C45/00—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor
- B29C45/14—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles
- B29C45/14639—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles for obtaining an insulating effect, e.g. for electrical components
- B29C45/14655—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles for obtaining an insulating effect, e.g. for electrical components connected to or mounted on a carrier, e.g. lead frame
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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Abstract
【解決手段】環状の枠体110と、枠体110内に位置し、配線112,113が接続された素子とを準備する工程と、枠体110の一方の軸方向端面によって規定される開口部を閉塞すると共に、配線112,113および素子を覆うように上金型210を配置する工程と、第1および下金型211が枠体110を挟持して、上金型210を一方の軸方向端面に圧着させて、第1軸方向端面を変形させると共に、下金型211を他方の軸方向端面に圧着させて、第2軸方向端面を変形させる工程と、第1および下金型211と、枠体110とによって規定される内部空間内に樹脂を充填して、内部空間内に位置する配線112,113および素子上を覆う樹脂部を形成する工程とを備える。
【選択図】図2
Description
図1は、本発明の実施の形態1に係る半導体装置100の断面図である。この図1に示されるように、半導体装置100は、環状に形成された枠体110と、この枠体110内に充填されたモールド樹脂部111と、このモールド樹脂部111内に埋設されたパワーチップ117と、枠体110の内周面から引き出された配線112および配線113とを備えている。ここで、配線112は、軸方向端面122上に位置する引出部114から引き出されており、配線113は、軸方向端面122上に位置する引出部115から引き出されている。
図5から図8を用いて、本発明の実施の形態2に係る半導体装置および半導体装置の製造方法について説明する。なお、上記図1から図4に示された構成と同一の構成については、同一の符号を付してその説明を省略する場合がある。
図9を用いて、本実施の形態3に係る半導体装置の製造方法について説明する。なお、図9において、上記図1から図8に示された構成と同一の構成については、同一の符号を付してその説明の省略する場合がある。
枠体110の軸方向端面123内に入り込んでいる。
図11および図12を用いて、本実施の形態4に係る半導体装置について説明する。なお、図11および図12に示す構成において、上記図1から図10に示された構成と同一の構成については、同一の符号を付してその説明を省略する場合がある。
図13から図16を用いて、本発明の実施の形態5に係る半導体装置300およびその製造方法について説明する。
Claims (8)
- 環状の枠体と、前記枠体の内周面から張り出す配線と、前記枠体内に位置し、前記配線が接続された素子とを準備する工程と、
前記枠体の一方の軸方向端面によって規定される開口部を閉塞すると共に、前記配線および前記素子を覆うように第1金型を配置する工程と、
前記枠体の他方の軸方向端面によって規定される開口部を閉塞すると共に、前記配線および前記素子を覆うように第2金型を配置する工程と、
前記第1および第2金型が前記枠体を挟持して、前記第1金型を前記一方の軸方向端面に圧着させて、前記第1軸方向端面を変形させると共に、前記第2金型を前記他方の軸方向端面に圧着させて、前記第2軸方向端面を変形させる工程と、
前記第1および第2金型と、前記枠体とによって規定される内部空間内に樹脂を充填して、前記内部空間内に位置する前記配線および前記素子上を覆う樹脂部を形成する工程と、
を備えた、半導体装置の製造方法。 - 前記配線は、前記一方の軸方向端面上の引出部から引き出され、
前記第1および第2金型が前記枠体を挟持する工程において、前記第1金型が前記一方の軸方向端面のうち、前記配線の引出部よりも内側に位置する部分を変形させる、請求項1に記載の半導体装置の製造方法。 - 前記枠体は、前記一方の軸方向端面のうち、該一方の軸方向端面の内周縁部と前記引出部との間に位置する部分に形成された環状の第1突起部と、前記他方の軸方向端面に形成された環状の第2突起部とを含み、
前記第1および第2金型が前記枠体を挟持する工程において、前記第1金型が前記第1突起部を全周に亘ってを変形させ、前記第2金型が前記第2突起部を全周に亘って変形させる、請求項2に記載の半導体装置の製造方法。 - 前記第1金型は、環状に延びる第1環状凸部を含み、前記第2金型は、環状に延びる第2環状凸部とを含み、
前記第1および第2金型が前記枠体を挟持する工程において、前記第1環状凸部が、前記枠体の前記一方の軸方向端面のうち、該一方の軸方向端面の内周縁部と前記引出部との間に位置する部分を変形して、第1溝部を形成すると共に、前記第2環状凸部が、前記枠体の前記他方の軸方向端面を変形して、第2溝部を形成する、請求項2に記載の半導体装置の製造方法。 - 前記第2金型に、前記樹脂が吐出する吐出口が形成され、
前記枠体には、前記他方の軸方向端面のうち、前記他の軸方向端面の外周縁部より内周縁部側に位置する部分から該内周縁部に達する切欠部が形成され、
前記切欠部を規定する前記枠体の内周面のうち、前記内周縁部よりも外周縁部側に位置する部分は、前記内周縁部に位置する部分よりも前記一方の端部に近接するように凹まされ、
前記切欠部が前記吐出口に位置するように、前記枠体を前記第2金型に配置して、ゲート部を規定する工程をさらに備える、請求項1から請求項4のいずれかに記載の半導体装置の製造方法。 - 前記枠体は、熱可塑性樹脂から形成され、前記樹脂部は、熱硬化性樹脂から形成された、請求項1から請求項5のいずれかに記載の半導体装置の製造方法。
- 環状の枠体と、
前記枠体内に充填された樹脂部と、
前記樹脂部内に埋設された素子と、
前記枠体の内周面から引き出され、前記枠体の一方の軸方向端面の引き出し部から引き出された配線と、
を備え、
前記樹脂部は、前記枠体の前記一方の軸方向端面のうち、前記配線より内周縁部側に位置する部分の一部を覆い、前記引出部よりも前記枠体の内周側に位置する部分と係合する前記配線第1係合部と、前記枠体の他方の軸方向端面の一部を覆う第2係合部とを含む、半導体装置。 - 前記配線は、前記端子に接続された第1配線と、前記素子に接続され、前記第1配線より厚さが薄い第2配線とを含み、前記第1配線と前記第2配線との少なくとも一部が、前記枠体の一方の軸方向端面から他方の軸方向端面に向かう方向に互いに重なり合う、請求項7に記載の半導体装置。
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012033793A (ja) * | 2010-08-02 | 2012-02-16 | Denso Corp | 半導体装置の製造方法 |
JP2013089607A (ja) * | 2011-10-13 | 2013-05-13 | Nissan Motor Co Ltd | モールド装置およびモールド方法 |
JP2014093451A (ja) * | 2012-11-05 | 2014-05-19 | Denso Corp | モールドパッケージの製造方法 |
EP2660858A4 (en) * | 2010-12-27 | 2016-03-30 | Nissan Motor | SEMICONDUCTOR MODULE, MOLDING DEVICE AND MOLDING PROCESS |
JP2019050324A (ja) * | 2017-09-12 | 2019-03-28 | 富士電機株式会社 | 半導体装置、半導体装置の積層体、及び、半導体装置の積層体の搬送方法 |
WO2020094411A1 (en) * | 2018-11-07 | 2020-05-14 | Danfoss Silicon Power Gmbh | Mold tool for molding a semiconductor power module with top-sided pin connectors and method of manufacturing such a semiconductor power module |
WO2024111242A1 (ja) * | 2022-11-21 | 2024-05-30 | I-Pex株式会社 | インサート部材およびインサート成形方法 |
Citations (2)
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JP2000340718A (ja) * | 1999-05-31 | 2000-12-08 | Mitsubishi Electric Corp | 電力用半導体装置 |
JP2005322784A (ja) * | 2004-05-10 | 2005-11-17 | Mitsubishi Electric Corp | 電力用半導体装置 |
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Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2000340718A (ja) * | 1999-05-31 | 2000-12-08 | Mitsubishi Electric Corp | 電力用半導体装置 |
JP2005322784A (ja) * | 2004-05-10 | 2005-11-17 | Mitsubishi Electric Corp | 電力用半導体装置 |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012033793A (ja) * | 2010-08-02 | 2012-02-16 | Denso Corp | 半導体装置の製造方法 |
EP2660858A4 (en) * | 2010-12-27 | 2016-03-30 | Nissan Motor | SEMICONDUCTOR MODULE, MOLDING DEVICE AND MOLDING PROCESS |
JP2013089607A (ja) * | 2011-10-13 | 2013-05-13 | Nissan Motor Co Ltd | モールド装置およびモールド方法 |
JP2014093451A (ja) * | 2012-11-05 | 2014-05-19 | Denso Corp | モールドパッケージの製造方法 |
JP2019050324A (ja) * | 2017-09-12 | 2019-03-28 | 富士電機株式会社 | 半導体装置、半導体装置の積層体、及び、半導体装置の積層体の搬送方法 |
JP7024269B2 (ja) | 2017-09-12 | 2022-02-24 | 富士電機株式会社 | 半導体装置、半導体装置の積層体、及び、半導体装置の積層体の搬送方法 |
WO2020094411A1 (en) * | 2018-11-07 | 2020-05-14 | Danfoss Silicon Power Gmbh | Mold tool for molding a semiconductor power module with top-sided pin connectors and method of manufacturing such a semiconductor power module |
WO2024111242A1 (ja) * | 2022-11-21 | 2024-05-30 | I-Pex株式会社 | インサート部材およびインサート成形方法 |
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