JP2009200278A - METHOD FOR MANUFACTURING SiC SCHOTTKY BARRIER DIODE - Google Patents
METHOD FOR MANUFACTURING SiC SCHOTTKY BARRIER DIODE Download PDFInfo
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- 230000004888 barrier function Effects 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 238000000034 method Methods 0.000 title claims abstract description 16
- 238000005498 polishing Methods 0.000 claims abstract description 18
- 238000010438 heat treatment Methods 0.000 claims abstract description 15
- 239000012535 impurity Substances 0.000 claims abstract description 8
- 238000001312 dry etching Methods 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims description 31
- 238000001020 plasma etching Methods 0.000 claims description 12
- 230000015556 catabolic process Effects 0.000 claims description 8
- 238000006731 degradation reaction Methods 0.000 claims description 6
- 150000002500 ions Chemical class 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 230000003746 surface roughness Effects 0.000 abstract description 2
- 239000012528 membrane Substances 0.000 abstract 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 42
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 40
- 238000010586 diagram Methods 0.000 description 6
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 230000004913 activation Effects 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 238000000089 atomic force micrograph Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- -1 aluminum ions Chemical class 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 125000004432 carbon atom Chemical group C* 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 238000005297 material degradation process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
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Abstract
Description
本発明は、SiCショットキバリアダイオードの製造方法に関し、特に終端構造を有するSiCショットキバリアダイオードの製造方法に関するものである。 The present invention relates to a method for manufacturing a SiC Schottky barrier diode, and more particularly to a method for manufacturing a SiC Schottky barrier diode having a termination structure.
SiCは、Siに比べて絶縁破壊耐圧において１桁高く、約２倍の電子飽和ドリフト速度という優れた物性を有しているため、SiCショットキバリアダイオードは、高周波でかつ大電力制御可能な素子として期待されている。しかしながら、大電力による高周波動作では、逆電圧の印加時にショットキー電極の周縁部に電界集中が発生し、本来見込まれている耐圧より低電圧で素子が破壊する場合がある。このような周縁部への電界集中を緩和して耐圧を確保するために、ガードリングなどの終端構造が必要となる。 Since SiC has an excellent physical property of about one order of magnitude higher in dielectric breakdown voltage than Si and about twice the electron saturation drift velocity, SiC Schottky barrier diodes are devices that can control high frequency and high power. Expected. However, in high-frequency operation with high power, electric field concentration occurs at the periphery of the Schottky electrode when a reverse voltage is applied, and the device may be destroyed at a voltage lower than the expected withstand voltage. A termination structure such as a guard ring is required in order to alleviate such electric field concentration on the peripheral portion and ensure a breakdown voltage.
SiCショットキバリアダイオードに終端構造を形成する一般的な方法は、n型のドリフト層上にレジストおよび酸化膜を形成してパターニングする工程、これをマスクとして、アルミニウムまたはホウ素などのp型不純物を選択的にイオン注入する工程、不純物注入後にマスクとしたレジスト膜および酸化膜を除去し、１５００℃以上の高温で熱処理を行う工程、により行われる。 A general method for forming termination structures in SiC Schottky barrier diodes is to form a resist and oxide film on an n-type drift layer and pattern it. Using this as a mask, p-type impurities such as aluminum or boron are selected. Ion implantation, and a step of removing a resist film and an oxide film used as a mask after impurity implantation and performing a heat treatment at a high temperature of 1500 ° C. or higher.
しかし、このように高温で熱処理を行うと、SiC表面からのSi原子やC原子の離脱による組成の不均一が発生し、表面近傍の膜質が劣化した膜質劣化層が発生する。また、バンチングステップの発生による表面の凹凸により、表面モフォロジーの低下が発生する。この膜質が劣化した層の上に直接ショットキ電極を形成すると、表面の欠陥から局所的に大きなリーク電流が発生し、さらにバンチングステップの凹凸によりリーク電流が増加するため、素子特性の劣化が避けられなかった。そのため、下記特許文献１には、活性化熱処理後に、基板表面を研磨することによって、活性化熱処理時に基板表面に生じた物質劣化層を短時間で除去する技術が開示されている。 However, when heat treatment is performed at such a high temperature, a compositional non-uniformity occurs due to the separation of Si atoms and C atoms from the SiC surface, and a film quality deteriorated layer is generated in which the film quality near the surface is deteriorated. Further, the surface morphology is deteriorated due to surface irregularities caused by the occurrence of the bunching step. If a Schottky electrode is formed directly on the layer with degraded film quality, a large leak current is locally generated from defects on the surface, and the leak current increases due to irregularities in the bunching step, so that deterioration of device characteristics can be avoided. There wasn't. Therefore, Patent Document 1 below discloses a technique for removing a material degradation layer generated on the substrate surface during the activation heat treatment in a short time by polishing the substrate surface after the activation heat treatment.
上記特許文献１に開示された方法は、研磨を行うことにより、膜質劣化層を除去し、バンチングステップによる凹凸を平坦化することが可能になる。しかしながら、研磨を行うことによって表面に新たに欠陥や傷が発生し、そのためリーク電流の増加を抑制することができないという問題があった。 According to the method disclosed in Patent Document 1, it is possible to remove the film quality deterioration layer by polishing and to flatten the unevenness caused by the bunching step. However, there has been a problem that new defects and scratches are generated on the surface by polishing, and therefore an increase in leakage current cannot be suppressed.
そこで本発明はかかる問題を解決するためになされたものであり、表面荒れを発生させることなく、逆方向のバイアス時にリーク電流の増加を抑制できるSiCショットキバリアダイオードの製造方法を得ることを目的とする。 Accordingly, the present invention has been made to solve such a problem, and an object of the present invention is to provide a method for manufacturing a SiC Schottky barrier diode capable of suppressing an increase in leakage current during reverse bias without causing surface roughness. To do.
本発明におけるSiCショットキバリアダイオードの製造方法は、（a）第１導電型のSiC基体を準備する工程と、（b）前記SiC基体に選択的に第２導電型の不純物イオンを注入する工程と、（c）前記SiC基体に熱処理を行い、前記第２導電型の不純物を活性化して終端構造を形成する工程と、（d）前記SiC基体の表面を研磨し、前記熱処理時に前記SiC基体の表面に発生した膜質劣化層を除去する工程と、（e）前記工程（d）の後に、前記SiC基体の表面にドライエッチングを行う工程と、（f）前記工程（e）の後に、前記SiC基体上にショットキ電極を形成する工程と、を備える。 The manufacturing method of the SiC Schottky barrier diode according to the present invention includes: (a) a step of preparing a first conductivity type SiC substrate; and (b) a step of selectively implanting second conductivity type impurity ions into the SiC substrate. (C) performing a heat treatment on the SiC substrate to activate the second conductivity type impurity to form a termination structure; and (d) polishing the surface of the SiC substrate and performing the heat treatment on the SiC substrate during the heat treatment. Removing the film quality degradation layer generated on the surface; (e) performing the dry etching on the surface of the SiC substrate after the step (d); and (f) performing the SiC after the step (e). Forming a Schottky electrode on the substrate.
本発明のSiCショットキバリアダイオードの製造方法によれば、研磨によって発生した表面の傷や欠陥を除去するため、リーク電流の増加を抑制することができる。 According to the method for manufacturing a SiC Schottky barrier diode of the present invention, since the surface scratches and defects generated by polishing are removed, an increase in leakage current can be suppressed.
＜実施の形態＞
図１は、本発明の実施の形態におけるSiCショットキバリアダイオード２０の製造工程を示した断面図である。以下、図１を参照して、本実施の形態におけるSiCショットキバリアダイオード２０を製造する方法について説明する。はじめに、SiC基体１２を形成する工程を行う。まず４H-SiC（０００１）シリコン面から８°オフのn型基板１を準備する。なお、４H-SiCとは四周期六方晶（４H）の炭化珪素単結晶を意味する。このn型基板１上にドーピング濃度５×１０15／cm3、膜厚１０μmのn型エピタキシャル層２を成長させる。n型エピタキシャル層２上に、犠牲酸化により酸化膜３を形成する（図１（a））。
<Embodiment>
FIG. 1 is a cross-sectional view showing a manufacturing process of SiC Schottky barrier diode 20 in the embodiment of the present invention. Hereinafter, a method for manufacturing SiC Schottky barrier diode 20 in the present embodiment will be described with reference to FIG. First, a step of forming the SiC substrate 12 is performed. First, an n-type substrate 1 that is 8 ° off from the 4H—SiC (0001) silicon surface is prepared. Note that 4H—SiC means a four-period hexagonal (4H) silicon carbide single crystal. An n-type epitaxial layer 2 having a doping concentration of 5 × 10 15 / cm 3 and a film thickness of 10 μm is grown on the n-type substrate 1. An oxide film 3 is formed on the n-type epitaxial layer 2 by sacrificial oxidation (FIG. 1A).
次に、p型終端構造を形成する工程を行う。酸化膜３上にレジスト４によるマスクパターンを形成する。このマスク上からアルミニウムを選択的にイオン注入５し、イオン注入層６を形成する（図１（b））。例えばイオン注入５条件は、注入量が５E１７／cm3、注入深さが０．８μmとなるようにAlイオンを室温で注入角度０°において、４０〜７００KeVのエネルギーで注入する。次に、レジスト４および酸化膜３を除去した後、注入したアルミニウムイオンを活性化させるためにAr雰囲気中で１７００℃、３０分間熱処理を行う。この熱処理工程により、p型終端構造が形成され、また、膜質劣化層７および高さ３０nm以上のバンチングステップによる凹凸が発生する（図１（c））。図２（a）は、この表面形状のAFM像を示した図であり、表面の凹凸の深さは３４．３０nmとなる。 Next, a step of forming a p-type termination structure is performed. A mask pattern made of resist 4 is formed on oxide film 3. Aluminum is selectively ion-implanted 5 from above the mask to form an ion-implanted layer 6 (FIG. 1B). For example, in the ion implantation 5 conditions, Al ions are implanted with an energy of 40 to 700 KeV at an implantation angle of 0 ° at room temperature so that the implantation amount is 5E17 / cm 3 and the implantation depth is 0.8 μm. Next, after removing the resist 4 and the oxide film 3, heat treatment is performed in an Ar atmosphere at 1700 ° C. for 30 minutes in order to activate the implanted aluminum ions. By this heat treatment step, a p-type termination structure is formed, and irregularities are generated due to the film quality degradation layer 7 and a bunching step having a height of 30 nm or more (FIG. 1C). FIG. 2A is a diagram showing an AFM image of this surface shape, and the depth of the unevenness on the surface is 34.30 nm.
次に、表面の膜質劣化層７の除去、および凹凸を平坦化するために、表面の研磨８を行う（図１（d））。例えば粒径１００nmのダイアモンドスラリーを用い、加重７００gで１０分間研磨８すると、表面は約１００nm研磨８され、膜質劣化層７は除去される（図１（e））。図２（b）は、この表面形状のAFM像を示した図であり、表面の凹凸の深さは２．２７nmとなる。図２（b）に示すように、研磨８により図２（a）で発生していた凹凸は平坦化されるが、同時に研磨８による傷も発生する。 Next, in order to remove the film quality degradation layer 7 on the surface and flatten the unevenness, the surface polishing 8 is performed (FIG. 1D). For example, when a diamond slurry having a particle size of 100 nm is used and polished 8 at a load of 700 g for 10 minutes, the surface is polished 8 by about 100 nm, and the film quality deterioration layer 7 is removed (FIG. 1 (e)). FIG. 2B is a diagram showing an AFM image of this surface shape, and the depth of the unevenness on the surface is 2.27 nm. As shown in FIG. 2B, the unevenness generated in FIG. 2A by the polishing 8 is flattened, but at the same time, scratches due to the polishing 8 are also generated.
次に、研磨８によって発生した傷を除去するためにSiC基体１２の表面にドライエッチング９を行う（図１（f））。本実施の形態ではRIE（リアクティブ・イオンエッチング）を用いて説明する。例えば、CF4：O2＝４：１の混合ガスを用い、１００mTorrの真空度、DCバイアス電圧３００V（電圧換算で３E５V／cm）の条件で５分間エッチングを行う。このRIEにより、表面は約１００nmエッチングされ、研磨８による傷が消滅し、平坦な表面形状が得られる。図２（c）は、この表面形状のAFM像を示した図であり、表面の凹凸の大きさは１．９２nmとなる。図２（C）に示すように、研磨８により図２（b）で発生していた傷が消滅する。本実施の形態ではRIEを用いて説明したが、等方性のプラズマエッチであってもよい。 Next, dry etching 9 is performed on the surface of the SiC substrate 12 in order to remove scratches generated by the polishing 8 (FIG. 1 (f)). In the present embodiment, description will be made using RIE (reactive ion etching). For example, etching is performed for 5 minutes using a mixed gas of CF 4 : O 2 = 4: 1 under the conditions of a vacuum of 100 mTorr and a DC bias voltage of 300 V (3E5 V / cm in terms of voltage). By this RIE, the surface is etched by about 100 nm, scratches due to polishing 8 disappear, and a flat surface shape is obtained. FIG. 2C is a diagram showing an AFM image of the surface shape, and the size of the surface irregularities is 1.92 nm. As shown in FIG. 2C, the scratches generated in FIG. Although this embodiment has been described using RIE, isotropic plasma etching may be used.
次に、SiC基体１２に硫酸過水、アンモニア過水、フッ酸の順でウェット処理を行う。ウェット処理後、SiC基体１２の表面に例えばチタンによるショットキ電極１０、SiC基体１２の裏面にオーミック電極１１を形成する（図１（g））。 Next, wet treatment is performed on the SiC substrate 12 in the order of sulfuric acid / hydrogen peroxide, ammonia / hydrogen peroxide, and hydrofluoric acid. After the wet treatment, a Schottky electrode 10 made of titanium, for example, is formed on the surface of the SiC substrate 12, and an ohmic electrode 11 is formed on the back surface of the SiC substrate 12 (FIG. 1 (g)).
以上の工程により、図２に示すような、SiC基体１２の表面の凹凸を平坦化し、かつ傷が消滅したSiCショットキバリアダイオード２０を得ることができる。 Through the above steps, it is possible to obtain a SiC Schottky barrier diode 20 in which the unevenness on the surface of the SiC substrate 12 is flattened and scratches are eliminated, as shown in FIG.
上述した工程により製造されたSiCショットキバリアダイオード２０の効果を確認するために、研磨８を実施後SiCウエハを二つに分割して、一つはRIEを行わないSiCショットキバリアダイオード、１つはRIEを実施したSiCショットキバリアダイオード２０を製造し、互いの特性を比較する。 In order to confirm the effect of the SiC Schottky barrier diode 20 manufactured by the above-described process, the SiC wafer is divided into two after the polishing 8 is performed, one is a SiC Schottky barrier diode that is not subjected to RIE, and one is The SiC Schottky barrier diode 20 subjected to RIE is manufactured, and the characteristics of each other are compared.
図３は、逆バイアス時のリーク電流特性を示した図である。図３（a）は、研磨８のみを実施した４個の電極面積０．５mmφのSiCショットキバリアダイオードの２００Vにおけるリーク電流特性を示した図である。図に示すように、１０-7〜１０-5Aであった。これに対し、図３（b）は、研磨８とリアクティブ・イオンエッチング９を実施した４個の電極面積０．５mmφのSiCショットキバリアダイオード２０の２００Vにおけるリーク電流特性を示した図である。図に示すように、１０-11〜１０-10Aであった。図３より、リーク電流は１００００倍程度減少していることがわかる。すなわち、研磨８後にリアクティブ・イオンエッチングを行うことにより、リーク電流は大幅に減少し、熱処理によるリーク電流発生を抑制することができる。 FIG. 3 is a diagram showing a leakage current characteristic at the time of reverse bias. FIG. 3 (a) is a diagram showing the leakage current characteristics at 200 V of four SiC area 0.5 mmφ SiC Schottky barrier diodes subjected to polishing 8 only. As shown in the figure, it was 10 −7 to 10 −5 A. On the other hand, FIG. 3B is a diagram showing a leakage current characteristic at 200 V of the SiC Schottky barrier diode 20 having four electrode areas of 0.5 mmφ subjected to the polishing 8 and the reactive ion etching 9. As shown in the figure, it was 10 −11 to 10 −10 A. From FIG. 3, it can be seen that the leakage current is reduced by about 10,000 times. That is, by performing reactive ion etching after polishing 8, the leakage current is greatly reduced, and generation of leakage current due to heat treatment can be suppressed.
以上より、本実施の形態におけるSiCショットキバリアダイオード２０の製造方法は、活性化のための熱処理によって発生した膜質劣化層７を除去するだけでなく、膜質劣化層７を除去するために実施した研磨８による傷や欠陥を除去するため、平坦で、かつリーク電流の少ないSiCショットキバリアダイオード２０を製造することができる。 As described above, the manufacturing method of the SiC Schottky barrier diode 20 in the present embodiment not only removes the film quality degradation layer 7 generated by the heat treatment for activation, but also performs polishing performed to remove the film quality degradation layer 7. Therefore, the SiC Schottky barrier diode 20 which is flat and has a small leakage current can be manufactured.
１ n型基板、２ n型エピタキシャル層、３ 酸化膜、４ レジスト、５ イオン注入、６ イオン注入層、７ 膜質劣化層、８ 研磨、９ ドライエッチング、１０ ショットキ電極、１１ オーミック電極、１２ SiC基体、２０ SiCショットキバリアダイオード。 1 n-type substrate, 2 n-type epitaxial layer, 3 oxide film, 4 resist, 5 ion implantation, 6 ion implantation layer, 7 film quality deteriorated layer, 8 polishing, 9 dry etching, 10 Schottky electrode, 11 ohmic electrode, 12 SiC substrate , 20 SiC Schottky barrier diode.
Claims (6)
（b）前記SiC基体に選択的に第２導電型の不純物イオンを注入する工程と、
（c）前記SiC基体に熱処理を行い、前記第２導電型の不純物を活性化して終端構造を形成する工程と、
（d）前記SiC基体の表面を研磨し、前記熱処理時に前記SiC基体の表面に発生した膜質劣化層を除去する工程と、
（e）前記工程（d）の後に、前記SiC基体の表面にドライエッチングを行う工程と、
（f）前記工程（e）の後に、前記SiC基体上にショットキ電極を形成する工程と、を備える、SiCショットキバリアダイオードの製造方法。 (A) preparing a first conductivity type SiC substrate;
(B) selectively implanting second conductivity type impurity ions into the SiC substrate;
(C) performing a heat treatment on the SiC substrate to activate the second conductivity type impurity to form a termination structure;
(D) polishing the surface of the SiC substrate and removing the film quality degradation layer generated on the surface of the SiC substrate during the heat treatment;
(E) after the step (d), performing a dry etching on the surface of the SiC substrate;
(F) A step of forming a Schottky electrode on the SiC substrate after the step (e), and a method for manufacturing a SiC Schottky barrier diode.
（g）第１導電型のSiC基板を準備する工程と、
（h）前記SiC基板上にエピタキシャル層を形成する工程と、を備える、請求項１に記載のSiCショットキバリアダイオードの製造方法。 The step (a)
(G) preparing a first conductivity type SiC substrate;
(H) The process of forming an epitaxial layer on the said SiC substrate, The manufacturing method of the SiC Schottky barrier diode of Claim 1 provided with.
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| JP2020127014A (en) * | 2012-06-06 | 2020-08-20 | ローム株式会社 | Semiconductor device |
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| JP2004221513A (en) * | 2002-03-28 | 2004-08-05 | Rohm Co Ltd | Semiconductor device and method of manufacturing the same |
| JP2004363326A (en) * | 2003-06-04 | 2004-12-24 | Fuji Electric Holdings Co Ltd | Method for manufacturing silicon carbide semiconductor device |
| JP2005039257A (en) * | 2003-07-02 | 2005-02-10 | Matsushita Electric Ind Co Ltd | Semiconductor device and method for manufacturing the same |
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| JP2004221513A (en) * | 2002-03-28 | 2004-08-05 | Rohm Co Ltd | Semiconductor device and method of manufacturing the same |
| JP2004363326A (en) * | 2003-06-04 | 2004-12-24 | Fuji Electric Holdings Co Ltd | Method for manufacturing silicon carbide semiconductor device |
| JP2005039257A (en) * | 2003-07-02 | 2005-02-10 | Matsushita Electric Ind Co Ltd | Semiconductor device and method for manufacturing the same |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2020127014A (en) * | 2012-06-06 | 2020-08-20 | ローム株式会社 | Semiconductor device |
| US11004939B2 (en) | 2012-06-06 | 2021-05-11 | Rohm Co., Ltd. | Semiconductor device having a junction portion contacting a Schottky metal |
| JP2022028867A (en) * | 2012-06-06 | 2022-02-16 | ローム株式会社 | Semiconductor device |
| US11610970B2 (en) | 2012-06-06 | 2023-03-21 | Rohm Co., Ltd. | Semiconductor device having a junction portion contacting a Schottky metal |
| US12057479B2 (en) | 2012-06-06 | 2024-08-06 | Rohm Co., Ltd. | Semiconductor device having a junction portion contacting a Schottky metal |
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