JP2009192461A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a delay overhead in a multiplexer-scanning flip-flop and make a layout area smaller. <P>SOLUTION: During normal operation, a selector 4a selects a data signal D, and a data-saving flip-flop 3 is in a holding state. During a scan path test, a scanning operation is performed by setting a standby signal Standby EN at a Lo level, and by setting the standby signal Standby EN at a Hi level, respectively. The data-saving flip-flop 3 always holds data obtained one cycle before, because data is transferred from the data-scanning flip-flop 3 to a multiplexer-scanning flip-flop 4. Thus, a buffer becomes unnecessary that is normally inserted in the scan path as measures to hold. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a flip-flop provided in a semiconductor integrated circuit device, and more particularly to a technique effective for reducing delay overhead in a flip-flop with a scan function.

  In a semiconductor integrated circuit device, a data holding flip-flop is widely used. This data holding flip-flop includes, for example, a scan flip-flop in which a MUX (multiplexer) scan 2-to-1 selector is connected to a data input unit, and the data saving flip-flop is directly connected via the scan flip-flop gate. What is connected is known.

  However, the present inventors have found that the data holding flip-flop as described above has the following problems.

  In general, MUX scan flip-flops use the system clock to perform synchronous transfer during scan operations that write or read flip-flop data from the outside, preventing hold violations between flip-flops. A delay is provided.

  This delay is designed with a large delay margin in consideration of manufacturing variations and the like, and accordingly, the layout area of the delay is increased, which may hinder the miniaturization of the semiconductor integrated circuit device.

  Further, since the data saving flip-flop is directly connected to the scan flip-flop, there is a problem that the capacity load increases, and as a result, the speed-up operation is hindered.

  An object of the present invention is to provide a technique capable of reducing a delay overhead and a layout area in a multiplexer scan flip-flop having a scan function.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The present invention is a semiconductor integrated circuit device having a plurality of logic modules configured by a plurality of internal logic circuit blocks, having a flip-flop with a function provided in an arbitrary logic module, and the flip-flop with a function A first flip-flop having a multiplexer scan function and connected so that an input signal is input to one input section, and used for data saving, and connected to the other input section of the first flip-flop. A second flip-flop to which the output unit is connected, and an output unit connected to the input unit of the second flip-flop, and data output from the first flip-flop based on a selection signal, or a scan path A selector that selects one of the test scan signals and outputs the selected scan signal to the second flip-flop. Selects the output signal of the first flip-flop during normal operation, selects and outputs the scan signal during the scan path test, and the second flip-flop operates as a saving flip-flop during normal operation, The scan signal output from the selector at the time of the test is delayed by a half cycle and output to the first flip-flop, and operates as a flip-flop for hold violation countermeasure of the first flip-flop.

  In the present invention, the first flip-flop selects and outputs data held by the second flip-flop when data is saved.

  Furthermore, the present invention includes a low power control unit that controls low power consumption of the logic module, and the logic module provided with a function flip-flop is a target of low power control by the low power control unit. .

  Further, according to the present invention, the second flip-flop holds data even when the power supply voltage is constantly supplied and the power of the logic module is shut off by the low power control of the low power control unit.

  Furthermore, the outline | summary of the other invention of this application is shown briefly.

  The present invention is a semiconductor integrated circuit device having a plurality of logic modules configured by a plurality of internal logic circuit blocks, having a flip-flop with a function provided in an arbitrary logic module, and the flip-flop with a function A first flip-flop having a multiplexer scan function and connected so that an input signal is input to one input unit, and used for data saving, and an input to the output unit of the first flip-flop The output part is connected to the second flip-flop to which the part is connected and the other input part of the first flip-flop, and the data output from the second flip-flop or the scan path based on the selection signal A selector that selects one of the test scan signals and outputs it to one input section of the first flip-flop. The selector selects and outputs the output signal of the second flip-flop during the normal operation, selects and outputs the scan signal during the scan path test, and the second flip-flop is a saving flip-flop during the normal operation. The signal output from the first flip-flop during the scan path test is output as a scan signal.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  (1) The delay overhead of the first flip-flop can be greatly reduced.

  (2) Further, according to the above (1), it is possible to eliminate the need for a delay element for holding during the scan path test, so that the layout area of the semiconductor integrated circuit device can be reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 1 is a block diagram showing a configuration example of a function-equipped flip-flop according to Embodiment 1 of the present invention, and FIG. 2 is an explanatory diagram showing an operation example of the flip-flop provided in the function-equipped flip-flop of FIG. 3 is an explanatory diagram showing an example of operation of a latch provided in the flip-flop with function of FIG. 1, and FIG. 4 shows an example of operation function of a flip-flop for data saving provided in the flip-flop with function of FIG. FIG. 5 is a circuit diagram describing the flip-flop with function of FIG. 1 at the gate level, and FIG. 6 is an internal logic circuit block and flip-flop with function of the semiconductor integrated circuit device according to the first embodiment of the present invention. FIG. 7 is a block diagram showing a configuration example of a semiconductor integrated circuit device to which the function-equipped flip-flop according to the first embodiment of the present invention is applied. 8 is an explanatory diagram of a control truth value showing an example of the function-equipped flip-flop in the semiconductor integrated circuit device of FIG. 7, FIG. 9 is a time chart showing an operation example of the function-equipped flip-flop of FIG. 1, and FIG. FIG. 11 is a time chart showing an operation example when the scan path test is applied to the function-equipped flip-flop of FIG. 1, and FIG. 11 is a time showing another example of the operation of the function-equipped flip-flop according to the first embodiment of the present invention. FIG. 12 is a flowchart showing a design example of a function-equipped flip-flop using the DA tool according to the first embodiment of the present invention.

  In the first embodiment, the function-equipped flip-flop 1 is a flip-flop provided in an internal logic circuit block of a semiconductor integrated circuit device and used as a latch. For example, a so-called multiplexer in which a test signal is switched by a multiplexer or the like. A scan path test by scanning (Mux Scan) is possible.

  As shown in FIG. 1, the function-equipped flip-flop 1 includes a selector 2, a data saving flip-flop 3, a multiplexer scan flip-flop 4, and buffers 5 and 6.

  In the function-equipped flip-flop 1, the data saving flip-flop 3 serving as the second flip-flop is connected to the input terminal of the multiplexer scan flip-flop 4 serving as the first flip-flop, and the data saving flip-flop 3 is connected. The selector 2 provided in the previous stage can select a scan input (scan input signal SIN) and an output signal from the multiplexer scan flip-flop 4.

  Further, the data saving flip-flop 3 and the multiplexer scan flip-flop 4 are arranged close to each other as a measure against a scan path hold.

  The selection terminal Scan / Hold, which is a data saving control signal, is connected to the control terminal of the selector 2 so that the scan input signal SIN is input to one input portion of the selector 2. It is connected to the.

  Further, the other input part of the selector 2 is connected so that an output signal outputted from the multiplexer scan flip-flop 4 is inputted. The output part of the selector 2 is connected to the input part of the data saving flip-flop 3.

  The selector 2 selects and outputs either the scan input signal SIN or the output signal output from the multiplexer scan flip-flop 4 based on the selection signal Scan / Hold input to the control terminal.

  The data saving flip-flop 3 includes a latch 3a, an AND circuit 3b, and an inverter 3c. An output part of the selector 2 is connected to the data terminal d of the latch 3a, and an output part of the AND circuit 3b is connected to the clock terminal ck of the latch 3a. The other input portion of the multiplexer scan flip-flop 4 is connected to the data output terminal q of the latch 3a.

  A standby signal StandbyEN, which is a data saving control signal, is connected to the input part of the inverter 3c, and one input part of the AND circuit 3b is connected to the output part of the inverter 3c. Yes.

  The other input section of the AND circuit 3b is connected to receive the clock signal CLK. When the standby signal StandbyEN becomes active, the clock signal CLK supplied to the latch 3a is stopped.

  The multiplexer scan flip-flop 4 includes a selector 4a and an edge trigger type flip-flop 4b. A selection signal SEN for selecting the scan input signal SIN and the normal data signal D is connected to the control terminal of the selector 4a.

  The output terminal of the selector 4a is connected to the input terminal of the flip-flop 4b. The other input section of the selector 2 and the input sections of the buffers 5 and 6 are connected to the output terminal of the flip-flop 4b. The output terminal of the flip-flop 4b is an output section of the multiplexer scan flip-flop 4.

  The signal output from the output unit of the buffer 5 becomes the output signal Q of the flip-flop 1 with function, and the signal output from the output unit of the buffer 6 becomes the scan output signal SOUT of the flip-flop 1 with function.

  FIG. 2 is an explanatory diagram showing an operation example of the flip-flop 4b.

  As shown in the figure, the flip-flop 4b takes in the data signal D at the rising or falling change point of the clock signal CLK serving as a latch pulse.

  FIG. 3 is an explanatory diagram showing an operation example of the latch 3a.

  In this case, the latch 3a takes in the data signal D during the Hi level period of the clock signal CLK as shown in the figure.

  FIG. 4 is an explanatory diagram showing an example of an operation function of the data saving flip-flop 3.

  The data saving flip-flop 3 is configured to be supplied with a power supply voltage VDD that is always ON. Thus, even if the power supply other than the data saving flip-flop 3 in the function-equipped flip-flop 1 is cut off, the standby signal StandbyEN is set to the Hi signal immediately before the power supply other than the data saving flip-flop 3 is cut off. Can be held.

  FIG. 5 is a circuit diagram describing the flip-flop 1 with function at the gate level.

  The selector 2 includes tristate buffers B1 and B2, and the data saving flip-flop 3 includes inverters Iv1 and Iv2, tristate buffer B3, transfer gate TG1, and a 2-input negative OR circuit for clock gates. It consists of NOR.

  In the multiplexer scan flip-flop 4, the selector 4a is composed of tristate buffers B4 and B5, like the selector 2. The flip-flop 4b includes transfer gates TG2 and TG3, inverters Iv3 to Iv7, and tristate buffers B6 and B7.

  The flip-flop 4b has a configuration in which a latch configured by the transfer gate TG2, the inverter Iv3, and the tristate buffer B6 and a latch configured by the transfer gate TG3, the inverter Iv4, and the tristate buffer B7 are connected in two stages. The first-stage latch is active when the clock signal CLK is at the Lo level, and the second-stage latch is adjusted so that the clock polarity is active when the clock signal CLK is at the Hi level.

  The selector 2 selects the scan input of the previous stage and the output signal of the multiplexer scan flip-flop 4 as the input of the data saving flip-flop 3.

  FIG. 6 is an explanatory diagram showing a connection configuration between the internal logic circuit block B and the function-equipped flip-flop 1 of the semiconductor integrated circuit device.

  In the flip-flop with function 1 provided in the preceding stage of the internal logic circuit block B, the output signal Q of the flip-flop with function 1 is connected so as to be input to the input section of the internal logic circuit block B.

  Further, the scan output signal SOUT of the flip-flop 1 with function provided in the preceding stage of the internal logic circuit block B is input to the flip-flop 1 with function provided in the preceding stage of the internal logic circuit block B as the scan input signal SIN. So that they are connected.

  The data saving flip-flop 3 operates as a data saving flip-flop in actual operation, and at the time of a scan path test of the semiconductor integrated circuit device, the scan data is delayed by half a cycle and output, thereby causing a hold violation countermeasure flip-flop. Works as.

  Further, the multiplexer scan flip-flop 4 and the data saving flip-flop 3 are preferably configured by, for example, one standard cell or arranged close to each other for layout in order to prevent hold.

  As a result, a delay element for countermeasure against hold violation at the time of the scan path test provided between the function-equipped flip-flops becomes unnecessary, and the overhead of the layout area of the semiconductor chip can be reduced.

  FIG. 7 is a block diagram showing a configuration example of the semiconductor integrated circuit device 7 to which the function-equipped flip-flop 1 is applied.

  The semiconductor integrated circuit device 7 includes logic modules 8 and 9 that can individually control power supply (shut down) such as low power consumption control, a power supply control module 10 that performs power supply control of the semiconductor integrated circuit device 7, and the semiconductor integrated circuit device 7. A test control module 11 for controlling the scan path test.

  The logic modules 8 and 9 are provided with a plurality of function-equipped flip-flops 1 and power switch circuits 8a and 9a for controlling the power of the logic module modules 8 and 9 based on the control of the power control module 10, respectively. Yes.

  The power supply control module 10 which is a low power control unit outputs selection signals Scan / Hold1, Scan / Hold2, standby signals StandbyEN1, StandbyEN2, power supply control signals Power1, Power2, and selection signals PSEN1, PSEN2. The test control module 11 outputs selection signals TSEN1 and TSEN2, respectively.

  The selection signal Scan / Hold1 and the standby signal StandbyEN1 are data saving control signals of the flip-flop 1 with function provided in the logic module 8, and the selection signal Scan / Hold2 and the standby signal StandbyEN2 are provided in the logic module 9. It becomes a data saving control signal of the functioned flip-flop 1.

  The power control signal Power1 is a control signal for controlling the power switch circuit 8a when setting the low power consumption mode, and the power control signal Power2 is a control for controlling the power switch circuit 9a when setting the low power consumption mode. Signal.

  The selection signals PSEN1 and TSEN1 are control signals for the multiplexer scan flip-flop 4 provided in the logic module 8 during the scan path test, and the selection signals PSEN2 and TSEN2 are multiplexers provided in the logic module 9 during the scan path test. This is a control signal for the scan flip-flop 4.

  The selection signals PSEN1, PSEN2, TSEN1, and TSEN2 are originally control signals for the scan path test. However, since the selection signals PSEN1 and PSEN2 need to be controlled when data is saved, for example, OR circuits OR1, It is connected to the logic modules 8 and 9 through gate logic such as OR2, and is input as the selection signal SEN.

  Since this gate logic forms an arbitrary logic according to the control method, it is not limited to an OR gate. Further, when driven by a high-speed clock, this gate logic is preferably arranged immediately after the test control module or just before being connected to the function-equipped flip-flop 1 in order to easily adjust the path delay. .

  FIG. 8 is an explanatory diagram of control truth values showing an example of the function-equipped flip-flop 1 in the semiconductor integrated circuit device 7 of FIG.

  When the semiconductor integrated circuit device 7 is operating normally, as shown in the figure, the standby signal StandbyEN becomes Hi ('1') level, and other signals (selection signals Scan / Hold, SEN) are Lo (' 0 ') level.

  Further, at the time of data saving, the standby signal Standbyby and the selection signals Scan / Hold, SEN are all at the Lo level, and when the logic module 8 (, 9) is powered off, the standby signal Standbyby is at the Hi level.

  Further, at the time of data scan in the scan path test, the standby signal StandbyBY becomes Lo level, and the selection signals Scan / Hold, SEN become Hi level. At the time of data capture of the scan path test, the standby signal StandbyBY and the selection signal SEN are at the Lo level, and the selection signal Scan / Hold is at the Hi level.

  Next, the operation of the function-equipped flip-flop 1 according to the present embodiment will be described.

  FIG. 9 is a time chart showing an operation example of the function-equipped flip-flop 1. In FIG. 9, from the upper side to the lower side, the clock signal CLK, the selection signal SEN, the standby signal StandbyEN, the power supply voltage supplied to the logic module, the selection signal Scan / Hold, the hold value of the multiplexer scan flip-flop 4, and the data saving Signal timings at the holding values of the flip-flop 3 are shown.

  In a normal use state, the selection signal SEN is at the Lo level, and the selector 4a selects the data signal D. In addition, when the standby signal StandbyEN is at the Hi level, the clock signal CLK supplied to the clock terminal ck of the latch 3a is suppressed, and the saving flip-flop 3 is held.

  By setting the clock signal CLK to the suppressed state, there is also an effect that the data saving flip-flop 3 is stopped in a normal use state so that useless power is not consumed.

  When saving the data, the selection signal SEN is set to the Hi level, the standby signal StandbyEN is set to the Lo level, and the clock signal CLK is applied to complete the data copy to the data saving flip-flop 3.

  Further, when the standby signal StandbyEN is set to the Hi level again to cut off the power supply voltage supplied to the functional module, the data can be held only in the data saving flip-flop 3.

  In order to recover after the power is turned on, the selection signal SEN is set to the Hi level, the standby signal StandbyBY is set to the Lo level, and the clock signal CLK is applied once, whereby the return to the data saving flip-flop 3 is completed.

  After that, in order to return to the normal use state, the selection signal SEN is set to Lo level, the selector 4a selects the data signal D, the standby signal StandbyEN is set to Hi level, and the suppression state of the clock signal CLK is released.

  In this case, the selection signal Scan / Hold is always at the Lo level because the selector 2 selects the scan-out of the multiplexer scan flip-flop 4, and the selection signal Scan / Hold is applied during the scan path test. Set to Hi level and select scan input.

  FIG. 10 is a time chart showing an operation example when the scan path test is applied to the flip-flop 1 with function. In FIG. 10, from the top to the bottom, the clock signal CLK, the selection signal SEN, the standby signal StandbyEN, the power supply voltage supplied to the logic module, the selection signal Scan / Hold, the hold value of the multiplexer scan flip-flop 4, and the data saving Signal timings at the holding values of the flip-flop 3 are shown.

  During the scan path test, the scan operation is performed by setting the standby signal StandbyEN to the Lo level state and the standby signal StandbyEN to the Hi level state.

  When the scan operation is performed, data is transferred from the data saving flip-flop 3 to the multiplexer scan flip-flop 4, and thus the data saving flip-flop 3 always holds data one cycle before.

  For example, with respect to the hold value S1 of the multiplexer scan flip-flop 4, the hold value of the data save flip-flop 3 becomes the hold value S2, but when the clock signal CLK is at the Hi level, the data save flip-flop 3 writes Because of this state, it is necessary to match the delay from the scan output of the flip-flop 1 with the function at the previous stage during this period.

  During the period when the clock signal CLK is at the Lo level, the data saving flip-flop 3 is in the holding state, so that the scan output of the preceding function-equipped flip-flop 1 is not accepted, but the transfer to the multiplexer scan flip-flop 4 is as follows. Since the data is transferred at the rising edge of the clock signal CLK, the data held by the data saving flip-flop 3 can be reliably transferred.

  In short, from the viewpoint of the multiplexer scan flip-flop 4, the setup becomes strict for 1/2 cycle, but it is not necessary to care on the hold side, so that a buffer inserted in the scan path is generally unnecessary as a countermeasure against the hold. be able to.

  When testing after transferring the test data by scanning, the selection signal SEN is set to Lo level, the data is fetched from the normal path as in FIG. 11 described later, and then the selection signal SEN is returned to Hi level. Output scan data.

  FIG. 11 is a time chart showing another example of the operation in the flip-flop 1 with function. Also in FIG. 11, from above to below, the clock signal CLK, the selection signal SEN, the standby signal StandbyEN, the power supply voltage supplied to the logic module, the selection signal Scan / Hold, the held value of the multiplexer scan flip-flop 4, and the data Signal timings at the holding values of the saving flip-flop 3 are shown.

  FIG. 11 shows a case where the selection signal SEN is set to Lo level in the normal use state of the function-equipped flip-flop 1, and data from the scan enters the data saving flip-flop 3 every cycle. This data is data from the scan path and is irrelevant in normal operation.

  In this case, although there is no functional problem, the data saving flip-flop 3 always operates, and thus power consumption increases.

  FIG. 12 is a flowchart showing a design example of the function-equipped flip-flop 1 using a DA (Design Automation) tool.

  First, a net list output by logic synthesis is inserted (step S101), a scan path test circuit is inserted using a DFT (Design For Test) tool (step S102), and at the same time, the flip-flop 1 with function is replaced.

  Since the function-equipped flip-flop 1 has a control signal for saving data, the corresponding signal is in a floating state (or a state where the signal is fixed at the Hi level / Lo level). Further, depending on the DFT tool, signals other than those for test use may not be handled, and thus processing for correctly connecting these signals to the power supply control module 10 (FIG. 7) is required (step S103).

  Below, the production | generation method of the power supply control module 10 is described.

  First, when the DFT tool cannot handle a signal other than the test purpose, a normal function flip-flop is generated and replaced with the function flip-flop 1 of the present invention. Thereafter, the net list of the power supply control module 10 is generated in the net list of the semiconductor integrated circuit device, and the control signal is connected.

  At this time, the selection signal SEN used for both the scan path test and the data save is inserted with gate logic at an arbitrary place, or gate logic is inserted in advance and a control signal is added to control the power supply. Generation of module 10 is complete. When the generation of the power supply control module 10 is completed, layout design is performed for layout on the semiconductor chip (step S104).

  Since the flip-flop with function 1 has a simple configuration that can be saved and restored with a clock and a control signal, it can be easily reflected in the tool library when designing with the DA tool.

  Thereby, according to the first embodiment, the delay overhead of the multiplexer scan flip-flop 4 can be reduced by arranging the saving flip-flop serving as a load in the scan path.

  In the scan path test, the data saving flip-flop 3 delays the scan data transfer cycle by a half cycle, so that a hold countermeasure delay element is unnecessary and the layout area of the semiconductor integrated circuit device 7 can be reduced. it can.

(Embodiment 2)
FIG. 13 is a block diagram showing a configuration example of a function-equipped flip-flop according to the second embodiment of the present invention, and FIG. 14 is a circuit diagram describing the function-equipped flip-flop of FIG. 13 at the gate level.

  In the second embodiment, the function-equipped flip-flop 1 is a flip-flop provided in an internal logic circuit block of a semiconductor integrated circuit device. As shown in FIG. 13, a selector 2, a data saving flip-flop 3, a multiplexer scan It consists of a flip-flop 4 and buffers 5 and 6.

  Similarly to the first embodiment, the data saving flip-flop 3 includes a latch 3a, an AND circuit 3b, and an inverter 3c. The multiplexer scan flip-flop 4 is of the edge trigger type and the selector 4a. And a flip-flop 4b.

  The functional flip-flop 1 shown in FIG. 13 is different from the functional flip-flop 1 of the first embodiment in that the data saving flip-flop 3 is connected to the output section of the multiplexer scan flip-flop 4.

  FIG. 14 is a circuit diagram describing the function-equipped flip-flop 1 of FIG. 13 at the gate level.

  In the selector 2, an inverter Iv8 is newly added to the same configuration as that of FIG. 5 including the tristate buffers B1 and B2. The inverter Iv8 is connected to the preceding stage of the tristate buffer B1.

  The data saving flip-flop 3 includes inverters Iv1 and Iv2, a tristate buffer B3, a transfer gate TG1, and a 2-input negative OR circuit NOR for a clock gate. Iv10 is newly added. The inverter Iv9 is connected to one input part of the NOR circuit NOR, and the inverter Iv10 is connected to the preceding stage of the buffer 6.

  Further, the multiplexer scan flip-flop 4 includes a selector 4a and a flip-flop 4b. The selector 4a is composed of tristate buffers B4 and B5 as in FIG. 5, and the flip-flop 4b is composed of transfer gates TG2 and TG3, inverters Iv3 to Iv7, and tristate buffers B6 and B7 as in FIG. Has been.

  The difference from FIG. 5 is that, as described above, the data saving flip-flop 3 is directly connected to the output section of the multiplexer scan flip-flop 4, and the output of the data saving flip-flop 3 remains as it is. It becomes a scan output.

  Thereby, also in the second embodiment, the delay overhead of the multiplexer scan flip-flop 4 can be reduced by arranging the data saving flip-flop serving as a load in the scan path.

  In the scan path test, the data saving flip-flop 3 delays the scan data transfer cycle by a half cycle, so that a delay element for holding is not required, and the layout area of the semiconductor integrated circuit device 7 can be reduced. it can.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, the function-equipped flip-flop 1 may draw a signal from the scan-out buffer 6 (SOUT) into the selector 2 of the data saving flip-flop 3, as shown in FIG.

  In this case, the function is the same as that in FIG. 1, but the wiring delay can be reduced as compared with the case where the wiring is directly drawn out from the flip-flop 4b.

  In the first embodiment, the source voltage VDD is always supplied to the data saving flip-flop 3 even if the power of other areas is shut off. The data saving flip-flop 3 is shown in FIG. As described above, the source voltage VDD may not be constantly supplied.

  Also in this case, the data saving flip-flop 3 includes the latch 3a, the AND circuit 3b, and the inverter 3c, and enters a standby state in which the standby signal StandbyEN becomes a Hi signal, thereby suppressing input from the clock terminal ck. .

  The present invention is suitable for a technique for reducing the layout area of a flip-flop with a function having a scan function used as a latch and delay overhead.

It is a block diagram which shows the structural example of the flip-flop with a function by Embodiment 1 of this invention. It is explanatory drawing which shows the operation example of the flip-flop provided in the flip-flop with a function of FIG. It is explanatory drawing which shows the operation example of the latch provided in the flip-flop with a function of FIG. FIG. 2 is an explanatory diagram illustrating an example of an operation function of a data saving flip-flop provided in the function-equipped flip-flop of FIG. 1. FIG. 2 is a circuit diagram describing the function-equipped flip-flop of FIG. 1 at a gate level. It is explanatory drawing which shows the connection structure of the internal logic circuit block and flip-flop with a function of the semiconductor integrated circuit device by Embodiment 1 of this invention. 1 is a block diagram illustrating a configuration example of a semiconductor integrated circuit device to which a function-equipped flip-flop according to a first embodiment of the present invention is applied. FIG. 8 is an explanatory diagram of control truth values showing an example of a function-equipped flip-flop in the semiconductor integrated circuit device of FIG. 7. 3 is a time chart showing an operation example of the function-equipped flip-flop of FIG. 1. FIG. 10 is a time chart showing an operation example when the scan path test is applied to the function-equipped flip-flop of FIG. It is a time chart which shows the other example of operation | movement in the flip-flop with a function by Embodiment 1 of this invention. It is a flowchart which shows the design example of the flip-flop with a function using the DA tool by Embodiment 1 of this invention. It is a block diagram which shows the structural example of the flip-flop with a function by Embodiment 2 of this invention. It is the circuit diagram which described the flip-flop with a function of FIG. 13 by the gate level. It is a block diagram which shows the structural example of the flip-flop with a function by other embodiment of this invention. It is explanatory drawing which showed the other example of the operation | movement function of the data saving flip-flop provided in the flip-flop with a function by other embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Flip-flop with function 2 Selector 3 Data saving flip-flop 3a Latch 3b AND circuit 3c Inverter 4 Multiplexer scan flip-flop 4a Selector 4b Flip-flop 5, 6 Buffer 7 Semiconductor integrated circuit device 8 Logic module 8a Power switch circuit 9 Logic module 9a Power switch circuit 10 Power control module 11 Test control module B Internal logic circuit blocks B1 to B7 Tristate buffers Iv1 to Iv10 Inverters TG1 to TG3 Transfer gate NOR Negative OR circuit

Claims (7)

A semiconductor integrated circuit device having a plurality of logic modules configured by a plurality of internal logic circuit blocks,
A flip-flop with a function provided in any of the logic modules;
The flip-flop with the function is
A first flip-flop having a multiplexer scan function and connected so that an input signal is input to one input unit;
A second flip-flop that is used for saving data and has an output connected to the other input of the first flip-flop;
An output unit is connected to an input unit of the second flip-flop, and either one of data output from the first flip-flop or a scan signal for a scan path test is selected based on a selection signal. And a selector that outputs to the second flip-flop,
The selector is
Select the output signal of the first flip-flop during normal operation, select and output the scan signal during the scan path test,
The second flip-flop
It operates as a saving flip-flop during normal operation, and a scan signal output from the selector during a scan path test is delayed by a half cycle and output to the first flip-flop, for countermeasure against hold violation of the first flip-flop. A semiconductor integrated circuit device which operates as a flip-flop. The semiconductor integrated circuit device according to claim 1.
The first flip-flop
2. A semiconductor integrated circuit device, wherein the data held by the second flip-flop is selected and output when data is saved. The semiconductor integrated circuit device according to claim 1 or 2,
A low power control unit for controlling low power consumption of the logic module;
The logic module provided with the flip-flop with the function is
A semiconductor integrated circuit device, which is a target of low power control by the low power control unit. The semiconductor integrated circuit device according to claim 3.
The second flip-flop
A semiconductor integrated circuit device, wherein a power supply voltage is constantly supplied and data is retained even when the power supply of the logic module is shut off by low power control of the low power control unit. A semiconductor integrated circuit device having a plurality of logic modules configured by a plurality of internal logic circuit blocks,
A flip-flop with a function provided in any of the logic modules;
The flip-flop with the function is
A first flip-flop having a multiplexer scan function and connected so that an input signal is input to one input unit;
A second flip-flop that is used for data saving and has an input connected to the output of the first flip-flop;
An output unit is connected to the other input unit of the first flip-flop, and either one of data output from the second flip-flop or a scan signal for a scan path test is received based on a selection signal. A selector that selects and outputs to one input of the first flip-flop;
The selector is
Select and output the output signal of the second flip-flop during normal operation, select and output the scan signal during a scan path test,
The second flip-flop
A semiconductor integrated circuit device which operates as a saving flip-flop during a normal operation and outputs a signal output from the first flip-flop as a scan signal during a scan path test. The semiconductor integrated circuit device according to claim 5.
The first flip-flop
2. A semiconductor integrated circuit device, wherein the data held by the second flip-flop is selected and output when data is saved. The semiconductor integrated circuit device according to claim 5 or 6,
A low power control unit for controlling low power consumption of the logic module;
The logic module provided with the flip-flop with the function is
A semiconductor integrated circuit device, which is a target of low power control by the low power control unit.

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