CN100585852C - Semiconductor device tested using minimum pins, and method of testing same - Google Patents

Abstract

The present invention provides a semiconductor device capable of being tested using one test pin, and using input/output pins without any test pins, and a method of testing the same. A semiconductor device includes: a test pin for inputting/outputting test data; an operation mode controller for activating an enable signal in response to an external reset signal and a clock signal; an operation mode storage means for responding to the enable signal to receive serial data in synchronization with the clock signal through the test pin; and an operation mode decoder for generating an operation mode selection signal in response to the serial data stored in the operation mode storage means.

Description

Semiconductor device tested using minimum pins, and method of testing same

Cross References to Related Applications

This application claims the benefit of Korean Patent Application No. 2005-10048 filed on February 3, 2005 and Korean Patent Application No. 2005-10748 filed on February 4, 2005, the contents of which are hereby incorporated by reference .

technical field

The present invention relates to a system-on-chip and a method of testing the same, and, more particularly, to a system-on-chip that can be tested by using one test pin or without any test pin, and how to test it.

Background technique

Typically, system-on-chip size and power consumption can increase as pins are added to the chip. Therefore, it is best to reduce or remove one or more test pins that are only used to test the device.

In the case of an image chip whose pins are provided only to receive a clock signal and a reset signal, there is no spare pin for receiving a test signal according to a test vector during a test. Thus, one or more pins are required to test the graphics chip.

In addition, new technology needs to be developed to set various test modes without additional test pins, because setting The various test patterns are complex.

Since electronic devices such as mobile devices require a minimized size, it is desirable to reduce the size of chips used in the electronic devices. In the case of reducing the chip size, it is complicated to properly arrange input/output pins such as data input/output pins and power supply pins on one side or both sides. Thus, eliminating test pins is beneficial. Additionally, test items for chips in portable electronic devices have increased, resulting in more test pins being included.

Figure 1 shows the pinout of a conventional system-on-chip with test pins arranged on its three sides, while Figure 2 shows the pinout of a conventional system-on-chip with test pins arranged on its two sides. The feet are arranged.

The chip in FIG. 1 has: a plurality of test pins TEST_1 to TEST_4, eg four, a RESET pin; a CLK pin, and a plurality of input/output pins IO_1 to IO_7. The input/output pins IO_1 to IO_7 are dedicated to the normal mode of operation. The chip in FIG. 2 has a test pin TEST, a reset pin RESET, a clock pin CLK, and a plurality of input/output pins IO_1 to IO_7. Part of the input/output pins IO_1 to IO_7 can be used for a test mode of operation. If the chip has fewer input/output pins, the test pattern to perform operations based on the test system of FIG. 2 is complicated.

Contents of the invention

An aspect of the present invention provides a system on chip capable of being tested using one test pin, and a method of testing the same.

The semiconductor device according to this aspect of the present invention includes: a test pin for inputting/outputting test data; an operation mode controller for activating an enable signal in response to an external reset signal and a clock signal; an operation mode storage means for receiving serial data in synchronization with the clock signal through the test pin in response to the enable signal; and an operation mode decoder for generating an operation mode selection signal in response to the serial data stored in the operation mode storage means .

In one exemplary embodiment, the operation mode controller includes: a bit counter for counting on rising edges of a clock signal in response to a low-to-high logic level transition of a reset signal; and a comparator for converting the output of the bit counter to The value is compared with the operating mode number to activate the enable signal when the output value is less than the operating mode number. In this embodiment, the operation mode number is determined by serial data.

In one exemplary embodiment, the enable signal is at a high logic level from a low to high logic level transition of the reset signal until the count value reaches the operating mode number.

In one exemplary embodiment, the operation mode storage device shifts the serial data in synchronization with a clock signal in response to an enable signal from the operation mode controller.

In an exemplary embodiment, the operating mode storage means is set to indicate the operating mode.

In an exemplary embodiment, the operating mode storage means is set to indicate low-level operating modes and test targets belonging to the operating modes. In this embodiment, the test target is a component in the semiconductor device to be tested.

In one exemplary embodiment, test targets include input/output interfaces, memory, and internal logic.

In one exemplary embodiment, the reset signal transitions from low to high logic level synchronously with the falling edge of the clock signal CLK.

In an exemplary embodiment, the operation mode includes a normal operation mode in which the semiconductor device performs a normal function and the normal operation mode is indicated in the shift register.

In one exemplary embodiment, the semiconductor device further includes a multiplexer for outputting the operation mode selection signal in response to a high-to-low logic level transition of the enable signal from the operation mode controller.

Another aspect of the present invention provides a method of testing a semiconductor device, including: activating an enable signal in response to a reset signal; receiving serial data through a test pin in synchronization with a clock signal in response to the enable signal ; deactivating the enable signal by determining whether the serial data is completely input; and generating an operation mode selection signal in response to the serial data when the enable signal is deactivated.

In one exemplary embodiment, the enable signal is activated by a low-to-high logic level transition and deactivated by a high-to-low logic level transition.

In an exemplary embodiment, the step of generating the operation mode selection signal further includes generating a test signal.

In one exemplary embodiment, the test signal is used to indicate a low-level operation mode and a test target of the operation mode set by the operation mode selection signal. In this embodiment, the test target is a component in the semiconductor device to be tested.

Another aspect of the present invention provides a system-on-chip capable of being tested using input/output pins without any test pins, and a method of testing the same. The test circuit according to this aspect of the present invention includes: an input/output pin for receiving test data in a test mode; a delay reset signal generator for delaying a reset signal; a counter for A clock signal counts to generate a count value; a mode register stores test data; and a decoder generates a selection signal to the mode register to designate a location in the mode register to write test data.

In an exemplary embodiment, the test circuit further includes an input/output controller, the input/output controller includes: a first tri-state buffer, the input end of which is connected to the internal logic, and the output end is connected to the input/output pin pin, which sends test data from the internal logic to the input/output pin; a second tri-state buffer, whose input is connected to this pin and whose output is connected to the mode register, so that test data is sent from this pin to the test mode register; and an OR gate, the output of which is connected to the enabling terminals of the first and second tri-state buffers, the first input is connected to the delay reset signal generator, and the second input is connected to the counter. In this embodiment, the first and second tri-state buffers are enabled by the output signal of the OR gate.

In an exemplary embodiment, when the count value of the counter reaches a predetermined value, the counter generates a count end signal to one output terminal of the OR gate. In this embodiment, the end-of-count signal is at a high logic level.

In one exemplary embodiment, the delayed reset signal generator outputs the delayed reset signal to the second output terminal of the OR gate, and the delayed reset signal generator delays the reset signal depending on the number of test patterns.

In one exemplary embodiment, the counter has a value of "0" when the reset signal is at a low logic level.

In one exemplary embodiment, the reset signal is delayed by at least |log ₂ N| cycles of the clock signal, where N is the number of test patterns.

Another aspect of the present invention provides a system-on-chip comprising: input/output pins for input and output of test data; clock input for receiving a clock signal; reset input for receiving a reset signal; delayed reset a signal generator for delaying a reset signal to generate a delayed reset signal; an input/output controller for a time period from a low-to-high logic level transition of the reset signal to a low-to-high logic level transition of the delayed reset signal period to make the I/O pins function as input pins; a counter to count the clock signal in synchronization with the low-to-high logic level transition of the reset signal; a mode register to store in response to a select signal from the decoder the test data; and a decoder for generating a select signal to specify a location of the test data from the I/O controller in the mode register depending on the output value of the counter.

In an exemplary embodiment, the system-on-chip further includes: a first tri-state buffer whose input is connected to the I/O controller and whose output is connected to the I/O pin, thereby sending test data from the internal logic to the input/output pin; a second tri-state buffer whose input is connected to the input/output pin and whose output is connected to the test mode register, thereby sending test data from the input/output pin to the mode register; and An OR gate, the output terminal of which is connected to the enabling terminals of the first and second tri-state buffers, the first input terminal is connected to the delayed reset signal generator, and the second input terminal is connected to the counter. In this embodiment, the first and second tri-state buffers are enabled by the output signal of the OR gate.

In an exemplary embodiment, the counter generates a count end signal of a high logic level to the first output terminal of the OR gate when the count value reaches a predetermined value.

In one exemplary embodiment, the delayed reset signal generator delays the reset signal depending on the number of test patterns, and the counter has a value '0' when the reset signal is at a low logic level.

In one exemplary embodiment, the delayed reset signal generator delays the reset signal by at least |log ₂ N| cycles of the clock signal, and N is the number of test patterns.

In an exemplary embodiment, the system-on-chip further includes a demultiplexer, the input of which is connected to the input pin, the first output of which is connected to the internal logic, and the second output of which is connected to the test mode register. In this embodiment, the demultiplexer is enabled by a logical combination of a count end signal and a delayed reset signal, and an input/output pin is used as an input pin.

Description of drawings

The accompanying drawings are included to provide a further understanding of the invention, illustrate exemplary embodiments of the invention and together with the description explain the principles of the invention. In the attached picture:

Figure 1 shows the pinout of a conventional system-on-chip with test pins arranged on three sides thereof;

Figure 2 shows the pinout of a conventional system-on-chip with test pins arranged on its two sides;

Fig. 3 shows the pin arrangement of the system on chip according to the present invention;

4 is a block diagram illustrating an internal structure of the system-on-chip of FIG. 3 according to the present invention;

5 and 6 are timing diagrams according to the present invention;

7 is a block diagram of a system on a chip according to another embodiment of the present invention;

8 is a circuit diagram of the input/output controller of FIG. 7 according to another embodiment of the present invention;

FIG. 9 is a timing diagram of the system-on-chip of FIG. 7 according to another embodiment of the present invention;

10 is a block diagram of a system on a chip according to another embodiment of the present invention; and

FIG. 11 is a timing diagram of the system-on-chip of FIG. 10 according to another embodiment of the present invention.

Detailed ways

Preferred embodiments of the present invention will be described in detail below by referring to the accompanying drawings. However, this invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the specification, the same reference numerals denote the same elements.

Hereinafter, a system on chip capable of being tested by using one test pin to reduce a chip size, and a method of testing the same will be described.

Fig. 3 shows the pinout of a system on chip according to the invention. Referring to FIG. 3 , the system on chip 100 includes a test pin IO_TEST, a reset pin IO_RESET, a clock input pin IO_CLK, and a plurality of input/output pins IO_1 to IO_7, for example seven. In order to set a test mode of operation of the system on chip 100 , serial data SD is input through the test pin IO_TEST. During the test mode of operation, the plurality of input/output pins IO_1 to IO_7 are not used.

FIG. 4 is a block diagram illustrating an internal structure of the system on chip of FIG. 3 according to the present invention. Referring to FIG. 4 , the SoC 100 includes an operation mode controller 110 , an operation mode storage device 120 , an operation mode decoder 130 , a multiplexer 160 , and a plurality of internal test modules 140 to 150 , for example k.

In this exemplary embodiment, it is assumed that the signal required to set the operating mode has log ₂ N bits (N=N ₁ +N ₂ +...+N _k , the number of operating modes). The operation mode controller 110 includes a bit counter (bitcounter) 111 and a comparator 112 . The bit counter 111 is started in synchronization with the low-to-high logic level transition of the reset signal RESET input through the reset pin IO_RESET in FIG. 3 . The bit counter 111 counts at the rising edge of the clock signal CLK received through the reset pin IO_RESET to generate the count value Y1 to the comparator 112 . The number of bits M of the bit counter 111 is an integer "log ₂ N".

The comparator 112 compares the output value Y1 of the bit counter 111 with the number N of operation modes. If the output value Y1 is less than the operating mode number N, the comparator 112 generates an enable signal Y2. In this case, the enable signal Y2 has a high logic level (“1”). The operation mode storage 120 includes k+1 shift registers 121 to 123 that operate in response to the enable signal Y2. When the reset signal RESET is disabled (that is, when the reset signal RESET has a low-to-high logic level transition), the k+1 shift registers 121 to 123 sequentially perform serial data input from the outside in synchronization with the clock signal CLK SD shift. The k+1 shift registers 121 to 123 stop when the output value Y1 of the bit counter 111 in the operation mode storage device 120 reaches the number N of operation modes. That is, the k+1 shift registers 121 to 123 operate when the enable signal Y2 is at a high logic level. One of the k+1 shift registers 121 to 123 is set to indicate at least one operation mode. FIG. 4 illustrates an example in which the shift register 121 is set to indicate an operation mode. In other words, when the enable signal Y2 is at a high logic level, the shift register 121 sequentially shifts the serial data SD in synchronization with the clock signal CLK, and outputs N1 number of serial data SD to the operation mode decoder 130. The shift register 122 sequentially shifts the serial data SD in synchronization with the clock signal CLK, and outputs N2 number of serial data SD to the internal test module 140 . Likewise, the shift register 123 outputs Nk pieces of serial data SD to the internal test module 150 .

The operation mode decoder 130 receives N1 serial data SD from the shift register 121 to output 2N1 operation mode selection signals to the multiplexer 160 . The internal test module 140 receives N2 serial data SD from the shift register 122 to generate 2N2 test signals, and the internal test module 150 generates 2N _k test signals. Each of the k internal test modules 140 to 150 is a device for testing a selected target in the system on chip 100 in each predetermined test mode.

The multiplexer 160 is activated by the enable signal R2 of the operation mode controller 110, and fixes the output OP_MODE to a constant value (for example, "0000...0000") until the completion of the operation mode storage device 120. up to the shift operation. If not, the output of the operation mode decoder 130 is changed. This may cause some problems during the test operation because an undesired operation mode may be set according to the output of the operation mode decoder 130 .

5 and 6 are timing diagrams according to the present invention. For simplicity, it is assumed that the operation mode storage device 120 in FIG. 4 includes four shift registers, and the number N of operation modes is nine. Referring to FIG. 5, the bit counter 111 in the operation mode controller 110 in FIG. 4 counts in synchronization with each rising edge of the clock signal. The reset signal RESET is disabled at the falling edge of the clock signal CLK to ensure a removal/recovery margin. The bit counter 111 operates in synchronization with the rising edge of the clock signal CLK, and, at the falling edge of the clock signal CLK, the serial data SD is input through the test pin IO_TEST to ensure a setup/hold margin.

The serial data SD is sequentially shifted in synchronization with the clock signal CLK. Some serial data C0, C1 and C2 are set in the shift register 123, other serial data B0 and B1 are set in the shift register 122, and the remaining serial data A0, A1 are set in the shift register 121 , A2 and A3. Outputs SEL2 and SEL3 of the shift registers 122 and 123 indicate a lower operation mode among specific operation modes, or select a lower test target. The output signal OP_MODE of the multiplexer 160 is fixed to a constant value until the registers 121, 122, and 123 are set according to the serial data SD. This is because the output of the operation mode decoder 130 has not changed.

As fully described above, in the test mode in which the serial data SD is input through the test pin IO_TEST according to the test vector, the timing among the reset signal RESET, the clock signal CLK, and the serial data SD can be easily adjusted . However, it is complicated to change the timing according to the clock signal CLK in the normal operation mode in which the chip operates and fixes the serial data SD to a constant value logic "0" or "1". Therefore, the values A0, A1, A2, and A3 of the register 121 indicating a specific operation mode are defined as logic "0" or logic "1".

Assume that the number of shift registers in FIG. 4 is one, and the number N of operation modes is four. Referring to FIG. 6, the bit counter 111 in the operation mode controller 110 performs a counting operation at a rising edge of a clock signal CLK. The reset signal RESET is disabled on the falling edge of the clock signal CLK. The bit counter 111 operates at the rising edge of the clock signal CLK, and inputs the serial data SD through the test pin IO_TEST at the falling edge of the clock signal. Therefore, the setup/hold margin related to the serial data SD is sufficiently ensured.

In the shift register 121, the serial data SD is sequentially shifted in synchronization with the clock signal CLK so as to be set. Values A0, A1, A2, and A3 each indicate a low-level mode of operation and normal operation. In each low-level operating mode, the input/output interfaces, memory and internal logic operations are tested separately. The output signal OP MODE of the multiplexer 160 is fixed at a constant value until the shift register 121 is fully set.

Hereinafter, a system on chip capable of testing by using input/output pins of a chip without requiring test pins, and a method thereof will be described.

FIG. 7 is a block diagram of a system-on-chip according to another embodiment of the present invention. Referring to Fig. 7, SoC 200 of the present invention comprises delay reset signal generator 203, counter 204, decoder 205, test mode register 206, input/output controller 240, clock signal input pin 210, reset signal input pin 220 , and input/output pins 230 .

The clock signal input pin 210 receives a clock signal CLK generated from an oscillator (not shown). Clock signal CLK is used to synchronize the inputs to counter 204 and test mode register 206 . The reset signal input pin 220 receives an external reset signal RESET, which is applied to the delayed reset signal generator 203 and the counter 204 . The reset signal RESET is used to determine the timing at which data indicating the test mode is set in the test mode register 206 . The input/output pin 230 is connected to an input/output controller 240 . When the test mode is set, the input/output controller 240 fixes the input/output pin 230 as an input pin for receiving external test data D_IN. After the test mode is completely set, the input/output controller 240 fixes the input/output pin 230 as an output pin for transmitting the output data D_OUT from the internal logic to the external memory.

The delayed reset signal generator 203 delays the reset signal RESET input from the reset input pin 220 and outputs the delayed reset signal DE_RESET to the input/output controller 230 . The reset signal RESET is delayed by more than a period corresponding to the absolute value of log ₂ N clock periods (ie, the number of test patterns in the chip). That is, the delayed reset signal generator 203 delays the reset signal RESET for a period of time to set the test mode in the chip. For example, when the number of test patterns is 6, the number of bits required to set the test pattern register is 3. Thus, the reset signal RESET is delayed by three cycles or more. In addition, the delayed reset signal generator 203 determines the timing at which the setting of the input/output pin 230 is changed from input to output. The counter 204 is set to maintain a value of "0" during the time interval that the reset signal RESET is at a low logic level. The counter 204 counts when the reset signal RESET transitions from a low to a high logic level. The counter 204 outputs the count value to the decoder 205, and generates a count end signal CNT_DONE if the count value reaches the absolute value of log ₂ N (ie, the number of test patterns in the chip). When the count end signal CNT_DONE is input to the input/output controller 240, the input/output controller 240 changes the setting of the input/output pin 230 from input to output.

The decoder 205 generates a selection signal for selecting a specific location of the test mode register 206 storing the test data D_IN from the input/output controller 240 . The test mode register 206 stores test data D_IN in synchronization with the clock signal CLK in response to a selection signal from the decoder 205 . As mentioned above, the number of bits of the test pattern register 206 is above the absolute value of log ₂ N (ie, the number of test patterns in the chip).

FIG. 8 is a circuit diagram of the input/output controller of FIG. 7 according to another embodiment of the present invention. Referring to FIG. 8 , the input/output controller 240 includes first and second tri-state buffers 242 and 243 , and an OR gate 241 . The input of the first tri-state buffer 242 is connected to the input/output pin 230 and the output thereof is connected to the test mode register 206 . An output terminal of the OR gate 241 is connected to enable terminals of the first and second tri-state buffers 242 and 243 , and one input terminal of the OR gate 241 is connected to the delayed reset signal generator 203 . The first and second tri-state buffers 242 and 243 are enabled or disabled by the output signal of the OR gate 241 . The output signal of the OR gate 241 is a logical combination signal of the delayed reset signal DE_RESET from the delayed reset signal generator 203 and the count end signal CNT_DONE from the counter 204 . When one of the delay reset signal DE_RESET and the count end signal CNT_DONE is at a high logic level, the first tri-state buffer 242 is enabled to output the output data D_OUT from the internal logic to, for example, the outside through the input/output pin 230 memory external devices. When both the delayed reset signal DE_RESET and the count end signal CNT_DONE are at low logic levels, the second tri-state buffer 243 is enabled to input the test data D_IN to the test mode register 206 through the input/output pin 230 .

FIG. 9 is a timing diagram of the system-on-chip of FIG. 7 according to another embodiment of the present invention. In FIG. 9, it is assumed that the number of test patterns is 5-8, and a test pattern that is binary data "101" is stored in a predetermined location of the pattern register 206 (for example, register bits [2:0]).

Referring to FIGS. 7 and 9, a reset signal RESET of a low logic level is applied to the chip through the reset input pin 220, and a period of time elapses. Reset signal RESET transitions from low to high logic level (at T1 ). Normally, the chip operates normally at the low-to-high logic level transition of the reset signal RESET. However, according to the present invention, the reset signal RESET is delayed for a predetermined time (at T6 ) by delaying the reset signal generator 203 . Thus, a value indicative of a test mode is set in the test mode register 206 between time T1 when reset signal RESET transitions from low to high logic level and time T6 when delayed reset signal DE_RESET transitions from low to high logic level. The input/output pin 230 is used as an input pin between time T1 and time T6. At T1, the counter 204 starts counting operation. The counter 204 counts rising edges after T1 in synchronization with the clock signal CLK. The decoder 205 generates a selection signal for selecting a predetermined location of the test mode register 206 that records the test data D_IN input through the input/output pin 230 according to the count value. The value {1, 0, 1} is recorded in the least significant bit (LSB) of the test mode register 206 . Since the output of the counter 204 is "0" at T2, the value "1" of the test data D_IN is written in [0] of the test mode register 206 . Since the value of the counter is "1" at T3, the value "0" of the test data D_IN is written in [1] of the test mode register 206 . Since the value of the counter is "2" at T4, the value "1" of the test data D_IN is written in [2] of the test mode register 206 . When the count value reaches an absolute value of log2N (ie, the number of test patterns in the chip), the counter 204 sends a count end signal CNT_DONE at a high logic level to the input/output controller 240 . The input/output controller 240 makes the input/output pin 230 function as an output pin in response to the count end signal CNT_DONE.

FIG. 10 is a block diagram of a system-on-chip according to another embodiment of the present invention. Referring to FIG. 10, a system-on-chip 200' of the present invention has a structure similar to the system-on-chip 200 in FIG. 1. Referring to FIG. However, the system on chip 200 ′ has an input pin 230 ′ instead of the input/output pin 230 , and a demultiplexer 250 instead of the input/output controller 240 . The components described with reference to FIG. 7 will not be further described, and the same components as those in FIG. 7 are denoted by the same reference numerals in FIG. 7 .

The input pin 230' connected to the demultiplexer 250 is used as a test pin for receiving external test data Test_IN when the test mode is set, and as a test pin for receiving data sent to the internal logic circuit after the test mode is completely set. Input pin for input data Func_IN. The delayed reset signal generator 203 delays the reset signal RESET input from the reset input pin 220 to transmit the delayed reset signal DE_RESET to the OR gate 241 . The delayed reset signal generator 203 generates a delayed reset signal DE_RESET that determines the moment when the input pin 230' changes its role from a test pin to a normal operation pin. The count end signal CNT_DONE generated from the counter 204 is applied to the OR gate to change the role of the input pin 230' from a test pin to an input pin. The input of the demultiplexer 250 is connected to the input pin 230', while its first output is connected to the internal logic circuit. A second output of the demultiplexer 250 is connected to the test mode register 206 . The demultiplexer 250 controls the data received through the input pin 230' according to the enable signal EN which is a logical combination signal of the count end signal CNT_DONE from the counter 204 and the delayed reset signal DE_RESET from the delayed reset signal generator 203. . That is, when the enable signal EN is at a low logic level, the first output terminal of the demultiplexer 250 is activated to transmit the test data TEST_IN to the test mode register 206 . Meanwhile, when the enable signal EN is at a high logic level, the second output terminal of the demultiplexer 250 is activated to transmit the input data Func_IN received through the input pin 230' in the normal operation mode to the internal logic.

FIG. 11 is a timing diagram of the system-on-chip of FIG. 10 according to another embodiment of the present invention. Assume that the number of test patterns is 5-8, and binary data "101" indicating one test pattern is recorded in a predetermined position (eg, [2:0]) of the test pattern register 206 .

Referring to FIGS. 10 and 11, a reset signal RESET at a low logic level is applied to the chip through the reset input pin 220, and a period of time elapses. The reset signal RESET transitions from low to high logic level at T1. Normally, the chip begins normal operation when the reset signal transitions from a low to a high logic level. However, the reset signal RESET is delayed until a predetermined time T6 by delaying the reset signal generator 203 . Therefore, between time T1 and time T6, a value indicative of the test mode is set in the test mode register 206 . The reset signal RESET transitions from low to high logic level at time T1, and the delayed reset signal transitions from low to high logic level at time T6. The input pin 230' is used as a test pin between time T1 and time T6. At T1, the counter 204 starts counting. The counter 204 counts rising edges of the clock signal CLK after T1 in synchronization with the clock signal CLK. The decoder 205 determines a specific position of the test mode register 206 to which the test data Test_IN is input through the input pin 230 ′ according to the count value of the counter 204 . In other words, the values {1, 0, 1} are written sequentially from the LSB in the test mode register 206 . Since the value of the counter is "0" at T2, the value "1" of the test data Test_IN is written in [0] of the test mode register. Since the value of the counter is "1" at T3, the value "1" of the test data Test_IN is written in [1] of the test mode register. Since the value of the counter is "2" at T4, the value "1" of the test data Test_IN is written in [2] of the test mode register.

When the count value reaches the absolute value of log ₂ N (ie, the number of test patterns in the chip), the counter 204 sends a count end signal CNT_DONE at a high logic level to the OR gate 241 . When the count end signal CNT_DONE is applied to the demultiplexer, the input pin 230' resumes its function as a normal input pin for receiving data Func_IN transmitted to the internal logic. Thus, the present invention can set various test modes without additional test pins.

According to exemplary embodiments of the present invention, the number of pins used in input/output of test signals is reduced to minimize the size of a system on chip and reduce power consumption.

According to an exemplary embodiment of the present invention, a test mode with various low-level operation modes can be set using one specific test pin. In this embodiment, the timing of the signal input for the test vector through one test pin can be adjusted using the clock signal and the reset signal. In addition, a specific mode of low-level operation mode can be set in the chip through a plurality of shift registers.

Although the invention has been described in connection with the exemplary embodiments of the invention illustrated in the drawings, the invention is not limited thereto. It will be apparent to those skilled in the art that various substitutions, modifications and changes can be made therein without departing from the scope and spirit of the invention.

Claims (11)

1. A semiconductor device comprising: Test pins for input/output of test data; an operation mode controller for activating an enable signal in response to an external reset signal and a clock signal; The first shift register is used to receive serial data synchronously with the clock signal through the test pin in response to the enable signal; a second shift register for receiving serial data from the first shift register in synchronization with the clock signal in response to the enable signal; an operation mode decoder for generating an operation mode selection signal by decoding serial data stored in one of the first shift register and the second shift register; and An internal test module for receiving serial data stored in the other of the first shift register and the second shift register as a test signal. 2. The device of claim 1, wherein the operating mode controller comprises: a bit counter for counting rising edges of the clock signal in response to a low-to-high logic level transition of the reset signal; and a comparator for comparing the output value of the bit counter with the operating mode number to activate the enable signal when the output value is less than the operating mode number, Among them, the number of operation modes is determined through serial data. 3. The device of claim 2, wherein the enable signal is at a high logic level when the count value reaches the operating mode number from a low to high logic level transition of the reset signal. 4. The device of claim 1, wherein the first shift register and the second shift register shift the serial data in response to an enable signal from an operation mode controller. 5. The device of claim 4, wherein the first shift register and the second shift register are set to indicate an operation mode. 6. The device of claim 4, wherein the first shift register and the second shift register are set to indicate a low-level operation mode and a test target belonging to an operation mode, Among them, the test target is a component in the semiconductor device to be tested. 7. The device of claim 6, wherein the test target includes an input/output interface, a memory, and an internal logic circuit. 8. The device of claim 1, wherein the reset signal transitions from low to high logic level in synchronization with a falling edge of the clock signal. 9. The device of claim 5, wherein the operation mode comprises a normal operation mode, wherein the semiconductor device performs a normal function. 10. The device of claim 9, wherein a normal operation mode is set in the first shift register and the second shift register. 11. The device of claim 3, further comprising a multiplexer to output the operation mode selection signal in response to a high-to-low logic level transition of the enable signal from the operation mode controller.

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